2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
29 #include <drm/drm_plane_helper.h>
31 #include "intel_drv.h"
32 #include "../../../platform/x86/intel_ips.h"
33 #include <linux/module.h>
34 #include <drm/drm_atomic_helper.h>
39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
55 #define INTEL_RC6_ENABLE (1<<0)
56 #define INTEL_RC6p_ENABLE (1<<1)
57 #define INTEL_RC6pp_ENABLE (1<<2)
59 static void gen9_init_clock_gating(struct drm_i915_private
*dev_priv
)
61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
62 I915_WRITE(CHICKEN_PAR1_1
,
63 I915_READ(CHICKEN_PAR1_1
) | SKL_EDP_PSR_FIX_RDWRAP
);
65 I915_WRITE(GEN8_CONFIG0
,
66 I915_READ(GEN8_CONFIG0
) | GEN9_DEFAULT_FIXES
);
68 /* WaEnableChickenDCPR:skl,bxt,kbl */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1
,
70 I915_READ(GEN8_CHICKEN_DCPR_1
) | MASK_WAKEMEM
);
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
73 /* WaFbcWakeMemOn:skl,bxt,kbl */
74 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
76 DISP_FBC_MEMORY_WAKE
);
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
80 ILK_DPFC_DISABLE_DUMMY0
);
83 static void bxt_init_clock_gating(struct drm_i915_private
*dev_priv
)
85 gen9_init_clock_gating(dev_priv
);
87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
95 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
102 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
103 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
104 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
107 static void i915_pineview_get_mem_freq(struct drm_i915_private
*dev_priv
)
111 tmp
= I915_READ(CLKCFG
);
113 switch (tmp
& CLKCFG_FSB_MASK
) {
115 dev_priv
->fsb_freq
= 533; /* 133*4 */
118 dev_priv
->fsb_freq
= 800; /* 200*4 */
121 dev_priv
->fsb_freq
= 667; /* 167*4 */
124 dev_priv
->fsb_freq
= 400; /* 100*4 */
128 switch (tmp
& CLKCFG_MEM_MASK
) {
130 dev_priv
->mem_freq
= 533;
133 dev_priv
->mem_freq
= 667;
136 dev_priv
->mem_freq
= 800;
140 /* detect pineview DDR3 setting */
141 tmp
= I915_READ(CSHRDDR3CTL
);
142 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
145 static void i915_ironlake_get_mem_freq(struct drm_i915_private
*dev_priv
)
149 ddrpll
= I915_READ16(DDRMPLL1
);
150 csipll
= I915_READ16(CSIPLL0
);
152 switch (ddrpll
& 0xff) {
154 dev_priv
->mem_freq
= 800;
157 dev_priv
->mem_freq
= 1066;
160 dev_priv
->mem_freq
= 1333;
163 dev_priv
->mem_freq
= 1600;
166 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
168 dev_priv
->mem_freq
= 0;
172 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
174 switch (csipll
& 0x3ff) {
176 dev_priv
->fsb_freq
= 3200;
179 dev_priv
->fsb_freq
= 3733;
182 dev_priv
->fsb_freq
= 4266;
185 dev_priv
->fsb_freq
= 4800;
188 dev_priv
->fsb_freq
= 5333;
191 dev_priv
->fsb_freq
= 5866;
194 dev_priv
->fsb_freq
= 6400;
197 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
199 dev_priv
->fsb_freq
= 0;
203 if (dev_priv
->fsb_freq
== 3200) {
204 dev_priv
->ips
.c_m
= 0;
205 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
206 dev_priv
->ips
.c_m
= 1;
208 dev_priv
->ips
.c_m
= 2;
212 static const struct cxsr_latency cxsr_latency_table
[] = {
213 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
214 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
215 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
216 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
217 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
219 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
220 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
221 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
222 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
223 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
225 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
226 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
227 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
228 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
229 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
231 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
232 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
233 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
234 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
235 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
237 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
238 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
239 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
240 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
241 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
243 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
244 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
245 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
246 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
247 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
250 static const struct cxsr_latency
*intel_get_cxsr_latency(bool is_desktop
,
255 const struct cxsr_latency
*latency
;
258 if (fsb
== 0 || mem
== 0)
261 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
262 latency
= &cxsr_latency_table
[i
];
263 if (is_desktop
== latency
->is_desktop
&&
264 is_ddr3
== latency
->is_ddr3
&&
265 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
269 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
274 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
278 mutex_lock(&dev_priv
->rps
.hw_lock
);
280 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
282 val
&= ~FORCE_DDR_HIGH_FREQ
;
284 val
|= FORCE_DDR_HIGH_FREQ
;
285 val
&= ~FORCE_DDR_LOW_FREQ
;
286 val
|= FORCE_DDR_FREQ_REQ_ACK
;
287 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
289 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
290 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
291 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
293 mutex_unlock(&dev_priv
->rps
.hw_lock
);
296 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
300 mutex_lock(&dev_priv
->rps
.hw_lock
);
302 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
304 val
|= DSP_MAXFIFO_PM5_ENABLE
;
306 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
307 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
309 mutex_unlock(&dev_priv
->rps
.hw_lock
);
312 #define FW_WM(value, plane) \
313 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
315 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
319 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
320 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
321 POSTING_READ(FW_BLC_SELF_VLV
);
322 dev_priv
->wm
.vlv
.cxsr
= enable
;
323 } else if (IS_G4X(dev_priv
) || IS_CRESTLINE(dev_priv
)) {
324 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
325 POSTING_READ(FW_BLC_SELF
);
326 } else if (IS_PINEVIEW(dev_priv
)) {
327 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
328 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
329 I915_WRITE(DSPFW3
, val
);
330 POSTING_READ(DSPFW3
);
331 } else if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
)) {
332 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
333 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
334 I915_WRITE(FW_BLC_SELF
, val
);
335 POSTING_READ(FW_BLC_SELF
);
336 } else if (IS_I915GM(dev_priv
)) {
338 * FIXME can't find a bit like this for 915G, and
339 * and yet it does have the related watermark in
340 * FW_BLC_SELF. What's going on?
342 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
343 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
344 I915_WRITE(INSTPM
, val
);
345 POSTING_READ(INSTPM
);
350 DRM_DEBUG_KMS("memory self-refresh is %s\n", enableddisabled(enable
));
355 * Latency for FIFO fetches is dependent on several factors:
356 * - memory configuration (speed, channels)
358 * - current MCH state
359 * It can be fairly high in some situations, so here we assume a fairly
360 * pessimal value. It's a tradeoff between extra memory fetches (if we
361 * set this value too high, the FIFO will fetch frequently to stay full)
362 * and power consumption (set it too low to save power and we might see
363 * FIFO underruns and display "flicker").
365 * A value of 5us seems to be a good balance; safe for very low end
366 * platforms but not overly aggressive on lower latency configs.
368 static const int pessimal_latency_ns
= 5000;
370 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
371 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
373 static int vlv_get_fifo_size(struct drm_i915_private
*dev_priv
,
374 enum pipe pipe
, int plane
)
376 int sprite0_start
, sprite1_start
, size
;
379 uint32_t dsparb
, dsparb2
, dsparb3
;
381 dsparb
= I915_READ(DSPARB
);
382 dsparb2
= I915_READ(DSPARB2
);
383 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
384 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
387 dsparb
= I915_READ(DSPARB
);
388 dsparb2
= I915_READ(DSPARB2
);
389 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
390 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
393 dsparb2
= I915_READ(DSPARB2
);
394 dsparb3
= I915_READ(DSPARB3
);
395 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
396 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
404 size
= sprite0_start
;
407 size
= sprite1_start
- sprite0_start
;
410 size
= 512 - 1 - sprite1_start
;
416 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
417 pipe_name(pipe
), plane
== 0 ? "primary" : "sprite",
418 plane
== 0 ? plane_name(pipe
) : sprite_name(pipe
, plane
- 1),
424 static int i9xx_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
426 uint32_t dsparb
= I915_READ(DSPARB
);
429 size
= dsparb
& 0x7f;
431 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
433 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
434 plane
? "B" : "A", size
);
439 static int i830_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
441 uint32_t dsparb
= I915_READ(DSPARB
);
444 size
= dsparb
& 0x1ff;
446 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
447 size
>>= 1; /* Convert to cachelines */
449 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
450 plane
? "B" : "A", size
);
455 static int i845_get_fifo_size(struct drm_i915_private
*dev_priv
, int plane
)
457 uint32_t dsparb
= I915_READ(DSPARB
);
460 size
= dsparb
& 0x7f;
461 size
>>= 2; /* Convert to cachelines */
463 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
470 /* Pineview has different values for various configs */
471 static const struct intel_watermark_params pineview_display_wm
= {
472 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
473 .max_wm
= PINEVIEW_MAX_WM
,
474 .default_wm
= PINEVIEW_DFT_WM
,
475 .guard_size
= PINEVIEW_GUARD_WM
,
476 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
478 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
479 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
480 .max_wm
= PINEVIEW_MAX_WM
,
481 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
482 .guard_size
= PINEVIEW_GUARD_WM
,
483 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
485 static const struct intel_watermark_params pineview_cursor_wm
= {
486 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
487 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
488 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
489 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
490 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
492 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
493 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
494 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
495 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
496 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
497 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
499 static const struct intel_watermark_params g4x_wm_info
= {
500 .fifo_size
= G4X_FIFO_SIZE
,
501 .max_wm
= G4X_MAX_WM
,
502 .default_wm
= G4X_MAX_WM
,
504 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
506 static const struct intel_watermark_params g4x_cursor_wm_info
= {
507 .fifo_size
= I965_CURSOR_FIFO
,
508 .max_wm
= I965_CURSOR_MAX_WM
,
509 .default_wm
= I965_CURSOR_DFT_WM
,
511 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
513 static const struct intel_watermark_params i965_cursor_wm_info
= {
514 .fifo_size
= I965_CURSOR_FIFO
,
515 .max_wm
= I965_CURSOR_MAX_WM
,
516 .default_wm
= I965_CURSOR_DFT_WM
,
518 .cacheline_size
= I915_FIFO_LINE_SIZE
,
520 static const struct intel_watermark_params i945_wm_info
= {
521 .fifo_size
= I945_FIFO_SIZE
,
522 .max_wm
= I915_MAX_WM
,
525 .cacheline_size
= I915_FIFO_LINE_SIZE
,
527 static const struct intel_watermark_params i915_wm_info
= {
528 .fifo_size
= I915_FIFO_SIZE
,
529 .max_wm
= I915_MAX_WM
,
532 .cacheline_size
= I915_FIFO_LINE_SIZE
,
534 static const struct intel_watermark_params i830_a_wm_info
= {
535 .fifo_size
= I855GM_FIFO_SIZE
,
536 .max_wm
= I915_MAX_WM
,
539 .cacheline_size
= I830_FIFO_LINE_SIZE
,
541 static const struct intel_watermark_params i830_bc_wm_info
= {
542 .fifo_size
= I855GM_FIFO_SIZE
,
543 .max_wm
= I915_MAX_WM
/2,
546 .cacheline_size
= I830_FIFO_LINE_SIZE
,
548 static const struct intel_watermark_params i845_wm_info
= {
549 .fifo_size
= I830_FIFO_SIZE
,
550 .max_wm
= I915_MAX_WM
,
553 .cacheline_size
= I830_FIFO_LINE_SIZE
,
557 * intel_calculate_wm - calculate watermark level
558 * @clock_in_khz: pixel clock
559 * @wm: chip FIFO params
560 * @cpp: bytes per pixel
561 * @latency_ns: memory latency for the platform
563 * Calculate the watermark level (the level at which the display plane will
564 * start fetching from memory again). Each chip has a different display
565 * FIFO size and allocation, so the caller needs to figure that out and pass
566 * in the correct intel_watermark_params structure.
568 * As the pixel clock runs, the FIFO will be drained at a rate that depends
569 * on the pixel size. When it reaches the watermark level, it'll start
570 * fetching FIFO line sized based chunks from memory until the FIFO fills
571 * past the watermark point. If the FIFO drains completely, a FIFO underrun
572 * will occur, and a display engine hang could result.
574 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
575 const struct intel_watermark_params
*wm
,
576 int fifo_size
, int cpp
,
577 unsigned long latency_ns
)
579 long entries_required
, wm_size
;
582 * Note: we need to make sure we don't overflow for various clock &
584 * clocks go from a few thousand to several hundred thousand.
585 * latency is usually a few thousand
587 entries_required
= ((clock_in_khz
/ 1000) * cpp
* latency_ns
) /
589 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
591 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
593 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
595 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
597 /* Don't promote wm_size to unsigned... */
598 if (wm_size
> (long)wm
->max_wm
)
599 wm_size
= wm
->max_wm
;
601 wm_size
= wm
->default_wm
;
604 * Bspec seems to indicate that the value shouldn't be lower than
605 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
606 * Lets go for 8 which is the burst size since certain platforms
607 * already use a hardcoded 8 (which is what the spec says should be
616 static struct intel_crtc
*single_enabled_crtc(struct drm_i915_private
*dev_priv
)
618 struct intel_crtc
*crtc
, *enabled
= NULL
;
620 for_each_intel_crtc(&dev_priv
->drm
, crtc
) {
621 if (intel_crtc_active(crtc
)) {
631 static void pineview_update_wm(struct intel_crtc
*unused_crtc
)
633 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
634 struct intel_crtc
*crtc
;
635 const struct cxsr_latency
*latency
;
639 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
644 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
645 intel_set_memory_cxsr(dev_priv
, false);
649 crtc
= single_enabled_crtc(dev_priv
);
651 const struct drm_display_mode
*adjusted_mode
=
652 &crtc
->config
->base
.adjusted_mode
;
653 const struct drm_framebuffer
*fb
=
654 crtc
->base
.primary
->state
->fb
;
655 int cpp
= fb
->format
->cpp
[0];
656 int clock
= adjusted_mode
->crtc_clock
;
659 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
660 pineview_display_wm
.fifo_size
,
661 cpp
, latency
->display_sr
);
662 reg
= I915_READ(DSPFW1
);
663 reg
&= ~DSPFW_SR_MASK
;
664 reg
|= FW_WM(wm
, SR
);
665 I915_WRITE(DSPFW1
, reg
);
666 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
669 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
670 pineview_display_wm
.fifo_size
,
671 cpp
, latency
->cursor_sr
);
672 reg
= I915_READ(DSPFW3
);
673 reg
&= ~DSPFW_CURSOR_SR_MASK
;
674 reg
|= FW_WM(wm
, CURSOR_SR
);
675 I915_WRITE(DSPFW3
, reg
);
677 /* Display HPLL off SR */
678 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
679 pineview_display_hplloff_wm
.fifo_size
,
680 cpp
, latency
->display_hpll_disable
);
681 reg
= I915_READ(DSPFW3
);
682 reg
&= ~DSPFW_HPLL_SR_MASK
;
683 reg
|= FW_WM(wm
, HPLL_SR
);
684 I915_WRITE(DSPFW3
, reg
);
686 /* cursor HPLL off SR */
687 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
688 pineview_display_hplloff_wm
.fifo_size
,
689 cpp
, latency
->cursor_hpll_disable
);
690 reg
= I915_READ(DSPFW3
);
691 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
692 reg
|= FW_WM(wm
, HPLL_CURSOR
);
693 I915_WRITE(DSPFW3
, reg
);
694 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
696 intel_set_memory_cxsr(dev_priv
, true);
698 intel_set_memory_cxsr(dev_priv
, false);
702 static bool g4x_compute_wm0(struct drm_i915_private
*dev_priv
,
704 const struct intel_watermark_params
*display
,
705 int display_latency_ns
,
706 const struct intel_watermark_params
*cursor
,
707 int cursor_latency_ns
,
711 struct intel_crtc
*crtc
;
712 const struct drm_display_mode
*adjusted_mode
;
713 const struct drm_framebuffer
*fb
;
714 int htotal
, hdisplay
, clock
, cpp
;
715 int line_time_us
, line_count
;
716 int entries
, tlb_miss
;
718 crtc
= intel_get_crtc_for_plane(dev_priv
, plane
);
719 if (!intel_crtc_active(crtc
)) {
720 *cursor_wm
= cursor
->guard_size
;
721 *plane_wm
= display
->guard_size
;
725 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
726 fb
= crtc
->base
.primary
->state
->fb
;
727 clock
= adjusted_mode
->crtc_clock
;
728 htotal
= adjusted_mode
->crtc_htotal
;
729 hdisplay
= crtc
->config
->pipe_src_w
;
730 cpp
= fb
->format
->cpp
[0];
732 /* Use the small buffer method to calculate plane watermark */
733 entries
= ((clock
* cpp
/ 1000) * display_latency_ns
) / 1000;
734 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
737 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
738 *plane_wm
= entries
+ display
->guard_size
;
739 if (*plane_wm
> (int)display
->max_wm
)
740 *plane_wm
= display
->max_wm
;
742 /* Use the large buffer method to calculate cursor watermark */
743 line_time_us
= max(htotal
* 1000 / clock
, 1);
744 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
745 entries
= line_count
* crtc
->base
.cursor
->state
->crtc_w
* cpp
;
746 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
749 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
750 *cursor_wm
= entries
+ cursor
->guard_size
;
751 if (*cursor_wm
> (int)cursor
->max_wm
)
752 *cursor_wm
= (int)cursor
->max_wm
;
758 * Check the wm result.
760 * If any calculated watermark values is larger than the maximum value that
761 * can be programmed into the associated watermark register, that watermark
764 static bool g4x_check_srwm(struct drm_i915_private
*dev_priv
,
765 int display_wm
, int cursor_wm
,
766 const struct intel_watermark_params
*display
,
767 const struct intel_watermark_params
*cursor
)
769 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
770 display_wm
, cursor_wm
);
772 if (display_wm
> display
->max_wm
) {
773 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
774 display_wm
, display
->max_wm
);
778 if (cursor_wm
> cursor
->max_wm
) {
779 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
780 cursor_wm
, cursor
->max_wm
);
784 if (!(display_wm
|| cursor_wm
)) {
785 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
792 static bool g4x_compute_srwm(struct drm_i915_private
*dev_priv
,
795 const struct intel_watermark_params
*display
,
796 const struct intel_watermark_params
*cursor
,
797 int *display_wm
, int *cursor_wm
)
799 struct intel_crtc
*crtc
;
800 const struct drm_display_mode
*adjusted_mode
;
801 const struct drm_framebuffer
*fb
;
802 int hdisplay
, htotal
, cpp
, clock
;
803 unsigned long line_time_us
;
804 int line_count
, line_size
;
809 *display_wm
= *cursor_wm
= 0;
813 crtc
= intel_get_crtc_for_plane(dev_priv
, plane
);
814 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
815 fb
= crtc
->base
.primary
->state
->fb
;
816 clock
= adjusted_mode
->crtc_clock
;
817 htotal
= adjusted_mode
->crtc_htotal
;
818 hdisplay
= crtc
->config
->pipe_src_w
;
819 cpp
= fb
->format
->cpp
[0];
821 line_time_us
= max(htotal
* 1000 / clock
, 1);
822 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
823 line_size
= hdisplay
* cpp
;
825 /* Use the minimum of the small and large buffer method for primary */
826 small
= ((clock
* cpp
/ 1000) * latency_ns
) / 1000;
827 large
= line_count
* line_size
;
829 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
830 *display_wm
= entries
+ display
->guard_size
;
832 /* calculate the self-refresh watermark for display cursor */
833 entries
= line_count
* cpp
* crtc
->base
.cursor
->state
->crtc_w
;
834 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
835 *cursor_wm
= entries
+ cursor
->guard_size
;
837 return g4x_check_srwm(dev_priv
,
838 *display_wm
, *cursor_wm
,
842 #define FW_WM_VLV(value, plane) \
843 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
845 static void vlv_write_wm_values(struct intel_crtc
*crtc
,
846 const struct vlv_wm_values
*wm
)
848 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
849 enum pipe pipe
= crtc
->pipe
;
851 I915_WRITE(VLV_DDL(pipe
),
852 (wm
->ddl
[pipe
].cursor
<< DDL_CURSOR_SHIFT
) |
853 (wm
->ddl
[pipe
].sprite
[1] << DDL_SPRITE_SHIFT(1)) |
854 (wm
->ddl
[pipe
].sprite
[0] << DDL_SPRITE_SHIFT(0)) |
855 (wm
->ddl
[pipe
].primary
<< DDL_PLANE_SHIFT
));
858 FW_WM(wm
->sr
.plane
, SR
) |
859 FW_WM(wm
->pipe
[PIPE_B
].cursor
, CURSORB
) |
860 FW_WM_VLV(wm
->pipe
[PIPE_B
].primary
, PLANEB
) |
861 FW_WM_VLV(wm
->pipe
[PIPE_A
].primary
, PLANEA
));
863 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[1], SPRITEB
) |
864 FW_WM(wm
->pipe
[PIPE_A
].cursor
, CURSORA
) |
865 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[0], SPRITEA
));
867 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
869 if (IS_CHERRYVIEW(dev_priv
)) {
870 I915_WRITE(DSPFW7_CHV
,
871 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
872 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
873 I915_WRITE(DSPFW8_CHV
,
874 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[1], SPRITEF
) |
875 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[0], SPRITEE
));
876 I915_WRITE(DSPFW9_CHV
,
877 FW_WM_VLV(wm
->pipe
[PIPE_C
].primary
, PLANEC
) |
878 FW_WM(wm
->pipe
[PIPE_C
].cursor
, CURSORC
));
880 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
881 FW_WM(wm
->pipe
[PIPE_C
].sprite
[1] >> 8, SPRITEF_HI
) |
882 FW_WM(wm
->pipe
[PIPE_C
].sprite
[0] >> 8, SPRITEE_HI
) |
883 FW_WM(wm
->pipe
[PIPE_C
].primary
>> 8, PLANEC_HI
) |
884 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
885 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
886 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
887 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
888 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
889 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
892 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
893 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
895 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
896 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
897 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
898 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
899 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
900 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
901 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
904 /* zero (unused) WM1 watermarks */
905 I915_WRITE(DSPFW4
, 0);
906 I915_WRITE(DSPFW5
, 0);
907 I915_WRITE(DSPFW6
, 0);
908 I915_WRITE(DSPHOWM1
, 0);
910 POSTING_READ(DSPFW1
);
918 VLV_WM_LEVEL_DDR_DVFS
,
921 /* latency must be in 0.1us units. */
922 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
923 unsigned int pipe_htotal
,
924 unsigned int horiz_pixels
,
926 unsigned int latency
)
930 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
931 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
932 ret
= DIV_ROUND_UP(ret
, 64);
937 static void vlv_setup_wm_latency(struct drm_i915_private
*dev_priv
)
939 /* all latencies in usec */
940 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
942 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
944 if (IS_CHERRYVIEW(dev_priv
)) {
945 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
946 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
948 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
952 static uint16_t vlv_compute_wm_level(struct intel_plane
*plane
,
953 struct intel_crtc
*crtc
,
954 const struct intel_plane_state
*state
,
957 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
958 int clock
, htotal
, cpp
, width
, wm
;
960 if (dev_priv
->wm
.pri_latency
[level
] == 0)
963 if (!state
->base
.visible
)
966 cpp
= state
->base
.fb
->format
->cpp
[0];
967 clock
= crtc
->config
->base
.adjusted_mode
.crtc_clock
;
968 htotal
= crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
969 width
= crtc
->config
->pipe_src_w
;
970 if (WARN_ON(htotal
== 0))
973 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
975 * FIXME the formula gives values that are
976 * too big for the cursor FIFO, and hence we
977 * would never be able to use cursors. For
978 * now just hardcode the watermark.
982 wm
= vlv_wm_method2(clock
, htotal
, width
, cpp
,
983 dev_priv
->wm
.pri_latency
[level
] * 10);
986 return min_t(int, wm
, USHRT_MAX
);
989 static void vlv_compute_fifo(struct intel_crtc
*crtc
)
991 struct drm_device
*dev
= crtc
->base
.dev
;
992 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
993 struct intel_plane
*plane
;
994 unsigned int total_rate
= 0;
995 const int fifo_size
= 512 - 1;
996 int fifo_extra
, fifo_left
= fifo_size
;
998 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
999 struct intel_plane_state
*state
=
1000 to_intel_plane_state(plane
->base
.state
);
1002 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
1005 if (state
->base
.visible
) {
1006 wm_state
->num_active_planes
++;
1007 total_rate
+= state
->base
.fb
->format
->cpp
[0];
1011 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1012 struct intel_plane_state
*state
=
1013 to_intel_plane_state(plane
->base
.state
);
1016 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1017 plane
->wm
.fifo_size
= 63;
1021 if (!state
->base
.visible
) {
1022 plane
->wm
.fifo_size
= 0;
1026 rate
= state
->base
.fb
->format
->cpp
[0];
1027 plane
->wm
.fifo_size
= fifo_size
* rate
/ total_rate
;
1028 fifo_left
-= plane
->wm
.fifo_size
;
1031 fifo_extra
= DIV_ROUND_UP(fifo_left
, wm_state
->num_active_planes
?: 1);
1033 /* spread the remainder evenly */
1034 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1040 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
1043 /* give it all to the first plane if none are active */
1044 if (plane
->wm
.fifo_size
== 0 &&
1045 wm_state
->num_active_planes
)
1048 plane_extra
= min(fifo_extra
, fifo_left
);
1049 plane
->wm
.fifo_size
+= plane_extra
;
1050 fifo_left
-= plane_extra
;
1053 WARN_ON(fifo_left
!= 0);
1056 static void vlv_invert_wms(struct intel_crtc
*crtc
)
1058 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1061 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1062 struct drm_device
*dev
= crtc
->base
.dev
;
1063 const int sr_fifo_size
=
1064 INTEL_INFO(to_i915(dev
))->num_pipes
* 512 - 1;
1065 struct intel_plane
*plane
;
1067 wm_state
->sr
[level
].plane
= sr_fifo_size
- wm_state
->sr
[level
].plane
;
1068 wm_state
->sr
[level
].cursor
= 63 - wm_state
->sr
[level
].cursor
;
1070 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1071 switch (plane
->base
.type
) {
1073 case DRM_PLANE_TYPE_CURSOR
:
1074 wm_state
->wm
[level
].cursor
= plane
->wm
.fifo_size
-
1075 wm_state
->wm
[level
].cursor
;
1077 case DRM_PLANE_TYPE_PRIMARY
:
1078 wm_state
->wm
[level
].primary
= plane
->wm
.fifo_size
-
1079 wm_state
->wm
[level
].primary
;
1081 case DRM_PLANE_TYPE_OVERLAY
:
1082 sprite
= plane
->plane
;
1083 wm_state
->wm
[level
].sprite
[sprite
] = plane
->wm
.fifo_size
-
1084 wm_state
->wm
[level
].sprite
[sprite
];
1091 static void vlv_compute_wm(struct intel_crtc
*crtc
)
1093 struct drm_device
*dev
= crtc
->base
.dev
;
1094 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1095 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1096 struct intel_plane
*plane
;
1097 int sr_fifo_size
= INTEL_INFO(dev_priv
)->num_pipes
* 512 - 1;
1100 memset(wm_state
, 0, sizeof(*wm_state
));
1102 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& crtc
->wm
.cxsr_allowed
;
1103 wm_state
->num_levels
= dev_priv
->wm
.max_level
+ 1;
1105 wm_state
->num_active_planes
= 0;
1107 vlv_compute_fifo(crtc
);
1109 if (wm_state
->num_active_planes
!= 1)
1110 wm_state
->cxsr
= false;
1112 if (wm_state
->cxsr
) {
1113 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1114 wm_state
->sr
[level
].plane
= sr_fifo_size
;
1115 wm_state
->sr
[level
].cursor
= 63;
1119 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1120 struct intel_plane_state
*state
=
1121 to_intel_plane_state(plane
->base
.state
);
1123 if (!state
->base
.visible
)
1126 /* normal watermarks */
1127 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1128 int wm
= vlv_compute_wm_level(plane
, crtc
, state
, level
);
1129 int max_wm
= plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
? 63 : 511;
1132 if (WARN_ON(level
== 0 && wm
> max_wm
))
1135 if (wm
> plane
->wm
.fifo_size
)
1138 switch (plane
->base
.type
) {
1140 case DRM_PLANE_TYPE_CURSOR
:
1141 wm_state
->wm
[level
].cursor
= wm
;
1143 case DRM_PLANE_TYPE_PRIMARY
:
1144 wm_state
->wm
[level
].primary
= wm
;
1146 case DRM_PLANE_TYPE_OVERLAY
:
1147 sprite
= plane
->plane
;
1148 wm_state
->wm
[level
].sprite
[sprite
] = wm
;
1153 wm_state
->num_levels
= level
;
1155 if (!wm_state
->cxsr
)
1158 /* maxfifo watermarks */
1159 switch (plane
->base
.type
) {
1161 case DRM_PLANE_TYPE_CURSOR
:
1162 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1163 wm_state
->sr
[level
].cursor
=
1164 wm_state
->wm
[level
].cursor
;
1166 case DRM_PLANE_TYPE_PRIMARY
:
1167 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1168 wm_state
->sr
[level
].plane
=
1169 min(wm_state
->sr
[level
].plane
,
1170 wm_state
->wm
[level
].primary
);
1172 case DRM_PLANE_TYPE_OVERLAY
:
1173 sprite
= plane
->plane
;
1174 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1175 wm_state
->sr
[level
].plane
=
1176 min(wm_state
->sr
[level
].plane
,
1177 wm_state
->wm
[level
].sprite
[sprite
]);
1182 /* clear any (partially) filled invalid levels */
1183 for (level
= wm_state
->num_levels
; level
< dev_priv
->wm
.max_level
+ 1; level
++) {
1184 memset(&wm_state
->wm
[level
], 0, sizeof(wm_state
->wm
[level
]));
1185 memset(&wm_state
->sr
[level
], 0, sizeof(wm_state
->sr
[level
]));
1188 vlv_invert_wms(crtc
);
1191 #define VLV_FIFO(plane, value) \
1192 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1194 static void vlv_pipe_set_fifo_size(struct intel_crtc
*crtc
)
1196 struct drm_device
*dev
= crtc
->base
.dev
;
1197 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1198 struct intel_plane
*plane
;
1199 int sprite0_start
= 0, sprite1_start
= 0, fifo_size
= 0;
1201 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1202 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1203 WARN_ON(plane
->wm
.fifo_size
!= 63);
1207 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
1208 sprite0_start
= plane
->wm
.fifo_size
;
1209 else if (plane
->plane
== 0)
1210 sprite1_start
= sprite0_start
+ plane
->wm
.fifo_size
;
1212 fifo_size
= sprite1_start
+ plane
->wm
.fifo_size
;
1215 WARN_ON(fifo_size
!= 512 - 1);
1217 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1218 pipe_name(crtc
->pipe
), sprite0_start
,
1219 sprite1_start
, fifo_size
);
1221 switch (crtc
->pipe
) {
1222 uint32_t dsparb
, dsparb2
, dsparb3
;
1224 dsparb
= I915_READ(DSPARB
);
1225 dsparb2
= I915_READ(DSPARB2
);
1227 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1228 VLV_FIFO(SPRITEB
, 0xff));
1229 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1230 VLV_FIFO(SPRITEB
, sprite1_start
));
1232 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1233 VLV_FIFO(SPRITEB_HI
, 0x1));
1234 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1235 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1237 I915_WRITE(DSPARB
, dsparb
);
1238 I915_WRITE(DSPARB2
, dsparb2
);
1241 dsparb
= I915_READ(DSPARB
);
1242 dsparb2
= I915_READ(DSPARB2
);
1244 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1245 VLV_FIFO(SPRITED
, 0xff));
1246 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1247 VLV_FIFO(SPRITED
, sprite1_start
));
1249 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1250 VLV_FIFO(SPRITED_HI
, 0xff));
1251 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1252 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1254 I915_WRITE(DSPARB
, dsparb
);
1255 I915_WRITE(DSPARB2
, dsparb2
);
1258 dsparb3
= I915_READ(DSPARB3
);
1259 dsparb2
= I915_READ(DSPARB2
);
1261 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
1262 VLV_FIFO(SPRITEF
, 0xff));
1263 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
1264 VLV_FIFO(SPRITEF
, sprite1_start
));
1266 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
1267 VLV_FIFO(SPRITEF_HI
, 0xff));
1268 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
1269 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
1271 I915_WRITE(DSPARB3
, dsparb3
);
1272 I915_WRITE(DSPARB2
, dsparb2
);
1281 static void vlv_merge_wm(struct drm_device
*dev
,
1282 struct vlv_wm_values
*wm
)
1284 struct intel_crtc
*crtc
;
1285 int num_active_crtcs
= 0;
1287 wm
->level
= to_i915(dev
)->wm
.max_level
;
1290 for_each_intel_crtc(dev
, crtc
) {
1291 const struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1296 if (!wm_state
->cxsr
)
1300 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
1303 if (num_active_crtcs
!= 1)
1306 if (num_active_crtcs
> 1)
1307 wm
->level
= VLV_WM_LEVEL_PM2
;
1309 for_each_intel_crtc(dev
, crtc
) {
1310 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1311 enum pipe pipe
= crtc
->pipe
;
1316 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
1318 wm
->sr
= wm_state
->sr
[wm
->level
];
1320 wm
->ddl
[pipe
].primary
= DDL_PRECISION_HIGH
| 2;
1321 wm
->ddl
[pipe
].sprite
[0] = DDL_PRECISION_HIGH
| 2;
1322 wm
->ddl
[pipe
].sprite
[1] = DDL_PRECISION_HIGH
| 2;
1323 wm
->ddl
[pipe
].cursor
= DDL_PRECISION_HIGH
| 2;
1327 static void vlv_update_wm(struct intel_crtc
*crtc
)
1329 struct drm_device
*dev
= crtc
->base
.dev
;
1330 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1331 enum pipe pipe
= crtc
->pipe
;
1332 struct vlv_wm_values wm
= {};
1334 vlv_compute_wm(crtc
);
1335 vlv_merge_wm(dev
, &wm
);
1337 if (memcmp(&dev_priv
->wm
.vlv
, &wm
, sizeof(wm
)) == 0) {
1338 /* FIXME should be part of crtc atomic commit */
1339 vlv_pipe_set_fifo_size(crtc
);
1343 if (wm
.level
< VLV_WM_LEVEL_DDR_DVFS
&&
1344 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_DDR_DVFS
)
1345 chv_set_memory_dvfs(dev_priv
, false);
1347 if (wm
.level
< VLV_WM_LEVEL_PM5
&&
1348 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_PM5
)
1349 chv_set_memory_pm5(dev_priv
, false);
1351 if (!wm
.cxsr
&& dev_priv
->wm
.vlv
.cxsr
)
1352 intel_set_memory_cxsr(dev_priv
, false);
1354 /* FIXME should be part of crtc atomic commit */
1355 vlv_pipe_set_fifo_size(crtc
);
1357 vlv_write_wm_values(crtc
, &wm
);
1359 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1360 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1361 pipe_name(pipe
), wm
.pipe
[pipe
].primary
, wm
.pipe
[pipe
].cursor
,
1362 wm
.pipe
[pipe
].sprite
[0], wm
.pipe
[pipe
].sprite
[1],
1363 wm
.sr
.plane
, wm
.sr
.cursor
, wm
.level
, wm
.cxsr
);
1365 if (wm
.cxsr
&& !dev_priv
->wm
.vlv
.cxsr
)
1366 intel_set_memory_cxsr(dev_priv
, true);
1368 if (wm
.level
>= VLV_WM_LEVEL_PM5
&&
1369 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_PM5
)
1370 chv_set_memory_pm5(dev_priv
, true);
1372 if (wm
.level
>= VLV_WM_LEVEL_DDR_DVFS
&&
1373 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_DDR_DVFS
)
1374 chv_set_memory_dvfs(dev_priv
, true);
1376 dev_priv
->wm
.vlv
= wm
;
1379 #define single_plane_enabled(mask) is_power_of_2(mask)
1381 static void g4x_update_wm(struct intel_crtc
*crtc
)
1383 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
1384 static const int sr_latency_ns
= 12000;
1385 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1386 int plane_sr
, cursor_sr
;
1387 unsigned int enabled
= 0;
1390 if (g4x_compute_wm0(dev_priv
, PIPE_A
,
1391 &g4x_wm_info
, pessimal_latency_ns
,
1392 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1393 &planea_wm
, &cursora_wm
))
1394 enabled
|= 1 << PIPE_A
;
1396 if (g4x_compute_wm0(dev_priv
, PIPE_B
,
1397 &g4x_wm_info
, pessimal_latency_ns
,
1398 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1399 &planeb_wm
, &cursorb_wm
))
1400 enabled
|= 1 << PIPE_B
;
1402 if (single_plane_enabled(enabled
) &&
1403 g4x_compute_srwm(dev_priv
, ffs(enabled
) - 1,
1406 &g4x_cursor_wm_info
,
1407 &plane_sr
, &cursor_sr
)) {
1408 cxsr_enabled
= true;
1410 cxsr_enabled
= false;
1411 intel_set_memory_cxsr(dev_priv
, false);
1412 plane_sr
= cursor_sr
= 0;
1415 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1416 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1417 planea_wm
, cursora_wm
,
1418 planeb_wm
, cursorb_wm
,
1419 plane_sr
, cursor_sr
);
1422 FW_WM(plane_sr
, SR
) |
1423 FW_WM(cursorb_wm
, CURSORB
) |
1424 FW_WM(planeb_wm
, PLANEB
) |
1425 FW_WM(planea_wm
, PLANEA
));
1427 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1428 FW_WM(cursora_wm
, CURSORA
));
1429 /* HPLL off in SR has some issues on G4x... disable it */
1431 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1432 FW_WM(cursor_sr
, CURSOR_SR
));
1435 intel_set_memory_cxsr(dev_priv
, true);
1438 static void i965_update_wm(struct intel_crtc
*unused_crtc
)
1440 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
1441 struct intel_crtc
*crtc
;
1446 /* Calc sr entries for one plane configs */
1447 crtc
= single_enabled_crtc(dev_priv
);
1449 /* self-refresh has much higher latency */
1450 static const int sr_latency_ns
= 12000;
1451 const struct drm_display_mode
*adjusted_mode
=
1452 &crtc
->config
->base
.adjusted_mode
;
1453 const struct drm_framebuffer
*fb
=
1454 crtc
->base
.primary
->state
->fb
;
1455 int clock
= adjusted_mode
->crtc_clock
;
1456 int htotal
= adjusted_mode
->crtc_htotal
;
1457 int hdisplay
= crtc
->config
->pipe_src_w
;
1458 int cpp
= fb
->format
->cpp
[0];
1459 unsigned long line_time_us
;
1462 line_time_us
= max(htotal
* 1000 / clock
, 1);
1464 /* Use ns/us then divide to preserve precision */
1465 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1467 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1468 srwm
= I965_FIFO_SIZE
- entries
;
1472 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1475 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1476 cpp
* crtc
->base
.cursor
->state
->crtc_w
;
1477 entries
= DIV_ROUND_UP(entries
,
1478 i965_cursor_wm_info
.cacheline_size
);
1479 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1480 (entries
+ i965_cursor_wm_info
.guard_size
);
1482 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1483 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1485 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1486 "cursor %d\n", srwm
, cursor_sr
);
1488 cxsr_enabled
= true;
1490 cxsr_enabled
= false;
1491 /* Turn off self refresh if both pipes are enabled */
1492 intel_set_memory_cxsr(dev_priv
, false);
1495 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1498 /* 965 has limitations... */
1499 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
1503 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
1504 FW_WM(8, PLANEC_OLD
));
1505 /* update cursor SR watermark */
1506 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
1509 intel_set_memory_cxsr(dev_priv
, true);
1514 static void i9xx_update_wm(struct intel_crtc
*unused_crtc
)
1516 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
1517 const struct intel_watermark_params
*wm_info
;
1522 int planea_wm
, planeb_wm
;
1523 struct intel_crtc
*crtc
, *enabled
= NULL
;
1525 if (IS_I945GM(dev_priv
))
1526 wm_info
= &i945_wm_info
;
1527 else if (!IS_GEN2(dev_priv
))
1528 wm_info
= &i915_wm_info
;
1530 wm_info
= &i830_a_wm_info
;
1532 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 0);
1533 crtc
= intel_get_crtc_for_plane(dev_priv
, 0);
1534 if (intel_crtc_active(crtc
)) {
1535 const struct drm_display_mode
*adjusted_mode
=
1536 &crtc
->config
->base
.adjusted_mode
;
1537 const struct drm_framebuffer
*fb
=
1538 crtc
->base
.primary
->state
->fb
;
1541 if (IS_GEN2(dev_priv
))
1544 cpp
= fb
->format
->cpp
[0];
1546 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1547 wm_info
, fifo_size
, cpp
,
1548 pessimal_latency_ns
);
1551 planea_wm
= fifo_size
- wm_info
->guard_size
;
1552 if (planea_wm
> (long)wm_info
->max_wm
)
1553 planea_wm
= wm_info
->max_wm
;
1556 if (IS_GEN2(dev_priv
))
1557 wm_info
= &i830_bc_wm_info
;
1559 fifo_size
= dev_priv
->display
.get_fifo_size(dev_priv
, 1);
1560 crtc
= intel_get_crtc_for_plane(dev_priv
, 1);
1561 if (intel_crtc_active(crtc
)) {
1562 const struct drm_display_mode
*adjusted_mode
=
1563 &crtc
->config
->base
.adjusted_mode
;
1564 const struct drm_framebuffer
*fb
=
1565 crtc
->base
.primary
->state
->fb
;
1568 if (IS_GEN2(dev_priv
))
1571 cpp
= fb
->format
->cpp
[0];
1573 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1574 wm_info
, fifo_size
, cpp
,
1575 pessimal_latency_ns
);
1576 if (enabled
== NULL
)
1581 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1582 if (planeb_wm
> (long)wm_info
->max_wm
)
1583 planeb_wm
= wm_info
->max_wm
;
1586 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1588 if (IS_I915GM(dev_priv
) && enabled
) {
1589 struct drm_i915_gem_object
*obj
;
1591 obj
= intel_fb_obj(enabled
->base
.primary
->state
->fb
);
1593 /* self-refresh seems busted with untiled */
1594 if (!i915_gem_object_is_tiled(obj
))
1599 * Overlay gets an aggressive default since video jitter is bad.
1603 /* Play safe and disable self-refresh before adjusting watermarks. */
1604 intel_set_memory_cxsr(dev_priv
, false);
1606 /* Calc sr entries for one plane configs */
1607 if (HAS_FW_BLC(dev_priv
) && enabled
) {
1608 /* self-refresh has much higher latency */
1609 static const int sr_latency_ns
= 6000;
1610 const struct drm_display_mode
*adjusted_mode
=
1611 &enabled
->config
->base
.adjusted_mode
;
1612 const struct drm_framebuffer
*fb
=
1613 enabled
->base
.primary
->state
->fb
;
1614 int clock
= adjusted_mode
->crtc_clock
;
1615 int htotal
= adjusted_mode
->crtc_htotal
;
1616 int hdisplay
= enabled
->config
->pipe_src_w
;
1618 unsigned long line_time_us
;
1621 if (IS_I915GM(dev_priv
) || IS_I945GM(dev_priv
))
1624 cpp
= fb
->format
->cpp
[0];
1626 line_time_us
= max(htotal
* 1000 / clock
, 1);
1628 /* Use ns/us then divide to preserve precision */
1629 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1631 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1632 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1633 srwm
= wm_info
->fifo_size
- entries
;
1637 if (IS_I945G(dev_priv
) || IS_I945GM(dev_priv
))
1638 I915_WRITE(FW_BLC_SELF
,
1639 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1641 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1644 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1645 planea_wm
, planeb_wm
, cwm
, srwm
);
1647 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1648 fwater_hi
= (cwm
& 0x1f);
1650 /* Set request length to 8 cachelines per fetch */
1651 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1652 fwater_hi
= fwater_hi
| (1 << 8);
1654 I915_WRITE(FW_BLC
, fwater_lo
);
1655 I915_WRITE(FW_BLC2
, fwater_hi
);
1658 intel_set_memory_cxsr(dev_priv
, true);
1661 static void i845_update_wm(struct intel_crtc
*unused_crtc
)
1663 struct drm_i915_private
*dev_priv
= to_i915(unused_crtc
->base
.dev
);
1664 struct intel_crtc
*crtc
;
1665 const struct drm_display_mode
*adjusted_mode
;
1669 crtc
= single_enabled_crtc(dev_priv
);
1673 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
1674 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1676 dev_priv
->display
.get_fifo_size(dev_priv
, 0),
1677 4, pessimal_latency_ns
);
1678 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1679 fwater_lo
|= (3<<8) | planea_wm
;
1681 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1683 I915_WRITE(FW_BLC
, fwater_lo
);
1686 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
1688 uint32_t pixel_rate
;
1690 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
1692 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1693 * adjust the pixel_rate here. */
1695 if (pipe_config
->pch_pfit
.enabled
) {
1696 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1697 uint32_t pfit_size
= pipe_config
->pch_pfit
.size
;
1699 pipe_w
= pipe_config
->pipe_src_w
;
1700 pipe_h
= pipe_config
->pipe_src_h
;
1702 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1703 pfit_h
= pfit_size
& 0xFFFF;
1704 if (pipe_w
< pfit_w
)
1706 if (pipe_h
< pfit_h
)
1709 if (WARN_ON(!pfit_w
|| !pfit_h
))
1712 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1719 /* latency must be in 0.1us units. */
1720 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t cpp
, uint32_t latency
)
1724 if (WARN(latency
== 0, "Latency value missing\n"))
1727 ret
= (uint64_t) pixel_rate
* cpp
* latency
;
1728 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1733 /* latency must be in 0.1us units. */
1734 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1735 uint32_t horiz_pixels
, uint8_t cpp
,
1740 if (WARN(latency
== 0, "Latency value missing\n"))
1742 if (WARN_ON(!pipe_htotal
))
1745 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1746 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
1747 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1751 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1755 * Neither of these should be possible since this function shouldn't be
1756 * called if the CRTC is off or the plane is invisible. But let's be
1757 * extra paranoid to avoid a potential divide-by-zero if we screw up
1758 * elsewhere in the driver.
1762 if (WARN_ON(!horiz_pixels
))
1765 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* cpp
) + 2;
1768 struct ilk_wm_maximums
{
1776 * For both WM_PIPE and WM_LP.
1777 * mem_value must be in 0.1us units.
1779 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
1780 const struct intel_plane_state
*pstate
,
1784 uint32_t method1
, method2
;
1787 if (!cstate
->base
.active
|| !pstate
->base
.visible
)
1790 cpp
= pstate
->base
.fb
->format
->cpp
[0];
1792 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), cpp
, mem_value
);
1797 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1798 cstate
->base
.adjusted_mode
.crtc_htotal
,
1799 drm_rect_width(&pstate
->base
.dst
),
1802 return min(method1
, method2
);
1806 * For both WM_PIPE and WM_LP.
1807 * mem_value must be in 0.1us units.
1809 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
1810 const struct intel_plane_state
*pstate
,
1813 uint32_t method1
, method2
;
1816 if (!cstate
->base
.active
|| !pstate
->base
.visible
)
1819 cpp
= pstate
->base
.fb
->format
->cpp
[0];
1821 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), cpp
, mem_value
);
1822 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1823 cstate
->base
.adjusted_mode
.crtc_htotal
,
1824 drm_rect_width(&pstate
->base
.dst
),
1826 return min(method1
, method2
);
1830 * For both WM_PIPE and WM_LP.
1831 * mem_value must be in 0.1us units.
1833 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
1834 const struct intel_plane_state
*pstate
,
1838 * We treat the cursor plane as always-on for the purposes of watermark
1839 * calculation. Until we have two-stage watermark programming merged,
1840 * this is necessary to avoid flickering.
1843 int width
= pstate
->base
.visible
? pstate
->base
.crtc_w
: 64;
1845 if (!cstate
->base
.active
)
1848 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1849 cstate
->base
.adjusted_mode
.crtc_htotal
,
1850 width
, cpp
, mem_value
);
1853 /* Only for WM_LP. */
1854 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
1855 const struct intel_plane_state
*pstate
,
1860 if (!cstate
->base
.active
|| !pstate
->base
.visible
)
1863 cpp
= pstate
->base
.fb
->format
->cpp
[0];
1865 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->base
.dst
), cpp
);
1869 ilk_display_fifo_size(const struct drm_i915_private
*dev_priv
)
1871 if (INTEL_GEN(dev_priv
) >= 8)
1873 else if (INTEL_GEN(dev_priv
) >= 7)
1880 ilk_plane_wm_reg_max(const struct drm_i915_private
*dev_priv
,
1881 int level
, bool is_sprite
)
1883 if (INTEL_GEN(dev_priv
) >= 8)
1884 /* BDW primary/sprite plane watermarks */
1885 return level
== 0 ? 255 : 2047;
1886 else if (INTEL_GEN(dev_priv
) >= 7)
1887 /* IVB/HSW primary/sprite plane watermarks */
1888 return level
== 0 ? 127 : 1023;
1889 else if (!is_sprite
)
1890 /* ILK/SNB primary plane watermarks */
1891 return level
== 0 ? 127 : 511;
1893 /* ILK/SNB sprite plane watermarks */
1894 return level
== 0 ? 63 : 255;
1898 ilk_cursor_wm_reg_max(const struct drm_i915_private
*dev_priv
, int level
)
1900 if (INTEL_GEN(dev_priv
) >= 7)
1901 return level
== 0 ? 63 : 255;
1903 return level
== 0 ? 31 : 63;
1906 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private
*dev_priv
)
1908 if (INTEL_GEN(dev_priv
) >= 8)
1914 /* Calculate the maximum primary/sprite plane watermark */
1915 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1917 const struct intel_wm_config
*config
,
1918 enum intel_ddb_partitioning ddb_partitioning
,
1921 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1922 unsigned int fifo_size
= ilk_display_fifo_size(dev_priv
);
1924 /* if sprites aren't enabled, sprites get nothing */
1925 if (is_sprite
&& !config
->sprites_enabled
)
1928 /* HSW allows LP1+ watermarks even with multiple pipes */
1929 if (level
== 0 || config
->num_pipes_active
> 1) {
1930 fifo_size
/= INTEL_INFO(dev_priv
)->num_pipes
;
1933 * For some reason the non self refresh
1934 * FIFO size is only half of the self
1935 * refresh FIFO size on ILK/SNB.
1937 if (INTEL_GEN(dev_priv
) <= 6)
1941 if (config
->sprites_enabled
) {
1942 /* level 0 is always calculated with 1:1 split */
1943 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1952 /* clamp to max that the registers can hold */
1953 return min(fifo_size
, ilk_plane_wm_reg_max(dev_priv
, level
, is_sprite
));
1956 /* Calculate the maximum cursor plane watermark */
1957 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1959 const struct intel_wm_config
*config
)
1961 /* HSW LP1+ watermarks w/ multiple pipes */
1962 if (level
> 0 && config
->num_pipes_active
> 1)
1965 /* otherwise just report max that registers can hold */
1966 return ilk_cursor_wm_reg_max(to_i915(dev
), level
);
1969 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1971 const struct intel_wm_config
*config
,
1972 enum intel_ddb_partitioning ddb_partitioning
,
1973 struct ilk_wm_maximums
*max
)
1975 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1976 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1977 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1978 max
->fbc
= ilk_fbc_wm_reg_max(to_i915(dev
));
1981 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private
*dev_priv
,
1983 struct ilk_wm_maximums
*max
)
1985 max
->pri
= ilk_plane_wm_reg_max(dev_priv
, level
, false);
1986 max
->spr
= ilk_plane_wm_reg_max(dev_priv
, level
, true);
1987 max
->cur
= ilk_cursor_wm_reg_max(dev_priv
, level
);
1988 max
->fbc
= ilk_fbc_wm_reg_max(dev_priv
);
1991 static bool ilk_validate_wm_level(int level
,
1992 const struct ilk_wm_maximums
*max
,
1993 struct intel_wm_level
*result
)
1997 /* already determined to be invalid? */
1998 if (!result
->enable
)
2001 result
->enable
= result
->pri_val
<= max
->pri
&&
2002 result
->spr_val
<= max
->spr
&&
2003 result
->cur_val
<= max
->cur
;
2005 ret
= result
->enable
;
2008 * HACK until we can pre-compute everything,
2009 * and thus fail gracefully if LP0 watermarks
2012 if (level
== 0 && !result
->enable
) {
2013 if (result
->pri_val
> max
->pri
)
2014 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2015 level
, result
->pri_val
, max
->pri
);
2016 if (result
->spr_val
> max
->spr
)
2017 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2018 level
, result
->spr_val
, max
->spr
);
2019 if (result
->cur_val
> max
->cur
)
2020 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2021 level
, result
->cur_val
, max
->cur
);
2023 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
2024 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
2025 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
2026 result
->enable
= true;
2032 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
2033 const struct intel_crtc
*intel_crtc
,
2035 struct intel_crtc_state
*cstate
,
2036 struct intel_plane_state
*pristate
,
2037 struct intel_plane_state
*sprstate
,
2038 struct intel_plane_state
*curstate
,
2039 struct intel_wm_level
*result
)
2041 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
2042 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
2043 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
2045 /* WM1+ latency values stored in 0.5us units */
2053 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
2054 pri_latency
, level
);
2055 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
2059 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
2062 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
2064 result
->enable
= true;
2068 hsw_compute_linetime_wm(const struct intel_crtc_state
*cstate
)
2070 const struct intel_atomic_state
*intel_state
=
2071 to_intel_atomic_state(cstate
->base
.state
);
2072 const struct drm_display_mode
*adjusted_mode
=
2073 &cstate
->base
.adjusted_mode
;
2074 u32 linetime
, ips_linetime
;
2076 if (!cstate
->base
.active
)
2078 if (WARN_ON(adjusted_mode
->crtc_clock
== 0))
2080 if (WARN_ON(intel_state
->cdclk
== 0))
2083 /* The WM are computed with base on how long it takes to fill a single
2084 * row at the given clock rate, multiplied by 8.
2086 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2087 adjusted_mode
->crtc_clock
);
2088 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2089 intel_state
->cdclk
);
2091 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2092 PIPE_WM_LINETIME_TIME(linetime
);
2095 static void intel_read_wm_latency(struct drm_i915_private
*dev_priv
,
2098 if (IS_GEN9(dev_priv
)) {
2101 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2103 /* read the first set of memory latencies[0:3] */
2104 val
= 0; /* data0 to be programmed to 0 for first set */
2105 mutex_lock(&dev_priv
->rps
.hw_lock
);
2106 ret
= sandybridge_pcode_read(dev_priv
,
2107 GEN9_PCODE_READ_MEM_LATENCY
,
2109 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2112 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2116 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2117 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2118 GEN9_MEM_LATENCY_LEVEL_MASK
;
2119 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2120 GEN9_MEM_LATENCY_LEVEL_MASK
;
2121 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2122 GEN9_MEM_LATENCY_LEVEL_MASK
;
2124 /* read the second set of memory latencies[4:7] */
2125 val
= 1; /* data0 to be programmed to 1 for second set */
2126 mutex_lock(&dev_priv
->rps
.hw_lock
);
2127 ret
= sandybridge_pcode_read(dev_priv
,
2128 GEN9_PCODE_READ_MEM_LATENCY
,
2130 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2132 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2136 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2137 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2138 GEN9_MEM_LATENCY_LEVEL_MASK
;
2139 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2140 GEN9_MEM_LATENCY_LEVEL_MASK
;
2141 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2142 GEN9_MEM_LATENCY_LEVEL_MASK
;
2145 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2146 * need to be disabled. We make sure to sanitize the values out
2147 * of the punit to satisfy this requirement.
2149 for (level
= 1; level
<= max_level
; level
++) {
2150 if (wm
[level
] == 0) {
2151 for (i
= level
+ 1; i
<= max_level
; i
++)
2158 * WaWmMemoryReadLatency:skl
2160 * punit doesn't take into account the read latency so we need
2161 * to add 2us to the various latency levels we retrieve from the
2162 * punit when level 0 response data us 0us.
2166 for (level
= 1; level
<= max_level
; level
++) {
2173 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2174 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2176 wm
[0] = (sskpd
>> 56) & 0xFF;
2178 wm
[0] = sskpd
& 0xF;
2179 wm
[1] = (sskpd
>> 4) & 0xFF;
2180 wm
[2] = (sskpd
>> 12) & 0xFF;
2181 wm
[3] = (sskpd
>> 20) & 0x1FF;
2182 wm
[4] = (sskpd
>> 32) & 0x1FF;
2183 } else if (INTEL_GEN(dev_priv
) >= 6) {
2184 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2186 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2187 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2188 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2189 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2190 } else if (INTEL_GEN(dev_priv
) >= 5) {
2191 uint32_t mltr
= I915_READ(MLTR_ILK
);
2193 /* ILK primary LP0 latency is 700 ns */
2195 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2196 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2200 static void intel_fixup_spr_wm_latency(struct drm_i915_private
*dev_priv
,
2203 /* ILK sprite LP0 latency is 1300 ns */
2204 if (IS_GEN5(dev_priv
))
2208 static void intel_fixup_cur_wm_latency(struct drm_i915_private
*dev_priv
,
2211 /* ILK cursor LP0 latency is 1300 ns */
2212 if (IS_GEN5(dev_priv
))
2215 /* WaDoubleCursorLP3Latency:ivb */
2216 if (IS_IVYBRIDGE(dev_priv
))
2220 int ilk_wm_max_level(const struct drm_i915_private
*dev_priv
)
2222 /* how many WM levels are we expecting */
2223 if (INTEL_GEN(dev_priv
) >= 9)
2225 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2227 else if (INTEL_GEN(dev_priv
) >= 6)
2233 static void intel_print_wm_latency(struct drm_i915_private
*dev_priv
,
2235 const uint16_t wm
[8])
2237 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2239 for (level
= 0; level
<= max_level
; level
++) {
2240 unsigned int latency
= wm
[level
];
2243 DRM_ERROR("%s WM%d latency not provided\n",
2249 * - latencies are in us on gen9.
2250 * - before then, WM1+ latency values are in 0.5us units
2252 if (IS_GEN9(dev_priv
))
2257 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2258 name
, level
, wm
[level
],
2259 latency
/ 10, latency
% 10);
2263 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2264 uint16_t wm
[5], uint16_t min
)
2266 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2271 wm
[0] = max(wm
[0], min
);
2272 for (level
= 1; level
<= max_level
; level
++)
2273 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2278 static void snb_wm_latency_quirk(struct drm_i915_private
*dev_priv
)
2283 * The BIOS provided WM memory latency values are often
2284 * inadequate for high resolution displays. Adjust them.
2286 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2287 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2288 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2293 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2294 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2295 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2296 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2299 static void ilk_setup_wm_latency(struct drm_i915_private
*dev_priv
)
2301 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
);
2303 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2304 sizeof(dev_priv
->wm
.pri_latency
));
2305 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2306 sizeof(dev_priv
->wm
.pri_latency
));
2308 intel_fixup_spr_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
);
2309 intel_fixup_cur_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
);
2311 intel_print_wm_latency(dev_priv
, "Primary", dev_priv
->wm
.pri_latency
);
2312 intel_print_wm_latency(dev_priv
, "Sprite", dev_priv
->wm
.spr_latency
);
2313 intel_print_wm_latency(dev_priv
, "Cursor", dev_priv
->wm
.cur_latency
);
2315 if (IS_GEN6(dev_priv
))
2316 snb_wm_latency_quirk(dev_priv
);
2319 static void skl_setup_wm_latency(struct drm_i915_private
*dev_priv
)
2321 intel_read_wm_latency(dev_priv
, dev_priv
->wm
.skl_latency
);
2322 intel_print_wm_latency(dev_priv
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
2325 static bool ilk_validate_pipe_wm(struct drm_device
*dev
,
2326 struct intel_pipe_wm
*pipe_wm
)
2328 /* LP0 watermark maximums depend on this pipe alone */
2329 const struct intel_wm_config config
= {
2330 .num_pipes_active
= 1,
2331 .sprites_enabled
= pipe_wm
->sprites_enabled
,
2332 .sprites_scaled
= pipe_wm
->sprites_scaled
,
2334 struct ilk_wm_maximums max
;
2336 /* LP0 watermarks always use 1/2 DDB partitioning */
2337 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2339 /* At least LP0 must be valid */
2340 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0])) {
2341 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2348 /* Compute new watermarks for the pipe */
2349 static int ilk_compute_pipe_wm(struct intel_crtc_state
*cstate
)
2351 struct drm_atomic_state
*state
= cstate
->base
.state
;
2352 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
2353 struct intel_pipe_wm
*pipe_wm
;
2354 struct drm_device
*dev
= state
->dev
;
2355 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
2356 struct intel_plane
*intel_plane
;
2357 struct intel_plane_state
*pristate
= NULL
;
2358 struct intel_plane_state
*sprstate
= NULL
;
2359 struct intel_plane_state
*curstate
= NULL
;
2360 int level
, max_level
= ilk_wm_max_level(dev_priv
), usable_level
;
2361 struct ilk_wm_maximums max
;
2363 pipe_wm
= &cstate
->wm
.ilk
.optimal
;
2365 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2366 struct intel_plane_state
*ps
;
2368 ps
= intel_atomic_get_existing_plane_state(state
,
2373 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
2375 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_OVERLAY
)
2377 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
2381 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
2383 pipe_wm
->sprites_enabled
= sprstate
->base
.visible
;
2384 pipe_wm
->sprites_scaled
= sprstate
->base
.visible
&&
2385 (drm_rect_width(&sprstate
->base
.dst
) != drm_rect_width(&sprstate
->base
.src
) >> 16 ||
2386 drm_rect_height(&sprstate
->base
.dst
) != drm_rect_height(&sprstate
->base
.src
) >> 16);
2389 usable_level
= max_level
;
2391 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2392 if (INTEL_GEN(dev_priv
) <= 6 && pipe_wm
->sprites_enabled
)
2395 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2396 if (pipe_wm
->sprites_scaled
)
2399 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
2400 pristate
, sprstate
, curstate
, &pipe_wm
->raw_wm
[0]);
2402 memset(&pipe_wm
->wm
, 0, sizeof(pipe_wm
->wm
));
2403 pipe_wm
->wm
[0] = pipe_wm
->raw_wm
[0];
2405 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2406 pipe_wm
->linetime
= hsw_compute_linetime_wm(cstate
);
2408 if (!ilk_validate_pipe_wm(dev
, pipe_wm
))
2411 ilk_compute_wm_reg_maximums(dev_priv
, 1, &max
);
2413 for (level
= 1; level
<= max_level
; level
++) {
2414 struct intel_wm_level
*wm
= &pipe_wm
->raw_wm
[level
];
2416 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
2417 pristate
, sprstate
, curstate
, wm
);
2420 * Disable any watermark level that exceeds the
2421 * register maximums since such watermarks are
2424 if (level
> usable_level
)
2427 if (ilk_validate_wm_level(level
, &max
, wm
))
2428 pipe_wm
->wm
[level
] = *wm
;
2430 usable_level
= level
;
2437 * Build a set of 'intermediate' watermark values that satisfy both the old
2438 * state and the new state. These can be programmed to the hardware
2441 static int ilk_compute_intermediate_wm(struct drm_device
*dev
,
2442 struct intel_crtc
*intel_crtc
,
2443 struct intel_crtc_state
*newstate
)
2445 struct intel_pipe_wm
*a
= &newstate
->wm
.ilk
.intermediate
;
2446 struct intel_pipe_wm
*b
= &intel_crtc
->wm
.active
.ilk
;
2447 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
2450 * Start with the final, target watermarks, then combine with the
2451 * currently active watermarks to get values that are safe both before
2452 * and after the vblank.
2454 *a
= newstate
->wm
.ilk
.optimal
;
2455 a
->pipe_enabled
|= b
->pipe_enabled
;
2456 a
->sprites_enabled
|= b
->sprites_enabled
;
2457 a
->sprites_scaled
|= b
->sprites_scaled
;
2459 for (level
= 0; level
<= max_level
; level
++) {
2460 struct intel_wm_level
*a_wm
= &a
->wm
[level
];
2461 const struct intel_wm_level
*b_wm
= &b
->wm
[level
];
2463 a_wm
->enable
&= b_wm
->enable
;
2464 a_wm
->pri_val
= max(a_wm
->pri_val
, b_wm
->pri_val
);
2465 a_wm
->spr_val
= max(a_wm
->spr_val
, b_wm
->spr_val
);
2466 a_wm
->cur_val
= max(a_wm
->cur_val
, b_wm
->cur_val
);
2467 a_wm
->fbc_val
= max(a_wm
->fbc_val
, b_wm
->fbc_val
);
2471 * We need to make sure that these merged watermark values are
2472 * actually a valid configuration themselves. If they're not,
2473 * there's no safe way to transition from the old state to
2474 * the new state, so we need to fail the atomic transaction.
2476 if (!ilk_validate_pipe_wm(dev
, a
))
2480 * If our intermediate WM are identical to the final WM, then we can
2481 * omit the post-vblank programming; only update if it's different.
2483 if (memcmp(a
, &newstate
->wm
.ilk
.optimal
, sizeof(*a
)) == 0)
2484 newstate
->wm
.need_postvbl_update
= false;
2490 * Merge the watermarks from all active pipes for a specific level.
2492 static void ilk_merge_wm_level(struct drm_device
*dev
,
2494 struct intel_wm_level
*ret_wm
)
2496 const struct intel_crtc
*intel_crtc
;
2498 ret_wm
->enable
= true;
2500 for_each_intel_crtc(dev
, intel_crtc
) {
2501 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
.ilk
;
2502 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2504 if (!active
->pipe_enabled
)
2508 * The watermark values may have been used in the past,
2509 * so we must maintain them in the registers for some
2510 * time even if the level is now disabled.
2513 ret_wm
->enable
= false;
2515 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2516 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2517 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2518 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2523 * Merge all low power watermarks for all active pipes.
2525 static void ilk_wm_merge(struct drm_device
*dev
,
2526 const struct intel_wm_config
*config
,
2527 const struct ilk_wm_maximums
*max
,
2528 struct intel_pipe_wm
*merged
)
2530 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2531 int level
, max_level
= ilk_wm_max_level(dev_priv
);
2532 int last_enabled_level
= max_level
;
2534 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2535 if ((INTEL_GEN(dev_priv
) <= 6 || IS_IVYBRIDGE(dev_priv
)) &&
2536 config
->num_pipes_active
> 1)
2537 last_enabled_level
= 0;
2539 /* ILK: FBC WM must be disabled always */
2540 merged
->fbc_wm_enabled
= INTEL_GEN(dev_priv
) >= 6;
2542 /* merge each WM1+ level */
2543 for (level
= 1; level
<= max_level
; level
++) {
2544 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2546 ilk_merge_wm_level(dev
, level
, wm
);
2548 if (level
> last_enabled_level
)
2550 else if (!ilk_validate_wm_level(level
, max
, wm
))
2551 /* make sure all following levels get disabled */
2552 last_enabled_level
= level
- 1;
2555 * The spec says it is preferred to disable
2556 * FBC WMs instead of disabling a WM level.
2558 if (wm
->fbc_val
> max
->fbc
) {
2560 merged
->fbc_wm_enabled
= false;
2565 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2567 * FIXME this is racy. FBC might get enabled later.
2568 * What we should check here is whether FBC can be
2569 * enabled sometime later.
2571 if (IS_GEN5(dev_priv
) && !merged
->fbc_wm_enabled
&&
2572 intel_fbc_is_active(dev_priv
)) {
2573 for (level
= 2; level
<= max_level
; level
++) {
2574 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2581 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2583 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2584 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2587 /* The value we need to program into the WM_LPx latency field */
2588 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2590 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2592 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
2595 return dev_priv
->wm
.pri_latency
[level
];
2598 static void ilk_compute_wm_results(struct drm_device
*dev
,
2599 const struct intel_pipe_wm
*merged
,
2600 enum intel_ddb_partitioning partitioning
,
2601 struct ilk_wm_values
*results
)
2603 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2604 struct intel_crtc
*intel_crtc
;
2607 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2608 results
->partitioning
= partitioning
;
2610 /* LP1+ register values */
2611 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2612 const struct intel_wm_level
*r
;
2614 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2616 r
= &merged
->wm
[level
];
2619 * Maintain the watermark values even if the level is
2620 * disabled. Doing otherwise could cause underruns.
2622 results
->wm_lp
[wm_lp
- 1] =
2623 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2624 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2628 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2630 if (INTEL_GEN(dev_priv
) >= 8)
2631 results
->wm_lp
[wm_lp
- 1] |=
2632 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2634 results
->wm_lp
[wm_lp
- 1] |=
2635 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2638 * Always set WM1S_LP_EN when spr_val != 0, even if the
2639 * level is disabled. Doing otherwise could cause underruns.
2641 if (INTEL_GEN(dev_priv
) <= 6 && r
->spr_val
) {
2642 WARN_ON(wm_lp
!= 1);
2643 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2645 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2648 /* LP0 register values */
2649 for_each_intel_crtc(dev
, intel_crtc
) {
2650 enum pipe pipe
= intel_crtc
->pipe
;
2651 const struct intel_wm_level
*r
=
2652 &intel_crtc
->wm
.active
.ilk
.wm
[0];
2654 if (WARN_ON(!r
->enable
))
2657 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.ilk
.linetime
;
2659 results
->wm_pipe
[pipe
] =
2660 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2661 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2666 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2667 * case both are at the same level. Prefer r1 in case they're the same. */
2668 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2669 struct intel_pipe_wm
*r1
,
2670 struct intel_pipe_wm
*r2
)
2672 int level
, max_level
= ilk_wm_max_level(to_i915(dev
));
2673 int level1
= 0, level2
= 0;
2675 for (level
= 1; level
<= max_level
; level
++) {
2676 if (r1
->wm
[level
].enable
)
2678 if (r2
->wm
[level
].enable
)
2682 if (level1
== level2
) {
2683 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2687 } else if (level1
> level2
) {
2694 /* dirty bits used to track which watermarks need changes */
2695 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2696 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2697 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2698 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2699 #define WM_DIRTY_FBC (1 << 24)
2700 #define WM_DIRTY_DDB (1 << 25)
2702 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2703 const struct ilk_wm_values
*old
,
2704 const struct ilk_wm_values
*new)
2706 unsigned int dirty
= 0;
2710 for_each_pipe(dev_priv
, pipe
) {
2711 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2712 dirty
|= WM_DIRTY_LINETIME(pipe
);
2713 /* Must disable LP1+ watermarks too */
2714 dirty
|= WM_DIRTY_LP_ALL
;
2717 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2718 dirty
|= WM_DIRTY_PIPE(pipe
);
2719 /* Must disable LP1+ watermarks too */
2720 dirty
|= WM_DIRTY_LP_ALL
;
2724 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2725 dirty
|= WM_DIRTY_FBC
;
2726 /* Must disable LP1+ watermarks too */
2727 dirty
|= WM_DIRTY_LP_ALL
;
2730 if (old
->partitioning
!= new->partitioning
) {
2731 dirty
|= WM_DIRTY_DDB
;
2732 /* Must disable LP1+ watermarks too */
2733 dirty
|= WM_DIRTY_LP_ALL
;
2736 /* LP1+ watermarks already deemed dirty, no need to continue */
2737 if (dirty
& WM_DIRTY_LP_ALL
)
2740 /* Find the lowest numbered LP1+ watermark in need of an update... */
2741 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2742 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2743 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2747 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2748 for (; wm_lp
<= 3; wm_lp
++)
2749 dirty
|= WM_DIRTY_LP(wm_lp
);
2754 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2757 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2758 bool changed
= false;
2760 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2761 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2762 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2765 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2766 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2767 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2770 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2771 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2772 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2777 * Don't touch WM1S_LP_EN here.
2778 * Doing so could cause underruns.
2785 * The spec says we shouldn't write when we don't need, because every write
2786 * causes WMs to be re-evaluated, expending some power.
2788 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2789 struct ilk_wm_values
*results
)
2791 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2795 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2799 _ilk_disable_lp_wm(dev_priv
, dirty
);
2801 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2802 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2803 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2804 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2805 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2806 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2808 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2809 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2810 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2811 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2812 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2813 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2815 if (dirty
& WM_DIRTY_DDB
) {
2816 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2817 val
= I915_READ(WM_MISC
);
2818 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2819 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2821 val
|= WM_MISC_DATA_PARTITION_5_6
;
2822 I915_WRITE(WM_MISC
, val
);
2824 val
= I915_READ(DISP_ARB_CTL2
);
2825 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2826 val
&= ~DISP_DATA_PARTITION_5_6
;
2828 val
|= DISP_DATA_PARTITION_5_6
;
2829 I915_WRITE(DISP_ARB_CTL2
, val
);
2833 if (dirty
& WM_DIRTY_FBC
) {
2834 val
= I915_READ(DISP_ARB_CTL
);
2835 if (results
->enable_fbc_wm
)
2836 val
&= ~DISP_FBC_WM_DIS
;
2838 val
|= DISP_FBC_WM_DIS
;
2839 I915_WRITE(DISP_ARB_CTL
, val
);
2842 if (dirty
& WM_DIRTY_LP(1) &&
2843 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2844 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2846 if (INTEL_GEN(dev_priv
) >= 7) {
2847 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2848 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2849 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2850 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2853 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2854 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2855 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2856 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2857 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2858 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2860 dev_priv
->wm
.hw
= *results
;
2863 bool ilk_disable_lp_wm(struct drm_device
*dev
)
2865 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2867 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2870 #define SKL_SAGV_BLOCK_TIME 30 /* µs */
2873 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2874 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2875 * other universal planes are in indices 1..n. Note that this may leave unused
2876 * indices between the top "sprite" plane and the cursor.
2879 skl_wm_plane_id(const struct intel_plane
*plane
)
2881 switch (plane
->base
.type
) {
2882 case DRM_PLANE_TYPE_PRIMARY
:
2884 case DRM_PLANE_TYPE_CURSOR
:
2885 return PLANE_CURSOR
;
2886 case DRM_PLANE_TYPE_OVERLAY
:
2887 return plane
->plane
+ 1;
2889 MISSING_CASE(plane
->base
.type
);
2890 return plane
->plane
;
2895 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2896 * so assume we'll always need it in order to avoid underruns.
2898 static bool skl_needs_memory_bw_wa(struct intel_atomic_state
*state
)
2900 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
2902 if (IS_SKYLAKE(dev_priv
) || IS_BROXTON(dev_priv
) ||
2903 IS_KABYLAKE(dev_priv
))
2910 intel_has_sagv(struct drm_i915_private
*dev_priv
)
2912 if (IS_KABYLAKE(dev_priv
))
2915 if (IS_SKYLAKE(dev_priv
) &&
2916 dev_priv
->sagv_status
!= I915_SAGV_NOT_CONTROLLED
)
2923 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2924 * depending on power and performance requirements. The display engine access
2925 * to system memory is blocked during the adjustment time. Because of the
2926 * blocking time, having this enabled can cause full system hangs and/or pipe
2927 * underruns if we don't meet all of the following requirements:
2929 * - <= 1 pipe enabled
2930 * - All planes can enable watermarks for latencies >= SAGV engine block time
2931 * - We're not using an interlaced display configuration
2934 intel_enable_sagv(struct drm_i915_private
*dev_priv
)
2938 if (!intel_has_sagv(dev_priv
))
2941 if (dev_priv
->sagv_status
== I915_SAGV_ENABLED
)
2944 DRM_DEBUG_KMS("Enabling the SAGV\n");
2945 mutex_lock(&dev_priv
->rps
.hw_lock
);
2947 ret
= sandybridge_pcode_write(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
2950 /* We don't need to wait for the SAGV when enabling */
2951 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2954 * Some skl systems, pre-release machines in particular,
2955 * don't actually have an SAGV.
2957 if (IS_SKYLAKE(dev_priv
) && ret
== -ENXIO
) {
2958 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2959 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
2961 } else if (ret
< 0) {
2962 DRM_ERROR("Failed to enable the SAGV\n");
2966 dev_priv
->sagv_status
= I915_SAGV_ENABLED
;
2971 intel_do_sagv_disable(struct drm_i915_private
*dev_priv
)
2974 uint32_t temp
= GEN9_SAGV_DISABLE
;
2976 ret
= sandybridge_pcode_read(dev_priv
, GEN9_PCODE_SAGV_CONTROL
,
2981 return temp
& GEN9_SAGV_IS_DISABLED
;
2985 intel_disable_sagv(struct drm_i915_private
*dev_priv
)
2989 if (!intel_has_sagv(dev_priv
))
2992 if (dev_priv
->sagv_status
== I915_SAGV_DISABLED
)
2995 DRM_DEBUG_KMS("Disabling the SAGV\n");
2996 mutex_lock(&dev_priv
->rps
.hw_lock
);
2998 /* bspec says to keep retrying for at least 1 ms */
2999 ret
= wait_for(result
= intel_do_sagv_disable(dev_priv
), 1);
3000 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3002 if (ret
== -ETIMEDOUT
) {
3003 DRM_ERROR("Request to disable SAGV timed out\n");
3008 * Some skl systems, pre-release machines in particular,
3009 * don't actually have an SAGV.
3011 if (IS_SKYLAKE(dev_priv
) && result
== -ENXIO
) {
3012 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
3013 dev_priv
->sagv_status
= I915_SAGV_NOT_CONTROLLED
;
3015 } else if (result
< 0) {
3016 DRM_ERROR("Failed to disable the SAGV\n");
3020 dev_priv
->sagv_status
= I915_SAGV_DISABLED
;
3024 bool intel_can_enable_sagv(struct drm_atomic_state
*state
)
3026 struct drm_device
*dev
= state
->dev
;
3027 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3028 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3029 struct intel_crtc
*crtc
;
3030 struct intel_plane
*plane
;
3031 struct intel_crtc_state
*cstate
;
3032 struct skl_plane_wm
*wm
;
3036 if (!intel_has_sagv(dev_priv
))
3040 * SKL workaround: bspec recommends we disable the SAGV when we have
3041 * more then one pipe enabled
3043 * If there are no active CRTCs, no additional checks need be performed
3045 if (hweight32(intel_state
->active_crtcs
) == 0)
3047 else if (hweight32(intel_state
->active_crtcs
) > 1)
3050 /* Since we're now guaranteed to only have one active CRTC... */
3051 pipe
= ffs(intel_state
->active_crtcs
) - 1;
3052 crtc
= intel_get_crtc_for_pipe(dev_priv
, pipe
);
3053 cstate
= to_intel_crtc_state(crtc
->base
.state
);
3055 if (crtc
->base
.state
->adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
3058 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
3059 wm
= &cstate
->wm
.skl
.optimal
.planes
[skl_wm_plane_id(plane
)];
3061 /* Skip this plane if it's not enabled */
3062 if (!wm
->wm
[0].plane_en
)
3065 /* Find the highest enabled wm level for this plane */
3066 for (level
= ilk_wm_max_level(dev_priv
);
3067 !wm
->wm
[level
].plane_en
; --level
)
3070 latency
= dev_priv
->wm
.skl_latency
[level
];
3072 if (skl_needs_memory_bw_wa(intel_state
) &&
3073 plane
->base
.state
->fb
->modifier
==
3074 I915_FORMAT_MOD_X_TILED
)
3078 * If any of the planes on this pipe don't enable wm levels
3079 * that incur memory latencies higher then 30µs we can't enable
3082 if (latency
< SKL_SAGV_BLOCK_TIME
)
3090 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
3091 const struct intel_crtc_state
*cstate
,
3092 struct skl_ddb_entry
*alloc
, /* out */
3093 int *num_active
/* out */)
3095 struct drm_atomic_state
*state
= cstate
->base
.state
;
3096 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3097 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3098 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
3099 unsigned int pipe_size
, ddb_size
;
3100 int nth_active_pipe
;
3102 if (WARN_ON(!state
) || !cstate
->base
.active
) {
3105 *num_active
= hweight32(dev_priv
->active_crtcs
);
3109 if (intel_state
->active_pipe_changes
)
3110 *num_active
= hweight32(intel_state
->active_crtcs
);
3112 *num_active
= hweight32(dev_priv
->active_crtcs
);
3114 ddb_size
= INTEL_INFO(dev_priv
)->ddb_size
;
3115 WARN_ON(ddb_size
== 0);
3117 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
3120 * If the state doesn't change the active CRTC's, then there's
3121 * no need to recalculate; the existing pipe allocation limits
3122 * should remain unchanged. Note that we're safe from racing
3123 * commits since any racing commit that changes the active CRTC
3124 * list would need to grab _all_ crtc locks, including the one
3125 * we currently hold.
3127 if (!intel_state
->active_pipe_changes
) {
3129 * alloc may be cleared by clear_intel_crtc_state,
3130 * copy from old state to be sure
3132 *alloc
= to_intel_crtc_state(for_crtc
->state
)->wm
.skl
.ddb
;
3136 nth_active_pipe
= hweight32(intel_state
->active_crtcs
&
3137 (drm_crtc_mask(for_crtc
) - 1));
3138 pipe_size
= ddb_size
/ hweight32(intel_state
->active_crtcs
);
3139 alloc
->start
= nth_active_pipe
* ddb_size
/ *num_active
;
3140 alloc
->end
= alloc
->start
+ pipe_size
;
3143 static unsigned int skl_cursor_allocation(int num_active
)
3145 if (num_active
== 1)
3151 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
3153 entry
->start
= reg
& 0x3ff;
3154 entry
->end
= (reg
>> 16) & 0x3ff;
3159 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
3160 struct skl_ddb_allocation
*ddb
/* out */)
3166 memset(ddb
, 0, sizeof(*ddb
));
3168 for_each_pipe(dev_priv
, pipe
) {
3169 enum intel_display_power_domain power_domain
;
3171 power_domain
= POWER_DOMAIN_PIPE(pipe
);
3172 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
3175 for_each_universal_plane(dev_priv
, pipe
, plane
) {
3176 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane
));
3177 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane
],
3181 val
= I915_READ(CUR_BUF_CFG(pipe
));
3182 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][PLANE_CURSOR
],
3185 intel_display_power_put(dev_priv
, power_domain
);
3190 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3191 * The bspec defines downscale amount as:
3194 * Horizontal down scale amount = maximum[1, Horizontal source size /
3195 * Horizontal destination size]
3196 * Vertical down scale amount = maximum[1, Vertical source size /
3197 * Vertical destination size]
3198 * Total down scale amount = Horizontal down scale amount *
3199 * Vertical down scale amount
3202 * Return value is provided in 16.16 fixed point form to retain fractional part.
3203 * Caller should take care of dividing & rounding off the value.
3206 skl_plane_downscale_amount(const struct intel_plane_state
*pstate
)
3208 uint32_t downscale_h
, downscale_w
;
3209 uint32_t src_w
, src_h
, dst_w
, dst_h
;
3211 if (WARN_ON(!pstate
->base
.visible
))
3212 return DRM_PLANE_HELPER_NO_SCALING
;
3214 /* n.b., src is 16.16 fixed point, dst is whole integer */
3215 src_w
= drm_rect_width(&pstate
->base
.src
);
3216 src_h
= drm_rect_height(&pstate
->base
.src
);
3217 dst_w
= drm_rect_width(&pstate
->base
.dst
);
3218 dst_h
= drm_rect_height(&pstate
->base
.dst
);
3219 if (drm_rotation_90_or_270(pstate
->base
.rotation
))
3222 downscale_h
= max(src_h
/ dst_h
, (uint32_t)DRM_PLANE_HELPER_NO_SCALING
);
3223 downscale_w
= max(src_w
/ dst_w
, (uint32_t)DRM_PLANE_HELPER_NO_SCALING
);
3225 /* Provide result in 16.16 fixed point */
3226 return (uint64_t)downscale_w
* downscale_h
>> 16;
3230 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
3231 const struct drm_plane_state
*pstate
,
3234 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3235 uint32_t down_scale_amount
, data_rate
;
3236 uint32_t width
= 0, height
= 0;
3237 struct drm_framebuffer
*fb
;
3240 if (!intel_pstate
->base
.visible
)
3244 format
= fb
->format
->format
;
3246 if (pstate
->plane
->type
== DRM_PLANE_TYPE_CURSOR
)
3248 if (y
&& format
!= DRM_FORMAT_NV12
)
3251 width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
3252 height
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
3254 if (drm_rotation_90_or_270(pstate
->rotation
))
3255 swap(width
, height
);
3257 /* for planar format */
3258 if (format
== DRM_FORMAT_NV12
) {
3259 if (y
) /* y-plane data rate */
3260 data_rate
= width
* height
*
3262 else /* uv-plane data rate */
3263 data_rate
= (width
/ 2) * (height
/ 2) *
3266 /* for packed formats */
3267 data_rate
= width
* height
* fb
->format
->cpp
[0];
3270 down_scale_amount
= skl_plane_downscale_amount(intel_pstate
);
3272 return (uint64_t)data_rate
* down_scale_amount
>> 16;
3276 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3277 * a 8192x4096@32bpp framebuffer:
3278 * 3 * 4096 * 8192 * 4 < 2^32
3281 skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate
,
3282 unsigned *plane_data_rate
,
3283 unsigned *plane_y_data_rate
)
3285 struct drm_crtc_state
*cstate
= &intel_cstate
->base
;
3286 struct drm_atomic_state
*state
= cstate
->state
;
3287 struct drm_plane
*plane
;
3288 const struct intel_plane
*intel_plane
;
3289 const struct drm_plane_state
*pstate
;
3290 unsigned int rate
, total_data_rate
= 0;
3293 if (WARN_ON(!state
))
3296 /* Calculate and cache data rate for each plane */
3297 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, cstate
) {
3298 id
= skl_wm_plane_id(to_intel_plane(plane
));
3299 intel_plane
= to_intel_plane(plane
);
3302 rate
= skl_plane_relative_data_rate(intel_cstate
,
3304 plane_data_rate
[id
] = rate
;
3306 total_data_rate
+= rate
;
3309 rate
= skl_plane_relative_data_rate(intel_cstate
,
3311 plane_y_data_rate
[id
] = rate
;
3313 total_data_rate
+= rate
;
3316 return total_data_rate
;
3320 skl_ddb_min_alloc(const struct drm_plane_state
*pstate
,
3323 struct drm_framebuffer
*fb
= pstate
->fb
;
3324 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
3325 uint32_t src_w
, src_h
;
3326 uint32_t min_scanlines
= 8;
3332 /* For packed formats, no y-plane, return 0 */
3333 if (y
&& fb
->format
->format
!= DRM_FORMAT_NV12
)
3336 /* For Non Y-tile return 8-blocks */
3337 if (fb
->modifier
!= I915_FORMAT_MOD_Y_TILED
&&
3338 fb
->modifier
!= I915_FORMAT_MOD_Yf_TILED
)
3341 src_w
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
3342 src_h
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
3344 if (drm_rotation_90_or_270(pstate
->rotation
))
3347 /* Halve UV plane width and height for NV12 */
3348 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
) {
3353 if (fb
->format
->format
== DRM_FORMAT_NV12
&& !y
)
3354 plane_bpp
= fb
->format
->cpp
[1];
3356 plane_bpp
= fb
->format
->cpp
[0];
3358 if (drm_rotation_90_or_270(pstate
->rotation
)) {
3359 switch (plane_bpp
) {
3373 WARN(1, "Unsupported pixel depth %u for rotation",
3379 return DIV_ROUND_UP((4 * src_w
* plane_bpp
), 512) * min_scanlines
/4 + 3;
3383 skl_ddb_calc_min(const struct intel_crtc_state
*cstate
, int num_active
,
3384 uint16_t *minimum
, uint16_t *y_minimum
)
3386 const struct drm_plane_state
*pstate
;
3387 struct drm_plane
*plane
;
3389 drm_atomic_crtc_state_for_each_plane_state(plane
, pstate
, &cstate
->base
) {
3390 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
3391 int id
= skl_wm_plane_id(intel_plane
);
3393 if (id
== PLANE_CURSOR
)
3396 if (!pstate
->visible
)
3399 minimum
[id
] = skl_ddb_min_alloc(pstate
, 0);
3400 y_minimum
[id
] = skl_ddb_min_alloc(pstate
, 1);
3403 minimum
[PLANE_CURSOR
] = skl_cursor_allocation(num_active
);
3407 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
3408 struct skl_ddb_allocation
*ddb
/* out */)
3410 struct drm_atomic_state
*state
= cstate
->base
.state
;
3411 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3412 struct drm_device
*dev
= crtc
->dev
;
3413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3414 enum pipe pipe
= intel_crtc
->pipe
;
3415 struct skl_ddb_entry
*alloc
= &cstate
->wm
.skl
.ddb
;
3416 uint16_t alloc_size
, start
;
3417 uint16_t minimum
[I915_MAX_PLANES
] = {};
3418 uint16_t y_minimum
[I915_MAX_PLANES
] = {};
3419 unsigned int total_data_rate
;
3422 unsigned plane_data_rate
[I915_MAX_PLANES
] = {};
3423 unsigned plane_y_data_rate
[I915_MAX_PLANES
] = {};
3425 /* Clear the partitioning for disabled planes. */
3426 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3427 memset(ddb
->y_plane
[pipe
], 0, sizeof(ddb
->y_plane
[pipe
]));
3429 if (WARN_ON(!state
))
3432 if (!cstate
->base
.active
) {
3433 alloc
->start
= alloc
->end
= 0;
3437 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, alloc
, &num_active
);
3438 alloc_size
= skl_ddb_entry_size(alloc
);
3439 if (alloc_size
== 0) {
3440 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3444 skl_ddb_calc_min(cstate
, num_active
, minimum
, y_minimum
);
3447 * 1. Allocate the mininum required blocks for each active plane
3448 * and allocate the cursor, it doesn't require extra allocation
3449 * proportional to the data rate.
3452 for (i
= 0; i
< I915_MAX_PLANES
; i
++) {
3453 alloc_size
-= minimum
[i
];
3454 alloc_size
-= y_minimum
[i
];
3457 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- minimum
[PLANE_CURSOR
];
3458 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
3461 * 2. Distribute the remaining space in proportion to the amount of
3462 * data each plane needs to fetch from memory.
3464 * FIXME: we may not allocate every single block here.
3466 total_data_rate
= skl_get_total_relative_data_rate(cstate
,
3469 if (total_data_rate
== 0)
3472 start
= alloc
->start
;
3473 for (id
= 0; id
< I915_MAX_PLANES
; id
++) {
3474 unsigned int data_rate
, y_data_rate
;
3475 uint16_t plane_blocks
, y_plane_blocks
= 0;
3477 if (id
== PLANE_CURSOR
)
3480 data_rate
= plane_data_rate
[id
];
3483 * allocation for (packed formats) or (uv-plane part of planar format):
3484 * promote the expression to 64 bits to avoid overflowing, the
3485 * result is < available as data_rate / total_data_rate < 1
3487 plane_blocks
= minimum
[id
];
3488 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
3491 /* Leave disabled planes at (0,0) */
3493 ddb
->plane
[pipe
][id
].start
= start
;
3494 ddb
->plane
[pipe
][id
].end
= start
+ plane_blocks
;
3497 start
+= plane_blocks
;
3500 * allocation for y_plane part of planar format:
3502 y_data_rate
= plane_y_data_rate
[id
];
3504 y_plane_blocks
= y_minimum
[id
];
3505 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
3509 ddb
->y_plane
[pipe
][id
].start
= start
;
3510 ddb
->y_plane
[pipe
][id
].end
= start
+ y_plane_blocks
;
3513 start
+= y_plane_blocks
;
3520 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3521 * for the read latency) and cpp should always be <= 8, so that
3522 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3523 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3525 static uint32_t skl_wm_method1(uint32_t pixel_rate
, uint8_t cpp
, uint32_t latency
)
3527 uint32_t wm_intermediate_val
, ret
;
3532 wm_intermediate_val
= latency
* pixel_rate
* cpp
/ 512;
3533 ret
= DIV_ROUND_UP(wm_intermediate_val
, 1000);
3538 static uint32_t skl_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
3539 uint32_t latency
, uint32_t plane_blocks_per_line
)
3542 uint32_t wm_intermediate_val
;
3547 wm_intermediate_val
= latency
* pixel_rate
;
3548 ret
= DIV_ROUND_UP(wm_intermediate_val
, pipe_htotal
* 1000) *
3549 plane_blocks_per_line
;
3554 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state
*cstate
,
3555 struct intel_plane_state
*pstate
)
3557 uint64_t adjusted_pixel_rate
;
3558 uint64_t downscale_amount
;
3559 uint64_t pixel_rate
;
3561 /* Shouldn't reach here on disabled planes... */
3562 if (WARN_ON(!pstate
->base
.visible
))
3566 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3567 * with additional adjustments for plane-specific scaling.
3569 adjusted_pixel_rate
= ilk_pipe_pixel_rate(cstate
);
3570 downscale_amount
= skl_plane_downscale_amount(pstate
);
3572 pixel_rate
= adjusted_pixel_rate
* downscale_amount
>> 16;
3573 WARN_ON(pixel_rate
!= clamp_t(uint32_t, pixel_rate
, 0, ~0));
3578 static int skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
3579 struct intel_crtc_state
*cstate
,
3580 struct intel_plane_state
*intel_pstate
,
3581 uint16_t ddb_allocation
,
3583 uint16_t *out_blocks
, /* out */
3584 uint8_t *out_lines
, /* out */
3585 bool *enabled
/* out */)
3587 struct drm_plane_state
*pstate
= &intel_pstate
->base
;
3588 struct drm_framebuffer
*fb
= pstate
->fb
;
3589 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
3590 uint32_t method1
, method2
;
3591 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3592 uint32_t res_blocks
, res_lines
;
3593 uint32_t selected_result
;
3595 uint32_t width
= 0, height
= 0;
3596 uint32_t plane_pixel_rate
;
3597 uint32_t y_tile_minimum
, y_min_scanlines
;
3598 struct intel_atomic_state
*state
=
3599 to_intel_atomic_state(cstate
->base
.state
);
3600 bool apply_memory_bw_wa
= skl_needs_memory_bw_wa(state
);
3602 if (latency
== 0 || !cstate
->base
.active
|| !intel_pstate
->base
.visible
) {
3607 if (apply_memory_bw_wa
&& fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
3610 width
= drm_rect_width(&intel_pstate
->base
.src
) >> 16;
3611 height
= drm_rect_height(&intel_pstate
->base
.src
) >> 16;
3613 if (drm_rotation_90_or_270(pstate
->rotation
))
3614 swap(width
, height
);
3616 cpp
= fb
->format
->cpp
[0];
3617 plane_pixel_rate
= skl_adjusted_plane_pixel_rate(cstate
, intel_pstate
);
3619 if (drm_rotation_90_or_270(pstate
->rotation
)) {
3620 int cpp
= (fb
->format
->format
== DRM_FORMAT_NV12
) ?
3621 fb
->format
->cpp
[1] :
3626 y_min_scanlines
= 16;
3629 y_min_scanlines
= 8;
3632 y_min_scanlines
= 4;
3639 y_min_scanlines
= 4;
3642 if (apply_memory_bw_wa
)
3643 y_min_scanlines
*= 2;
3645 plane_bytes_per_line
= width
* cpp
;
3646 if (fb
->modifier
== I915_FORMAT_MOD_Y_TILED
||
3647 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED
) {
3648 plane_blocks_per_line
=
3649 DIV_ROUND_UP(plane_bytes_per_line
* y_min_scanlines
, 512);
3650 plane_blocks_per_line
/= y_min_scanlines
;
3651 } else if (fb
->modifier
== DRM_FORMAT_MOD_NONE
) {
3652 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512)
3655 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3658 method1
= skl_wm_method1(plane_pixel_rate
, cpp
, latency
);
3659 method2
= skl_wm_method2(plane_pixel_rate
,
3660 cstate
->base
.adjusted_mode
.crtc_htotal
,
3662 plane_blocks_per_line
);
3664 y_tile_minimum
= plane_blocks_per_line
* y_min_scanlines
;
3666 if (fb
->modifier
== I915_FORMAT_MOD_Y_TILED
||
3667 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED
) {
3668 selected_result
= max(method2
, y_tile_minimum
);
3670 if ((cpp
* cstate
->base
.adjusted_mode
.crtc_htotal
/ 512 < 1) &&
3671 (plane_bytes_per_line
/ 512 < 1))
3672 selected_result
= method2
;
3673 else if ((ddb_allocation
/ plane_blocks_per_line
) >= 1)
3674 selected_result
= min(method1
, method2
);
3676 selected_result
= method1
;
3679 res_blocks
= selected_result
+ 1;
3680 res_lines
= DIV_ROUND_UP(selected_result
, plane_blocks_per_line
);
3682 if (level
>= 1 && level
<= 7) {
3683 if (fb
->modifier
== I915_FORMAT_MOD_Y_TILED
||
3684 fb
->modifier
== I915_FORMAT_MOD_Yf_TILED
) {
3685 res_blocks
+= y_tile_minimum
;
3686 res_lines
+= y_min_scanlines
;
3692 if (res_blocks
>= ddb_allocation
|| res_lines
> 31) {
3696 * If there are no valid level 0 watermarks, then we can't
3697 * support this display configuration.
3702 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3703 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3704 to_intel_crtc(cstate
->base
.crtc
)->pipe
,
3705 skl_wm_plane_id(to_intel_plane(pstate
->plane
)),
3706 res_blocks
, ddb_allocation
, res_lines
);
3712 *out_blocks
= res_blocks
;
3713 *out_lines
= res_lines
;
3720 skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
3721 struct skl_ddb_allocation
*ddb
,
3722 struct intel_crtc_state
*cstate
,
3723 struct intel_plane
*intel_plane
,
3725 struct skl_wm_level
*result
)
3727 struct drm_atomic_state
*state
= cstate
->base
.state
;
3728 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3729 struct drm_plane
*plane
= &intel_plane
->base
;
3730 struct intel_plane_state
*intel_pstate
= NULL
;
3731 uint16_t ddb_blocks
;
3732 enum pipe pipe
= intel_crtc
->pipe
;
3734 int i
= skl_wm_plane_id(intel_plane
);
3738 intel_atomic_get_existing_plane_state(state
,
3742 * Note: If we start supporting multiple pending atomic commits against
3743 * the same planes/CRTC's in the future, plane->state will no longer be
3744 * the correct pre-state to use for the calculations here and we'll
3745 * need to change where we get the 'unchanged' plane data from.
3747 * For now this is fine because we only allow one queued commit against
3748 * a CRTC. Even if the plane isn't modified by this transaction and we
3749 * don't have a plane lock, we still have the CRTC's lock, so we know
3750 * that no other transactions are racing with us to update it.
3753 intel_pstate
= to_intel_plane_state(plane
->state
);
3755 WARN_ON(!intel_pstate
->base
.fb
);
3757 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][i
]);
3759 ret
= skl_compute_plane_wm(dev_priv
,
3764 &result
->plane_res_b
,
3765 &result
->plane_res_l
,
3774 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
3776 uint32_t pixel_rate
;
3778 if (!cstate
->base
.active
)
3781 pixel_rate
= ilk_pipe_pixel_rate(cstate
);
3783 if (WARN_ON(pixel_rate
== 0))
3786 return DIV_ROUND_UP(8 * cstate
->base
.adjusted_mode
.crtc_htotal
* 1000,
3790 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
3791 struct skl_wm_level
*trans_wm
/* out */)
3793 if (!cstate
->base
.active
)
3796 /* Until we know more, just disable transition WMs */
3797 trans_wm
->plane_en
= false;
3800 static int skl_build_pipe_wm(struct intel_crtc_state
*cstate
,
3801 struct skl_ddb_allocation
*ddb
,
3802 struct skl_pipe_wm
*pipe_wm
)
3804 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
3805 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
3806 struct intel_plane
*intel_plane
;
3807 struct skl_plane_wm
*wm
;
3808 int level
, max_level
= ilk_wm_max_level(dev_priv
);
3812 * We'll only calculate watermarks for planes that are actually
3813 * enabled, so make sure all other planes are set as disabled.
3815 memset(pipe_wm
->planes
, 0, sizeof(pipe_wm
->planes
));
3817 for_each_intel_plane_mask(&dev_priv
->drm
,
3819 cstate
->base
.plane_mask
) {
3820 wm
= &pipe_wm
->planes
[skl_wm_plane_id(intel_plane
)];
3822 for (level
= 0; level
<= max_level
; level
++) {
3823 ret
= skl_compute_wm_level(dev_priv
, ddb
, cstate
,
3829 skl_compute_transition_wm(cstate
, &wm
->trans_wm
);
3831 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
3836 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
,
3838 const struct skl_ddb_entry
*entry
)
3841 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
3846 static void skl_write_wm_level(struct drm_i915_private
*dev_priv
,
3848 const struct skl_wm_level
*level
)
3852 if (level
->plane_en
) {
3854 val
|= level
->plane_res_b
;
3855 val
|= level
->plane_res_l
<< PLANE_WM_LINES_SHIFT
;
3858 I915_WRITE(reg
, val
);
3861 static void skl_write_plane_wm(struct intel_crtc
*intel_crtc
,
3862 const struct skl_plane_wm
*wm
,
3863 const struct skl_ddb_allocation
*ddb
,
3866 struct drm_crtc
*crtc
= &intel_crtc
->base
;
3867 struct drm_device
*dev
= crtc
->dev
;
3868 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3869 int level
, max_level
= ilk_wm_max_level(dev_priv
);
3870 enum pipe pipe
= intel_crtc
->pipe
;
3872 for (level
= 0; level
<= max_level
; level
++) {
3873 skl_write_wm_level(dev_priv
, PLANE_WM(pipe
, plane
, level
),
3876 skl_write_wm_level(dev_priv
, PLANE_WM_TRANS(pipe
, plane
),
3879 skl_ddb_entry_write(dev_priv
, PLANE_BUF_CFG(pipe
, plane
),
3880 &ddb
->plane
[pipe
][plane
]);
3881 skl_ddb_entry_write(dev_priv
, PLANE_NV12_BUF_CFG(pipe
, plane
),
3882 &ddb
->y_plane
[pipe
][plane
]);
3885 static void skl_write_cursor_wm(struct intel_crtc
*intel_crtc
,
3886 const struct skl_plane_wm
*wm
,
3887 const struct skl_ddb_allocation
*ddb
)
3889 struct drm_crtc
*crtc
= &intel_crtc
->base
;
3890 struct drm_device
*dev
= crtc
->dev
;
3891 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3892 int level
, max_level
= ilk_wm_max_level(dev_priv
);
3893 enum pipe pipe
= intel_crtc
->pipe
;
3895 for (level
= 0; level
<= max_level
; level
++) {
3896 skl_write_wm_level(dev_priv
, CUR_WM(pipe
, level
),
3899 skl_write_wm_level(dev_priv
, CUR_WM_TRANS(pipe
), &wm
->trans_wm
);
3901 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
3902 &ddb
->plane
[pipe
][PLANE_CURSOR
]);
3905 bool skl_wm_level_equals(const struct skl_wm_level
*l1
,
3906 const struct skl_wm_level
*l2
)
3908 if (l1
->plane_en
!= l2
->plane_en
)
3911 /* If both planes aren't enabled, the rest shouldn't matter */
3915 return (l1
->plane_res_l
== l2
->plane_res_l
&&
3916 l1
->plane_res_b
== l2
->plane_res_b
);
3919 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry
*a
,
3920 const struct skl_ddb_entry
*b
)
3922 return a
->start
< b
->end
&& b
->start
< a
->end
;
3925 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry
**entries
,
3926 const struct skl_ddb_entry
*ddb
,
3931 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3932 if (i
!= ignore
&& entries
[i
] &&
3933 skl_ddb_entries_overlap(ddb
, entries
[i
]))
3939 static int skl_update_pipe_wm(struct drm_crtc_state
*cstate
,
3940 const struct skl_pipe_wm
*old_pipe_wm
,
3941 struct skl_pipe_wm
*pipe_wm
, /* out */
3942 struct skl_ddb_allocation
*ddb
, /* out */
3943 bool *changed
/* out */)
3945 struct intel_crtc_state
*intel_cstate
= to_intel_crtc_state(cstate
);
3948 ret
= skl_build_pipe_wm(intel_cstate
, ddb
, pipe_wm
);
3952 if (!memcmp(old_pipe_wm
, pipe_wm
, sizeof(*pipe_wm
)))
3961 pipes_modified(struct drm_atomic_state
*state
)
3963 struct drm_crtc
*crtc
;
3964 struct drm_crtc_state
*cstate
;
3965 uint32_t i
, ret
= 0;
3967 for_each_crtc_in_state(state
, crtc
, cstate
, i
)
3968 ret
|= drm_crtc_mask(crtc
);
3974 skl_ddb_add_affected_planes(struct intel_crtc_state
*cstate
)
3976 struct drm_atomic_state
*state
= cstate
->base
.state
;
3977 struct drm_device
*dev
= state
->dev
;
3978 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3979 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3980 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3981 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
3982 struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
3983 struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3984 struct drm_plane_state
*plane_state
;
3985 struct drm_plane
*plane
;
3986 enum pipe pipe
= intel_crtc
->pipe
;
3989 WARN_ON(!drm_atomic_get_existing_crtc_state(state
, crtc
));
3991 drm_for_each_plane_mask(plane
, dev
, cstate
->base
.plane_mask
) {
3992 id
= skl_wm_plane_id(to_intel_plane(plane
));
3994 if (skl_ddb_entry_equal(&cur_ddb
->plane
[pipe
][id
],
3995 &new_ddb
->plane
[pipe
][id
]) &&
3996 skl_ddb_entry_equal(&cur_ddb
->y_plane
[pipe
][id
],
3997 &new_ddb
->y_plane
[pipe
][id
]))
4000 plane_state
= drm_atomic_get_plane_state(state
, plane
);
4001 if (IS_ERR(plane_state
))
4002 return PTR_ERR(plane_state
);
4009 skl_compute_ddb(struct drm_atomic_state
*state
)
4011 struct drm_device
*dev
= state
->dev
;
4012 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4013 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4014 struct intel_crtc
*intel_crtc
;
4015 struct skl_ddb_allocation
*ddb
= &intel_state
->wm_results
.ddb
;
4016 uint32_t realloc_pipes
= pipes_modified(state
);
4020 * If this is our first atomic update following hardware readout,
4021 * we can't trust the DDB that the BIOS programmed for us. Let's
4022 * pretend that all pipes switched active status so that we'll
4023 * ensure a full DDB recompute.
4025 if (dev_priv
->wm
.distrust_bios_wm
) {
4026 ret
= drm_modeset_lock(&dev
->mode_config
.connection_mutex
,
4027 state
->acquire_ctx
);
4031 intel_state
->active_pipe_changes
= ~0;
4034 * We usually only initialize intel_state->active_crtcs if we
4035 * we're doing a modeset; make sure this field is always
4036 * initialized during the sanitization process that happens
4037 * on the first commit too.
4039 if (!intel_state
->modeset
)
4040 intel_state
->active_crtcs
= dev_priv
->active_crtcs
;
4044 * If the modeset changes which CRTC's are active, we need to
4045 * recompute the DDB allocation for *all* active pipes, even
4046 * those that weren't otherwise being modified in any way by this
4047 * atomic commit. Due to the shrinking of the per-pipe allocations
4048 * when new active CRTC's are added, it's possible for a pipe that
4049 * we were already using and aren't changing at all here to suddenly
4050 * become invalid if its DDB needs exceeds its new allocation.
4052 * Note that if we wind up doing a full DDB recompute, we can't let
4053 * any other display updates race with this transaction, so we need
4054 * to grab the lock on *all* CRTC's.
4056 if (intel_state
->active_pipe_changes
) {
4058 intel_state
->wm_results
.dirty_pipes
= ~0;
4062 * We're not recomputing for the pipes not included in the commit, so
4063 * make sure we start with the current state.
4065 memcpy(ddb
, &dev_priv
->wm
.skl_hw
.ddb
, sizeof(*ddb
));
4067 for_each_intel_crtc_mask(dev
, intel_crtc
, realloc_pipes
) {
4068 struct intel_crtc_state
*cstate
;
4070 cstate
= intel_atomic_get_crtc_state(state
, intel_crtc
);
4072 return PTR_ERR(cstate
);
4074 ret
= skl_allocate_pipe_ddb(cstate
, ddb
);
4078 ret
= skl_ddb_add_affected_planes(cstate
);
4087 skl_copy_wm_for_pipe(struct skl_wm_values
*dst
,
4088 struct skl_wm_values
*src
,
4091 memcpy(dst
->ddb
.y_plane
[pipe
], src
->ddb
.y_plane
[pipe
],
4092 sizeof(dst
->ddb
.y_plane
[pipe
]));
4093 memcpy(dst
->ddb
.plane
[pipe
], src
->ddb
.plane
[pipe
],
4094 sizeof(dst
->ddb
.plane
[pipe
]));
4098 skl_print_wm_changes(const struct drm_atomic_state
*state
)
4100 const struct drm_device
*dev
= state
->dev
;
4101 const struct drm_i915_private
*dev_priv
= to_i915(dev
);
4102 const struct intel_atomic_state
*intel_state
=
4103 to_intel_atomic_state(state
);
4104 const struct drm_crtc
*crtc
;
4105 const struct drm_crtc_state
*cstate
;
4106 const struct intel_plane
*intel_plane
;
4107 const struct skl_ddb_allocation
*old_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4108 const struct skl_ddb_allocation
*new_ddb
= &intel_state
->wm_results
.ddb
;
4112 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
4113 const struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4114 enum pipe pipe
= intel_crtc
->pipe
;
4116 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
4117 const struct skl_ddb_entry
*old
, *new;
4119 id
= skl_wm_plane_id(intel_plane
);
4120 old
= &old_ddb
->plane
[pipe
][id
];
4121 new = &new_ddb
->plane
[pipe
][id
];
4123 if (skl_ddb_entry_equal(old
, new))
4126 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4127 intel_plane
->base
.base
.id
,
4128 intel_plane
->base
.name
,
4129 old
->start
, old
->end
,
4130 new->start
, new->end
);
4136 skl_compute_wm(struct drm_atomic_state
*state
)
4138 struct drm_crtc
*crtc
;
4139 struct drm_crtc_state
*cstate
;
4140 struct intel_atomic_state
*intel_state
= to_intel_atomic_state(state
);
4141 struct skl_wm_values
*results
= &intel_state
->wm_results
;
4142 struct skl_pipe_wm
*pipe_wm
;
4143 bool changed
= false;
4147 * If this transaction isn't actually touching any CRTC's, don't
4148 * bother with watermark calculation. Note that if we pass this
4149 * test, we're guaranteed to hold at least one CRTC state mutex,
4150 * which means we can safely use values like dev_priv->active_crtcs
4151 * since any racing commits that want to update them would need to
4152 * hold _all_ CRTC state mutexes.
4154 for_each_crtc_in_state(state
, crtc
, cstate
, i
)
4159 /* Clear all dirty flags */
4160 results
->dirty_pipes
= 0;
4162 ret
= skl_compute_ddb(state
);
4167 * Calculate WM's for all pipes that are part of this transaction.
4168 * Note that the DDB allocation above may have added more CRTC's that
4169 * weren't otherwise being modified (and set bits in dirty_pipes) if
4170 * pipe allocations had to change.
4172 * FIXME: Now that we're doing this in the atomic check phase, we
4173 * should allow skl_update_pipe_wm() to return failure in cases where
4174 * no suitable watermark values can be found.
4176 for_each_crtc_in_state(state
, crtc
, cstate
, i
) {
4177 struct intel_crtc_state
*intel_cstate
=
4178 to_intel_crtc_state(cstate
);
4179 const struct skl_pipe_wm
*old_pipe_wm
=
4180 &to_intel_crtc_state(crtc
->state
)->wm
.skl
.optimal
;
4182 pipe_wm
= &intel_cstate
->wm
.skl
.optimal
;
4183 ret
= skl_update_pipe_wm(cstate
, old_pipe_wm
, pipe_wm
,
4184 &results
->ddb
, &changed
);
4189 results
->dirty_pipes
|= drm_crtc_mask(crtc
);
4191 if ((results
->dirty_pipes
& drm_crtc_mask(crtc
)) == 0)
4192 /* This pipe's WM's did not change */
4195 intel_cstate
->update_wm_pre
= true;
4198 skl_print_wm_changes(state
);
4203 static void skl_atomic_update_crtc_wm(struct intel_atomic_state
*state
,
4204 struct intel_crtc_state
*cstate
)
4206 struct intel_crtc
*crtc
= to_intel_crtc(cstate
->base
.crtc
);
4207 struct drm_i915_private
*dev_priv
= to_i915(state
->base
.dev
);
4208 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.skl
.optimal
;
4209 const struct skl_ddb_allocation
*ddb
= &state
->wm_results
.ddb
;
4210 enum pipe pipe
= crtc
->pipe
;
4213 if (!(state
->wm_results
.dirty_pipes
& drm_crtc_mask(&crtc
->base
)))
4216 I915_WRITE(PIPE_WM_LINETIME(pipe
), pipe_wm
->linetime
);
4218 for_each_universal_plane(dev_priv
, pipe
, plane
)
4219 skl_write_plane_wm(crtc
, &pipe_wm
->planes
[plane
], ddb
, plane
);
4221 skl_write_cursor_wm(crtc
, &pipe_wm
->planes
[PLANE_CURSOR
], ddb
);
4224 static void skl_initial_wm(struct intel_atomic_state
*state
,
4225 struct intel_crtc_state
*cstate
)
4227 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4228 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4229 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4230 struct skl_wm_values
*results
= &state
->wm_results
;
4231 struct skl_wm_values
*hw_vals
= &dev_priv
->wm
.skl_hw
;
4232 enum pipe pipe
= intel_crtc
->pipe
;
4234 if ((results
->dirty_pipes
& drm_crtc_mask(&intel_crtc
->base
)) == 0)
4237 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4239 if (cstate
->base
.active_changed
)
4240 skl_atomic_update_crtc_wm(state
, cstate
);
4242 skl_copy_wm_for_pipe(hw_vals
, results
, pipe
);
4244 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4247 static void ilk_compute_wm_config(struct drm_device
*dev
,
4248 struct intel_wm_config
*config
)
4250 struct intel_crtc
*crtc
;
4252 /* Compute the currently _active_ config */
4253 for_each_intel_crtc(dev
, crtc
) {
4254 const struct intel_pipe_wm
*wm
= &crtc
->wm
.active
.ilk
;
4256 if (!wm
->pipe_enabled
)
4259 config
->sprites_enabled
|= wm
->sprites_enabled
;
4260 config
->sprites_scaled
|= wm
->sprites_scaled
;
4261 config
->num_pipes_active
++;
4265 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
4267 struct drm_device
*dev
= &dev_priv
->drm
;
4268 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
4269 struct ilk_wm_maximums max
;
4270 struct intel_wm_config config
= {};
4271 struct ilk_wm_values results
= {};
4272 enum intel_ddb_partitioning partitioning
;
4274 ilk_compute_wm_config(dev
, &config
);
4276 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
4277 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
4279 /* 5/6 split only in single pipe config on IVB+ */
4280 if (INTEL_GEN(dev_priv
) >= 7 &&
4281 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
4282 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
4283 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
4285 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
4287 best_lp_wm
= &lp_wm_1_2
;
4290 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
4291 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
4293 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
4295 ilk_write_wm_values(dev_priv
, &results
);
4298 static void ilk_initial_watermarks(struct intel_atomic_state
*state
,
4299 struct intel_crtc_state
*cstate
)
4301 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
4302 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4304 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4305 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.intermediate
;
4306 ilk_program_watermarks(dev_priv
);
4307 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4310 static void ilk_optimize_watermarks(struct intel_atomic_state
*state
,
4311 struct intel_crtc_state
*cstate
)
4313 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
4314 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
4316 mutex_lock(&dev_priv
->wm
.wm_mutex
);
4317 if (cstate
->wm
.need_postvbl_update
) {
4318 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.optimal
;
4319 ilk_program_watermarks(dev_priv
);
4321 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
4324 static inline void skl_wm_level_from_reg_val(uint32_t val
,
4325 struct skl_wm_level
*level
)
4327 level
->plane_en
= val
& PLANE_WM_EN
;
4328 level
->plane_res_b
= val
& PLANE_WM_BLOCKS_MASK
;
4329 level
->plane_res_l
= (val
>> PLANE_WM_LINES_SHIFT
) &
4330 PLANE_WM_LINES_MASK
;
4333 void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
,
4334 struct skl_pipe_wm
*out
)
4336 struct drm_device
*dev
= crtc
->dev
;
4337 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4338 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4339 struct intel_plane
*intel_plane
;
4340 struct skl_plane_wm
*wm
;
4341 enum pipe pipe
= intel_crtc
->pipe
;
4342 int level
, id
, max_level
;
4345 max_level
= ilk_wm_max_level(dev_priv
);
4347 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
4348 id
= skl_wm_plane_id(intel_plane
);
4349 wm
= &out
->planes
[id
];
4351 for (level
= 0; level
<= max_level
; level
++) {
4352 if (id
!= PLANE_CURSOR
)
4353 val
= I915_READ(PLANE_WM(pipe
, id
, level
));
4355 val
= I915_READ(CUR_WM(pipe
, level
));
4357 skl_wm_level_from_reg_val(val
, &wm
->wm
[level
]);
4360 if (id
!= PLANE_CURSOR
)
4361 val
= I915_READ(PLANE_WM_TRANS(pipe
, id
));
4363 val
= I915_READ(CUR_WM_TRANS(pipe
));
4365 skl_wm_level_from_reg_val(val
, &wm
->trans_wm
);
4368 if (!intel_crtc
->active
)
4371 out
->linetime
= I915_READ(PIPE_WM_LINETIME(pipe
));
4374 void skl_wm_get_hw_state(struct drm_device
*dev
)
4376 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4377 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
4378 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
4379 struct drm_crtc
*crtc
;
4380 struct intel_crtc
*intel_crtc
;
4381 struct intel_crtc_state
*cstate
;
4383 skl_ddb_get_hw_state(dev_priv
, ddb
);
4384 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4385 intel_crtc
= to_intel_crtc(crtc
);
4386 cstate
= to_intel_crtc_state(crtc
->state
);
4388 skl_pipe_wm_get_hw_state(crtc
, &cstate
->wm
.skl
.optimal
);
4390 if (intel_crtc
->active
)
4391 hw
->dirty_pipes
|= drm_crtc_mask(crtc
);
4394 if (dev_priv
->active_crtcs
) {
4395 /* Fully recompute DDB on first atomic commit */
4396 dev_priv
->wm
.distrust_bios_wm
= true;
4398 /* Easy/common case; just sanitize DDB now if everything off */
4399 memset(ddb
, 0, sizeof(*ddb
));
4403 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
4405 struct drm_device
*dev
= crtc
->dev
;
4406 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4407 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4408 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4409 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
4410 struct intel_pipe_wm
*active
= &cstate
->wm
.ilk
.optimal
;
4411 enum pipe pipe
= intel_crtc
->pipe
;
4412 static const i915_reg_t wm0_pipe_reg
[] = {
4413 [PIPE_A
] = WM0_PIPEA_ILK
,
4414 [PIPE_B
] = WM0_PIPEB_ILK
,
4415 [PIPE_C
] = WM0_PIPEC_IVB
,
4418 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
4419 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4420 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
4422 memset(active
, 0, sizeof(*active
));
4424 active
->pipe_enabled
= intel_crtc
->active
;
4426 if (active
->pipe_enabled
) {
4427 u32 tmp
= hw
->wm_pipe
[pipe
];
4430 * For active pipes LP0 watermark is marked as
4431 * enabled, and LP1+ watermaks as disabled since
4432 * we can't really reverse compute them in case
4433 * multiple pipes are active.
4435 active
->wm
[0].enable
= true;
4436 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
4437 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
4438 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
4439 active
->linetime
= hw
->wm_linetime
[pipe
];
4441 int level
, max_level
= ilk_wm_max_level(dev_priv
);
4444 * For inactive pipes, all watermark levels
4445 * should be marked as enabled but zeroed,
4446 * which is what we'd compute them to.
4448 for (level
= 0; level
<= max_level
; level
++)
4449 active
->wm
[level
].enable
= true;
4452 intel_crtc
->wm
.active
.ilk
= *active
;
4455 #define _FW_WM(value, plane) \
4456 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4457 #define _FW_WM_VLV(value, plane) \
4458 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4460 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
4461 struct vlv_wm_values
*wm
)
4466 for_each_pipe(dev_priv
, pipe
) {
4467 tmp
= I915_READ(VLV_DDL(pipe
));
4469 wm
->ddl
[pipe
].primary
=
4470 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4471 wm
->ddl
[pipe
].cursor
=
4472 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4473 wm
->ddl
[pipe
].sprite
[0] =
4474 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4475 wm
->ddl
[pipe
].sprite
[1] =
4476 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4479 tmp
= I915_READ(DSPFW1
);
4480 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
4481 wm
->pipe
[PIPE_B
].cursor
= _FW_WM(tmp
, CURSORB
);
4482 wm
->pipe
[PIPE_B
].primary
= _FW_WM_VLV(tmp
, PLANEB
);
4483 wm
->pipe
[PIPE_A
].primary
= _FW_WM_VLV(tmp
, PLANEA
);
4485 tmp
= I915_READ(DSPFW2
);
4486 wm
->pipe
[PIPE_A
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEB
);
4487 wm
->pipe
[PIPE_A
].cursor
= _FW_WM(tmp
, CURSORA
);
4488 wm
->pipe
[PIPE_A
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEA
);
4490 tmp
= I915_READ(DSPFW3
);
4491 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
4493 if (IS_CHERRYVIEW(dev_priv
)) {
4494 tmp
= I915_READ(DSPFW7_CHV
);
4495 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
4496 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
4498 tmp
= I915_READ(DSPFW8_CHV
);
4499 wm
->pipe
[PIPE_C
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEF
);
4500 wm
->pipe
[PIPE_C
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEE
);
4502 tmp
= I915_READ(DSPFW9_CHV
);
4503 wm
->pipe
[PIPE_C
].primary
= _FW_WM_VLV(tmp
, PLANEC
);
4504 wm
->pipe
[PIPE_C
].cursor
= _FW_WM(tmp
, CURSORC
);
4506 tmp
= I915_READ(DSPHOWM
);
4507 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4508 wm
->pipe
[PIPE_C
].sprite
[1] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
4509 wm
->pipe
[PIPE_C
].sprite
[0] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
4510 wm
->pipe
[PIPE_C
].primary
|= _FW_WM(tmp
, PLANEC_HI
) << 8;
4511 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4512 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4513 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
4514 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4515 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4516 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
4518 tmp
= I915_READ(DSPFW7
);
4519 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
4520 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
4522 tmp
= I915_READ(DSPHOWM
);
4523 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4524 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4525 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4526 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
4527 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4528 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4529 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
4536 void vlv_wm_get_hw_state(struct drm_device
*dev
)
4538 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4539 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
4540 struct intel_plane
*plane
;
4544 vlv_read_wm_values(dev_priv
, wm
);
4546 for_each_intel_plane(dev
, plane
) {
4547 switch (plane
->base
.type
) {
4549 case DRM_PLANE_TYPE_CURSOR
:
4550 plane
->wm
.fifo_size
= 63;
4552 case DRM_PLANE_TYPE_PRIMARY
:
4553 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev_priv
, plane
->pipe
, 0);
4555 case DRM_PLANE_TYPE_OVERLAY
:
4556 sprite
= plane
->plane
;
4557 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev_priv
, plane
->pipe
, sprite
+ 1);
4562 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
4563 wm
->level
= VLV_WM_LEVEL_PM2
;
4565 if (IS_CHERRYVIEW(dev_priv
)) {
4566 mutex_lock(&dev_priv
->rps
.hw_lock
);
4568 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4569 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
4570 wm
->level
= VLV_WM_LEVEL_PM5
;
4573 * If DDR DVFS is disabled in the BIOS, Punit
4574 * will never ack the request. So if that happens
4575 * assume we don't have to enable/disable DDR DVFS
4576 * dynamically. To test that just set the REQ_ACK
4577 * bit to poke the Punit, but don't change the
4578 * HIGH/LOW bits so that we don't actually change
4579 * the current state.
4581 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4582 val
|= FORCE_DDR_FREQ_REQ_ACK
;
4583 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
4585 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
4586 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
4587 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4588 "assuming DDR DVFS is disabled\n");
4589 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
4591 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4592 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
4593 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
4596 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4599 for_each_pipe(dev_priv
, pipe
)
4600 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4601 pipe_name(pipe
), wm
->pipe
[pipe
].primary
, wm
->pipe
[pipe
].cursor
,
4602 wm
->pipe
[pipe
].sprite
[0], wm
->pipe
[pipe
].sprite
[1]);
4604 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4605 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
4608 void ilk_wm_get_hw_state(struct drm_device
*dev
)
4610 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4611 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4612 struct drm_crtc
*crtc
;
4614 for_each_crtc(dev
, crtc
)
4615 ilk_pipe_wm_get_hw_state(crtc
);
4617 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
4618 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
4619 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
4621 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
4622 if (INTEL_GEN(dev_priv
) >= 7) {
4623 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
4624 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
4627 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4628 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
4629 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4630 else if (IS_IVYBRIDGE(dev_priv
))
4631 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
4632 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4635 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
4639 * intel_update_watermarks - update FIFO watermark values based on current modes
4641 * Calculate watermark values for the various WM regs based on current mode
4642 * and plane configuration.
4644 * There are several cases to deal with here:
4645 * - normal (i.e. non-self-refresh)
4646 * - self-refresh (SR) mode
4647 * - lines are large relative to FIFO size (buffer can hold up to 2)
4648 * - lines are small relative to FIFO size (buffer can hold more than 2
4649 * lines), so need to account for TLB latency
4651 * The normal calculation is:
4652 * watermark = dotclock * bytes per pixel * latency
4653 * where latency is platform & configuration dependent (we assume pessimal
4656 * The SR calculation is:
4657 * watermark = (trunc(latency/line time)+1) * surface width *
4660 * line time = htotal / dotclock
4661 * surface width = hdisplay for normal plane and 64 for cursor
4662 * and latency is assumed to be high, as above.
4664 * The final value programmed to the register should always be rounded up,
4665 * and include an extra 2 entries to account for clock crossings.
4667 * We don't use the sprite, so we can ignore that. And on Crestline we have
4668 * to set the non-SR watermarks to 8.
4670 void intel_update_watermarks(struct intel_crtc
*crtc
)
4672 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
4674 if (dev_priv
->display
.update_wm
)
4675 dev_priv
->display
.update_wm(crtc
);
4679 * Lock protecting IPS related data structures
4681 DEFINE_SPINLOCK(mchdev_lock
);
4683 /* Global for IPS driver to get at the current i915 device. Protected by
4685 static struct drm_i915_private
*i915_mch_dev
;
4687 bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
)
4691 assert_spin_locked(&mchdev_lock
);
4693 rgvswctl
= I915_READ16(MEMSWCTL
);
4694 if (rgvswctl
& MEMCTL_CMD_STS
) {
4695 DRM_DEBUG("gpu busy, RCS change rejected\n");
4696 return false; /* still busy with another command */
4699 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
4700 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
4701 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4702 POSTING_READ16(MEMSWCTL
);
4704 rgvswctl
|= MEMCTL_CMD_STS
;
4705 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4710 static void ironlake_enable_drps(struct drm_i915_private
*dev_priv
)
4713 u8 fmax
, fmin
, fstart
, vstart
;
4715 spin_lock_irq(&mchdev_lock
);
4717 rgvmodectl
= I915_READ(MEMMODECTL
);
4719 /* Enable temp reporting */
4720 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
4721 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
4723 /* 100ms RC evaluation intervals */
4724 I915_WRITE(RCUPEI
, 100000);
4725 I915_WRITE(RCDNEI
, 100000);
4727 /* Set max/min thresholds to 90ms and 80ms respectively */
4728 I915_WRITE(RCBMAXAVG
, 90000);
4729 I915_WRITE(RCBMINAVG
, 80000);
4731 I915_WRITE(MEMIHYST
, 1);
4733 /* Set up min, max, and cur for interrupt handling */
4734 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
4735 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
4736 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
4737 MEMMODE_FSTART_SHIFT
;
4739 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
4742 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
4743 dev_priv
->ips
.fstart
= fstart
;
4745 dev_priv
->ips
.max_delay
= fstart
;
4746 dev_priv
->ips
.min_delay
= fmin
;
4747 dev_priv
->ips
.cur_delay
= fstart
;
4749 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4750 fmax
, fmin
, fstart
);
4752 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
4755 * Interrupts will be enabled in ironlake_irq_postinstall
4758 I915_WRITE(VIDSTART
, vstart
);
4759 POSTING_READ(VIDSTART
);
4761 rgvmodectl
|= MEMMODE_SWMODE_EN
;
4762 I915_WRITE(MEMMODECTL
, rgvmodectl
);
4764 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
4765 DRM_ERROR("stuck trying to change perf mode\n");
4768 ironlake_set_drps(dev_priv
, fstart
);
4770 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
4771 I915_READ(DDREC
) + I915_READ(CSIEC
);
4772 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
4773 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
4774 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
4776 spin_unlock_irq(&mchdev_lock
);
4779 static void ironlake_disable_drps(struct drm_i915_private
*dev_priv
)
4783 spin_lock_irq(&mchdev_lock
);
4785 rgvswctl
= I915_READ16(MEMSWCTL
);
4787 /* Ack interrupts, disable EFC interrupt */
4788 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
4789 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
4790 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
4791 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
4792 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
4794 /* Go back to the starting frequency */
4795 ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
);
4797 rgvswctl
|= MEMCTL_CMD_STS
;
4798 I915_WRITE(MEMSWCTL
, rgvswctl
);
4801 spin_unlock_irq(&mchdev_lock
);
4804 /* There's a funny hw issue where the hw returns all 0 when reading from
4805 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4806 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4807 * all limits and the gpu stuck at whatever frequency it is at atm).
4809 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
4813 /* Only set the down limit when we've reached the lowest level to avoid
4814 * getting more interrupts, otherwise leave this clear. This prevents a
4815 * race in the hw when coming out of rc6: There's a tiny window where
4816 * the hw runs at the minimal clock before selecting the desired
4817 * frequency, if the down threshold expires in that window we will not
4818 * receive a down interrupt. */
4819 if (IS_GEN9(dev_priv
)) {
4820 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
4821 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4822 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
4824 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
4825 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4826 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
4832 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
4835 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
4836 u32 ei_up
= 0, ei_down
= 0;
4838 new_power
= dev_priv
->rps
.power
;
4839 switch (dev_priv
->rps
.power
) {
4841 if (val
> dev_priv
->rps
.efficient_freq
+ 1 &&
4842 val
> dev_priv
->rps
.cur_freq
)
4843 new_power
= BETWEEN
;
4847 if (val
<= dev_priv
->rps
.efficient_freq
&&
4848 val
< dev_priv
->rps
.cur_freq
)
4849 new_power
= LOW_POWER
;
4850 else if (val
>= dev_priv
->rps
.rp0_freq
&&
4851 val
> dev_priv
->rps
.cur_freq
)
4852 new_power
= HIGH_POWER
;
4856 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 &&
4857 val
< dev_priv
->rps
.cur_freq
)
4858 new_power
= BETWEEN
;
4861 /* Max/min bins are special */
4862 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4863 new_power
= LOW_POWER
;
4864 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
4865 new_power
= HIGH_POWER
;
4866 if (new_power
== dev_priv
->rps
.power
)
4869 /* Note the units here are not exactly 1us, but 1280ns. */
4870 switch (new_power
) {
4872 /* Upclock if more than 95% busy over 16ms */
4876 /* Downclock if less than 85% busy over 32ms */
4878 threshold_down
= 85;
4882 /* Upclock if more than 90% busy over 13ms */
4886 /* Downclock if less than 75% busy over 32ms */
4888 threshold_down
= 75;
4892 /* Upclock if more than 85% busy over 10ms */
4896 /* Downclock if less than 60% busy over 32ms */
4898 threshold_down
= 60;
4902 I915_WRITE(GEN6_RP_UP_EI
,
4903 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
4904 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
4905 GT_INTERVAL_FROM_US(dev_priv
,
4906 ei_up
* threshold_up
/ 100));
4908 I915_WRITE(GEN6_RP_DOWN_EI
,
4909 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
4910 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
4911 GT_INTERVAL_FROM_US(dev_priv
,
4912 ei_down
* threshold_down
/ 100));
4914 I915_WRITE(GEN6_RP_CONTROL
,
4915 GEN6_RP_MEDIA_TURBO
|
4916 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4917 GEN6_RP_MEDIA_IS_GFX
|
4919 GEN6_RP_UP_BUSY_AVG
|
4920 GEN6_RP_DOWN_IDLE_AVG
);
4922 dev_priv
->rps
.power
= new_power
;
4923 dev_priv
->rps
.up_threshold
= threshold_up
;
4924 dev_priv
->rps
.down_threshold
= threshold_down
;
4925 dev_priv
->rps
.last_adj
= 0;
4928 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
4932 if (val
> dev_priv
->rps
.min_freq_softlimit
)
4933 mask
|= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
4934 if (val
< dev_priv
->rps
.max_freq_softlimit
)
4935 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
4937 mask
&= dev_priv
->pm_rps_events
;
4939 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
4942 /* gen6_set_rps is called to update the frequency request, but should also be
4943 * called when the range (min_delay and max_delay) is modified so that we can
4944 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4945 static void gen6_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4947 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4948 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
4951 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4952 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4953 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4955 /* min/max delay may still have been modified so be sure to
4956 * write the limits value.
4958 if (val
!= dev_priv
->rps
.cur_freq
) {
4959 gen6_set_rps_thresholds(dev_priv
, val
);
4961 if (IS_GEN9(dev_priv
))
4962 I915_WRITE(GEN6_RPNSWREQ
,
4963 GEN9_FREQUENCY(val
));
4964 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4965 I915_WRITE(GEN6_RPNSWREQ
,
4966 HSW_FREQUENCY(val
));
4968 I915_WRITE(GEN6_RPNSWREQ
,
4969 GEN6_FREQUENCY(val
) |
4971 GEN6_AGGRESSIVE_TURBO
);
4974 /* Make sure we continue to get interrupts
4975 * until we hit the minimum or maximum frequencies.
4977 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
4978 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4980 POSTING_READ(GEN6_RPNSWREQ
);
4982 dev_priv
->rps
.cur_freq
= val
;
4983 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4986 static void valleyview_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4988 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4989 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4990 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4992 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv
) && (val
& 1),
4993 "Odd GPU freq value\n"))
4996 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4998 if (val
!= dev_priv
->rps
.cur_freq
) {
4999 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
5000 if (!IS_CHERRYVIEW(dev_priv
))
5001 gen6_set_rps_thresholds(dev_priv
, val
);
5004 dev_priv
->rps
.cur_freq
= val
;
5005 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
5008 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
5010 * * If Gfx is Idle, then
5011 * 1. Forcewake Media well.
5012 * 2. Request idle freq.
5013 * 3. Release Forcewake of Media well.
5015 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
5017 u32 val
= dev_priv
->rps
.idle_freq
;
5019 if (dev_priv
->rps
.cur_freq
<= val
)
5022 /* Wake up the media well, as that takes a lot less
5023 * power than the Render well. */
5024 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
5025 valleyview_set_rps(dev_priv
, val
);
5026 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
5029 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
5031 mutex_lock(&dev_priv
->rps
.hw_lock
);
5032 if (dev_priv
->rps
.enabled
) {
5033 if (dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
))
5034 gen6_rps_reset_ei(dev_priv
);
5035 I915_WRITE(GEN6_PMINTRMSK
,
5036 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
5038 gen6_enable_rps_interrupts(dev_priv
);
5040 /* Ensure we start at the user's desired frequency */
5041 intel_set_rps(dev_priv
,
5042 clamp(dev_priv
->rps
.cur_freq
,
5043 dev_priv
->rps
.min_freq_softlimit
,
5044 dev_priv
->rps
.max_freq_softlimit
));
5046 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5049 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
5051 /* Flush our bottom-half so that it does not race with us
5052 * setting the idle frequency and so that it is bounded by
5053 * our rpm wakeref. And then disable the interrupts to stop any
5054 * futher RPS reclocking whilst we are asleep.
5056 gen6_disable_rps_interrupts(dev_priv
);
5058 mutex_lock(&dev_priv
->rps
.hw_lock
);
5059 if (dev_priv
->rps
.enabled
) {
5060 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5061 vlv_set_rps_idle(dev_priv
);
5063 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5064 dev_priv
->rps
.last_adj
= 0;
5065 I915_WRITE(GEN6_PMINTRMSK
,
5066 gen6_sanitize_rps_pm_mask(dev_priv
, ~0));
5068 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5070 spin_lock(&dev_priv
->rps
.client_lock
);
5071 while (!list_empty(&dev_priv
->rps
.clients
))
5072 list_del_init(dev_priv
->rps
.clients
.next
);
5073 spin_unlock(&dev_priv
->rps
.client_lock
);
5076 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
5077 struct intel_rps_client
*rps
,
5078 unsigned long submitted
)
5080 /* This is intentionally racy! We peek at the state here, then
5081 * validate inside the RPS worker.
5083 if (!(dev_priv
->gt
.awake
&&
5084 dev_priv
->rps
.enabled
&&
5085 dev_priv
->rps
.cur_freq
< dev_priv
->rps
.boost_freq
))
5088 /* Force a RPS boost (and don't count it against the client) if
5089 * the GPU is severely congested.
5091 if (rps
&& time_after(jiffies
, submitted
+ DRM_I915_THROTTLE_JIFFIES
))
5094 spin_lock(&dev_priv
->rps
.client_lock
);
5095 if (rps
== NULL
|| list_empty(&rps
->link
)) {
5096 spin_lock_irq(&dev_priv
->irq_lock
);
5097 if (dev_priv
->rps
.interrupts_enabled
) {
5098 dev_priv
->rps
.client_boost
= true;
5099 schedule_work(&dev_priv
->rps
.work
);
5101 spin_unlock_irq(&dev_priv
->irq_lock
);
5104 list_add(&rps
->link
, &dev_priv
->rps
.clients
);
5107 dev_priv
->rps
.boosts
++;
5109 spin_unlock(&dev_priv
->rps
.client_lock
);
5112 void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
5114 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
5115 valleyview_set_rps(dev_priv
, val
);
5117 gen6_set_rps(dev_priv
, val
);
5120 static void gen9_disable_rc6(struct drm_i915_private
*dev_priv
)
5122 I915_WRITE(GEN6_RC_CONTROL
, 0);
5123 I915_WRITE(GEN9_PG_ENABLE
, 0);
5126 static void gen9_disable_rps(struct drm_i915_private
*dev_priv
)
5128 I915_WRITE(GEN6_RP_CONTROL
, 0);
5131 static void gen6_disable_rps(struct drm_i915_private
*dev_priv
)
5133 I915_WRITE(GEN6_RC_CONTROL
, 0);
5134 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
5135 I915_WRITE(GEN6_RP_CONTROL
, 0);
5138 static void cherryview_disable_rps(struct drm_i915_private
*dev_priv
)
5140 I915_WRITE(GEN6_RC_CONTROL
, 0);
5143 static void valleyview_disable_rps(struct drm_i915_private
*dev_priv
)
5145 /* we're doing forcewake before Disabling RC6,
5146 * This what the BIOS expects when going into suspend */
5147 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5149 I915_WRITE(GEN6_RC_CONTROL
, 0);
5151 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5154 static void intel_print_rc6_info(struct drm_i915_private
*dev_priv
, u32 mode
)
5156 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
5157 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
5158 mode
= GEN6_RC_CTL_RC6_ENABLE
;
5162 if (HAS_RC6p(dev_priv
))
5163 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5164 "RC6 %s RC6p %s RC6pp %s\n",
5165 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
),
5166 onoff(mode
& GEN6_RC_CTL_RC6p_ENABLE
),
5167 onoff(mode
& GEN6_RC_CTL_RC6pp_ENABLE
));
5170 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5171 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
));
5174 static bool bxt_check_bios_rc6_setup(struct drm_i915_private
*dev_priv
)
5176 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5177 bool enable_rc6
= true;
5178 unsigned long rc6_ctx_base
;
5182 rc_ctl
= I915_READ(GEN6_RC_CONTROL
);
5183 rc_sw_target
= (I915_READ(GEN6_RC_STATE
) & RC_SW_TARGET_STATE_MASK
) >>
5184 RC_SW_TARGET_STATE_SHIFT
;
5185 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5186 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5187 onoff(rc_ctl
& GEN6_RC_CTL_HW_ENABLE
),
5188 onoff(rc_ctl
& GEN6_RC_CTL_RC6_ENABLE
),
5191 if (!(I915_READ(RC6_LOCATION
) & RC6_CTX_IN_DRAM
)) {
5192 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5197 * The exact context size is not known for BXT, so assume a page size
5200 rc6_ctx_base
= I915_READ(RC6_CTX_BASE
) & RC6_CTX_BASE_MASK
;
5201 if (!((rc6_ctx_base
>= ggtt
->stolen_reserved_base
) &&
5202 (rc6_ctx_base
+ PAGE_SIZE
<= ggtt
->stolen_reserved_base
+
5203 ggtt
->stolen_reserved_size
))) {
5204 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5208 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
5209 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0
) & IDLE_TIME_MASK
) > 1) &&
5210 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
5211 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT
) & IDLE_TIME_MASK
) > 1))) {
5212 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5216 if (!I915_READ(GEN8_PUSHBUS_CONTROL
) ||
5217 !I915_READ(GEN8_PUSHBUS_ENABLE
) ||
5218 !I915_READ(GEN8_PUSHBUS_SHIFT
)) {
5219 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5223 if (!I915_READ(GEN6_GFXPAUSE
)) {
5224 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5228 if (!I915_READ(GEN8_MISC_CTRL0
)) {
5229 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5236 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
)
5238 /* No RC6 before Ironlake and code is gone for ilk. */
5239 if (INTEL_INFO(dev_priv
)->gen
< 6)
5245 if (IS_BROXTON(dev_priv
) && !bxt_check_bios_rc6_setup(dev_priv
)) {
5246 DRM_INFO("RC6 disabled by BIOS\n");
5250 /* Respect the kernel parameter if it is set */
5251 if (enable_rc6
>= 0) {
5254 if (HAS_RC6p(dev_priv
))
5255 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
5258 mask
= INTEL_RC6_ENABLE
;
5260 if ((enable_rc6
& mask
) != enable_rc6
)
5261 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5262 "(requested %d, valid %d)\n",
5263 enable_rc6
& mask
, enable_rc6
, mask
);
5265 return enable_rc6
& mask
;
5268 if (IS_IVYBRIDGE(dev_priv
))
5269 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
5271 return INTEL_RC6_ENABLE
;
5274 static void gen6_init_rps_frequencies(struct drm_i915_private
*dev_priv
)
5276 /* All of these values are in units of 50MHz */
5278 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5279 if (IS_BROXTON(dev_priv
)) {
5280 u32 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
5281 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
5282 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
5283 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
5285 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
5286 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
5287 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
5288 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
5290 /* hw_max = RP0 until we check for overclocking */
5291 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
5293 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
5294 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
) ||
5295 IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5296 u32 ddcc_status
= 0;
5298 if (sandybridge_pcode_read(dev_priv
,
5299 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
5301 dev_priv
->rps
.efficient_freq
=
5303 ((ddcc_status
>> 8) & 0xff),
5304 dev_priv
->rps
.min_freq
,
5305 dev_priv
->rps
.max_freq
);
5308 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5309 /* Store the frequency values in 16.66 MHZ units, which is
5310 * the natural hardware unit for SKL
5312 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
5313 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
5314 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
5315 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
5316 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
5320 static void reset_rps(struct drm_i915_private
*dev_priv
,
5321 void (*set
)(struct drm_i915_private
*, u8
))
5323 u8 freq
= dev_priv
->rps
.cur_freq
;
5326 dev_priv
->rps
.power
= -1;
5327 dev_priv
->rps
.cur_freq
= -1;
5329 set(dev_priv
, freq
);
5332 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5333 static void gen9_enable_rps(struct drm_i915_private
*dev_priv
)
5335 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5337 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5338 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
5340 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5341 * clear out the Control register just to avoid inconsitency
5342 * with debugfs interface, which will show Turbo as enabled
5343 * only and that is not expected by the User after adding the
5344 * WaGsvDisableTurbo. Apart from this there is no problem even
5345 * if the Turbo is left enabled in the Control register, as the
5346 * Up/Down interrupts would remain masked.
5348 gen9_disable_rps(dev_priv
);
5349 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5353 /* Program defaults and thresholds for RPS*/
5354 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5355 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5357 /* 1 second timeout*/
5358 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
5359 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
5361 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
5363 /* Leaning on the below call to gen6_set_rps to program/setup the
5364 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5365 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5366 reset_rps(dev_priv
, gen6_set_rps
);
5368 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5371 static void gen9_enable_rc6(struct drm_i915_private
*dev_priv
)
5373 struct intel_engine_cs
*engine
;
5374 enum intel_engine_id id
;
5375 uint32_t rc6_mask
= 0;
5377 /* 1a: Software RC state - RC0 */
5378 I915_WRITE(GEN6_RC_STATE
, 0);
5380 /* 1b: Get forcewake during program sequence. Although the driver
5381 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5382 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5384 /* 2a: Disable RC states. */
5385 I915_WRITE(GEN6_RC_CONTROL
, 0);
5387 /* 2b: Program RC6 thresholds.*/
5389 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5390 if (IS_SKYLAKE(dev_priv
))
5391 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
5393 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
5394 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5395 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5396 for_each_engine(engine
, dev_priv
, id
)
5397 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5399 if (HAS_GUC(dev_priv
))
5400 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
5402 I915_WRITE(GEN6_RC_SLEEP
, 0);
5404 /* 2c: Program Coarse Power Gating Policies. */
5405 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
5406 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
5408 /* 3a: Enable RC6 */
5409 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5410 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
5411 DRM_INFO("RC6 %s\n", onoff(rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
));
5412 /* WaRsUseTimeoutMode:bxt */
5413 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
5414 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us */
5415 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5416 GEN7_RC_CTL_TO_MODE
|
5419 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
5420 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5421 GEN6_RC_CTL_EI_MODE(1) |
5426 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5427 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5429 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
5430 I915_WRITE(GEN9_PG_ENABLE
, 0);
5432 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
5433 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
5435 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5438 static void gen8_enable_rps(struct drm_i915_private
*dev_priv
)
5440 struct intel_engine_cs
*engine
;
5441 enum intel_engine_id id
;
5442 uint32_t rc6_mask
= 0;
5444 /* 1a: Software RC state - RC0 */
5445 I915_WRITE(GEN6_RC_STATE
, 0);
5447 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5448 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5449 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5451 /* 2a: Disable RC states. */
5452 I915_WRITE(GEN6_RC_CONTROL
, 0);
5454 /* 2b: Program RC6 thresholds.*/
5455 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5456 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5457 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5458 for_each_engine(engine
, dev_priv
, id
)
5459 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5460 I915_WRITE(GEN6_RC_SLEEP
, 0);
5461 if (IS_BROADWELL(dev_priv
))
5462 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
5464 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
5467 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5468 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
5469 intel_print_rc6_info(dev_priv
, rc6_mask
);
5470 if (IS_BROADWELL(dev_priv
))
5471 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5472 GEN7_RC_CTL_TO_MODE
|
5475 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
5476 GEN6_RC_CTL_EI_MODE(1) |
5479 /* 4 Program defaults and thresholds for RPS*/
5480 I915_WRITE(GEN6_RPNSWREQ
,
5481 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5482 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5483 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5484 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5485 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
5487 /* Docs recommend 900MHz, and 300 MHz respectively */
5488 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
5489 dev_priv
->rps
.max_freq_softlimit
<< 24 |
5490 dev_priv
->rps
.min_freq_softlimit
<< 16);
5492 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
5493 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5494 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
5495 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
5497 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5500 I915_WRITE(GEN6_RP_CONTROL
,
5501 GEN6_RP_MEDIA_TURBO
|
5502 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5503 GEN6_RP_MEDIA_IS_GFX
|
5505 GEN6_RP_UP_BUSY_AVG
|
5506 GEN6_RP_DOWN_IDLE_AVG
);
5508 /* 6: Ring frequency + overclocking (our driver does this later */
5510 reset_rps(dev_priv
, gen6_set_rps
);
5512 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5515 static void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
5517 struct intel_engine_cs
*engine
;
5518 enum intel_engine_id id
;
5519 u32 rc6vids
, rc6_mask
= 0;
5524 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5526 /* Here begins a magic sequence of register writes to enable
5527 * auto-downclocking.
5529 * Perhaps there might be some value in exposing these to
5532 I915_WRITE(GEN6_RC_STATE
, 0);
5534 /* Clear the DBG now so we don't confuse earlier errors */
5535 gtfifodbg
= I915_READ(GTFIFODBG
);
5537 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
5538 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5541 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5543 /* disable the counters and set deterministic thresholds */
5544 I915_WRITE(GEN6_RC_CONTROL
, 0);
5546 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
5547 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
5548 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
5549 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5550 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5552 for_each_engine(engine
, dev_priv
, id
)
5553 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5555 I915_WRITE(GEN6_RC_SLEEP
, 0);
5556 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
5557 if (IS_IVYBRIDGE(dev_priv
))
5558 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
5560 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
5561 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
5562 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
5564 /* Check if we are enabling RC6 */
5565 rc6_mode
= intel_enable_rc6();
5566 if (rc6_mode
& INTEL_RC6_ENABLE
)
5567 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
5569 /* We don't use those on Haswell */
5570 if (!IS_HASWELL(dev_priv
)) {
5571 if (rc6_mode
& INTEL_RC6p_ENABLE
)
5572 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
5574 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
5575 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
5578 intel_print_rc6_info(dev_priv
, rc6_mask
);
5580 I915_WRITE(GEN6_RC_CONTROL
,
5582 GEN6_RC_CTL_EI_MODE(1) |
5583 GEN6_RC_CTL_HW_ENABLE
);
5585 /* Power down if completely idle for over 50ms */
5586 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
5587 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5589 reset_rps(dev_priv
, gen6_set_rps
);
5592 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
5593 if (IS_GEN6(dev_priv
) && ret
) {
5594 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5595 } else if (IS_GEN6(dev_priv
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
5596 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5597 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
5598 rc6vids
&= 0xffff00;
5599 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
5600 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
5602 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5605 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5608 static void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
5611 unsigned int gpu_freq
;
5612 unsigned int max_ia_freq
, min_ring_freq
;
5613 unsigned int max_gpu_freq
, min_gpu_freq
;
5614 int scaling_factor
= 180;
5615 struct cpufreq_policy
*policy
;
5617 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5619 policy
= cpufreq_cpu_get(0);
5621 max_ia_freq
= policy
->cpuinfo
.max_freq
;
5622 cpufreq_cpu_put(policy
);
5625 * Default to measured freq if none found, PCU will ensure we
5628 max_ia_freq
= tsc_khz
;
5631 /* Convert from kHz to MHz */
5632 max_ia_freq
/= 1000;
5634 min_ring_freq
= I915_READ(DCLK
) & 0xf;
5635 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5636 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
5638 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5639 /* Convert GT frequency to 50 HZ units */
5640 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
5641 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
5643 min_gpu_freq
= dev_priv
->rps
.min_freq
;
5644 max_gpu_freq
= dev_priv
->rps
.max_freq
;
5648 * For each potential GPU frequency, load a ring frequency we'd like
5649 * to use for memory access. We do this by specifying the IA frequency
5650 * the PCU should use as a reference to determine the ring frequency.
5652 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
5653 int diff
= max_gpu_freq
- gpu_freq
;
5654 unsigned int ia_freq
= 0, ring_freq
= 0;
5656 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5658 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5659 * No floor required for ring frequency on SKL.
5661 ring_freq
= gpu_freq
;
5662 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
5663 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5664 ring_freq
= max(min_ring_freq
, gpu_freq
);
5665 } else if (IS_HASWELL(dev_priv
)) {
5666 ring_freq
= mult_frac(gpu_freq
, 5, 4);
5667 ring_freq
= max(min_ring_freq
, ring_freq
);
5668 /* leave ia_freq as the default, chosen by cpufreq */
5670 /* On older processors, there is no separate ring
5671 * clock domain, so in order to boost the bandwidth
5672 * of the ring, we need to upclock the CPU (ia_freq).
5674 * For GPU frequencies less than 750MHz,
5675 * just use the lowest ring freq.
5677 if (gpu_freq
< min_freq
)
5680 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
5681 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
5684 sandybridge_pcode_write(dev_priv
,
5685 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
5686 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
5687 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
5692 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5696 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5698 switch (INTEL_INFO(dev_priv
)->sseu
.eu_total
) {
5700 /* (2 * 4) config */
5701 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
5704 /* (2 * 6) config */
5705 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
5708 /* (2 * 8) config */
5710 /* Setting (2 * 8) Min RP0 for any other combination */
5711 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
5715 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
5720 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5724 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
5725 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
5730 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5734 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5735 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
5740 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5744 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5746 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
5751 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5755 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5757 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
5759 rp0
= min_t(u32
, rp0
, 0xea);
5764 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5768 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
5769 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
5770 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
5771 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
5776 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
5780 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
5782 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5783 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5784 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5785 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5786 * to make sure it matches what Punit accepts.
5788 return max_t(u32
, val
, 0xc0);
5791 /* Check that the pctx buffer wasn't move under us. */
5792 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
5794 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5796 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
5797 dev_priv
->vlv_pctx
->stolen
->start
);
5801 /* Check that the pcbr address is not empty. */
5802 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
5804 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5806 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
5809 static void cherryview_setup_pctx(struct drm_i915_private
*dev_priv
)
5811 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5812 unsigned long pctx_paddr
, paddr
;
5814 int pctx_size
= 32*1024;
5816 pcbr
= I915_READ(VLV_PCBR
);
5817 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
5818 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5819 paddr
= (dev_priv
->mm
.stolen_base
+
5820 (ggtt
->stolen_size
- pctx_size
));
5822 pctx_paddr
= (paddr
& (~4095));
5823 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5826 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5829 static void valleyview_setup_pctx(struct drm_i915_private
*dev_priv
)
5831 struct drm_i915_gem_object
*pctx
;
5832 unsigned long pctx_paddr
;
5834 int pctx_size
= 24*1024;
5836 pcbr
= I915_READ(VLV_PCBR
);
5838 /* BIOS set it up already, grab the pre-alloc'd space */
5841 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
5842 pctx
= i915_gem_object_create_stolen_for_preallocated(&dev_priv
->drm
,
5844 I915_GTT_OFFSET_NONE
,
5849 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5852 * From the Gunit register HAS:
5853 * The Gfx driver is expected to program this register and ensure
5854 * proper allocation within Gfx stolen memory. For example, this
5855 * register should be programmed such than the PCBR range does not
5856 * overlap with other ranges, such as the frame buffer, protected
5857 * memory, or any other relevant ranges.
5859 pctx
= i915_gem_object_create_stolen(&dev_priv
->drm
, pctx_size
);
5861 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5865 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
5866 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5869 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5870 dev_priv
->vlv_pctx
= pctx
;
5873 static void valleyview_cleanup_pctx(struct drm_i915_private
*dev_priv
)
5875 if (WARN_ON(!dev_priv
->vlv_pctx
))
5878 i915_gem_object_put(dev_priv
->vlv_pctx
);
5879 dev_priv
->vlv_pctx
= NULL
;
5882 static void vlv_init_gpll_ref_freq(struct drm_i915_private
*dev_priv
)
5884 dev_priv
->rps
.gpll_ref_freq
=
5885 vlv_get_cck_clock(dev_priv
, "GPLL ref",
5886 CCK_GPLL_CLOCK_CONTROL
,
5887 dev_priv
->czclk_freq
);
5889 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5890 dev_priv
->rps
.gpll_ref_freq
);
5893 static void valleyview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
5897 valleyview_setup_pctx(dev_priv
);
5899 vlv_init_gpll_ref_freq(dev_priv
);
5901 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5902 switch ((val
>> 6) & 3) {
5905 dev_priv
->mem_freq
= 800;
5908 dev_priv
->mem_freq
= 1066;
5911 dev_priv
->mem_freq
= 1333;
5914 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5916 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
5917 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5918 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5919 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5920 dev_priv
->rps
.max_freq
);
5922 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
5923 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5924 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5925 dev_priv
->rps
.efficient_freq
);
5927 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
5928 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5929 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5930 dev_priv
->rps
.rp1_freq
);
5932 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
5933 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5934 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5935 dev_priv
->rps
.min_freq
);
5938 static void cherryview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
5942 cherryview_setup_pctx(dev_priv
);
5944 vlv_init_gpll_ref_freq(dev_priv
);
5946 mutex_lock(&dev_priv
->sb_lock
);
5947 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
5948 mutex_unlock(&dev_priv
->sb_lock
);
5950 switch ((val
>> 2) & 0x7) {
5952 dev_priv
->mem_freq
= 2000;
5955 dev_priv
->mem_freq
= 1600;
5958 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5960 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
5961 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5962 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5963 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5964 dev_priv
->rps
.max_freq
);
5966 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
5967 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5968 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5969 dev_priv
->rps
.efficient_freq
);
5971 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
5972 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5973 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5974 dev_priv
->rps
.rp1_freq
);
5976 /* PUnit validated range is only [RPe, RP0] */
5977 dev_priv
->rps
.min_freq
= dev_priv
->rps
.efficient_freq
;
5978 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5979 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5980 dev_priv
->rps
.min_freq
);
5982 WARN_ONCE((dev_priv
->rps
.max_freq
|
5983 dev_priv
->rps
.efficient_freq
|
5984 dev_priv
->rps
.rp1_freq
|
5985 dev_priv
->rps
.min_freq
) & 1,
5986 "Odd GPU freq values\n");
5989 static void valleyview_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
5991 valleyview_cleanup_pctx(dev_priv
);
5994 static void cherryview_enable_rps(struct drm_i915_private
*dev_priv
)
5996 struct intel_engine_cs
*engine
;
5997 enum intel_engine_id id
;
5998 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
6000 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6002 gtfifodbg
= I915_READ(GTFIFODBG
) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV
|
6003 GT_FIFO_FREE_ENTRIES_CHV
);
6005 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6007 I915_WRITE(GTFIFODBG
, gtfifodbg
);
6010 cherryview_check_pctx(dev_priv
);
6012 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6013 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
6014 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6016 /* Disable RC states. */
6017 I915_WRITE(GEN6_RC_CONTROL
, 0);
6019 /* 2a: Program RC6 thresholds.*/
6020 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
6021 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
6022 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
6024 for_each_engine(engine
, dev_priv
, id
)
6025 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6026 I915_WRITE(GEN6_RC_SLEEP
, 0);
6028 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6029 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
6031 /* allows RC6 residency counter to work */
6032 I915_WRITE(VLV_COUNTER_CONTROL
,
6033 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
6034 VLV_MEDIA_RC6_COUNT_EN
|
6035 VLV_RENDER_RC6_COUNT_EN
));
6037 /* For now we assume BIOS is allocating and populating the PCBR */
6038 pcbr
= I915_READ(VLV_PCBR
);
6041 if ((intel_enable_rc6() & INTEL_RC6_ENABLE
) &&
6042 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
6043 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
6045 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
6047 /* 4 Program defaults and thresholds for RPS*/
6048 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
6049 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
6050 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
6051 I915_WRITE(GEN6_RP_UP_EI
, 66000);
6052 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
6054 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6057 I915_WRITE(GEN6_RP_CONTROL
,
6058 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6059 GEN6_RP_MEDIA_IS_GFX
|
6061 GEN6_RP_UP_BUSY_AVG
|
6062 GEN6_RP_DOWN_IDLE_AVG
);
6064 /* Setting Fixed Bias */
6065 val
= VLV_OVERRIDE_EN
|
6067 CHV_BIAS_CPU_50_SOC_50
;
6068 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
6070 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
6072 /* RPS code assumes GPLL is used */
6073 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
6075 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
6076 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
6078 reset_rps(dev_priv
, valleyview_set_rps
);
6080 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6083 static void valleyview_enable_rps(struct drm_i915_private
*dev_priv
)
6085 struct intel_engine_cs
*engine
;
6086 enum intel_engine_id id
;
6087 u32 gtfifodbg
, val
, rc6_mode
= 0;
6089 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6091 valleyview_check_pctx(dev_priv
);
6093 gtfifodbg
= I915_READ(GTFIFODBG
);
6095 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6097 I915_WRITE(GTFIFODBG
, gtfifodbg
);
6100 /* If VLV, Forcewake all wells, else re-direct to regular path */
6101 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
6103 /* Disable RC states. */
6104 I915_WRITE(GEN6_RC_CONTROL
, 0);
6106 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
6107 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
6108 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
6109 I915_WRITE(GEN6_RP_UP_EI
, 66000);
6110 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
6112 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
6114 I915_WRITE(GEN6_RP_CONTROL
,
6115 GEN6_RP_MEDIA_TURBO
|
6116 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
6117 GEN6_RP_MEDIA_IS_GFX
|
6119 GEN6_RP_UP_BUSY_AVG
|
6120 GEN6_RP_DOWN_IDLE_CONT
);
6122 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
6123 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
6124 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
6126 for_each_engine(engine
, dev_priv
, id
)
6127 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
6129 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
6131 /* allows RC6 residency counter to work */
6132 I915_WRITE(VLV_COUNTER_CONTROL
,
6133 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
6134 VLV_RENDER_RC0_COUNT_EN
|
6135 VLV_MEDIA_RC6_COUNT_EN
|
6136 VLV_RENDER_RC6_COUNT_EN
));
6138 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
6139 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
6141 intel_print_rc6_info(dev_priv
, rc6_mode
);
6143 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
6145 /* Setting Fixed Bias */
6146 val
= VLV_OVERRIDE_EN
|
6148 VLV_BIAS_CPU_125_SOC_875
;
6149 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
6151 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
6153 /* RPS code assumes GPLL is used */
6154 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
6156 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
6157 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
6159 reset_rps(dev_priv
, valleyview_set_rps
);
6161 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
6164 static unsigned long intel_pxfreq(u32 vidfreq
)
6167 int div
= (vidfreq
& 0x3f0000) >> 16;
6168 int post
= (vidfreq
& 0x3000) >> 12;
6169 int pre
= (vidfreq
& 0x7);
6174 freq
= ((div
* 133333) / ((1<<post
) * pre
));
6179 static const struct cparams
{
6185 { 1, 1333, 301, 28664 },
6186 { 1, 1066, 294, 24460 },
6187 { 1, 800, 294, 25192 },
6188 { 0, 1333, 276, 27605 },
6189 { 0, 1066, 276, 27605 },
6190 { 0, 800, 231, 23784 },
6193 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
6195 u64 total_count
, diff
, ret
;
6196 u32 count1
, count2
, count3
, m
= 0, c
= 0;
6197 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
6200 assert_spin_locked(&mchdev_lock
);
6202 diff1
= now
- dev_priv
->ips
.last_time1
;
6204 /* Prevent division-by-zero if we are asking too fast.
6205 * Also, we don't get interesting results if we are polling
6206 * faster than once in 10ms, so just return the saved value
6210 return dev_priv
->ips
.chipset_power
;
6212 count1
= I915_READ(DMIEC
);
6213 count2
= I915_READ(DDREC
);
6214 count3
= I915_READ(CSIEC
);
6216 total_count
= count1
+ count2
+ count3
;
6218 /* FIXME: handle per-counter overflow */
6219 if (total_count
< dev_priv
->ips
.last_count1
) {
6220 diff
= ~0UL - dev_priv
->ips
.last_count1
;
6221 diff
+= total_count
;
6223 diff
= total_count
- dev_priv
->ips
.last_count1
;
6226 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
6227 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
6228 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
6235 diff
= div_u64(diff
, diff1
);
6236 ret
= ((m
* diff
) + c
);
6237 ret
= div_u64(ret
, 10);
6239 dev_priv
->ips
.last_count1
= total_count
;
6240 dev_priv
->ips
.last_time1
= now
;
6242 dev_priv
->ips
.chipset_power
= ret
;
6247 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
6251 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6254 spin_lock_irq(&mchdev_lock
);
6256 val
= __i915_chipset_val(dev_priv
);
6258 spin_unlock_irq(&mchdev_lock
);
6263 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
6265 unsigned long m
, x
, b
;
6268 tsfs
= I915_READ(TSFS
);
6270 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
6271 x
= I915_READ8(TR1
);
6273 b
= tsfs
& TSFS_INTR_MASK
;
6275 return ((m
* x
) / 127) - b
;
6278 static int _pxvid_to_vd(u8 pxvid
)
6283 if (pxvid
>= 8 && pxvid
< 31)
6286 return (pxvid
+ 2) * 125;
6289 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
6291 const int vd
= _pxvid_to_vd(pxvid
);
6292 const int vm
= vd
- 1125;
6294 if (INTEL_INFO(dev_priv
)->is_mobile
)
6295 return vm
> 0 ? vm
: 0;
6300 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
6302 u64 now
, diff
, diffms
;
6305 assert_spin_locked(&mchdev_lock
);
6307 now
= ktime_get_raw_ns();
6308 diffms
= now
- dev_priv
->ips
.last_time2
;
6309 do_div(diffms
, NSEC_PER_MSEC
);
6311 /* Don't divide by 0 */
6315 count
= I915_READ(GFXEC
);
6317 if (count
< dev_priv
->ips
.last_count2
) {
6318 diff
= ~0UL - dev_priv
->ips
.last_count2
;
6321 diff
= count
- dev_priv
->ips
.last_count2
;
6324 dev_priv
->ips
.last_count2
= count
;
6325 dev_priv
->ips
.last_time2
= now
;
6327 /* More magic constants... */
6329 diff
= div_u64(diff
, diffms
* 10);
6330 dev_priv
->ips
.gfx_power
= diff
;
6333 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
6335 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6338 spin_lock_irq(&mchdev_lock
);
6340 __i915_update_gfx_val(dev_priv
);
6342 spin_unlock_irq(&mchdev_lock
);
6345 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
6347 unsigned long t
, corr
, state1
, corr2
, state2
;
6350 assert_spin_locked(&mchdev_lock
);
6352 pxvid
= I915_READ(PXVFREQ(dev_priv
->rps
.cur_freq
));
6353 pxvid
= (pxvid
>> 24) & 0x7f;
6354 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
6358 t
= i915_mch_val(dev_priv
);
6360 /* Revel in the empirically derived constants */
6362 /* Correction factor in 1/100000 units */
6364 corr
= ((t
* 2349) + 135940);
6366 corr
= ((t
* 964) + 29317);
6368 corr
= ((t
* 301) + 1004);
6370 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
6372 corr2
= (corr
* dev_priv
->ips
.corr
);
6374 state2
= (corr2
* state1
) / 10000;
6375 state2
/= 100; /* convert to mW */
6377 __i915_update_gfx_val(dev_priv
);
6379 return dev_priv
->ips
.gfx_power
+ state2
;
6382 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
6386 if (INTEL_INFO(dev_priv
)->gen
!= 5)
6389 spin_lock_irq(&mchdev_lock
);
6391 val
= __i915_gfx_val(dev_priv
);
6393 spin_unlock_irq(&mchdev_lock
);
6399 * i915_read_mch_val - return value for IPS use
6401 * Calculate and return a value for the IPS driver to use when deciding whether
6402 * we have thermal and power headroom to increase CPU or GPU power budget.
6404 unsigned long i915_read_mch_val(void)
6406 struct drm_i915_private
*dev_priv
;
6407 unsigned long chipset_val
, graphics_val
, ret
= 0;
6409 spin_lock_irq(&mchdev_lock
);
6412 dev_priv
= i915_mch_dev
;
6414 chipset_val
= __i915_chipset_val(dev_priv
);
6415 graphics_val
= __i915_gfx_val(dev_priv
);
6417 ret
= chipset_val
+ graphics_val
;
6420 spin_unlock_irq(&mchdev_lock
);
6424 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
6427 * i915_gpu_raise - raise GPU frequency limit
6429 * Raise the limit; IPS indicates we have thermal headroom.
6431 bool i915_gpu_raise(void)
6433 struct drm_i915_private
*dev_priv
;
6436 spin_lock_irq(&mchdev_lock
);
6437 if (!i915_mch_dev
) {
6441 dev_priv
= i915_mch_dev
;
6443 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
6444 dev_priv
->ips
.max_delay
--;
6447 spin_unlock_irq(&mchdev_lock
);
6451 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
6454 * i915_gpu_lower - lower GPU frequency limit
6456 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6457 * frequency maximum.
6459 bool i915_gpu_lower(void)
6461 struct drm_i915_private
*dev_priv
;
6464 spin_lock_irq(&mchdev_lock
);
6465 if (!i915_mch_dev
) {
6469 dev_priv
= i915_mch_dev
;
6471 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
6472 dev_priv
->ips
.max_delay
++;
6475 spin_unlock_irq(&mchdev_lock
);
6479 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
6482 * i915_gpu_busy - indicate GPU business to IPS
6484 * Tell the IPS driver whether or not the GPU is busy.
6486 bool i915_gpu_busy(void)
6490 spin_lock_irq(&mchdev_lock
);
6492 ret
= i915_mch_dev
->gt
.awake
;
6493 spin_unlock_irq(&mchdev_lock
);
6497 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
6500 * i915_gpu_turbo_disable - disable graphics turbo
6502 * Disable graphics turbo by resetting the max frequency and setting the
6503 * current frequency to the default.
6505 bool i915_gpu_turbo_disable(void)
6507 struct drm_i915_private
*dev_priv
;
6510 spin_lock_irq(&mchdev_lock
);
6511 if (!i915_mch_dev
) {
6515 dev_priv
= i915_mch_dev
;
6517 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
6519 if (!ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
))
6523 spin_unlock_irq(&mchdev_lock
);
6527 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
6530 * Tells the intel_ips driver that the i915 driver is now loaded, if
6531 * IPS got loaded first.
6533 * This awkward dance is so that neither module has to depend on the
6534 * other in order for IPS to do the appropriate communication of
6535 * GPU turbo limits to i915.
6538 ips_ping_for_i915_load(void)
6542 link
= symbol_get(ips_link_to_i915_driver
);
6545 symbol_put(ips_link_to_i915_driver
);
6549 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
6551 /* We only register the i915 ips part with intel-ips once everything is
6552 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6553 spin_lock_irq(&mchdev_lock
);
6554 i915_mch_dev
= dev_priv
;
6555 spin_unlock_irq(&mchdev_lock
);
6557 ips_ping_for_i915_load();
6560 void intel_gpu_ips_teardown(void)
6562 spin_lock_irq(&mchdev_lock
);
6563 i915_mch_dev
= NULL
;
6564 spin_unlock_irq(&mchdev_lock
);
6567 static void intel_init_emon(struct drm_i915_private
*dev_priv
)
6573 /* Disable to program */
6577 /* Program energy weights for various events */
6578 I915_WRITE(SDEW
, 0x15040d00);
6579 I915_WRITE(CSIEW0
, 0x007f0000);
6580 I915_WRITE(CSIEW1
, 0x1e220004);
6581 I915_WRITE(CSIEW2
, 0x04000004);
6583 for (i
= 0; i
< 5; i
++)
6584 I915_WRITE(PEW(i
), 0);
6585 for (i
= 0; i
< 3; i
++)
6586 I915_WRITE(DEW(i
), 0);
6588 /* Program P-state weights to account for frequency power adjustment */
6589 for (i
= 0; i
< 16; i
++) {
6590 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
6591 unsigned long freq
= intel_pxfreq(pxvidfreq
);
6592 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
6597 val
*= (freq
/ 1000);
6599 val
/= (127*127*900);
6601 DRM_ERROR("bad pxval: %ld\n", val
);
6604 /* Render standby states get 0 weight */
6608 for (i
= 0; i
< 4; i
++) {
6609 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
6610 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
6611 I915_WRITE(PXW(i
), val
);
6614 /* Adjust magic regs to magic values (more experimental results) */
6615 I915_WRITE(OGW0
, 0);
6616 I915_WRITE(OGW1
, 0);
6617 I915_WRITE(EG0
, 0x00007f00);
6618 I915_WRITE(EG1
, 0x0000000e);
6619 I915_WRITE(EG2
, 0x000e0000);
6620 I915_WRITE(EG3
, 0x68000300);
6621 I915_WRITE(EG4
, 0x42000000);
6622 I915_WRITE(EG5
, 0x00140031);
6626 for (i
= 0; i
< 8; i
++)
6627 I915_WRITE(PXWL(i
), 0);
6629 /* Enable PMON + select events */
6630 I915_WRITE(ECR
, 0x80000019);
6632 lcfuse
= I915_READ(LCFUSE02
);
6634 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
6637 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6640 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6643 if (!i915
.enable_rc6
) {
6644 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6645 intel_runtime_pm_get(dev_priv
);
6648 mutex_lock(&dev_priv
->drm
.struct_mutex
);
6649 mutex_lock(&dev_priv
->rps
.hw_lock
);
6651 /* Initialize RPS limits (for userspace) */
6652 if (IS_CHERRYVIEW(dev_priv
))
6653 cherryview_init_gt_powersave(dev_priv
);
6654 else if (IS_VALLEYVIEW(dev_priv
))
6655 valleyview_init_gt_powersave(dev_priv
);
6656 else if (INTEL_GEN(dev_priv
) >= 6)
6657 gen6_init_rps_frequencies(dev_priv
);
6659 /* Derive initial user preferences/limits from the hardware limits */
6660 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
6661 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.idle_freq
;
6663 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
6664 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
6666 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
6667 dev_priv
->rps
.min_freq_softlimit
=
6669 dev_priv
->rps
.efficient_freq
,
6670 intel_freq_opcode(dev_priv
, 450));
6672 /* After setting max-softlimit, find the overclock max freq */
6673 if (IS_GEN6(dev_priv
) ||
6674 IS_IVYBRIDGE(dev_priv
) || IS_HASWELL(dev_priv
)) {
6677 sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, ¶ms
);
6678 if (params
& BIT(31)) { /* OC supported */
6679 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6680 (dev_priv
->rps
.max_freq
& 0xff) * 50,
6681 (params
& 0xff) * 50);
6682 dev_priv
->rps
.max_freq
= params
& 0xff;
6686 /* Finally allow us to boost to max by default */
6687 dev_priv
->rps
.boost_freq
= dev_priv
->rps
.max_freq
;
6689 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6690 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
6692 intel_autoenable_gt_powersave(dev_priv
);
6695 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
6697 if (IS_VALLEYVIEW(dev_priv
))
6698 valleyview_cleanup_gt_powersave(dev_priv
);
6700 if (!i915
.enable_rc6
)
6701 intel_runtime_pm_put(dev_priv
);
6705 * intel_suspend_gt_powersave - suspend PM work and helper threads
6706 * @dev_priv: i915 device
6708 * We don't want to disable RC6 or other features here, we just want
6709 * to make sure any work we've queued has finished and won't bother
6710 * us while we're suspended.
6712 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
)
6714 if (INTEL_GEN(dev_priv
) < 6)
6717 if (cancel_delayed_work_sync(&dev_priv
->rps
.autoenable_work
))
6718 intel_runtime_pm_put(dev_priv
);
6720 /* gen6_rps_idle() will be called later to disable interrupts */
6723 void intel_sanitize_gt_powersave(struct drm_i915_private
*dev_priv
)
6725 dev_priv
->rps
.enabled
= true; /* force disabling */
6726 intel_disable_gt_powersave(dev_priv
);
6728 gen6_reset_rps_interrupts(dev_priv
);
6731 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
)
6733 if (!READ_ONCE(dev_priv
->rps
.enabled
))
6736 mutex_lock(&dev_priv
->rps
.hw_lock
);
6738 if (INTEL_GEN(dev_priv
) >= 9) {
6739 gen9_disable_rc6(dev_priv
);
6740 gen9_disable_rps(dev_priv
);
6741 } else if (IS_CHERRYVIEW(dev_priv
)) {
6742 cherryview_disable_rps(dev_priv
);
6743 } else if (IS_VALLEYVIEW(dev_priv
)) {
6744 valleyview_disable_rps(dev_priv
);
6745 } else if (INTEL_GEN(dev_priv
) >= 6) {
6746 gen6_disable_rps(dev_priv
);
6747 } else if (IS_IRONLAKE_M(dev_priv
)) {
6748 ironlake_disable_drps(dev_priv
);
6751 dev_priv
->rps
.enabled
= false;
6752 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6755 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
)
6757 /* We shouldn't be disabling as we submit, so this should be less
6758 * racy than it appears!
6760 if (READ_ONCE(dev_priv
->rps
.enabled
))
6763 /* Powersaving is controlled by the host when inside a VM */
6764 if (intel_vgpu_active(dev_priv
))
6767 mutex_lock(&dev_priv
->rps
.hw_lock
);
6769 if (IS_CHERRYVIEW(dev_priv
)) {
6770 cherryview_enable_rps(dev_priv
);
6771 } else if (IS_VALLEYVIEW(dev_priv
)) {
6772 valleyview_enable_rps(dev_priv
);
6773 } else if (INTEL_GEN(dev_priv
) >= 9) {
6774 gen9_enable_rc6(dev_priv
);
6775 gen9_enable_rps(dev_priv
);
6776 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
6777 gen6_update_ring_freq(dev_priv
);
6778 } else if (IS_BROADWELL(dev_priv
)) {
6779 gen8_enable_rps(dev_priv
);
6780 gen6_update_ring_freq(dev_priv
);
6781 } else if (INTEL_GEN(dev_priv
) >= 6) {
6782 gen6_enable_rps(dev_priv
);
6783 gen6_update_ring_freq(dev_priv
);
6784 } else if (IS_IRONLAKE_M(dev_priv
)) {
6785 ironlake_enable_drps(dev_priv
);
6786 intel_init_emon(dev_priv
);
6789 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
6790 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
6792 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
6793 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
6795 dev_priv
->rps
.enabled
= true;
6796 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6799 static void __intel_autoenable_gt_powersave(struct work_struct
*work
)
6801 struct drm_i915_private
*dev_priv
=
6802 container_of(work
, typeof(*dev_priv
), rps
.autoenable_work
.work
);
6803 struct intel_engine_cs
*rcs
;
6804 struct drm_i915_gem_request
*req
;
6806 if (READ_ONCE(dev_priv
->rps
.enabled
))
6809 rcs
= dev_priv
->engine
[RCS
];
6810 if (rcs
->last_context
)
6813 if (!rcs
->init_context
)
6816 mutex_lock(&dev_priv
->drm
.struct_mutex
);
6818 req
= i915_gem_request_alloc(rcs
, dev_priv
->kernel_context
);
6822 if (!i915
.enable_execlists
&& i915_switch_context(req
) == 0)
6823 rcs
->init_context(req
);
6825 /* Mark the device busy, calling intel_enable_gt_powersave() */
6826 i915_add_request_no_flush(req
);
6829 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
6831 intel_runtime_pm_put(dev_priv
);
6834 void intel_autoenable_gt_powersave(struct drm_i915_private
*dev_priv
)
6836 if (READ_ONCE(dev_priv
->rps
.enabled
))
6839 if (IS_IRONLAKE_M(dev_priv
)) {
6840 ironlake_enable_drps(dev_priv
);
6841 intel_init_emon(dev_priv
);
6842 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
6844 * PCU communication is slow and this doesn't need to be
6845 * done at any specific time, so do this out of our fast path
6846 * to make resume and init faster.
6848 * We depend on the HW RC6 power context save/restore
6849 * mechanism when entering D3 through runtime PM suspend. So
6850 * disable RPM until RPS/RC6 is properly setup. We can only
6851 * get here via the driver load/system resume/runtime resume
6852 * paths, so the _noresume version is enough (and in case of
6853 * runtime resume it's necessary).
6855 if (queue_delayed_work(dev_priv
->wq
,
6856 &dev_priv
->rps
.autoenable_work
,
6857 round_jiffies_up_relative(HZ
)))
6858 intel_runtime_pm_get_noresume(dev_priv
);
6862 static void ibx_init_clock_gating(struct drm_i915_private
*dev_priv
)
6865 * On Ibex Peak and Cougar Point, we need to disable clock
6866 * gating for the panel power sequencer or it will fail to
6867 * start up when no ports are active.
6869 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
6872 static void g4x_disable_trickle_feed(struct drm_i915_private
*dev_priv
)
6876 for_each_pipe(dev_priv
, pipe
) {
6877 I915_WRITE(DSPCNTR(pipe
),
6878 I915_READ(DSPCNTR(pipe
)) |
6879 DISPPLANE_TRICKLE_FEED_DISABLE
);
6881 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
6882 POSTING_READ(DSPSURF(pipe
));
6886 static void ilk_init_lp_watermarks(struct drm_i915_private
*dev_priv
)
6888 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
6889 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
6890 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
6893 * Don't touch WM1S_LP_EN here.
6894 * Doing so could cause underruns.
6898 static void ironlake_init_clock_gating(struct drm_i915_private
*dev_priv
)
6900 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6904 * WaFbcDisableDpfcClockGating:ilk
6906 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
6907 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
6908 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
6910 I915_WRITE(PCH_3DCGDIS0
,
6911 MARIUNIT_CLOCK_GATE_DISABLE
|
6912 SVSMUNIT_CLOCK_GATE_DISABLE
);
6913 I915_WRITE(PCH_3DCGDIS1
,
6914 VFMUNIT_CLOCK_GATE_DISABLE
);
6917 * According to the spec the following bits should be set in
6918 * order to enable memory self-refresh
6919 * The bit 22/21 of 0x42004
6920 * The bit 5 of 0x42020
6921 * The bit 15 of 0x45000
6923 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6924 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
6925 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
6926 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
6927 I915_WRITE(DISP_ARB_CTL
,
6928 (I915_READ(DISP_ARB_CTL
) |
6931 ilk_init_lp_watermarks(dev_priv
);
6934 * Based on the document from hardware guys the following bits
6935 * should be set unconditionally in order to enable FBC.
6936 * The bit 22 of 0x42000
6937 * The bit 22 of 0x42004
6938 * The bit 7,8,9 of 0x42020.
6940 if (IS_IRONLAKE_M(dev_priv
)) {
6941 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6942 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6943 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6945 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6946 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6950 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6952 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6953 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6954 ILK_ELPIN_409_SELECT
);
6955 I915_WRITE(_3D_CHICKEN2
,
6956 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
6957 _3D_CHICKEN2_WM_READ_PIPELINED
);
6959 /* WaDisableRenderCachePipelinedFlush:ilk */
6960 I915_WRITE(CACHE_MODE_0
,
6961 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6963 /* WaDisable_RenderCache_OperationalFlush:ilk */
6964 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6966 g4x_disable_trickle_feed(dev_priv
);
6968 ibx_init_clock_gating(dev_priv
);
6971 static void cpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
6977 * On Ibex Peak and Cougar Point, we need to disable clock
6978 * gating for the panel power sequencer or it will fail to
6979 * start up when no ports are active.
6981 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
6982 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
6983 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
6984 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
6985 DPLS_EDP_PPS_FIX_DIS
);
6986 /* The below fixes the weird display corruption, a few pixels shifted
6987 * downward, on (only) LVDS of some HP laptops with IVY.
6989 for_each_pipe(dev_priv
, pipe
) {
6990 val
= I915_READ(TRANS_CHICKEN2(pipe
));
6991 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
6992 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6993 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
6994 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6995 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
6996 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
6997 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
6998 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
7000 /* WADP0ClockGatingDisable */
7001 for_each_pipe(dev_priv
, pipe
) {
7002 I915_WRITE(TRANS_CHICKEN1(pipe
),
7003 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
7007 static void gen6_check_mch_setup(struct drm_i915_private
*dev_priv
)
7011 tmp
= I915_READ(MCH_SSKPD
);
7012 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
7013 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7017 static void gen6_init_clock_gating(struct drm_i915_private
*dev_priv
)
7019 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
7021 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
7023 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7024 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7025 ILK_ELPIN_409_SELECT
);
7027 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
7028 I915_WRITE(_3D_CHICKEN
,
7029 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
7031 /* WaDisable_RenderCache_OperationalFlush:snb */
7032 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7035 * BSpec recoomends 8x4 when MSAA is used,
7036 * however in practice 16x4 seems fastest.
7038 * Note that PS/WM thread counts depend on the WIZ hashing
7039 * disable bit, which we don't touch here, but it's good
7040 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7042 I915_WRITE(GEN6_GT_MODE
,
7043 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7045 ilk_init_lp_watermarks(dev_priv
);
7047 I915_WRITE(CACHE_MODE_0
,
7048 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
7050 I915_WRITE(GEN6_UCGCTL1
,
7051 I915_READ(GEN6_UCGCTL1
) |
7052 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
7053 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
7055 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7056 * gating disable must be set. Failure to set it results in
7057 * flickering pixels due to Z write ordering failures after
7058 * some amount of runtime in the Mesa "fire" demo, and Unigine
7059 * Sanctuary and Tropics, and apparently anything else with
7060 * alpha test or pixel discard.
7062 * According to the spec, bit 11 (RCCUNIT) must also be set,
7063 * but we didn't debug actual testcases to find it out.
7065 * WaDisableRCCUnitClockGating:snb
7066 * WaDisableRCPBUnitClockGating:snb
7068 I915_WRITE(GEN6_UCGCTL2
,
7069 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
7070 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
7072 /* WaStripsFansDisableFastClipPerformanceFix:snb */
7073 I915_WRITE(_3D_CHICKEN3
,
7074 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
7078 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7079 * 3DSTATE_SF number of SF output attributes is more than 16."
7081 I915_WRITE(_3D_CHICKEN3
,
7082 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
7085 * According to the spec the following bits should be
7086 * set in order to enable memory self-refresh and fbc:
7087 * The bit21 and bit22 of 0x42000
7088 * The bit21 and bit22 of 0x42004
7089 * The bit5 and bit7 of 0x42020
7090 * The bit14 of 0x70180
7091 * The bit14 of 0x71180
7093 * WaFbcAsynchFlipDisableFbcQueue:snb
7095 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
7096 I915_READ(ILK_DISPLAY_CHICKEN1
) |
7097 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
7098 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
7099 I915_READ(ILK_DISPLAY_CHICKEN2
) |
7100 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
7101 I915_WRITE(ILK_DSPCLK_GATE_D
,
7102 I915_READ(ILK_DSPCLK_GATE_D
) |
7103 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
7104 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
7106 g4x_disable_trickle_feed(dev_priv
);
7108 cpt_init_clock_gating(dev_priv
);
7110 gen6_check_mch_setup(dev_priv
);
7113 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
7115 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
7118 * WaVSThreadDispatchOverride:ivb,vlv
7120 * This actually overrides the dispatch
7121 * mode for all thread types.
7123 reg
&= ~GEN7_FF_SCHED_MASK
;
7124 reg
|= GEN7_FF_TS_SCHED_HW
;
7125 reg
|= GEN7_FF_VS_SCHED_HW
;
7126 reg
|= GEN7_FF_DS_SCHED_HW
;
7128 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
7131 static void lpt_init_clock_gating(struct drm_i915_private
*dev_priv
)
7134 * TODO: this bit should only be enabled when really needed, then
7135 * disabled when not needed anymore in order to save power.
7137 if (HAS_PCH_LPT_LP(dev_priv
))
7138 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
7139 I915_READ(SOUTH_DSPCLK_GATE_D
) |
7140 PCH_LP_PARTITION_LEVEL_DISABLE
);
7142 /* WADPOClockGatingDisable:hsw */
7143 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
7144 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
7145 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
7148 static void lpt_suspend_hw(struct drm_i915_private
*dev_priv
)
7150 if (HAS_PCH_LPT_LP(dev_priv
)) {
7151 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7153 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7154 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7158 static void gen8_set_l3sqc_credits(struct drm_i915_private
*dev_priv
,
7159 int general_prio_credits
,
7160 int high_prio_credits
)
7164 /* WaTempDisableDOPClkGating:bdw */
7165 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
7166 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
7168 I915_WRITE(GEN8_L3SQCREG1
,
7169 L3_GENERAL_PRIO_CREDITS(general_prio_credits
) |
7170 L3_HIGH_PRIO_CREDITS(high_prio_credits
));
7173 * Wait at least 100 clocks before re-enabling clock gating.
7174 * See the definition of L3SQCREG1 in BSpec.
7176 POSTING_READ(GEN8_L3SQCREG1
);
7178 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
7181 static void kabylake_init_clock_gating(struct drm_i915_private
*dev_priv
)
7183 gen9_init_clock_gating(dev_priv
);
7185 /* WaDisableSDEUnitClockGating:kbl */
7186 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
7187 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7188 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7190 /* WaDisableGamClockGating:kbl */
7191 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
7192 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
7193 GEN6_GAMUNIT_CLOCK_GATE_DISABLE
);
7195 /* WaFbcNukeOnHostModify:kbl */
7196 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
7197 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
7200 static void skylake_init_clock_gating(struct drm_i915_private
*dev_priv
)
7202 gen9_init_clock_gating(dev_priv
);
7204 /* WAC6entrylatency:skl */
7205 I915_WRITE(FBC_LLC_READ_CTRL
, I915_READ(FBC_LLC_READ_CTRL
) |
7206 FBC_LLC_FULLY_OPEN
);
7208 /* WaFbcNukeOnHostModify:skl */
7209 I915_WRITE(ILK_DPFC_CHICKEN
, I915_READ(ILK_DPFC_CHICKEN
) |
7210 ILK_DPFC_NUKE_ON_ANY_MODIFICATION
);
7213 static void broadwell_init_clock_gating(struct drm_i915_private
*dev_priv
)
7217 ilk_init_lp_watermarks(dev_priv
);
7219 /* WaSwitchSolVfFArbitrationPriority:bdw */
7220 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
7222 /* WaPsrDPAMaskVBlankInSRD:bdw */
7223 I915_WRITE(CHICKEN_PAR1_1
,
7224 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
7226 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7227 for_each_pipe(dev_priv
, pipe
) {
7228 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
7229 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
7230 BDW_DPRS_MASK_VBLANK_SRD
);
7233 /* WaVSRefCountFullforceMissDisable:bdw */
7234 /* WaDSRefCountFullforceMissDisable:bdw */
7235 I915_WRITE(GEN7_FF_THREAD_MODE
,
7236 I915_READ(GEN7_FF_THREAD_MODE
) &
7237 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7239 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7240 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7242 /* WaDisableSDEUnitClockGating:bdw */
7243 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7244 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7246 /* WaProgramL3SqcReg1Default:bdw */
7247 gen8_set_l3sqc_credits(dev_priv
, 30, 2);
7250 * WaGttCachingOffByDefault:bdw
7251 * GTT cache may not work with big pages, so if those
7252 * are ever enabled GTT cache may need to be disabled.
7254 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7256 /* WaKVMNotificationOnConfigChange:bdw */
7257 I915_WRITE(CHICKEN_PAR2_1
, I915_READ(CHICKEN_PAR2_1
)
7258 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
);
7260 lpt_init_clock_gating(dev_priv
);
7263 static void haswell_init_clock_gating(struct drm_i915_private
*dev_priv
)
7265 ilk_init_lp_watermarks(dev_priv
);
7267 /* L3 caching of data atomics doesn't work -- disable it. */
7268 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
7269 I915_WRITE(HSW_ROW_CHICKEN3
,
7270 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
7272 /* This is required by WaCatErrorRejectionIssue:hsw */
7273 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7274 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7275 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7277 /* WaVSRefCountFullforceMissDisable:hsw */
7278 I915_WRITE(GEN7_FF_THREAD_MODE
,
7279 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
7281 /* WaDisable_RenderCache_OperationalFlush:hsw */
7282 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7284 /* enable HiZ Raw Stall Optimization */
7285 I915_WRITE(CACHE_MODE_0_GEN7
,
7286 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
7288 /* WaDisable4x2SubspanOptimization:hsw */
7289 I915_WRITE(CACHE_MODE_1
,
7290 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7293 * BSpec recommends 8x4 when MSAA is used,
7294 * however in practice 16x4 seems fastest.
7296 * Note that PS/WM thread counts depend on the WIZ hashing
7297 * disable bit, which we don't touch here, but it's good
7298 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7300 I915_WRITE(GEN7_GT_MODE
,
7301 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7303 /* WaSampleCChickenBitEnable:hsw */
7304 I915_WRITE(HALF_SLICE_CHICKEN3
,
7305 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
7307 /* WaSwitchSolVfFArbitrationPriority:hsw */
7308 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
7310 /* WaRsPkgCStateDisplayPMReq:hsw */
7311 I915_WRITE(CHICKEN_PAR1_1
,
7312 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
7314 lpt_init_clock_gating(dev_priv
);
7317 static void ivybridge_init_clock_gating(struct drm_i915_private
*dev_priv
)
7321 ilk_init_lp_watermarks(dev_priv
);
7323 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
7325 /* WaDisableEarlyCull:ivb */
7326 I915_WRITE(_3D_CHICKEN3
,
7327 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
7329 /* WaDisableBackToBackFlipFix:ivb */
7330 I915_WRITE(IVB_CHICKEN3
,
7331 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
7332 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
7334 /* WaDisablePSDDualDispatchEnable:ivb */
7335 if (IS_IVB_GT1(dev_priv
))
7336 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
7337 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
7339 /* WaDisable_RenderCache_OperationalFlush:ivb */
7340 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7342 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7343 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
7344 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
7346 /* WaApplyL3ControlAndL3ChickenMode:ivb */
7347 I915_WRITE(GEN7_L3CNTLREG1
,
7348 GEN7_WA_FOR_GEN7_L3_CONTROL
);
7349 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
7350 GEN7_WA_L3_CHICKEN_MODE
);
7351 if (IS_IVB_GT1(dev_priv
))
7352 I915_WRITE(GEN7_ROW_CHICKEN2
,
7353 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7355 /* must write both registers */
7356 I915_WRITE(GEN7_ROW_CHICKEN2
,
7357 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7358 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
7359 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7362 /* WaForceL3Serialization:ivb */
7363 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
7364 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
7367 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7368 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7370 I915_WRITE(GEN6_UCGCTL2
,
7371 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
7373 /* This is required by WaCatErrorRejectionIssue:ivb */
7374 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7375 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7376 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7378 g4x_disable_trickle_feed(dev_priv
);
7380 gen7_setup_fixed_func_scheduler(dev_priv
);
7382 if (0) { /* causes HiZ corruption on ivb:gt1 */
7383 /* enable HiZ Raw Stall Optimization */
7384 I915_WRITE(CACHE_MODE_0_GEN7
,
7385 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
7388 /* WaDisable4x2SubspanOptimization:ivb */
7389 I915_WRITE(CACHE_MODE_1
,
7390 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7393 * BSpec recommends 8x4 when MSAA is used,
7394 * however in practice 16x4 seems fastest.
7396 * Note that PS/WM thread counts depend on the WIZ hashing
7397 * disable bit, which we don't touch here, but it's good
7398 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7400 I915_WRITE(GEN7_GT_MODE
,
7401 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7403 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
7404 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
7405 snpcr
|= GEN6_MBC_SNPCR_MED
;
7406 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
7408 if (!HAS_PCH_NOP(dev_priv
))
7409 cpt_init_clock_gating(dev_priv
);
7411 gen6_check_mch_setup(dev_priv
);
7414 static void valleyview_init_clock_gating(struct drm_i915_private
*dev_priv
)
7416 /* WaDisableEarlyCull:vlv */
7417 I915_WRITE(_3D_CHICKEN3
,
7418 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
7420 /* WaDisableBackToBackFlipFix:vlv */
7421 I915_WRITE(IVB_CHICKEN3
,
7422 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
7423 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
7425 /* WaPsdDispatchEnable:vlv */
7426 /* WaDisablePSDDualDispatchEnable:vlv */
7427 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
7428 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
7429 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
7431 /* WaDisable_RenderCache_OperationalFlush:vlv */
7432 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7434 /* WaForceL3Serialization:vlv */
7435 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
7436 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
7438 /* WaDisableDopClockGating:vlv */
7439 I915_WRITE(GEN7_ROW_CHICKEN2
,
7440 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
7442 /* This is required by WaCatErrorRejectionIssue:vlv */
7443 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
7444 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
7445 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
7447 gen7_setup_fixed_func_scheduler(dev_priv
);
7450 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7451 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7453 I915_WRITE(GEN6_UCGCTL2
,
7454 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
7456 /* WaDisableL3Bank2xClockGate:vlv
7457 * Disabling L3 clock gating- MMIO 940c[25] = 1
7458 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7459 I915_WRITE(GEN7_UCGCTL4
,
7460 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
7463 * BSpec says this must be set, even though
7464 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7466 I915_WRITE(CACHE_MODE_1
,
7467 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
7470 * BSpec recommends 8x4 when MSAA is used,
7471 * however in practice 16x4 seems fastest.
7473 * Note that PS/WM thread counts depend on the WIZ hashing
7474 * disable bit, which we don't touch here, but it's good
7475 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7477 I915_WRITE(GEN7_GT_MODE
,
7478 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
7481 * WaIncreaseL3CreditsForVLVB0:vlv
7482 * This is the hardware default actually.
7484 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
7487 * WaDisableVLVClockGating_VBIIssue:vlv
7488 * Disable clock gating on th GCFG unit to prevent a delay
7489 * in the reporting of vblank events.
7491 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
7494 static void cherryview_init_clock_gating(struct drm_i915_private
*dev_priv
)
7496 /* WaVSRefCountFullforceMissDisable:chv */
7497 /* WaDSRefCountFullforceMissDisable:chv */
7498 I915_WRITE(GEN7_FF_THREAD_MODE
,
7499 I915_READ(GEN7_FF_THREAD_MODE
) &
7500 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7502 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7503 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7504 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7506 /* WaDisableCSUnitClockGating:chv */
7507 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
7508 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
7510 /* WaDisableSDEUnitClockGating:chv */
7511 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7512 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7515 * WaProgramL3SqcReg1Default:chv
7516 * See gfxspecs/Related Documents/Performance Guide/
7517 * LSQC Setting Recommendations.
7519 gen8_set_l3sqc_credits(dev_priv
, 38, 2);
7522 * GTT cache may not work with big pages, so if those
7523 * are ever enabled GTT cache may need to be disabled.
7525 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7528 static void g4x_init_clock_gating(struct drm_i915_private
*dev_priv
)
7530 uint32_t dspclk_gate
;
7532 I915_WRITE(RENCLK_GATE_D1
, 0);
7533 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
7534 GS_UNIT_CLOCK_GATE_DISABLE
|
7535 CL_UNIT_CLOCK_GATE_DISABLE
);
7536 I915_WRITE(RAMCLK_GATE_D
, 0);
7537 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
7538 OVRUNIT_CLOCK_GATE_DISABLE
|
7539 OVCUNIT_CLOCK_GATE_DISABLE
;
7540 if (IS_GM45(dev_priv
))
7541 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
7542 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
7544 /* WaDisableRenderCachePipelinedFlush */
7545 I915_WRITE(CACHE_MODE_0
,
7546 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
7548 /* WaDisable_RenderCache_OperationalFlush:g4x */
7549 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7551 g4x_disable_trickle_feed(dev_priv
);
7554 static void crestline_init_clock_gating(struct drm_i915_private
*dev_priv
)
7556 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
7557 I915_WRITE(RENCLK_GATE_D2
, 0);
7558 I915_WRITE(DSPCLK_GATE_D
, 0);
7559 I915_WRITE(RAMCLK_GATE_D
, 0);
7560 I915_WRITE16(DEUC
, 0);
7561 I915_WRITE(MI_ARB_STATE
,
7562 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7564 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7565 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7568 static void broadwater_init_clock_gating(struct drm_i915_private
*dev_priv
)
7570 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
7571 I965_RCC_CLOCK_GATE_DISABLE
|
7572 I965_RCPB_CLOCK_GATE_DISABLE
|
7573 I965_ISC_CLOCK_GATE_DISABLE
|
7574 I965_FBC_CLOCK_GATE_DISABLE
);
7575 I915_WRITE(RENCLK_GATE_D2
, 0);
7576 I915_WRITE(MI_ARB_STATE
,
7577 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7579 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7580 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7583 static void gen3_init_clock_gating(struct drm_i915_private
*dev_priv
)
7585 u32 dstate
= I915_READ(D_STATE
);
7587 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
7588 DSTATE_DOT_CLOCK_GATING
;
7589 I915_WRITE(D_STATE
, dstate
);
7591 if (IS_PINEVIEW(dev_priv
))
7592 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
7594 /* IIR "flip pending" means done if this bit is set */
7595 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
7597 /* interrupts should cause a wake up from C3 */
7598 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
7600 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7601 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
7603 I915_WRITE(MI_ARB_STATE
,
7604 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7607 static void i85x_init_clock_gating(struct drm_i915_private
*dev_priv
)
7609 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
7611 /* interrupts should cause a wake up from C3 */
7612 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
7613 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
7615 I915_WRITE(MEM_MODE
,
7616 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
7619 static void i830_init_clock_gating(struct drm_i915_private
*dev_priv
)
7621 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
7623 I915_WRITE(MEM_MODE
,
7624 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
7625 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
7628 void intel_init_clock_gating(struct drm_i915_private
*dev_priv
)
7630 dev_priv
->display
.init_clock_gating(dev_priv
);
7633 void intel_suspend_hw(struct drm_i915_private
*dev_priv
)
7635 if (HAS_PCH_LPT(dev_priv
))
7636 lpt_suspend_hw(dev_priv
);
7639 static void nop_init_clock_gating(struct drm_i915_private
*dev_priv
)
7641 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7645 * intel_init_clock_gating_hooks - setup the clock gating hooks
7646 * @dev_priv: device private
7648 * Setup the hooks that configure which clocks of a given platform can be
7649 * gated and also apply various GT and display specific workarounds for these
7650 * platforms. Note that some GT specific workarounds are applied separately
7651 * when GPU contexts or batchbuffers start their execution.
7653 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
)
7655 if (IS_SKYLAKE(dev_priv
))
7656 dev_priv
->display
.init_clock_gating
= skylake_init_clock_gating
;
7657 else if (IS_KABYLAKE(dev_priv
))
7658 dev_priv
->display
.init_clock_gating
= kabylake_init_clock_gating
;
7659 else if (IS_BROXTON(dev_priv
))
7660 dev_priv
->display
.init_clock_gating
= bxt_init_clock_gating
;
7661 else if (IS_BROADWELL(dev_priv
))
7662 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
7663 else if (IS_CHERRYVIEW(dev_priv
))
7664 dev_priv
->display
.init_clock_gating
= cherryview_init_clock_gating
;
7665 else if (IS_HASWELL(dev_priv
))
7666 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
7667 else if (IS_IVYBRIDGE(dev_priv
))
7668 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7669 else if (IS_VALLEYVIEW(dev_priv
))
7670 dev_priv
->display
.init_clock_gating
= valleyview_init_clock_gating
;
7671 else if (IS_GEN6(dev_priv
))
7672 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7673 else if (IS_GEN5(dev_priv
))
7674 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
7675 else if (IS_G4X(dev_priv
))
7676 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
7677 else if (IS_CRESTLINE(dev_priv
))
7678 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7679 else if (IS_BROADWATER(dev_priv
))
7680 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7681 else if (IS_GEN3(dev_priv
))
7682 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7683 else if (IS_I85X(dev_priv
) || IS_I865G(dev_priv
))
7684 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7685 else if (IS_GEN2(dev_priv
))
7686 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7688 MISSING_CASE(INTEL_DEVID(dev_priv
));
7689 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
7693 /* Set up chip specific power management-related functions */
7694 void intel_init_pm(struct drm_i915_private
*dev_priv
)
7696 intel_fbc_init(dev_priv
);
7699 if (IS_PINEVIEW(dev_priv
))
7700 i915_pineview_get_mem_freq(dev_priv
);
7701 else if (IS_GEN5(dev_priv
))
7702 i915_ironlake_get_mem_freq(dev_priv
);
7704 /* For FIFO watermark updates */
7705 if (INTEL_GEN(dev_priv
) >= 9) {
7706 skl_setup_wm_latency(dev_priv
);
7707 dev_priv
->display
.initial_watermarks
= skl_initial_wm
;
7708 dev_priv
->display
.atomic_update_watermarks
= skl_atomic_update_crtc_wm
;
7709 dev_priv
->display
.compute_global_watermarks
= skl_compute_wm
;
7710 } else if (HAS_PCH_SPLIT(dev_priv
)) {
7711 ilk_setup_wm_latency(dev_priv
);
7713 if ((IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[1] &&
7714 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
7715 (!IS_GEN5(dev_priv
) && dev_priv
->wm
.pri_latency
[0] &&
7716 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
7717 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
7718 dev_priv
->display
.compute_intermediate_wm
=
7719 ilk_compute_intermediate_wm
;
7720 dev_priv
->display
.initial_watermarks
=
7721 ilk_initial_watermarks
;
7722 dev_priv
->display
.optimize_watermarks
=
7723 ilk_optimize_watermarks
;
7725 DRM_DEBUG_KMS("Failed to read display plane latency. "
7728 } else if (IS_CHERRYVIEW(dev_priv
)) {
7729 vlv_setup_wm_latency(dev_priv
);
7730 dev_priv
->display
.update_wm
= vlv_update_wm
;
7731 } else if (IS_VALLEYVIEW(dev_priv
)) {
7732 vlv_setup_wm_latency(dev_priv
);
7733 dev_priv
->display
.update_wm
= vlv_update_wm
;
7734 } else if (IS_PINEVIEW(dev_priv
)) {
7735 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv
),
7738 dev_priv
->mem_freq
)) {
7739 DRM_INFO("failed to find known CxSR latency "
7740 "(found ddr%s fsb freq %d, mem freq %d), "
7742 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
7743 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7744 /* Disable CxSR and never update its watermark again */
7745 intel_set_memory_cxsr(dev_priv
, false);
7746 dev_priv
->display
.update_wm
= NULL
;
7748 dev_priv
->display
.update_wm
= pineview_update_wm
;
7749 } else if (IS_G4X(dev_priv
)) {
7750 dev_priv
->display
.update_wm
= g4x_update_wm
;
7751 } else if (IS_GEN4(dev_priv
)) {
7752 dev_priv
->display
.update_wm
= i965_update_wm
;
7753 } else if (IS_GEN3(dev_priv
)) {
7754 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7755 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7756 } else if (IS_GEN2(dev_priv
)) {
7757 if (INTEL_INFO(dev_priv
)->num_pipes
== 1) {
7758 dev_priv
->display
.update_wm
= i845_update_wm
;
7759 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7761 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7762 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7765 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7769 static inline int gen6_check_mailbox_status(struct drm_i915_private
*dev_priv
)
7772 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
7775 case GEN6_PCODE_SUCCESS
:
7777 case GEN6_PCODE_UNIMPLEMENTED_CMD
:
7778 case GEN6_PCODE_ILLEGAL_CMD
:
7780 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
7781 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
7783 case GEN6_PCODE_TIMEOUT
:
7791 static inline int gen7_check_mailbox_status(struct drm_i915_private
*dev_priv
)
7794 I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_ERROR_MASK
;
7797 case GEN6_PCODE_SUCCESS
:
7799 case GEN6_PCODE_ILLEGAL_CMD
:
7801 case GEN7_PCODE_TIMEOUT
:
7803 case GEN7_PCODE_ILLEGAL_DATA
:
7805 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE
:
7808 MISSING_CASE(flags
);
7813 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
7817 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7819 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7820 * use te fw I915_READ variants to reduce the amount of work
7821 * required when reading/writing.
7824 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7825 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7829 I915_WRITE_FW(GEN6_PCODE_DATA
, *val
);
7830 I915_WRITE_FW(GEN6_PCODE_DATA1
, 0);
7831 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7833 if (intel_wait_for_register_fw(dev_priv
,
7834 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
7836 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
7840 *val
= I915_READ_FW(GEN6_PCODE_DATA
);
7841 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
7843 if (INTEL_GEN(dev_priv
) > 6)
7844 status
= gen7_check_mailbox_status(dev_priv
);
7846 status
= gen6_check_mailbox_status(dev_priv
);
7849 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7857 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
,
7862 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7864 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7865 * use te fw I915_READ variants to reduce the amount of work
7866 * required when reading/writing.
7869 if (I915_READ_FW(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7870 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7874 I915_WRITE_FW(GEN6_PCODE_DATA
, val
);
7875 I915_WRITE_FW(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7877 if (intel_wait_for_register_fw(dev_priv
,
7878 GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
, 0,
7880 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
7884 I915_WRITE_FW(GEN6_PCODE_DATA
, 0);
7886 if (INTEL_GEN(dev_priv
) > 6)
7887 status
= gen7_check_mailbox_status(dev_priv
);
7889 status
= gen6_check_mailbox_status(dev_priv
);
7892 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7900 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7904 * Slow = Fast = GPLL ref * N
7906 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* (val
- 0xb7), 1000);
7909 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7911 return DIV_ROUND_CLOSEST(1000 * val
, dev_priv
->rps
.gpll_ref_freq
) + 0xb7;
7914 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7918 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7920 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* val
, 2 * 2 * 1000);
7923 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7925 /* CHV needs even values */
7926 return DIV_ROUND_CLOSEST(2 * 1000 * val
, dev_priv
->rps
.gpll_ref_freq
) * 2;
7929 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7931 if (IS_GEN9(dev_priv
))
7932 return DIV_ROUND_CLOSEST(val
* GT_FREQUENCY_MULTIPLIER
,
7934 else if (IS_CHERRYVIEW(dev_priv
))
7935 return chv_gpu_freq(dev_priv
, val
);
7936 else if (IS_VALLEYVIEW(dev_priv
))
7937 return byt_gpu_freq(dev_priv
, val
);
7939 return val
* GT_FREQUENCY_MULTIPLIER
;
7942 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7944 if (IS_GEN9(dev_priv
))
7945 return DIV_ROUND_CLOSEST(val
* GEN9_FREQ_SCALER
,
7946 GT_FREQUENCY_MULTIPLIER
);
7947 else if (IS_CHERRYVIEW(dev_priv
))
7948 return chv_freq_opcode(dev_priv
, val
);
7949 else if (IS_VALLEYVIEW(dev_priv
))
7950 return byt_freq_opcode(dev_priv
, val
);
7952 return DIV_ROUND_CLOSEST(val
, GT_FREQUENCY_MULTIPLIER
);
7955 struct request_boost
{
7956 struct work_struct work
;
7957 struct drm_i915_gem_request
*req
;
7960 static void __intel_rps_boost_work(struct work_struct
*work
)
7962 struct request_boost
*boost
= container_of(work
, struct request_boost
, work
);
7963 struct drm_i915_gem_request
*req
= boost
->req
;
7965 if (!i915_gem_request_completed(req
))
7966 gen6_rps_boost(req
->i915
, NULL
, req
->emitted_jiffies
);
7968 i915_gem_request_put(req
);
7972 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
)
7974 struct request_boost
*boost
;
7976 if (req
== NULL
|| INTEL_GEN(req
->i915
) < 6)
7979 if (i915_gem_request_completed(req
))
7982 boost
= kmalloc(sizeof(*boost
), GFP_ATOMIC
);
7986 boost
->req
= i915_gem_request_get(req
);
7988 INIT_WORK(&boost
->work
, __intel_rps_boost_work
);
7989 queue_work(req
->i915
->wq
, &boost
->work
);
7992 void intel_pm_setup(struct drm_device
*dev
)
7994 struct drm_i915_private
*dev_priv
= to_i915(dev
);
7996 mutex_init(&dev_priv
->rps
.hw_lock
);
7997 spin_lock_init(&dev_priv
->rps
.client_lock
);
7999 INIT_DELAYED_WORK(&dev_priv
->rps
.autoenable_work
,
8000 __intel_autoenable_gt_powersave
);
8001 INIT_LIST_HEAD(&dev_priv
->rps
.clients
);
8003 dev_priv
->pm
.suspended
= false;
8004 atomic_set(&dev_priv
->pm
.wakeref_count
, 0);