2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
53 #define INTEL_RC6_ENABLE (1<<0)
54 #define INTEL_RC6p_ENABLE (1<<1)
55 #define INTEL_RC6pp_ENABLE (1<<2)
57 static void bxt_init_clock_gating(struct drm_device
*dev
)
59 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
69 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ
);
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
76 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
77 I915_WRITE(GEN9_CLKGATE_DIS_0
, I915_READ(GEN9_CLKGATE_DIS_0
) |
78 PWM1_GATING_DIS
| PWM2_GATING_DIS
);
81 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
83 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 tmp
= I915_READ(CLKCFG
);
88 switch (tmp
& CLKCFG_FSB_MASK
) {
90 dev_priv
->fsb_freq
= 533; /* 133*4 */
93 dev_priv
->fsb_freq
= 800; /* 200*4 */
96 dev_priv
->fsb_freq
= 667; /* 167*4 */
99 dev_priv
->fsb_freq
= 400; /* 100*4 */
103 switch (tmp
& CLKCFG_MEM_MASK
) {
105 dev_priv
->mem_freq
= 533;
108 dev_priv
->mem_freq
= 667;
111 dev_priv
->mem_freq
= 800;
115 /* detect pineview DDR3 setting */
116 tmp
= I915_READ(CSHRDDR3CTL
);
117 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
120 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
125 ddrpll
= I915_READ16(DDRMPLL1
);
126 csipll
= I915_READ16(CSIPLL0
);
128 switch (ddrpll
& 0xff) {
130 dev_priv
->mem_freq
= 800;
133 dev_priv
->mem_freq
= 1066;
136 dev_priv
->mem_freq
= 1333;
139 dev_priv
->mem_freq
= 1600;
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
144 dev_priv
->mem_freq
= 0;
148 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
150 switch (csipll
& 0x3ff) {
152 dev_priv
->fsb_freq
= 3200;
155 dev_priv
->fsb_freq
= 3733;
158 dev_priv
->fsb_freq
= 4266;
161 dev_priv
->fsb_freq
= 4800;
164 dev_priv
->fsb_freq
= 5333;
167 dev_priv
->fsb_freq
= 5866;
170 dev_priv
->fsb_freq
= 6400;
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
175 dev_priv
->fsb_freq
= 0;
179 if (dev_priv
->fsb_freq
== 3200) {
180 dev_priv
->ips
.c_m
= 0;
181 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
182 dev_priv
->ips
.c_m
= 1;
184 dev_priv
->ips
.c_m
= 2;
188 static const struct cxsr_latency cxsr_latency_table
[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
226 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
231 const struct cxsr_latency
*latency
;
234 if (fsb
== 0 || mem
== 0)
237 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
238 latency
= &cxsr_latency_table
[i
];
239 if (is_desktop
== latency
->is_desktop
&&
240 is_ddr3
== latency
->is_ddr3
&&
241 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
250 static void chv_set_memory_dvfs(struct drm_i915_private
*dev_priv
, bool enable
)
254 mutex_lock(&dev_priv
->rps
.hw_lock
);
256 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
258 val
&= ~FORCE_DDR_HIGH_FREQ
;
260 val
|= FORCE_DDR_HIGH_FREQ
;
261 val
&= ~FORCE_DDR_LOW_FREQ
;
262 val
|= FORCE_DDR_FREQ_REQ_ACK
;
263 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
265 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
266 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
269 mutex_unlock(&dev_priv
->rps
.hw_lock
);
272 static void chv_set_memory_pm5(struct drm_i915_private
*dev_priv
, bool enable
)
276 mutex_lock(&dev_priv
->rps
.hw_lock
);
278 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
280 val
|= DSP_MAXFIFO_PM5_ENABLE
;
282 val
&= ~DSP_MAXFIFO_PM5_ENABLE
;
283 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
285 mutex_unlock(&dev_priv
->rps
.hw_lock
);
288 #define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
291 void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
, bool enable
)
293 struct drm_device
*dev
= dev_priv
->dev
;
296 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
297 I915_WRITE(FW_BLC_SELF_VLV
, enable
? FW_CSPWRDWNEN
: 0);
298 POSTING_READ(FW_BLC_SELF_VLV
);
299 dev_priv
->wm
.vlv
.cxsr
= enable
;
300 } else if (IS_G4X(dev
) || IS_CRESTLINE(dev
)) {
301 I915_WRITE(FW_BLC_SELF
, enable
? FW_BLC_SELF_EN
: 0);
302 POSTING_READ(FW_BLC_SELF
);
303 } else if (IS_PINEVIEW(dev
)) {
304 val
= I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
;
305 val
|= enable
? PINEVIEW_SELF_REFRESH_EN
: 0;
306 I915_WRITE(DSPFW3
, val
);
307 POSTING_READ(DSPFW3
);
308 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
309 val
= enable
? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN
) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN
);
311 I915_WRITE(FW_BLC_SELF
, val
);
312 POSTING_READ(FW_BLC_SELF
);
313 } else if (IS_I915GM(dev
)) {
314 val
= enable
? _MASKED_BIT_ENABLE(INSTPM_SELF_EN
) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN
);
316 I915_WRITE(INSTPM
, val
);
317 POSTING_READ(INSTPM
);
322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable
? "enabled" : "disabled");
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
341 static const int pessimal_latency_ns
= 5000;
343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
346 static int vlv_get_fifo_size(struct drm_device
*dev
,
347 enum pipe pipe
, int plane
)
349 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
350 int sprite0_start
, sprite1_start
, size
;
353 uint32_t dsparb
, dsparb2
, dsparb3
;
355 dsparb
= I915_READ(DSPARB
);
356 dsparb2
= I915_READ(DSPARB2
);
357 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 0, 0);
358 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 8, 4);
361 dsparb
= I915_READ(DSPARB
);
362 dsparb2
= I915_READ(DSPARB2
);
363 sprite0_start
= VLV_FIFO_START(dsparb
, dsparb2
, 16, 8);
364 sprite1_start
= VLV_FIFO_START(dsparb
, dsparb2
, 24, 12);
367 dsparb2
= I915_READ(DSPARB2
);
368 dsparb3
= I915_READ(DSPARB3
);
369 sprite0_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 0, 16);
370 sprite1_start
= VLV_FIFO_START(dsparb3
, dsparb2
, 8, 20);
378 size
= sprite0_start
;
381 size
= sprite1_start
- sprite0_start
;
384 size
= 512 - 1 - sprite1_start
;
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe
), plane
== 0 ? "primary" : "sprite",
392 plane
== 0 ? plane_name(pipe
) : sprite_name(pipe
, plane
- 1),
398 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
400 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
401 uint32_t dsparb
= I915_READ(DSPARB
);
404 size
= dsparb
& 0x7f;
406 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
409 plane
? "B" : "A", size
);
414 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
417 uint32_t dsparb
= I915_READ(DSPARB
);
420 size
= dsparb
& 0x1ff;
422 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
423 size
>>= 1; /* Convert to cachelines */
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
426 plane
? "B" : "A", size
);
431 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
434 uint32_t dsparb
= I915_READ(DSPARB
);
437 size
= dsparb
& 0x7f;
438 size
>>= 2; /* Convert to cachelines */
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
447 /* Pineview has different values for various configs */
448 static const struct intel_watermark_params pineview_display_wm
= {
449 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
450 .max_wm
= PINEVIEW_MAX_WM
,
451 .default_wm
= PINEVIEW_DFT_WM
,
452 .guard_size
= PINEVIEW_GUARD_WM
,
453 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
455 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
456 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
457 .max_wm
= PINEVIEW_MAX_WM
,
458 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
459 .guard_size
= PINEVIEW_GUARD_WM
,
460 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
462 static const struct intel_watermark_params pineview_cursor_wm
= {
463 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
464 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
465 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
466 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
467 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
469 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
470 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
471 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
472 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
473 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
474 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
476 static const struct intel_watermark_params g4x_wm_info
= {
477 .fifo_size
= G4X_FIFO_SIZE
,
478 .max_wm
= G4X_MAX_WM
,
479 .default_wm
= G4X_MAX_WM
,
481 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
483 static const struct intel_watermark_params g4x_cursor_wm_info
= {
484 .fifo_size
= I965_CURSOR_FIFO
,
485 .max_wm
= I965_CURSOR_MAX_WM
,
486 .default_wm
= I965_CURSOR_DFT_WM
,
488 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
490 static const struct intel_watermark_params i965_cursor_wm_info
= {
491 .fifo_size
= I965_CURSOR_FIFO
,
492 .max_wm
= I965_CURSOR_MAX_WM
,
493 .default_wm
= I965_CURSOR_DFT_WM
,
495 .cacheline_size
= I915_FIFO_LINE_SIZE
,
497 static const struct intel_watermark_params i945_wm_info
= {
498 .fifo_size
= I945_FIFO_SIZE
,
499 .max_wm
= I915_MAX_WM
,
502 .cacheline_size
= I915_FIFO_LINE_SIZE
,
504 static const struct intel_watermark_params i915_wm_info
= {
505 .fifo_size
= I915_FIFO_SIZE
,
506 .max_wm
= I915_MAX_WM
,
509 .cacheline_size
= I915_FIFO_LINE_SIZE
,
511 static const struct intel_watermark_params i830_a_wm_info
= {
512 .fifo_size
= I855GM_FIFO_SIZE
,
513 .max_wm
= I915_MAX_WM
,
516 .cacheline_size
= I830_FIFO_LINE_SIZE
,
518 static const struct intel_watermark_params i830_bc_wm_info
= {
519 .fifo_size
= I855GM_FIFO_SIZE
,
520 .max_wm
= I915_MAX_WM
/2,
523 .cacheline_size
= I830_FIFO_LINE_SIZE
,
525 static const struct intel_watermark_params i845_wm_info
= {
526 .fifo_size
= I830_FIFO_SIZE
,
527 .max_wm
= I915_MAX_WM
,
530 .cacheline_size
= I830_FIFO_LINE_SIZE
,
534 * intel_calculate_wm - calculate watermark level
535 * @clock_in_khz: pixel clock
536 * @wm: chip FIFO params
537 * @cpp: bytes per pixel
538 * @latency_ns: memory latency for the platform
540 * Calculate the watermark level (the level at which the display plane will
541 * start fetching from memory again). Each chip has a different display
542 * FIFO size and allocation, so the caller needs to figure that out and pass
543 * in the correct intel_watermark_params structure.
545 * As the pixel clock runs, the FIFO will be drained at a rate that depends
546 * on the pixel size. When it reaches the watermark level, it'll start
547 * fetching FIFO line sized based chunks from memory until the FIFO fills
548 * past the watermark point. If the FIFO drains completely, a FIFO underrun
549 * will occur, and a display engine hang could result.
551 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
552 const struct intel_watermark_params
*wm
,
553 int fifo_size
, int cpp
,
554 unsigned long latency_ns
)
556 long entries_required
, wm_size
;
559 * Note: we need to make sure we don't overflow for various clock &
561 * clocks go from a few thousand to several hundred thousand.
562 * latency is usually a few thousand
564 entries_required
= ((clock_in_khz
/ 1000) * cpp
* latency_ns
) /
566 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
568 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
570 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
572 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
574 /* Don't promote wm_size to unsigned... */
575 if (wm_size
> (long)wm
->max_wm
)
576 wm_size
= wm
->max_wm
;
578 wm_size
= wm
->default_wm
;
581 * Bspec seems to indicate that the value shouldn't be lower than
582 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
583 * Lets go for 8 which is the burst size since certain platforms
584 * already use a hardcoded 8 (which is what the spec says should be
593 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
595 struct drm_crtc
*crtc
, *enabled
= NULL
;
597 for_each_crtc(dev
, crtc
) {
598 if (intel_crtc_active(crtc
)) {
608 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
610 struct drm_device
*dev
= unused_crtc
->dev
;
611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
612 struct drm_crtc
*crtc
;
613 const struct cxsr_latency
*latency
;
617 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
618 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
620 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
621 intel_set_memory_cxsr(dev_priv
, false);
625 crtc
= single_enabled_crtc(dev
);
627 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
628 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
629 int clock
= adjusted_mode
->crtc_clock
;
632 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
633 pineview_display_wm
.fifo_size
,
634 cpp
, latency
->display_sr
);
635 reg
= I915_READ(DSPFW1
);
636 reg
&= ~DSPFW_SR_MASK
;
637 reg
|= FW_WM(wm
, SR
);
638 I915_WRITE(DSPFW1
, reg
);
639 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
642 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
643 pineview_display_wm
.fifo_size
,
644 cpp
, latency
->cursor_sr
);
645 reg
= I915_READ(DSPFW3
);
646 reg
&= ~DSPFW_CURSOR_SR_MASK
;
647 reg
|= FW_WM(wm
, CURSOR_SR
);
648 I915_WRITE(DSPFW3
, reg
);
650 /* Display HPLL off SR */
651 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
652 pineview_display_hplloff_wm
.fifo_size
,
653 cpp
, latency
->display_hpll_disable
);
654 reg
= I915_READ(DSPFW3
);
655 reg
&= ~DSPFW_HPLL_SR_MASK
;
656 reg
|= FW_WM(wm
, HPLL_SR
);
657 I915_WRITE(DSPFW3
, reg
);
659 /* cursor HPLL off SR */
660 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
661 pineview_display_hplloff_wm
.fifo_size
,
662 cpp
, latency
->cursor_hpll_disable
);
663 reg
= I915_READ(DSPFW3
);
664 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
665 reg
|= FW_WM(wm
, HPLL_CURSOR
);
666 I915_WRITE(DSPFW3
, reg
);
667 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
669 intel_set_memory_cxsr(dev_priv
, true);
671 intel_set_memory_cxsr(dev_priv
, false);
675 static bool g4x_compute_wm0(struct drm_device
*dev
,
677 const struct intel_watermark_params
*display
,
678 int display_latency_ns
,
679 const struct intel_watermark_params
*cursor
,
680 int cursor_latency_ns
,
684 struct drm_crtc
*crtc
;
685 const struct drm_display_mode
*adjusted_mode
;
686 int htotal
, hdisplay
, clock
, cpp
;
687 int line_time_us
, line_count
;
688 int entries
, tlb_miss
;
690 crtc
= intel_get_crtc_for_plane(dev
, plane
);
691 if (!intel_crtc_active(crtc
)) {
692 *cursor_wm
= cursor
->guard_size
;
693 *plane_wm
= display
->guard_size
;
697 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
698 clock
= adjusted_mode
->crtc_clock
;
699 htotal
= adjusted_mode
->crtc_htotal
;
700 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
701 cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
703 /* Use the small buffer method to calculate plane watermark */
704 entries
= ((clock
* cpp
/ 1000) * display_latency_ns
) / 1000;
705 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
708 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
709 *plane_wm
= entries
+ display
->guard_size
;
710 if (*plane_wm
> (int)display
->max_wm
)
711 *plane_wm
= display
->max_wm
;
713 /* Use the large buffer method to calculate cursor watermark */
714 line_time_us
= max(htotal
* 1000 / clock
, 1);
715 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
716 entries
= line_count
* crtc
->cursor
->state
->crtc_w
* cpp
;
717 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
720 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
721 *cursor_wm
= entries
+ cursor
->guard_size
;
722 if (*cursor_wm
> (int)cursor
->max_wm
)
723 *cursor_wm
= (int)cursor
->max_wm
;
729 * Check the wm result.
731 * If any calculated watermark values is larger than the maximum value that
732 * can be programmed into the associated watermark register, that watermark
735 static bool g4x_check_srwm(struct drm_device
*dev
,
736 int display_wm
, int cursor_wm
,
737 const struct intel_watermark_params
*display
,
738 const struct intel_watermark_params
*cursor
)
740 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
741 display_wm
, cursor_wm
);
743 if (display_wm
> display
->max_wm
) {
744 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
745 display_wm
, display
->max_wm
);
749 if (cursor_wm
> cursor
->max_wm
) {
750 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
751 cursor_wm
, cursor
->max_wm
);
755 if (!(display_wm
|| cursor_wm
)) {
756 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
763 static bool g4x_compute_srwm(struct drm_device
*dev
,
766 const struct intel_watermark_params
*display
,
767 const struct intel_watermark_params
*cursor
,
768 int *display_wm
, int *cursor_wm
)
770 struct drm_crtc
*crtc
;
771 const struct drm_display_mode
*adjusted_mode
;
772 int hdisplay
, htotal
, cpp
, clock
;
773 unsigned long line_time_us
;
774 int line_count
, line_size
;
779 *display_wm
= *cursor_wm
= 0;
783 crtc
= intel_get_crtc_for_plane(dev
, plane
);
784 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
785 clock
= adjusted_mode
->crtc_clock
;
786 htotal
= adjusted_mode
->crtc_htotal
;
787 hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
788 cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
790 line_time_us
= max(htotal
* 1000 / clock
, 1);
791 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
792 line_size
= hdisplay
* cpp
;
794 /* Use the minimum of the small and large buffer method for primary */
795 small
= ((clock
* cpp
/ 1000) * latency_ns
) / 1000;
796 large
= line_count
* line_size
;
798 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
799 *display_wm
= entries
+ display
->guard_size
;
801 /* calculate the self-refresh watermark for display cursor */
802 entries
= line_count
* cpp
* crtc
->cursor
->state
->crtc_w
;
803 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
804 *cursor_wm
= entries
+ cursor
->guard_size
;
806 return g4x_check_srwm(dev
,
807 *display_wm
, *cursor_wm
,
811 #define FW_WM_VLV(value, plane) \
812 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
814 static void vlv_write_wm_values(struct intel_crtc
*crtc
,
815 const struct vlv_wm_values
*wm
)
817 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
818 enum pipe pipe
= crtc
->pipe
;
820 I915_WRITE(VLV_DDL(pipe
),
821 (wm
->ddl
[pipe
].cursor
<< DDL_CURSOR_SHIFT
) |
822 (wm
->ddl
[pipe
].sprite
[1] << DDL_SPRITE_SHIFT(1)) |
823 (wm
->ddl
[pipe
].sprite
[0] << DDL_SPRITE_SHIFT(0)) |
824 (wm
->ddl
[pipe
].primary
<< DDL_PLANE_SHIFT
));
827 FW_WM(wm
->sr
.plane
, SR
) |
828 FW_WM(wm
->pipe
[PIPE_B
].cursor
, CURSORB
) |
829 FW_WM_VLV(wm
->pipe
[PIPE_B
].primary
, PLANEB
) |
830 FW_WM_VLV(wm
->pipe
[PIPE_A
].primary
, PLANEA
));
832 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[1], SPRITEB
) |
833 FW_WM(wm
->pipe
[PIPE_A
].cursor
, CURSORA
) |
834 FW_WM_VLV(wm
->pipe
[PIPE_A
].sprite
[0], SPRITEA
));
836 FW_WM(wm
->sr
.cursor
, CURSOR_SR
));
838 if (IS_CHERRYVIEW(dev_priv
)) {
839 I915_WRITE(DSPFW7_CHV
,
840 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
841 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
842 I915_WRITE(DSPFW8_CHV
,
843 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[1], SPRITEF
) |
844 FW_WM_VLV(wm
->pipe
[PIPE_C
].sprite
[0], SPRITEE
));
845 I915_WRITE(DSPFW9_CHV
,
846 FW_WM_VLV(wm
->pipe
[PIPE_C
].primary
, PLANEC
) |
847 FW_WM(wm
->pipe
[PIPE_C
].cursor
, CURSORC
));
849 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
850 FW_WM(wm
->pipe
[PIPE_C
].sprite
[1] >> 8, SPRITEF_HI
) |
851 FW_WM(wm
->pipe
[PIPE_C
].sprite
[0] >> 8, SPRITEE_HI
) |
852 FW_WM(wm
->pipe
[PIPE_C
].primary
>> 8, PLANEC_HI
) |
853 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
854 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
855 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
856 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
857 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
858 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
861 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[1], SPRITED
) |
862 FW_WM_VLV(wm
->pipe
[PIPE_B
].sprite
[0], SPRITEC
));
864 FW_WM(wm
->sr
.plane
>> 9, SR_HI
) |
865 FW_WM(wm
->pipe
[PIPE_B
].sprite
[1] >> 8, SPRITED_HI
) |
866 FW_WM(wm
->pipe
[PIPE_B
].sprite
[0] >> 8, SPRITEC_HI
) |
867 FW_WM(wm
->pipe
[PIPE_B
].primary
>> 8, PLANEB_HI
) |
868 FW_WM(wm
->pipe
[PIPE_A
].sprite
[1] >> 8, SPRITEB_HI
) |
869 FW_WM(wm
->pipe
[PIPE_A
].sprite
[0] >> 8, SPRITEA_HI
) |
870 FW_WM(wm
->pipe
[PIPE_A
].primary
>> 8, PLANEA_HI
));
873 /* zero (unused) WM1 watermarks */
874 I915_WRITE(DSPFW4
, 0);
875 I915_WRITE(DSPFW5
, 0);
876 I915_WRITE(DSPFW6
, 0);
877 I915_WRITE(DSPHOWM1
, 0);
879 POSTING_READ(DSPFW1
);
887 VLV_WM_LEVEL_DDR_DVFS
,
890 /* latency must be in 0.1us units. */
891 static unsigned int vlv_wm_method2(unsigned int pixel_rate
,
892 unsigned int pipe_htotal
,
893 unsigned int horiz_pixels
,
895 unsigned int latency
)
899 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
900 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
901 ret
= DIV_ROUND_UP(ret
, 64);
906 static void vlv_setup_wm_latency(struct drm_device
*dev
)
908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
910 /* all latencies in usec */
911 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM2
] = 3;
913 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM2
;
915 if (IS_CHERRYVIEW(dev_priv
)) {
916 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_PM5
] = 12;
917 dev_priv
->wm
.pri_latency
[VLV_WM_LEVEL_DDR_DVFS
] = 33;
919 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_DDR_DVFS
;
923 static uint16_t vlv_compute_wm_level(struct intel_plane
*plane
,
924 struct intel_crtc
*crtc
,
925 const struct intel_plane_state
*state
,
928 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
929 int clock
, htotal
, cpp
, width
, wm
;
931 if (dev_priv
->wm
.pri_latency
[level
] == 0)
937 cpp
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
938 clock
= crtc
->config
->base
.adjusted_mode
.crtc_clock
;
939 htotal
= crtc
->config
->base
.adjusted_mode
.crtc_htotal
;
940 width
= crtc
->config
->pipe_src_w
;
941 if (WARN_ON(htotal
== 0))
944 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
946 * FIXME the formula gives values that are
947 * too big for the cursor FIFO, and hence we
948 * would never be able to use cursors. For
949 * now just hardcode the watermark.
953 wm
= vlv_wm_method2(clock
, htotal
, width
, cpp
,
954 dev_priv
->wm
.pri_latency
[level
] * 10);
957 return min_t(int, wm
, USHRT_MAX
);
960 static void vlv_compute_fifo(struct intel_crtc
*crtc
)
962 struct drm_device
*dev
= crtc
->base
.dev
;
963 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
964 struct intel_plane
*plane
;
965 unsigned int total_rate
= 0;
966 const int fifo_size
= 512 - 1;
967 int fifo_extra
, fifo_left
= fifo_size
;
969 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
970 struct intel_plane_state
*state
=
971 to_intel_plane_state(plane
->base
.state
);
973 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
976 if (state
->visible
) {
977 wm_state
->num_active_planes
++;
978 total_rate
+= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
982 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
983 struct intel_plane_state
*state
=
984 to_intel_plane_state(plane
->base
.state
);
987 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
988 plane
->wm
.fifo_size
= 63;
992 if (!state
->visible
) {
993 plane
->wm
.fifo_size
= 0;
997 rate
= drm_format_plane_cpp(state
->base
.fb
->pixel_format
, 0);
998 plane
->wm
.fifo_size
= fifo_size
* rate
/ total_rate
;
999 fifo_left
-= plane
->wm
.fifo_size
;
1002 fifo_extra
= DIV_ROUND_UP(fifo_left
, wm_state
->num_active_planes
?: 1);
1004 /* spread the remainder evenly */
1005 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1011 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
1014 /* give it all to the first plane if none are active */
1015 if (plane
->wm
.fifo_size
== 0 &&
1016 wm_state
->num_active_planes
)
1019 plane_extra
= min(fifo_extra
, fifo_left
);
1020 plane
->wm
.fifo_size
+= plane_extra
;
1021 fifo_left
-= plane_extra
;
1024 WARN_ON(fifo_left
!= 0);
1027 static void vlv_invert_wms(struct intel_crtc
*crtc
)
1029 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1032 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1033 struct drm_device
*dev
= crtc
->base
.dev
;
1034 const int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1035 struct intel_plane
*plane
;
1037 wm_state
->sr
[level
].plane
= sr_fifo_size
- wm_state
->sr
[level
].plane
;
1038 wm_state
->sr
[level
].cursor
= 63 - wm_state
->sr
[level
].cursor
;
1040 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1041 switch (plane
->base
.type
) {
1043 case DRM_PLANE_TYPE_CURSOR
:
1044 wm_state
->wm
[level
].cursor
= plane
->wm
.fifo_size
-
1045 wm_state
->wm
[level
].cursor
;
1047 case DRM_PLANE_TYPE_PRIMARY
:
1048 wm_state
->wm
[level
].primary
= plane
->wm
.fifo_size
-
1049 wm_state
->wm
[level
].primary
;
1051 case DRM_PLANE_TYPE_OVERLAY
:
1052 sprite
= plane
->plane
;
1053 wm_state
->wm
[level
].sprite
[sprite
] = plane
->wm
.fifo_size
-
1054 wm_state
->wm
[level
].sprite
[sprite
];
1061 static void vlv_compute_wm(struct intel_crtc
*crtc
)
1063 struct drm_device
*dev
= crtc
->base
.dev
;
1064 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1065 struct intel_plane
*plane
;
1066 int sr_fifo_size
= INTEL_INFO(dev
)->num_pipes
* 512 - 1;
1069 memset(wm_state
, 0, sizeof(*wm_state
));
1071 wm_state
->cxsr
= crtc
->pipe
!= PIPE_C
&& crtc
->wm
.cxsr_allowed
;
1072 wm_state
->num_levels
= to_i915(dev
)->wm
.max_level
+ 1;
1074 wm_state
->num_active_planes
= 0;
1076 vlv_compute_fifo(crtc
);
1078 if (wm_state
->num_active_planes
!= 1)
1079 wm_state
->cxsr
= false;
1081 if (wm_state
->cxsr
) {
1082 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1083 wm_state
->sr
[level
].plane
= sr_fifo_size
;
1084 wm_state
->sr
[level
].cursor
= 63;
1088 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1089 struct intel_plane_state
*state
=
1090 to_intel_plane_state(plane
->base
.state
);
1092 if (!state
->visible
)
1095 /* normal watermarks */
1096 for (level
= 0; level
< wm_state
->num_levels
; level
++) {
1097 int wm
= vlv_compute_wm_level(plane
, crtc
, state
, level
);
1098 int max_wm
= plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
? 63 : 511;
1101 if (WARN_ON(level
== 0 && wm
> max_wm
))
1104 if (wm
> plane
->wm
.fifo_size
)
1107 switch (plane
->base
.type
) {
1109 case DRM_PLANE_TYPE_CURSOR
:
1110 wm_state
->wm
[level
].cursor
= wm
;
1112 case DRM_PLANE_TYPE_PRIMARY
:
1113 wm_state
->wm
[level
].primary
= wm
;
1115 case DRM_PLANE_TYPE_OVERLAY
:
1116 sprite
= plane
->plane
;
1117 wm_state
->wm
[level
].sprite
[sprite
] = wm
;
1122 wm_state
->num_levels
= level
;
1124 if (!wm_state
->cxsr
)
1127 /* maxfifo watermarks */
1128 switch (plane
->base
.type
) {
1130 case DRM_PLANE_TYPE_CURSOR
:
1131 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1132 wm_state
->sr
[level
].cursor
=
1133 wm_state
->wm
[level
].cursor
;
1135 case DRM_PLANE_TYPE_PRIMARY
:
1136 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1137 wm_state
->sr
[level
].plane
=
1138 min(wm_state
->sr
[level
].plane
,
1139 wm_state
->wm
[level
].primary
);
1141 case DRM_PLANE_TYPE_OVERLAY
:
1142 sprite
= plane
->plane
;
1143 for (level
= 0; level
< wm_state
->num_levels
; level
++)
1144 wm_state
->sr
[level
].plane
=
1145 min(wm_state
->sr
[level
].plane
,
1146 wm_state
->wm
[level
].sprite
[sprite
]);
1151 /* clear any (partially) filled invalid levels */
1152 for (level
= wm_state
->num_levels
; level
< to_i915(dev
)->wm
.max_level
+ 1; level
++) {
1153 memset(&wm_state
->wm
[level
], 0, sizeof(wm_state
->wm
[level
]));
1154 memset(&wm_state
->sr
[level
], 0, sizeof(wm_state
->sr
[level
]));
1157 vlv_invert_wms(crtc
);
1160 #define VLV_FIFO(plane, value) \
1161 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1163 static void vlv_pipe_set_fifo_size(struct intel_crtc
*crtc
)
1165 struct drm_device
*dev
= crtc
->base
.dev
;
1166 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1167 struct intel_plane
*plane
;
1168 int sprite0_start
= 0, sprite1_start
= 0, fifo_size
= 0;
1170 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
1171 if (plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
) {
1172 WARN_ON(plane
->wm
.fifo_size
!= 63);
1176 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
1177 sprite0_start
= plane
->wm
.fifo_size
;
1178 else if (plane
->plane
== 0)
1179 sprite1_start
= sprite0_start
+ plane
->wm
.fifo_size
;
1181 fifo_size
= sprite1_start
+ plane
->wm
.fifo_size
;
1184 WARN_ON(fifo_size
!= 512 - 1);
1186 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187 pipe_name(crtc
->pipe
), sprite0_start
,
1188 sprite1_start
, fifo_size
);
1190 switch (crtc
->pipe
) {
1191 uint32_t dsparb
, dsparb2
, dsparb3
;
1193 dsparb
= I915_READ(DSPARB
);
1194 dsparb2
= I915_READ(DSPARB2
);
1196 dsparb
&= ~(VLV_FIFO(SPRITEA
, 0xff) |
1197 VLV_FIFO(SPRITEB
, 0xff));
1198 dsparb
|= (VLV_FIFO(SPRITEA
, sprite0_start
) |
1199 VLV_FIFO(SPRITEB
, sprite1_start
));
1201 dsparb2
&= ~(VLV_FIFO(SPRITEA_HI
, 0x1) |
1202 VLV_FIFO(SPRITEB_HI
, 0x1));
1203 dsparb2
|= (VLV_FIFO(SPRITEA_HI
, sprite0_start
>> 8) |
1204 VLV_FIFO(SPRITEB_HI
, sprite1_start
>> 8));
1206 I915_WRITE(DSPARB
, dsparb
);
1207 I915_WRITE(DSPARB2
, dsparb2
);
1210 dsparb
= I915_READ(DSPARB
);
1211 dsparb2
= I915_READ(DSPARB2
);
1213 dsparb
&= ~(VLV_FIFO(SPRITEC
, 0xff) |
1214 VLV_FIFO(SPRITED
, 0xff));
1215 dsparb
|= (VLV_FIFO(SPRITEC
, sprite0_start
) |
1216 VLV_FIFO(SPRITED
, sprite1_start
));
1218 dsparb2
&= ~(VLV_FIFO(SPRITEC_HI
, 0xff) |
1219 VLV_FIFO(SPRITED_HI
, 0xff));
1220 dsparb2
|= (VLV_FIFO(SPRITEC_HI
, sprite0_start
>> 8) |
1221 VLV_FIFO(SPRITED_HI
, sprite1_start
>> 8));
1223 I915_WRITE(DSPARB
, dsparb
);
1224 I915_WRITE(DSPARB2
, dsparb2
);
1227 dsparb3
= I915_READ(DSPARB3
);
1228 dsparb2
= I915_READ(DSPARB2
);
1230 dsparb3
&= ~(VLV_FIFO(SPRITEE
, 0xff) |
1231 VLV_FIFO(SPRITEF
, 0xff));
1232 dsparb3
|= (VLV_FIFO(SPRITEE
, sprite0_start
) |
1233 VLV_FIFO(SPRITEF
, sprite1_start
));
1235 dsparb2
&= ~(VLV_FIFO(SPRITEE_HI
, 0xff) |
1236 VLV_FIFO(SPRITEF_HI
, 0xff));
1237 dsparb2
|= (VLV_FIFO(SPRITEE_HI
, sprite0_start
>> 8) |
1238 VLV_FIFO(SPRITEF_HI
, sprite1_start
>> 8));
1240 I915_WRITE(DSPARB3
, dsparb3
);
1241 I915_WRITE(DSPARB2
, dsparb2
);
1250 static void vlv_merge_wm(struct drm_device
*dev
,
1251 struct vlv_wm_values
*wm
)
1253 struct intel_crtc
*crtc
;
1254 int num_active_crtcs
= 0;
1256 wm
->level
= to_i915(dev
)->wm
.max_level
;
1259 for_each_intel_crtc(dev
, crtc
) {
1260 const struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1265 if (!wm_state
->cxsr
)
1269 wm
->level
= min_t(int, wm
->level
, wm_state
->num_levels
- 1);
1272 if (num_active_crtcs
!= 1)
1275 if (num_active_crtcs
> 1)
1276 wm
->level
= VLV_WM_LEVEL_PM2
;
1278 for_each_intel_crtc(dev
, crtc
) {
1279 struct vlv_wm_state
*wm_state
= &crtc
->wm_state
;
1280 enum pipe pipe
= crtc
->pipe
;
1285 wm
->pipe
[pipe
] = wm_state
->wm
[wm
->level
];
1287 wm
->sr
= wm_state
->sr
[wm
->level
];
1289 wm
->ddl
[pipe
].primary
= DDL_PRECISION_HIGH
| 2;
1290 wm
->ddl
[pipe
].sprite
[0] = DDL_PRECISION_HIGH
| 2;
1291 wm
->ddl
[pipe
].sprite
[1] = DDL_PRECISION_HIGH
| 2;
1292 wm
->ddl
[pipe
].cursor
= DDL_PRECISION_HIGH
| 2;
1296 static void vlv_update_wm(struct drm_crtc
*crtc
)
1298 struct drm_device
*dev
= crtc
->dev
;
1299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1300 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1301 enum pipe pipe
= intel_crtc
->pipe
;
1302 struct vlv_wm_values wm
= {};
1304 vlv_compute_wm(intel_crtc
);
1305 vlv_merge_wm(dev
, &wm
);
1307 if (memcmp(&dev_priv
->wm
.vlv
, &wm
, sizeof(wm
)) == 0) {
1308 /* FIXME should be part of crtc atomic commit */
1309 vlv_pipe_set_fifo_size(intel_crtc
);
1313 if (wm
.level
< VLV_WM_LEVEL_DDR_DVFS
&&
1314 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_DDR_DVFS
)
1315 chv_set_memory_dvfs(dev_priv
, false);
1317 if (wm
.level
< VLV_WM_LEVEL_PM5
&&
1318 dev_priv
->wm
.vlv
.level
>= VLV_WM_LEVEL_PM5
)
1319 chv_set_memory_pm5(dev_priv
, false);
1321 if (!wm
.cxsr
&& dev_priv
->wm
.vlv
.cxsr
)
1322 intel_set_memory_cxsr(dev_priv
, false);
1324 /* FIXME should be part of crtc atomic commit */
1325 vlv_pipe_set_fifo_size(intel_crtc
);
1327 vlv_write_wm_values(intel_crtc
, &wm
);
1329 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331 pipe_name(pipe
), wm
.pipe
[pipe
].primary
, wm
.pipe
[pipe
].cursor
,
1332 wm
.pipe
[pipe
].sprite
[0], wm
.pipe
[pipe
].sprite
[1],
1333 wm
.sr
.plane
, wm
.sr
.cursor
, wm
.level
, wm
.cxsr
);
1335 if (wm
.cxsr
&& !dev_priv
->wm
.vlv
.cxsr
)
1336 intel_set_memory_cxsr(dev_priv
, true);
1338 if (wm
.level
>= VLV_WM_LEVEL_PM5
&&
1339 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_PM5
)
1340 chv_set_memory_pm5(dev_priv
, true);
1342 if (wm
.level
>= VLV_WM_LEVEL_DDR_DVFS
&&
1343 dev_priv
->wm
.vlv
.level
< VLV_WM_LEVEL_DDR_DVFS
)
1344 chv_set_memory_dvfs(dev_priv
, true);
1346 dev_priv
->wm
.vlv
= wm
;
1349 #define single_plane_enabled(mask) is_power_of_2(mask)
1351 static void g4x_update_wm(struct drm_crtc
*crtc
)
1353 struct drm_device
*dev
= crtc
->dev
;
1354 static const int sr_latency_ns
= 12000;
1355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1356 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1357 int plane_sr
, cursor_sr
;
1358 unsigned int enabled
= 0;
1361 if (g4x_compute_wm0(dev
, PIPE_A
,
1362 &g4x_wm_info
, pessimal_latency_ns
,
1363 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1364 &planea_wm
, &cursora_wm
))
1365 enabled
|= 1 << PIPE_A
;
1367 if (g4x_compute_wm0(dev
, PIPE_B
,
1368 &g4x_wm_info
, pessimal_latency_ns
,
1369 &g4x_cursor_wm_info
, pessimal_latency_ns
,
1370 &planeb_wm
, &cursorb_wm
))
1371 enabled
|= 1 << PIPE_B
;
1373 if (single_plane_enabled(enabled
) &&
1374 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1377 &g4x_cursor_wm_info
,
1378 &plane_sr
, &cursor_sr
)) {
1379 cxsr_enabled
= true;
1381 cxsr_enabled
= false;
1382 intel_set_memory_cxsr(dev_priv
, false);
1383 plane_sr
= cursor_sr
= 0;
1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1388 planea_wm
, cursora_wm
,
1389 planeb_wm
, cursorb_wm
,
1390 plane_sr
, cursor_sr
);
1393 FW_WM(plane_sr
, SR
) |
1394 FW_WM(cursorb_wm
, CURSORB
) |
1395 FW_WM(planeb_wm
, PLANEB
) |
1396 FW_WM(planea_wm
, PLANEA
));
1398 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1399 FW_WM(cursora_wm
, CURSORA
));
1400 /* HPLL off in SR has some issues on G4x... disable it */
1402 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1403 FW_WM(cursor_sr
, CURSOR_SR
));
1406 intel_set_memory_cxsr(dev_priv
, true);
1409 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1411 struct drm_device
*dev
= unused_crtc
->dev
;
1412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1413 struct drm_crtc
*crtc
;
1418 /* Calc sr entries for one plane configs */
1419 crtc
= single_enabled_crtc(dev
);
1421 /* self-refresh has much higher latency */
1422 static const int sr_latency_ns
= 12000;
1423 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1424 int clock
= adjusted_mode
->crtc_clock
;
1425 int htotal
= adjusted_mode
->crtc_htotal
;
1426 int hdisplay
= to_intel_crtc(crtc
)->config
->pipe_src_w
;
1427 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
1428 unsigned long line_time_us
;
1431 line_time_us
= max(htotal
* 1000 / clock
, 1);
1433 /* Use ns/us then divide to preserve precision */
1434 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1436 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1437 srwm
= I965_FIFO_SIZE
- entries
;
1441 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1444 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1445 cpp
* crtc
->cursor
->state
->crtc_w
;
1446 entries
= DIV_ROUND_UP(entries
,
1447 i965_cursor_wm_info
.cacheline_size
);
1448 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1449 (entries
+ i965_cursor_wm_info
.guard_size
);
1451 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1452 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1454 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455 "cursor %d\n", srwm
, cursor_sr
);
1457 cxsr_enabled
= true;
1459 cxsr_enabled
= false;
1460 /* Turn off self refresh if both pipes are enabled */
1461 intel_set_memory_cxsr(dev_priv
, false);
1464 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1467 /* 965 has limitations... */
1468 I915_WRITE(DSPFW1
, FW_WM(srwm
, SR
) |
1472 I915_WRITE(DSPFW2
, FW_WM(8, CURSORA
) |
1473 FW_WM(8, PLANEC_OLD
));
1474 /* update cursor SR watermark */
1475 I915_WRITE(DSPFW3
, FW_WM(cursor_sr
, CURSOR_SR
));
1478 intel_set_memory_cxsr(dev_priv
, true);
1483 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1485 struct drm_device
*dev
= unused_crtc
->dev
;
1486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1487 const struct intel_watermark_params
*wm_info
;
1492 int planea_wm
, planeb_wm
;
1493 struct drm_crtc
*crtc
, *enabled
= NULL
;
1496 wm_info
= &i945_wm_info
;
1497 else if (!IS_GEN2(dev
))
1498 wm_info
= &i915_wm_info
;
1500 wm_info
= &i830_a_wm_info
;
1502 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1503 crtc
= intel_get_crtc_for_plane(dev
, 0);
1504 if (intel_crtc_active(crtc
)) {
1505 const struct drm_display_mode
*adjusted_mode
;
1506 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
1510 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1511 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1512 wm_info
, fifo_size
, cpp
,
1513 pessimal_latency_ns
);
1516 planea_wm
= fifo_size
- wm_info
->guard_size
;
1517 if (planea_wm
> (long)wm_info
->max_wm
)
1518 planea_wm
= wm_info
->max_wm
;
1522 wm_info
= &i830_bc_wm_info
;
1524 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1525 crtc
= intel_get_crtc_for_plane(dev
, 1);
1526 if (intel_crtc_active(crtc
)) {
1527 const struct drm_display_mode
*adjusted_mode
;
1528 int cpp
= drm_format_plane_cpp(crtc
->primary
->state
->fb
->pixel_format
, 0);
1532 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1533 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1534 wm_info
, fifo_size
, cpp
,
1535 pessimal_latency_ns
);
1536 if (enabled
== NULL
)
1541 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1542 if (planeb_wm
> (long)wm_info
->max_wm
)
1543 planeb_wm
= wm_info
->max_wm
;
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1548 if (IS_I915GM(dev
) && enabled
) {
1549 struct drm_i915_gem_object
*obj
;
1551 obj
= intel_fb_obj(enabled
->primary
->state
->fb
);
1553 /* self-refresh seems busted with untiled */
1554 if (obj
->tiling_mode
== I915_TILING_NONE
)
1559 * Overlay gets an aggressive default since video jitter is bad.
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
1564 intel_set_memory_cxsr(dev_priv
, false);
1566 /* Calc sr entries for one plane configs */
1567 if (HAS_FW_BLC(dev
) && enabled
) {
1568 /* self-refresh has much higher latency */
1569 static const int sr_latency_ns
= 6000;
1570 const struct drm_display_mode
*adjusted_mode
= &to_intel_crtc(enabled
)->config
->base
.adjusted_mode
;
1571 int clock
= adjusted_mode
->crtc_clock
;
1572 int htotal
= adjusted_mode
->crtc_htotal
;
1573 int hdisplay
= to_intel_crtc(enabled
)->config
->pipe_src_w
;
1574 int cpp
= drm_format_plane_cpp(enabled
->primary
->state
->fb
->pixel_format
, 0);
1575 unsigned long line_time_us
;
1578 line_time_us
= max(htotal
* 1000 / clock
, 1);
1580 /* Use ns/us then divide to preserve precision */
1581 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1583 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1584 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1585 srwm
= wm_info
->fifo_size
- entries
;
1589 if (IS_I945G(dev
) || IS_I945GM(dev
))
1590 I915_WRITE(FW_BLC_SELF
,
1591 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1592 else if (IS_I915GM(dev
))
1593 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1596 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597 planea_wm
, planeb_wm
, cwm
, srwm
);
1599 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1600 fwater_hi
= (cwm
& 0x1f);
1602 /* Set request length to 8 cachelines per fetch */
1603 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1604 fwater_hi
= fwater_hi
| (1 << 8);
1606 I915_WRITE(FW_BLC
, fwater_lo
);
1607 I915_WRITE(FW_BLC2
, fwater_hi
);
1610 intel_set_memory_cxsr(dev_priv
, true);
1613 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1615 struct drm_device
*dev
= unused_crtc
->dev
;
1616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1617 struct drm_crtc
*crtc
;
1618 const struct drm_display_mode
*adjusted_mode
;
1622 crtc
= single_enabled_crtc(dev
);
1626 adjusted_mode
= &to_intel_crtc(crtc
)->config
->base
.adjusted_mode
;
1627 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1629 dev_priv
->display
.get_fifo_size(dev
, 0),
1630 4, pessimal_latency_ns
);
1631 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1632 fwater_lo
|= (3<<8) | planea_wm
;
1634 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1636 I915_WRITE(FW_BLC
, fwater_lo
);
1639 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
*pipe_config
)
1641 uint32_t pixel_rate
;
1643 pixel_rate
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
1645 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646 * adjust the pixel_rate here. */
1648 if (pipe_config
->pch_pfit
.enabled
) {
1649 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1650 uint32_t pfit_size
= pipe_config
->pch_pfit
.size
;
1652 pipe_w
= pipe_config
->pipe_src_w
;
1653 pipe_h
= pipe_config
->pipe_src_h
;
1655 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1656 pfit_h
= pfit_size
& 0xFFFF;
1657 if (pipe_w
< pfit_w
)
1659 if (pipe_h
< pfit_h
)
1662 if (WARN_ON(!pfit_w
|| !pfit_h
))
1665 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1672 /* latency must be in 0.1us units. */
1673 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t cpp
, uint32_t latency
)
1677 if (WARN(latency
== 0, "Latency value missing\n"))
1680 ret
= (uint64_t) pixel_rate
* cpp
* latency
;
1681 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1686 /* latency must be in 0.1us units. */
1687 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1688 uint32_t horiz_pixels
, uint8_t cpp
,
1693 if (WARN(latency
== 0, "Latency value missing\n"))
1695 if (WARN_ON(!pipe_htotal
))
1698 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1699 ret
= (ret
+ 1) * horiz_pixels
* cpp
;
1700 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1704 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1708 * Neither of these should be possible since this function shouldn't be
1709 * called if the CRTC is off or the plane is invisible. But let's be
1710 * extra paranoid to avoid a potential divide-by-zero if we screw up
1711 * elsewhere in the driver.
1715 if (WARN_ON(!horiz_pixels
))
1718 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* cpp
) + 2;
1721 struct ilk_wm_maximums
{
1729 * For both WM_PIPE and WM_LP.
1730 * mem_value must be in 0.1us units.
1732 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state
*cstate
,
1733 const struct intel_plane_state
*pstate
,
1737 int cpp
= pstate
->base
.fb
?
1738 drm_format_plane_cpp(pstate
->base
.fb
->pixel_format
, 0) : 0;
1739 uint32_t method1
, method2
;
1741 if (!cstate
->base
.active
|| !pstate
->visible
)
1744 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), cpp
, mem_value
);
1749 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1750 cstate
->base
.adjusted_mode
.crtc_htotal
,
1751 drm_rect_width(&pstate
->dst
),
1754 return min(method1
, method2
);
1758 * For both WM_PIPE and WM_LP.
1759 * mem_value must be in 0.1us units.
1761 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state
*cstate
,
1762 const struct intel_plane_state
*pstate
,
1765 int cpp
= pstate
->base
.fb
?
1766 drm_format_plane_cpp(pstate
->base
.fb
->pixel_format
, 0) : 0;
1767 uint32_t method1
, method2
;
1769 if (!cstate
->base
.active
|| !pstate
->visible
)
1772 method1
= ilk_wm_method1(ilk_pipe_pixel_rate(cstate
), cpp
, mem_value
);
1773 method2
= ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1774 cstate
->base
.adjusted_mode
.crtc_htotal
,
1775 drm_rect_width(&pstate
->dst
),
1777 return min(method1
, method2
);
1781 * For both WM_PIPE and WM_LP.
1782 * mem_value must be in 0.1us units.
1784 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state
*cstate
,
1785 const struct intel_plane_state
*pstate
,
1789 * We treat the cursor plane as always-on for the purposes of watermark
1790 * calculation. Until we have two-stage watermark programming merged,
1791 * this is necessary to avoid flickering.
1794 int width
= pstate
->visible
? pstate
->base
.crtc_w
: 64;
1796 if (!cstate
->base
.active
)
1799 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate
),
1800 cstate
->base
.adjusted_mode
.crtc_htotal
,
1801 width
, cpp
, mem_value
);
1804 /* Only for WM_LP. */
1805 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state
*cstate
,
1806 const struct intel_plane_state
*pstate
,
1809 int cpp
= pstate
->base
.fb
?
1810 drm_format_plane_cpp(pstate
->base
.fb
->pixel_format
, 0) : 0;
1812 if (!cstate
->base
.active
|| !pstate
->visible
)
1815 return ilk_wm_fbc(pri_val
, drm_rect_width(&pstate
->dst
), cpp
);
1818 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1820 if (INTEL_INFO(dev
)->gen
>= 8)
1822 else if (INTEL_INFO(dev
)->gen
>= 7)
1828 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1829 int level
, bool is_sprite
)
1831 if (INTEL_INFO(dev
)->gen
>= 8)
1832 /* BDW primary/sprite plane watermarks */
1833 return level
== 0 ? 255 : 2047;
1834 else if (INTEL_INFO(dev
)->gen
>= 7)
1835 /* IVB/HSW primary/sprite plane watermarks */
1836 return level
== 0 ? 127 : 1023;
1837 else if (!is_sprite
)
1838 /* ILK/SNB primary plane watermarks */
1839 return level
== 0 ? 127 : 511;
1841 /* ILK/SNB sprite plane watermarks */
1842 return level
== 0 ? 63 : 255;
1845 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1848 if (INTEL_INFO(dev
)->gen
>= 7)
1849 return level
== 0 ? 63 : 255;
1851 return level
== 0 ? 31 : 63;
1854 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1856 if (INTEL_INFO(dev
)->gen
>= 8)
1862 /* Calculate the maximum primary/sprite plane watermark */
1863 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1865 const struct intel_wm_config
*config
,
1866 enum intel_ddb_partitioning ddb_partitioning
,
1869 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1871 /* if sprites aren't enabled, sprites get nothing */
1872 if (is_sprite
&& !config
->sprites_enabled
)
1875 /* HSW allows LP1+ watermarks even with multiple pipes */
1876 if (level
== 0 || config
->num_pipes_active
> 1) {
1877 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1880 * For some reason the non self refresh
1881 * FIFO size is only half of the self
1882 * refresh FIFO size on ILK/SNB.
1884 if (INTEL_INFO(dev
)->gen
<= 6)
1888 if (config
->sprites_enabled
) {
1889 /* level 0 is always calculated with 1:1 split */
1890 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1899 /* clamp to max that the registers can hold */
1900 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1903 /* Calculate the maximum cursor plane watermark */
1904 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1906 const struct intel_wm_config
*config
)
1908 /* HSW LP1+ watermarks w/ multiple pipes */
1909 if (level
> 0 && config
->num_pipes_active
> 1)
1912 /* otherwise just report max that registers can hold */
1913 return ilk_cursor_wm_reg_max(dev
, level
);
1916 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1918 const struct intel_wm_config
*config
,
1919 enum intel_ddb_partitioning ddb_partitioning
,
1920 struct ilk_wm_maximums
*max
)
1922 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1923 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1924 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1925 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1928 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1930 struct ilk_wm_maximums
*max
)
1932 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1933 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1934 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1935 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1938 static bool ilk_validate_wm_level(int level
,
1939 const struct ilk_wm_maximums
*max
,
1940 struct intel_wm_level
*result
)
1944 /* already determined to be invalid? */
1945 if (!result
->enable
)
1948 result
->enable
= result
->pri_val
<= max
->pri
&&
1949 result
->spr_val
<= max
->spr
&&
1950 result
->cur_val
<= max
->cur
;
1952 ret
= result
->enable
;
1955 * HACK until we can pre-compute everything,
1956 * and thus fail gracefully if LP0 watermarks
1959 if (level
== 0 && !result
->enable
) {
1960 if (result
->pri_val
> max
->pri
)
1961 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962 level
, result
->pri_val
, max
->pri
);
1963 if (result
->spr_val
> max
->spr
)
1964 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965 level
, result
->spr_val
, max
->spr
);
1966 if (result
->cur_val
> max
->cur
)
1967 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968 level
, result
->cur_val
, max
->cur
);
1970 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
1971 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
1972 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
1973 result
->enable
= true;
1979 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
1980 const struct intel_crtc
*intel_crtc
,
1982 struct intel_crtc_state
*cstate
,
1983 struct intel_plane_state
*pristate
,
1984 struct intel_plane_state
*sprstate
,
1985 struct intel_plane_state
*curstate
,
1986 struct intel_wm_level
*result
)
1988 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
1989 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
1990 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
1992 /* WM1+ latency values stored in 0.5us units */
2000 result
->pri_val
= ilk_compute_pri_wm(cstate
, pristate
,
2001 pri_latency
, level
);
2002 result
->fbc_val
= ilk_compute_fbc_wm(cstate
, pristate
, result
->pri_val
);
2006 result
->spr_val
= ilk_compute_spr_wm(cstate
, sprstate
, spr_latency
);
2009 result
->cur_val
= ilk_compute_cur_wm(cstate
, curstate
, cur_latency
);
2011 result
->enable
= true;
2015 hsw_compute_linetime_wm(const struct intel_crtc_state
*cstate
)
2017 const struct intel_atomic_state
*intel_state
=
2018 to_intel_atomic_state(cstate
->base
.state
);
2019 const struct drm_display_mode
*adjusted_mode
=
2020 &cstate
->base
.adjusted_mode
;
2021 u32 linetime
, ips_linetime
;
2023 if (!cstate
->base
.active
)
2025 if (WARN_ON(adjusted_mode
->crtc_clock
== 0))
2027 if (WARN_ON(intel_state
->cdclk
== 0))
2030 /* The WM are computed with base on how long it takes to fill a single
2031 * row at the given clock rate, multiplied by 8.
2033 linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2034 adjusted_mode
->crtc_clock
);
2035 ips_linetime
= DIV_ROUND_CLOSEST(adjusted_mode
->crtc_htotal
* 1000 * 8,
2036 intel_state
->cdclk
);
2038 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2039 PIPE_WM_LINETIME_TIME(linetime
);
2042 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[8])
2044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2049 int level
, max_level
= ilk_wm_max_level(dev
);
2051 /* read the first set of memory latencies[0:3] */
2052 val
= 0; /* data0 to be programmed to 0 for first set */
2053 mutex_lock(&dev_priv
->rps
.hw_lock
);
2054 ret
= sandybridge_pcode_read(dev_priv
,
2055 GEN9_PCODE_READ_MEM_LATENCY
,
2057 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2060 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2064 wm
[0] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2065 wm
[1] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2066 GEN9_MEM_LATENCY_LEVEL_MASK
;
2067 wm
[2] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2068 GEN9_MEM_LATENCY_LEVEL_MASK
;
2069 wm
[3] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2070 GEN9_MEM_LATENCY_LEVEL_MASK
;
2072 /* read the second set of memory latencies[4:7] */
2073 val
= 1; /* data0 to be programmed to 1 for second set */
2074 mutex_lock(&dev_priv
->rps
.hw_lock
);
2075 ret
= sandybridge_pcode_read(dev_priv
,
2076 GEN9_PCODE_READ_MEM_LATENCY
,
2078 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2080 DRM_ERROR("SKL Mailbox read error = %d\n", ret
);
2084 wm
[4] = val
& GEN9_MEM_LATENCY_LEVEL_MASK
;
2085 wm
[5] = (val
>> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT
) &
2086 GEN9_MEM_LATENCY_LEVEL_MASK
;
2087 wm
[6] = (val
>> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT
) &
2088 GEN9_MEM_LATENCY_LEVEL_MASK
;
2089 wm
[7] = (val
>> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT
) &
2090 GEN9_MEM_LATENCY_LEVEL_MASK
;
2093 * WaWmMemoryReadLatency:skl
2095 * punit doesn't take into account the read latency so we need
2096 * to add 2us to the various latency levels we retrieve from
2098 * - W0 is a bit special in that it's the only level that
2099 * can't be disabled if we want to have display working, so
2100 * we always add 2us there.
2101 * - For levels >=1, punit returns 0us latency when they are
2102 * disabled, so we respect that and don't add 2us then
2104 * Additionally, if a level n (n > 1) has a 0us latency, all
2105 * levels m (m >= n) need to be disabled. We make sure to
2106 * sanitize the values out of the punit to satisfy this
2110 for (level
= 1; level
<= max_level
; level
++)
2114 for (i
= level
+ 1; i
<= max_level
; i
++)
2119 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2120 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2122 wm
[0] = (sskpd
>> 56) & 0xFF;
2124 wm
[0] = sskpd
& 0xF;
2125 wm
[1] = (sskpd
>> 4) & 0xFF;
2126 wm
[2] = (sskpd
>> 12) & 0xFF;
2127 wm
[3] = (sskpd
>> 20) & 0x1FF;
2128 wm
[4] = (sskpd
>> 32) & 0x1FF;
2129 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2130 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2132 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2133 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2134 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2135 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2136 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2137 uint32_t mltr
= I915_READ(MLTR_ILK
);
2139 /* ILK primary LP0 latency is 700 ns */
2141 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2142 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2146 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2148 /* ILK sprite LP0 latency is 1300 ns */
2153 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2155 /* ILK cursor LP0 latency is 1300 ns */
2159 /* WaDoubleCursorLP3Latency:ivb */
2160 if (IS_IVYBRIDGE(dev
))
2164 int ilk_wm_max_level(const struct drm_device
*dev
)
2166 /* how many WM levels are we expecting */
2167 if (INTEL_INFO(dev
)->gen
>= 9)
2169 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2171 else if (INTEL_INFO(dev
)->gen
>= 6)
2177 static void intel_print_wm_latency(struct drm_device
*dev
,
2179 const uint16_t wm
[8])
2181 int level
, max_level
= ilk_wm_max_level(dev
);
2183 for (level
= 0; level
<= max_level
; level
++) {
2184 unsigned int latency
= wm
[level
];
2187 DRM_ERROR("%s WM%d latency not provided\n",
2193 * - latencies are in us on gen9.
2194 * - before then, WM1+ latency values are in 0.5us units
2201 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2202 name
, level
, wm
[level
],
2203 latency
/ 10, latency
% 10);
2207 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2208 uint16_t wm
[5], uint16_t min
)
2210 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
2215 wm
[0] = max(wm
[0], min
);
2216 for (level
= 1; level
<= max_level
; level
++)
2217 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2222 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2228 * The BIOS provided WM memory latency values are often
2229 * inadequate for high resolution displays. Adjust them.
2231 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2232 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2233 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2238 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2239 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2240 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2241 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2244 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2248 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2250 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2251 sizeof(dev_priv
->wm
.pri_latency
));
2252 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2253 sizeof(dev_priv
->wm
.pri_latency
));
2255 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2256 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2258 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2259 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2260 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2263 snb_wm_latency_quirk(dev
);
2266 static void skl_setup_wm_latency(struct drm_device
*dev
)
2268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2270 intel_read_wm_latency(dev
, dev_priv
->wm
.skl_latency
);
2271 intel_print_wm_latency(dev
, "Gen9 Plane", dev_priv
->wm
.skl_latency
);
2274 static bool ilk_validate_pipe_wm(struct drm_device
*dev
,
2275 struct intel_pipe_wm
*pipe_wm
)
2277 /* LP0 watermark maximums depend on this pipe alone */
2278 const struct intel_wm_config config
= {
2279 .num_pipes_active
= 1,
2280 .sprites_enabled
= pipe_wm
->sprites_enabled
,
2281 .sprites_scaled
= pipe_wm
->sprites_scaled
,
2283 struct ilk_wm_maximums max
;
2285 /* LP0 watermarks always use 1/2 DDB partitioning */
2286 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2288 /* At least LP0 must be valid */
2289 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0])) {
2290 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2297 /* Compute new watermarks for the pipe */
2298 static int ilk_compute_pipe_wm(struct intel_crtc_state
*cstate
)
2300 struct drm_atomic_state
*state
= cstate
->base
.state
;
2301 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
2302 struct intel_pipe_wm
*pipe_wm
;
2303 struct drm_device
*dev
= state
->dev
;
2304 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2305 struct intel_plane
*intel_plane
;
2306 struct intel_plane_state
*pristate
= NULL
;
2307 struct intel_plane_state
*sprstate
= NULL
;
2308 struct intel_plane_state
*curstate
= NULL
;
2309 int level
, max_level
= ilk_wm_max_level(dev
), usable_level
;
2310 struct ilk_wm_maximums max
;
2312 pipe_wm
= &cstate
->wm
.ilk
.optimal
;
2314 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
2315 struct intel_plane_state
*ps
;
2317 ps
= intel_atomic_get_existing_plane_state(state
,
2322 if (intel_plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
2324 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_OVERLAY
)
2326 else if (intel_plane
->base
.type
== DRM_PLANE_TYPE_CURSOR
)
2330 pipe_wm
->pipe_enabled
= cstate
->base
.active
;
2332 pipe_wm
->sprites_enabled
= sprstate
->visible
;
2333 pipe_wm
->sprites_scaled
= sprstate
->visible
&&
2334 (drm_rect_width(&sprstate
->dst
) != drm_rect_width(&sprstate
->src
) >> 16 ||
2335 drm_rect_height(&sprstate
->dst
) != drm_rect_height(&sprstate
->src
) >> 16);
2338 usable_level
= max_level
;
2340 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2341 if (INTEL_INFO(dev
)->gen
<= 6 && pipe_wm
->sprites_enabled
)
2344 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2345 if (pipe_wm
->sprites_scaled
)
2348 ilk_compute_wm_level(dev_priv
, intel_crtc
, 0, cstate
,
2349 pristate
, sprstate
, curstate
, &pipe_wm
->raw_wm
[0]);
2351 memset(&pipe_wm
->wm
, 0, sizeof(pipe_wm
->wm
));
2352 pipe_wm
->wm
[0] = pipe_wm
->raw_wm
[0];
2354 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2355 pipe_wm
->linetime
= hsw_compute_linetime_wm(cstate
);
2357 if (!ilk_validate_pipe_wm(dev
, pipe_wm
))
2360 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2362 for (level
= 1; level
<= max_level
; level
++) {
2363 struct intel_wm_level
*wm
= &pipe_wm
->raw_wm
[level
];
2365 ilk_compute_wm_level(dev_priv
, intel_crtc
, level
, cstate
,
2366 pristate
, sprstate
, curstate
, wm
);
2369 * Disable any watermark level that exceeds the
2370 * register maximums since such watermarks are
2373 if (level
> usable_level
)
2376 if (ilk_validate_wm_level(level
, &max
, wm
))
2377 pipe_wm
->wm
[level
] = *wm
;
2379 usable_level
= level
;
2386 * Build a set of 'intermediate' watermark values that satisfy both the old
2387 * state and the new state. These can be programmed to the hardware
2390 static int ilk_compute_intermediate_wm(struct drm_device
*dev
,
2391 struct intel_crtc
*intel_crtc
,
2392 struct intel_crtc_state
*newstate
)
2394 struct intel_pipe_wm
*a
= &newstate
->wm
.ilk
.intermediate
;
2395 struct intel_pipe_wm
*b
= &intel_crtc
->wm
.active
.ilk
;
2396 int level
, max_level
= ilk_wm_max_level(dev
);
2399 * Start with the final, target watermarks, then combine with the
2400 * currently active watermarks to get values that are safe both before
2401 * and after the vblank.
2403 *a
= newstate
->wm
.ilk
.optimal
;
2404 a
->pipe_enabled
|= b
->pipe_enabled
;
2405 a
->sprites_enabled
|= b
->sprites_enabled
;
2406 a
->sprites_scaled
|= b
->sprites_scaled
;
2408 for (level
= 0; level
<= max_level
; level
++) {
2409 struct intel_wm_level
*a_wm
= &a
->wm
[level
];
2410 const struct intel_wm_level
*b_wm
= &b
->wm
[level
];
2412 a_wm
->enable
&= b_wm
->enable
;
2413 a_wm
->pri_val
= max(a_wm
->pri_val
, b_wm
->pri_val
);
2414 a_wm
->spr_val
= max(a_wm
->spr_val
, b_wm
->spr_val
);
2415 a_wm
->cur_val
= max(a_wm
->cur_val
, b_wm
->cur_val
);
2416 a_wm
->fbc_val
= max(a_wm
->fbc_val
, b_wm
->fbc_val
);
2420 * We need to make sure that these merged watermark values are
2421 * actually a valid configuration themselves. If they're not,
2422 * there's no safe way to transition from the old state to
2423 * the new state, so we need to fail the atomic transaction.
2425 if (!ilk_validate_pipe_wm(dev
, a
))
2429 * If our intermediate WM are identical to the final WM, then we can
2430 * omit the post-vblank programming; only update if it's different.
2432 if (memcmp(a
, &newstate
->wm
.ilk
.optimal
, sizeof(*a
)) == 0)
2433 newstate
->wm
.need_postvbl_update
= false;
2439 * Merge the watermarks from all active pipes for a specific level.
2441 static void ilk_merge_wm_level(struct drm_device
*dev
,
2443 struct intel_wm_level
*ret_wm
)
2445 const struct intel_crtc
*intel_crtc
;
2447 ret_wm
->enable
= true;
2449 for_each_intel_crtc(dev
, intel_crtc
) {
2450 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
.ilk
;
2451 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2453 if (!active
->pipe_enabled
)
2457 * The watermark values may have been used in the past,
2458 * so we must maintain them in the registers for some
2459 * time even if the level is now disabled.
2462 ret_wm
->enable
= false;
2464 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2465 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2466 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2467 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2472 * Merge all low power watermarks for all active pipes.
2474 static void ilk_wm_merge(struct drm_device
*dev
,
2475 const struct intel_wm_config
*config
,
2476 const struct ilk_wm_maximums
*max
,
2477 struct intel_pipe_wm
*merged
)
2479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2480 int level
, max_level
= ilk_wm_max_level(dev
);
2481 int last_enabled_level
= max_level
;
2483 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2484 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2485 config
->num_pipes_active
> 1)
2486 last_enabled_level
= 0;
2488 /* ILK: FBC WM must be disabled always */
2489 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2491 /* merge each WM1+ level */
2492 for (level
= 1; level
<= max_level
; level
++) {
2493 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2495 ilk_merge_wm_level(dev
, level
, wm
);
2497 if (level
> last_enabled_level
)
2499 else if (!ilk_validate_wm_level(level
, max
, wm
))
2500 /* make sure all following levels get disabled */
2501 last_enabled_level
= level
- 1;
2504 * The spec says it is preferred to disable
2505 * FBC WMs instead of disabling a WM level.
2507 if (wm
->fbc_val
> max
->fbc
) {
2509 merged
->fbc_wm_enabled
= false;
2514 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2516 * FIXME this is racy. FBC might get enabled later.
2517 * What we should check here is whether FBC can be
2518 * enabled sometime later.
2520 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&&
2521 intel_fbc_is_active(dev_priv
)) {
2522 for (level
= 2; level
<= max_level
; level
++) {
2523 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2530 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2532 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2533 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2536 /* The value we need to program into the WM_LPx latency field */
2537 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2541 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2544 return dev_priv
->wm
.pri_latency
[level
];
2547 static void ilk_compute_wm_results(struct drm_device
*dev
,
2548 const struct intel_pipe_wm
*merged
,
2549 enum intel_ddb_partitioning partitioning
,
2550 struct ilk_wm_values
*results
)
2552 struct intel_crtc
*intel_crtc
;
2555 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2556 results
->partitioning
= partitioning
;
2558 /* LP1+ register values */
2559 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2560 const struct intel_wm_level
*r
;
2562 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2564 r
= &merged
->wm
[level
];
2567 * Maintain the watermark values even if the level is
2568 * disabled. Doing otherwise could cause underruns.
2570 results
->wm_lp
[wm_lp
- 1] =
2571 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2572 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2576 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2578 if (INTEL_INFO(dev
)->gen
>= 8)
2579 results
->wm_lp
[wm_lp
- 1] |=
2580 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2582 results
->wm_lp
[wm_lp
- 1] |=
2583 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2586 * Always set WM1S_LP_EN when spr_val != 0, even if the
2587 * level is disabled. Doing otherwise could cause underruns.
2589 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2590 WARN_ON(wm_lp
!= 1);
2591 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2593 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2596 /* LP0 register values */
2597 for_each_intel_crtc(dev
, intel_crtc
) {
2598 enum pipe pipe
= intel_crtc
->pipe
;
2599 const struct intel_wm_level
*r
=
2600 &intel_crtc
->wm
.active
.ilk
.wm
[0];
2602 if (WARN_ON(!r
->enable
))
2605 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.ilk
.linetime
;
2607 results
->wm_pipe
[pipe
] =
2608 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2609 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2614 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2615 * case both are at the same level. Prefer r1 in case they're the same. */
2616 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2617 struct intel_pipe_wm
*r1
,
2618 struct intel_pipe_wm
*r2
)
2620 int level
, max_level
= ilk_wm_max_level(dev
);
2621 int level1
= 0, level2
= 0;
2623 for (level
= 1; level
<= max_level
; level
++) {
2624 if (r1
->wm
[level
].enable
)
2626 if (r2
->wm
[level
].enable
)
2630 if (level1
== level2
) {
2631 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2635 } else if (level1
> level2
) {
2642 /* dirty bits used to track which watermarks need changes */
2643 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2644 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2645 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2646 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2647 #define WM_DIRTY_FBC (1 << 24)
2648 #define WM_DIRTY_DDB (1 << 25)
2650 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private
*dev_priv
,
2651 const struct ilk_wm_values
*old
,
2652 const struct ilk_wm_values
*new)
2654 unsigned int dirty
= 0;
2658 for_each_pipe(dev_priv
, pipe
) {
2659 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2660 dirty
|= WM_DIRTY_LINETIME(pipe
);
2661 /* Must disable LP1+ watermarks too */
2662 dirty
|= WM_DIRTY_LP_ALL
;
2665 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2666 dirty
|= WM_DIRTY_PIPE(pipe
);
2667 /* Must disable LP1+ watermarks too */
2668 dirty
|= WM_DIRTY_LP_ALL
;
2672 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2673 dirty
|= WM_DIRTY_FBC
;
2674 /* Must disable LP1+ watermarks too */
2675 dirty
|= WM_DIRTY_LP_ALL
;
2678 if (old
->partitioning
!= new->partitioning
) {
2679 dirty
|= WM_DIRTY_DDB
;
2680 /* Must disable LP1+ watermarks too */
2681 dirty
|= WM_DIRTY_LP_ALL
;
2684 /* LP1+ watermarks already deemed dirty, no need to continue */
2685 if (dirty
& WM_DIRTY_LP_ALL
)
2688 /* Find the lowest numbered LP1+ watermark in need of an update... */
2689 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2690 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2691 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2695 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2696 for (; wm_lp
<= 3; wm_lp
++)
2697 dirty
|= WM_DIRTY_LP(wm_lp
);
2702 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2705 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2706 bool changed
= false;
2708 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2709 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2710 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2713 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2714 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2715 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2718 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2719 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2720 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2725 * Don't touch WM1S_LP_EN here.
2726 * Doing so could cause underruns.
2733 * The spec says we shouldn't write when we don't need, because every write
2734 * causes WMs to be re-evaluated, expending some power.
2736 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2737 struct ilk_wm_values
*results
)
2739 struct drm_device
*dev
= dev_priv
->dev
;
2740 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2744 dirty
= ilk_compute_wm_dirty(dev_priv
, previous
, results
);
2748 _ilk_disable_lp_wm(dev_priv
, dirty
);
2750 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2751 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2752 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2753 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2754 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2755 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2757 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2758 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2759 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2760 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2761 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2762 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2764 if (dirty
& WM_DIRTY_DDB
) {
2765 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2766 val
= I915_READ(WM_MISC
);
2767 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2768 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2770 val
|= WM_MISC_DATA_PARTITION_5_6
;
2771 I915_WRITE(WM_MISC
, val
);
2773 val
= I915_READ(DISP_ARB_CTL2
);
2774 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2775 val
&= ~DISP_DATA_PARTITION_5_6
;
2777 val
|= DISP_DATA_PARTITION_5_6
;
2778 I915_WRITE(DISP_ARB_CTL2
, val
);
2782 if (dirty
& WM_DIRTY_FBC
) {
2783 val
= I915_READ(DISP_ARB_CTL
);
2784 if (results
->enable_fbc_wm
)
2785 val
&= ~DISP_FBC_WM_DIS
;
2787 val
|= DISP_FBC_WM_DIS
;
2788 I915_WRITE(DISP_ARB_CTL
, val
);
2791 if (dirty
& WM_DIRTY_LP(1) &&
2792 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2793 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2795 if (INTEL_INFO(dev
)->gen
>= 7) {
2796 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2797 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2798 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2799 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2802 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2803 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2804 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2805 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2806 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2807 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2809 dev_priv
->wm
.hw
= *results
;
2812 bool ilk_disable_lp_wm(struct drm_device
*dev
)
2814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2816 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2820 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2821 * different active planes.
2824 #define SKL_DDB_SIZE 896 /* in blocks */
2825 #define BXT_DDB_SIZE 512
2828 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2829 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2830 * other universal planes are in indices 1..n. Note that this may leave unused
2831 * indices between the top "sprite" plane and the cursor.
2834 skl_wm_plane_id(const struct intel_plane
*plane
)
2836 switch (plane
->base
.type
) {
2837 case DRM_PLANE_TYPE_PRIMARY
:
2839 case DRM_PLANE_TYPE_CURSOR
:
2840 return PLANE_CURSOR
;
2841 case DRM_PLANE_TYPE_OVERLAY
:
2842 return plane
->plane
+ 1;
2844 MISSING_CASE(plane
->base
.type
);
2845 return plane
->plane
;
2850 skl_ddb_get_pipe_allocation_limits(struct drm_device
*dev
,
2851 const struct intel_crtc_state
*cstate
,
2852 const struct intel_wm_config
*config
,
2853 struct skl_ddb_entry
*alloc
/* out */)
2855 struct drm_crtc
*for_crtc
= cstate
->base
.crtc
;
2856 struct drm_crtc
*crtc
;
2857 unsigned int pipe_size
, ddb_size
;
2858 int nth_active_pipe
;
2860 if (!cstate
->base
.active
) {
2866 if (IS_BROXTON(dev
))
2867 ddb_size
= BXT_DDB_SIZE
;
2869 ddb_size
= SKL_DDB_SIZE
;
2871 ddb_size
-= 4; /* 4 blocks for bypass path allocation */
2873 nth_active_pipe
= 0;
2874 for_each_crtc(dev
, crtc
) {
2875 if (!to_intel_crtc(crtc
)->active
)
2878 if (crtc
== for_crtc
)
2884 pipe_size
= ddb_size
/ config
->num_pipes_active
;
2885 alloc
->start
= nth_active_pipe
* ddb_size
/ config
->num_pipes_active
;
2886 alloc
->end
= alloc
->start
+ pipe_size
;
2889 static unsigned int skl_cursor_allocation(const struct intel_wm_config
*config
)
2891 if (config
->num_pipes_active
== 1)
2897 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry
*entry
, u32 reg
)
2899 entry
->start
= reg
& 0x3ff;
2900 entry
->end
= (reg
>> 16) & 0x3ff;
2905 void skl_ddb_get_hw_state(struct drm_i915_private
*dev_priv
,
2906 struct skl_ddb_allocation
*ddb
/* out */)
2912 memset(ddb
, 0, sizeof(*ddb
));
2914 for_each_pipe(dev_priv
, pipe
) {
2915 enum intel_display_power_domain power_domain
;
2917 power_domain
= POWER_DOMAIN_PIPE(pipe
);
2918 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
))
2921 for_each_plane(dev_priv
, pipe
, plane
) {
2922 val
= I915_READ(PLANE_BUF_CFG(pipe
, plane
));
2923 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][plane
],
2927 val
= I915_READ(CUR_BUF_CFG(pipe
));
2928 skl_ddb_entry_init_from_hw(&ddb
->plane
[pipe
][PLANE_CURSOR
],
2931 intel_display_power_put(dev_priv
, power_domain
);
2936 skl_plane_relative_data_rate(const struct intel_crtc_state
*cstate
,
2937 const struct drm_plane_state
*pstate
,
2940 struct intel_plane_state
*intel_pstate
= to_intel_plane_state(pstate
);
2941 struct drm_framebuffer
*fb
= pstate
->fb
;
2942 uint32_t width
= 0, height
= 0;
2943 unsigned format
= fb
? fb
->pixel_format
: DRM_FORMAT_XRGB8888
;
2945 if (!intel_pstate
->visible
)
2947 if (pstate
->plane
->type
== DRM_PLANE_TYPE_CURSOR
)
2949 if (y
&& format
!= DRM_FORMAT_NV12
)
2952 width
= drm_rect_width(&intel_pstate
->src
) >> 16;
2953 height
= drm_rect_height(&intel_pstate
->src
) >> 16;
2955 if (intel_rotation_90_or_270(pstate
->rotation
))
2956 swap(width
, height
);
2958 /* for planar format */
2959 if (format
== DRM_FORMAT_NV12
) {
2960 if (y
) /* y-plane data rate */
2961 return width
* height
*
2962 drm_format_plane_cpp(format
, 0);
2963 else /* uv-plane data rate */
2964 return (width
/ 2) * (height
/ 2) *
2965 drm_format_plane_cpp(format
, 1);
2968 /* for packed formats */
2969 return width
* height
* drm_format_plane_cpp(format
, 0);
2973 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2974 * a 8192x4096@32bpp framebuffer:
2975 * 3 * 4096 * 8192 * 4 < 2^32
2978 skl_get_total_relative_data_rate(struct intel_crtc_state
*intel_cstate
)
2980 struct drm_crtc_state
*cstate
= &intel_cstate
->base
;
2981 struct drm_atomic_state
*state
= cstate
->state
;
2982 struct drm_crtc
*crtc
= cstate
->crtc
;
2983 struct drm_device
*dev
= crtc
->dev
;
2984 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2985 const struct intel_plane
*intel_plane
;
2986 unsigned int rate
, total_data_rate
= 0;
2989 /* Calculate and cache data rate for each plane */
2991 * FIXME: At the moment this function can be called on either an
2992 * in-flight or a committed state object. If it's in-flight then we
2993 * only want to re-calculate the plane data rate for planes that are
2994 * part of the transaction (i.e., we don't want to grab any additional
2995 * plane states if we don't have to). If we're operating on committed
2996 * state, we'll just go ahead and recalculate the plane data rate for
2999 * Once we finish moving our DDB allocation to the atomic check phase,
3000 * we'll only be calling this function on in-flight state objects, so
3001 * the 'else' branch here will go away.
3004 struct drm_plane
*plane
;
3005 struct drm_plane_state
*pstate
;
3008 for_each_plane_in_state(state
, plane
, pstate
, i
) {
3009 intel_plane
= to_intel_plane(plane
);
3010 id
= skl_wm_plane_id(intel_plane
);
3012 if (intel_plane
->pipe
!= intel_crtc
->pipe
)
3016 rate
= skl_plane_relative_data_rate(intel_cstate
,
3018 intel_cstate
->wm
.skl
.plane_data_rate
[id
] = rate
;
3021 rate
= skl_plane_relative_data_rate(intel_cstate
,
3023 intel_cstate
->wm
.skl
.plane_y_data_rate
[id
] = rate
;
3026 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3027 const struct drm_plane_state
*pstate
=
3028 intel_plane
->base
.state
;
3029 int id
= skl_wm_plane_id(intel_plane
);
3032 rate
= skl_plane_relative_data_rate(intel_cstate
,
3034 intel_cstate
->wm
.skl
.plane_data_rate
[id
] = rate
;
3037 rate
= skl_plane_relative_data_rate(intel_cstate
,
3039 intel_cstate
->wm
.skl
.plane_y_data_rate
[id
] = rate
;
3043 /* Calculate CRTC's total data rate from cached values */
3044 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3045 int id
= skl_wm_plane_id(intel_plane
);
3048 total_data_rate
+= intel_cstate
->wm
.skl
.plane_data_rate
[id
];
3049 total_data_rate
+= intel_cstate
->wm
.skl
.plane_y_data_rate
[id
];
3052 WARN_ON(cstate
->plane_mask
&& total_data_rate
== 0);
3054 return total_data_rate
;
3058 skl_allocate_pipe_ddb(struct intel_crtc_state
*cstate
,
3059 struct skl_ddb_allocation
*ddb
/* out */)
3061 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3062 struct drm_device
*dev
= crtc
->dev
;
3063 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3064 struct intel_wm_config
*config
= &dev_priv
->wm
.config
;
3065 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3066 struct intel_plane
*intel_plane
;
3067 enum pipe pipe
= intel_crtc
->pipe
;
3068 struct skl_ddb_entry
*alloc
= &ddb
->pipe
[pipe
];
3069 uint16_t alloc_size
, start
, cursor_blocks
;
3070 uint16_t *minimum
= cstate
->wm
.skl
.minimum_blocks
;
3071 uint16_t *y_minimum
= cstate
->wm
.skl
.minimum_y_blocks
;
3072 unsigned int total_data_rate
;
3074 skl_ddb_get_pipe_allocation_limits(dev
, cstate
, config
, alloc
);
3075 alloc_size
= skl_ddb_entry_size(alloc
);
3076 if (alloc_size
== 0) {
3077 memset(ddb
->plane
[pipe
], 0, sizeof(ddb
->plane
[pipe
]));
3078 memset(&ddb
->plane
[pipe
][PLANE_CURSOR
], 0,
3079 sizeof(ddb
->plane
[pipe
][PLANE_CURSOR
]));
3083 cursor_blocks
= skl_cursor_allocation(config
);
3084 ddb
->plane
[pipe
][PLANE_CURSOR
].start
= alloc
->end
- cursor_blocks
;
3085 ddb
->plane
[pipe
][PLANE_CURSOR
].end
= alloc
->end
;
3087 alloc_size
-= cursor_blocks
;
3088 alloc
->end
-= cursor_blocks
;
3090 /* 1. Allocate the mininum required blocks for each active plane */
3091 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3092 struct drm_plane
*plane
= &intel_plane
->base
;
3093 struct drm_framebuffer
*fb
= plane
->state
->fb
;
3094 int id
= skl_wm_plane_id(intel_plane
);
3096 if (!to_intel_plane_state(plane
->state
)->visible
)
3099 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
3103 alloc_size
-= minimum
[id
];
3104 y_minimum
[id
] = (fb
->pixel_format
== DRM_FORMAT_NV12
) ? 8 : 0;
3105 alloc_size
-= y_minimum
[id
];
3109 * 2. Distribute the remaining space in proportion to the amount of
3110 * data each plane needs to fetch from memory.
3112 * FIXME: we may not allocate every single block here.
3114 total_data_rate
= skl_get_total_relative_data_rate(cstate
);
3115 if (total_data_rate
== 0)
3118 start
= alloc
->start
;
3119 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3120 struct drm_plane
*plane
= &intel_plane
->base
;
3121 struct drm_plane_state
*pstate
= intel_plane
->base
.state
;
3122 unsigned int data_rate
, y_data_rate
;
3123 uint16_t plane_blocks
, y_plane_blocks
= 0;
3124 int id
= skl_wm_plane_id(intel_plane
);
3126 if (!to_intel_plane_state(pstate
)->visible
)
3128 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
3131 data_rate
= cstate
->wm
.skl
.plane_data_rate
[id
];
3134 * allocation for (packed formats) or (uv-plane part of planar format):
3135 * promote the expression to 64 bits to avoid overflowing, the
3136 * result is < available as data_rate / total_data_rate < 1
3138 plane_blocks
= minimum
[id
];
3139 plane_blocks
+= div_u64((uint64_t)alloc_size
* data_rate
,
3142 ddb
->plane
[pipe
][id
].start
= start
;
3143 ddb
->plane
[pipe
][id
].end
= start
+ plane_blocks
;
3145 start
+= plane_blocks
;
3148 * allocation for y_plane part of planar format:
3150 y_data_rate
= cstate
->wm
.skl
.plane_y_data_rate
[id
];
3152 y_plane_blocks
= y_minimum
[id
];
3153 y_plane_blocks
+= div_u64((uint64_t)alloc_size
* y_data_rate
,
3156 ddb
->y_plane
[pipe
][id
].start
= start
;
3157 ddb
->y_plane
[pipe
][id
].end
= start
+ y_plane_blocks
;
3159 start
+= y_plane_blocks
;
3164 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state
*config
)
3166 /* TODO: Take into account the scalers once we support them */
3167 return config
->base
.adjusted_mode
.crtc_clock
;
3171 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3172 * for the read latency) and cpp should always be <= 8, so that
3173 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3174 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3176 static uint32_t skl_wm_method1(uint32_t pixel_rate
, uint8_t cpp
, uint32_t latency
)
3178 uint32_t wm_intermediate_val
, ret
;
3183 wm_intermediate_val
= latency
* pixel_rate
* cpp
/ 512;
3184 ret
= DIV_ROUND_UP(wm_intermediate_val
, 1000);
3189 static uint32_t skl_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
3190 uint32_t horiz_pixels
, uint8_t cpp
,
3191 uint64_t tiling
, uint32_t latency
)
3194 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3195 uint32_t wm_intermediate_val
;
3200 plane_bytes_per_line
= horiz_pixels
* cpp
;
3202 if (tiling
== I915_FORMAT_MOD_Y_TILED
||
3203 tiling
== I915_FORMAT_MOD_Yf_TILED
) {
3204 plane_bytes_per_line
*= 4;
3205 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3206 plane_blocks_per_line
/= 4;
3208 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3211 wm_intermediate_val
= latency
* pixel_rate
;
3212 ret
= DIV_ROUND_UP(wm_intermediate_val
, pipe_htotal
* 1000) *
3213 plane_blocks_per_line
;
3218 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation
*new_ddb
,
3219 const struct intel_crtc
*intel_crtc
)
3221 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3223 const struct skl_ddb_allocation
*cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3226 * If ddb allocation of pipes changed, it may require recalculation of
3229 if (memcmp(new_ddb
->pipe
, cur_ddb
->pipe
, sizeof(new_ddb
->pipe
)))
3235 static bool skl_compute_plane_wm(const struct drm_i915_private
*dev_priv
,
3236 struct intel_crtc_state
*cstate
,
3237 struct intel_plane
*intel_plane
,
3238 uint16_t ddb_allocation
,
3240 uint16_t *out_blocks
, /* out */
3241 uint8_t *out_lines
/* out */)
3243 struct drm_plane
*plane
= &intel_plane
->base
;
3244 struct drm_framebuffer
*fb
= plane
->state
->fb
;
3245 struct intel_plane_state
*intel_pstate
=
3246 to_intel_plane_state(plane
->state
);
3247 uint32_t latency
= dev_priv
->wm
.skl_latency
[level
];
3248 uint32_t method1
, method2
;
3249 uint32_t plane_bytes_per_line
, plane_blocks_per_line
;
3250 uint32_t res_blocks
, res_lines
;
3251 uint32_t selected_result
;
3253 uint32_t width
= 0, height
= 0;
3255 if (latency
== 0 || !cstate
->base
.active
|| !intel_pstate
->visible
)
3258 width
= drm_rect_width(&intel_pstate
->src
) >> 16;
3259 height
= drm_rect_height(&intel_pstate
->src
) >> 16;
3261 if (intel_rotation_90_or_270(plane
->state
->rotation
))
3262 swap(width
, height
);
3264 cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
3265 method1
= skl_wm_method1(skl_pipe_pixel_rate(cstate
),
3267 method2
= skl_wm_method2(skl_pipe_pixel_rate(cstate
),
3268 cstate
->base
.adjusted_mode
.crtc_htotal
,
3274 plane_bytes_per_line
= width
* cpp
;
3275 plane_blocks_per_line
= DIV_ROUND_UP(plane_bytes_per_line
, 512);
3277 if (fb
->modifier
[0] == I915_FORMAT_MOD_Y_TILED
||
3278 fb
->modifier
[0] == I915_FORMAT_MOD_Yf_TILED
) {
3279 uint32_t min_scanlines
= 4;
3280 uint32_t y_tile_minimum
;
3281 if (intel_rotation_90_or_270(plane
->state
->rotation
)) {
3282 int cpp
= (fb
->pixel_format
== DRM_FORMAT_NV12
) ?
3283 drm_format_plane_cpp(fb
->pixel_format
, 1) :
3284 drm_format_plane_cpp(fb
->pixel_format
, 0);
3294 WARN(1, "Unsupported pixel depth for rotation");
3297 y_tile_minimum
= plane_blocks_per_line
* min_scanlines
;
3298 selected_result
= max(method2
, y_tile_minimum
);
3300 if ((ddb_allocation
/ plane_blocks_per_line
) >= 1)
3301 selected_result
= min(method1
, method2
);
3303 selected_result
= method1
;
3306 res_blocks
= selected_result
+ 1;
3307 res_lines
= DIV_ROUND_UP(selected_result
, plane_blocks_per_line
);
3309 if (level
>= 1 && level
<= 7) {
3310 if (fb
->modifier
[0] == I915_FORMAT_MOD_Y_TILED
||
3311 fb
->modifier
[0] == I915_FORMAT_MOD_Yf_TILED
)
3317 if (res_blocks
>= ddb_allocation
|| res_lines
> 31)
3320 *out_blocks
= res_blocks
;
3321 *out_lines
= res_lines
;
3326 static void skl_compute_wm_level(const struct drm_i915_private
*dev_priv
,
3327 struct skl_ddb_allocation
*ddb
,
3328 struct intel_crtc_state
*cstate
,
3330 struct skl_wm_level
*result
)
3332 struct drm_device
*dev
= dev_priv
->dev
;
3333 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3334 struct intel_plane
*intel_plane
;
3335 uint16_t ddb_blocks
;
3336 enum pipe pipe
= intel_crtc
->pipe
;
3338 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3339 int i
= skl_wm_plane_id(intel_plane
);
3341 ddb_blocks
= skl_ddb_entry_size(&ddb
->plane
[pipe
][i
]);
3343 result
->plane_en
[i
] = skl_compute_plane_wm(dev_priv
,
3348 &result
->plane_res_b
[i
],
3349 &result
->plane_res_l
[i
]);
3354 skl_compute_linetime_wm(struct intel_crtc_state
*cstate
)
3356 if (!cstate
->base
.active
)
3359 if (WARN_ON(skl_pipe_pixel_rate(cstate
) == 0))
3362 return DIV_ROUND_UP(8 * cstate
->base
.adjusted_mode
.crtc_htotal
* 1000,
3363 skl_pipe_pixel_rate(cstate
));
3366 static void skl_compute_transition_wm(struct intel_crtc_state
*cstate
,
3367 struct skl_wm_level
*trans_wm
/* out */)
3369 struct drm_crtc
*crtc
= cstate
->base
.crtc
;
3370 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3371 struct intel_plane
*intel_plane
;
3373 if (!cstate
->base
.active
)
3376 /* Until we know more, just disable transition WMs */
3377 for_each_intel_plane_on_crtc(crtc
->dev
, intel_crtc
, intel_plane
) {
3378 int i
= skl_wm_plane_id(intel_plane
);
3380 trans_wm
->plane_en
[i
] = false;
3384 static void skl_build_pipe_wm(struct intel_crtc_state
*cstate
,
3385 struct skl_ddb_allocation
*ddb
,
3386 struct skl_pipe_wm
*pipe_wm
)
3388 struct drm_device
*dev
= cstate
->base
.crtc
->dev
;
3389 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3390 int level
, max_level
= ilk_wm_max_level(dev
);
3392 for (level
= 0; level
<= max_level
; level
++) {
3393 skl_compute_wm_level(dev_priv
, ddb
, cstate
,
3394 level
, &pipe_wm
->wm
[level
]);
3396 pipe_wm
->linetime
= skl_compute_linetime_wm(cstate
);
3398 skl_compute_transition_wm(cstate
, &pipe_wm
->trans_wm
);
3401 static void skl_compute_wm_results(struct drm_device
*dev
,
3402 struct skl_pipe_wm
*p_wm
,
3403 struct skl_wm_values
*r
,
3404 struct intel_crtc
*intel_crtc
)
3406 int level
, max_level
= ilk_wm_max_level(dev
);
3407 enum pipe pipe
= intel_crtc
->pipe
;
3411 for (level
= 0; level
<= max_level
; level
++) {
3412 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3415 temp
|= p_wm
->wm
[level
].plane_res_l
[i
] <<
3416 PLANE_WM_LINES_SHIFT
;
3417 temp
|= p_wm
->wm
[level
].plane_res_b
[i
];
3418 if (p_wm
->wm
[level
].plane_en
[i
])
3419 temp
|= PLANE_WM_EN
;
3421 r
->plane
[pipe
][i
][level
] = temp
;
3426 temp
|= p_wm
->wm
[level
].plane_res_l
[PLANE_CURSOR
] << PLANE_WM_LINES_SHIFT
;
3427 temp
|= p_wm
->wm
[level
].plane_res_b
[PLANE_CURSOR
];
3429 if (p_wm
->wm
[level
].plane_en
[PLANE_CURSOR
])
3430 temp
|= PLANE_WM_EN
;
3432 r
->plane
[pipe
][PLANE_CURSOR
][level
] = temp
;
3436 /* transition WMs */
3437 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3439 temp
|= p_wm
->trans_wm
.plane_res_l
[i
] << PLANE_WM_LINES_SHIFT
;
3440 temp
|= p_wm
->trans_wm
.plane_res_b
[i
];
3441 if (p_wm
->trans_wm
.plane_en
[i
])
3442 temp
|= PLANE_WM_EN
;
3444 r
->plane_trans
[pipe
][i
] = temp
;
3448 temp
|= p_wm
->trans_wm
.plane_res_l
[PLANE_CURSOR
] << PLANE_WM_LINES_SHIFT
;
3449 temp
|= p_wm
->trans_wm
.plane_res_b
[PLANE_CURSOR
];
3450 if (p_wm
->trans_wm
.plane_en
[PLANE_CURSOR
])
3451 temp
|= PLANE_WM_EN
;
3453 r
->plane_trans
[pipe
][PLANE_CURSOR
] = temp
;
3455 r
->wm_linetime
[pipe
] = p_wm
->linetime
;
3458 static void skl_ddb_entry_write(struct drm_i915_private
*dev_priv
,
3460 const struct skl_ddb_entry
*entry
)
3463 I915_WRITE(reg
, (entry
->end
- 1) << 16 | entry
->start
);
3468 static void skl_write_wm_values(struct drm_i915_private
*dev_priv
,
3469 const struct skl_wm_values
*new)
3471 struct drm_device
*dev
= dev_priv
->dev
;
3472 struct intel_crtc
*crtc
;
3474 for_each_intel_crtc(dev
, crtc
) {
3475 int i
, level
, max_level
= ilk_wm_max_level(dev
);
3476 enum pipe pipe
= crtc
->pipe
;
3478 if (!new->dirty
[pipe
])
3481 I915_WRITE(PIPE_WM_LINETIME(pipe
), new->wm_linetime
[pipe
]);
3483 for (level
= 0; level
<= max_level
; level
++) {
3484 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3485 I915_WRITE(PLANE_WM(pipe
, i
, level
),
3486 new->plane
[pipe
][i
][level
]);
3487 I915_WRITE(CUR_WM(pipe
, level
),
3488 new->plane
[pipe
][PLANE_CURSOR
][level
]);
3490 for (i
= 0; i
< intel_num_planes(crtc
); i
++)
3491 I915_WRITE(PLANE_WM_TRANS(pipe
, i
),
3492 new->plane_trans
[pipe
][i
]);
3493 I915_WRITE(CUR_WM_TRANS(pipe
),
3494 new->plane_trans
[pipe
][PLANE_CURSOR
]);
3496 for (i
= 0; i
< intel_num_planes(crtc
); i
++) {
3497 skl_ddb_entry_write(dev_priv
,
3498 PLANE_BUF_CFG(pipe
, i
),
3499 &new->ddb
.plane
[pipe
][i
]);
3500 skl_ddb_entry_write(dev_priv
,
3501 PLANE_NV12_BUF_CFG(pipe
, i
),
3502 &new->ddb
.y_plane
[pipe
][i
]);
3505 skl_ddb_entry_write(dev_priv
, CUR_BUF_CFG(pipe
),
3506 &new->ddb
.plane
[pipe
][PLANE_CURSOR
]);
3511 * When setting up a new DDB allocation arrangement, we need to correctly
3512 * sequence the times at which the new allocations for the pipes are taken into
3513 * account or we'll have pipes fetching from space previously allocated to
3516 * Roughly the sequence looks like:
3517 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3518 * overlapping with a previous light-up pipe (another way to put it is:
3519 * pipes with their new allocation strickly included into their old ones).
3520 * 2. re-allocate the other pipes that get their allocation reduced
3521 * 3. allocate the pipes having their allocation increased
3523 * Steps 1. and 2. are here to take care of the following case:
3524 * - Initially DDB looks like this:
3527 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3531 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3535 skl_wm_flush_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int pass
)
3539 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe
), pass
);
3541 for_each_plane(dev_priv
, pipe
, plane
) {
3542 I915_WRITE(PLANE_SURF(pipe
, plane
),
3543 I915_READ(PLANE_SURF(pipe
, plane
)));
3545 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3549 skl_ddb_allocation_included(const struct skl_ddb_allocation
*old
,
3550 const struct skl_ddb_allocation
*new,
3553 uint16_t old_size
, new_size
;
3555 old_size
= skl_ddb_entry_size(&old
->pipe
[pipe
]);
3556 new_size
= skl_ddb_entry_size(&new->pipe
[pipe
]);
3558 return old_size
!= new_size
&&
3559 new->pipe
[pipe
].start
>= old
->pipe
[pipe
].start
&&
3560 new->pipe
[pipe
].end
<= old
->pipe
[pipe
].end
;
3563 static void skl_flush_wm_values(struct drm_i915_private
*dev_priv
,
3564 struct skl_wm_values
*new_values
)
3566 struct drm_device
*dev
= dev_priv
->dev
;
3567 struct skl_ddb_allocation
*cur_ddb
, *new_ddb
;
3568 bool reallocated
[I915_MAX_PIPES
] = {};
3569 struct intel_crtc
*crtc
;
3572 new_ddb
= &new_values
->ddb
;
3573 cur_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3576 * First pass: flush the pipes with the new allocation contained into
3579 * We'll wait for the vblank on those pipes to ensure we can safely
3580 * re-allocate the freed space without this pipe fetching from it.
3582 for_each_intel_crtc(dev
, crtc
) {
3588 if (!skl_ddb_allocation_included(cur_ddb
, new_ddb
, pipe
))
3591 skl_wm_flush_pipe(dev_priv
, pipe
, 1);
3592 intel_wait_for_vblank(dev
, pipe
);
3594 reallocated
[pipe
] = true;
3599 * Second pass: flush the pipes that are having their allocation
3600 * reduced, but overlapping with a previous allocation.
3602 * Here as well we need to wait for the vblank to make sure the freed
3603 * space is not used anymore.
3605 for_each_intel_crtc(dev
, crtc
) {
3611 if (reallocated
[pipe
])
3614 if (skl_ddb_entry_size(&new_ddb
->pipe
[pipe
]) <
3615 skl_ddb_entry_size(&cur_ddb
->pipe
[pipe
])) {
3616 skl_wm_flush_pipe(dev_priv
, pipe
, 2);
3617 intel_wait_for_vblank(dev
, pipe
);
3618 reallocated
[pipe
] = true;
3623 * Third pass: flush the pipes that got more space allocated.
3625 * We don't need to actively wait for the update here, next vblank
3626 * will just get more DDB space with the correct WM values.
3628 for_each_intel_crtc(dev
, crtc
) {
3635 * At this point, only the pipes more space than before are
3636 * left to re-allocate.
3638 if (reallocated
[pipe
])
3641 skl_wm_flush_pipe(dev_priv
, pipe
, 3);
3645 static bool skl_update_pipe_wm(struct drm_crtc
*crtc
,
3646 struct skl_ddb_allocation
*ddb
, /* out */
3647 struct skl_pipe_wm
*pipe_wm
/* out */)
3649 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3650 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3652 skl_allocate_pipe_ddb(cstate
, ddb
);
3653 skl_build_pipe_wm(cstate
, ddb
, pipe_wm
);
3655 if (!memcmp(&intel_crtc
->wm
.active
.skl
, pipe_wm
, sizeof(*pipe_wm
)))
3658 intel_crtc
->wm
.active
.skl
= *pipe_wm
;
3663 static void skl_update_other_pipe_wm(struct drm_device
*dev
,
3664 struct drm_crtc
*crtc
,
3665 struct skl_wm_values
*r
)
3667 struct intel_crtc
*intel_crtc
;
3668 struct intel_crtc
*this_crtc
= to_intel_crtc(crtc
);
3671 * If the WM update hasn't changed the allocation for this_crtc (the
3672 * crtc we are currently computing the new WM values for), other
3673 * enabled crtcs will keep the same allocation and we don't need to
3674 * recompute anything for them.
3676 if (!skl_ddb_allocation_changed(&r
->ddb
, this_crtc
))
3680 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3681 * other active pipes need new DDB allocation and WM values.
3683 for_each_intel_crtc(dev
, intel_crtc
) {
3684 struct skl_pipe_wm pipe_wm
= {};
3687 if (this_crtc
->pipe
== intel_crtc
->pipe
)
3690 if (!intel_crtc
->active
)
3693 wm_changed
= skl_update_pipe_wm(&intel_crtc
->base
,
3697 * If we end up re-computing the other pipe WM values, it's
3698 * because it was really needed, so we expect the WM values to
3701 WARN_ON(!wm_changed
);
3703 skl_compute_wm_results(dev
, &pipe_wm
, r
, intel_crtc
);
3704 r
->dirty
[intel_crtc
->pipe
] = true;
3708 static void skl_clear_wm(struct skl_wm_values
*watermarks
, enum pipe pipe
)
3710 watermarks
->wm_linetime
[pipe
] = 0;
3711 memset(watermarks
->plane
[pipe
], 0,
3712 sizeof(uint32_t) * 8 * I915_MAX_PLANES
);
3713 memset(watermarks
->plane_trans
[pipe
],
3714 0, sizeof(uint32_t) * I915_MAX_PLANES
);
3715 watermarks
->plane_trans
[pipe
][PLANE_CURSOR
] = 0;
3717 /* Clear ddb entries for pipe */
3718 memset(&watermarks
->ddb
.pipe
[pipe
], 0, sizeof(struct skl_ddb_entry
));
3719 memset(&watermarks
->ddb
.plane
[pipe
], 0,
3720 sizeof(struct skl_ddb_entry
) * I915_MAX_PLANES
);
3721 memset(&watermarks
->ddb
.y_plane
[pipe
], 0,
3722 sizeof(struct skl_ddb_entry
) * I915_MAX_PLANES
);
3723 memset(&watermarks
->ddb
.plane
[pipe
][PLANE_CURSOR
], 0,
3724 sizeof(struct skl_ddb_entry
));
3728 static void skl_update_wm(struct drm_crtc
*crtc
)
3730 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3731 struct drm_device
*dev
= crtc
->dev
;
3732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3733 struct skl_wm_values
*results
= &dev_priv
->wm
.skl_results
;
3734 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3735 struct skl_pipe_wm
*pipe_wm
= &cstate
->wm
.skl
.optimal
;
3738 /* Clear all dirty flags */
3739 memset(results
->dirty
, 0, sizeof(bool) * I915_MAX_PIPES
);
3741 skl_clear_wm(results
, intel_crtc
->pipe
);
3743 if (!skl_update_pipe_wm(crtc
, &results
->ddb
, pipe_wm
))
3746 skl_compute_wm_results(dev
, pipe_wm
, results
, intel_crtc
);
3747 results
->dirty
[intel_crtc
->pipe
] = true;
3749 skl_update_other_pipe_wm(dev
, crtc
, results
);
3750 skl_write_wm_values(dev_priv
, results
);
3751 skl_flush_wm_values(dev_priv
, results
);
3753 /* store the new configuration */
3754 dev_priv
->wm
.skl_hw
= *results
;
3757 static void ilk_compute_wm_config(struct drm_device
*dev
,
3758 struct intel_wm_config
*config
)
3760 struct intel_crtc
*crtc
;
3762 /* Compute the currently _active_ config */
3763 for_each_intel_crtc(dev
, crtc
) {
3764 const struct intel_pipe_wm
*wm
= &crtc
->wm
.active
.ilk
;
3766 if (!wm
->pipe_enabled
)
3769 config
->sprites_enabled
|= wm
->sprites_enabled
;
3770 config
->sprites_scaled
|= wm
->sprites_scaled
;
3771 config
->num_pipes_active
++;
3775 static void ilk_program_watermarks(struct drm_i915_private
*dev_priv
)
3777 struct drm_device
*dev
= dev_priv
->dev
;
3778 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
3779 struct ilk_wm_maximums max
;
3780 struct intel_wm_config config
= {};
3781 struct ilk_wm_values results
= {};
3782 enum intel_ddb_partitioning partitioning
;
3784 ilk_compute_wm_config(dev
, &config
);
3786 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
3787 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
3789 /* 5/6 split only in single pipe config on IVB+ */
3790 if (INTEL_INFO(dev
)->gen
>= 7 &&
3791 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
3792 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
3793 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
3795 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
3797 best_lp_wm
= &lp_wm_1_2
;
3800 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
3801 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
3803 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
3805 ilk_write_wm_values(dev_priv
, &results
);
3808 static void ilk_initial_watermarks(struct intel_crtc_state
*cstate
)
3810 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
3811 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3813 mutex_lock(&dev_priv
->wm
.wm_mutex
);
3814 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.intermediate
;
3815 ilk_program_watermarks(dev_priv
);
3816 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
3819 static void ilk_optimize_watermarks(struct intel_crtc_state
*cstate
)
3821 struct drm_i915_private
*dev_priv
= to_i915(cstate
->base
.crtc
->dev
);
3822 struct intel_crtc
*intel_crtc
= to_intel_crtc(cstate
->base
.crtc
);
3824 mutex_lock(&dev_priv
->wm
.wm_mutex
);
3825 if (cstate
->wm
.need_postvbl_update
) {
3826 intel_crtc
->wm
.active
.ilk
= cstate
->wm
.ilk
.optimal
;
3827 ilk_program_watermarks(dev_priv
);
3829 mutex_unlock(&dev_priv
->wm
.wm_mutex
);
3832 static void skl_pipe_wm_active_state(uint32_t val
,
3833 struct skl_pipe_wm
*active
,
3839 bool is_enabled
= (val
& PLANE_WM_EN
) != 0;
3843 active
->wm
[level
].plane_en
[i
] = is_enabled
;
3844 active
->wm
[level
].plane_res_b
[i
] =
3845 val
& PLANE_WM_BLOCKS_MASK
;
3846 active
->wm
[level
].plane_res_l
[i
] =
3847 (val
>> PLANE_WM_LINES_SHIFT
) &
3848 PLANE_WM_LINES_MASK
;
3850 active
->wm
[level
].plane_en
[PLANE_CURSOR
] = is_enabled
;
3851 active
->wm
[level
].plane_res_b
[PLANE_CURSOR
] =
3852 val
& PLANE_WM_BLOCKS_MASK
;
3853 active
->wm
[level
].plane_res_l
[PLANE_CURSOR
] =
3854 (val
>> PLANE_WM_LINES_SHIFT
) &
3855 PLANE_WM_LINES_MASK
;
3859 active
->trans_wm
.plane_en
[i
] = is_enabled
;
3860 active
->trans_wm
.plane_res_b
[i
] =
3861 val
& PLANE_WM_BLOCKS_MASK
;
3862 active
->trans_wm
.plane_res_l
[i
] =
3863 (val
>> PLANE_WM_LINES_SHIFT
) &
3864 PLANE_WM_LINES_MASK
;
3866 active
->trans_wm
.plane_en
[PLANE_CURSOR
] = is_enabled
;
3867 active
->trans_wm
.plane_res_b
[PLANE_CURSOR
] =
3868 val
& PLANE_WM_BLOCKS_MASK
;
3869 active
->trans_wm
.plane_res_l
[PLANE_CURSOR
] =
3870 (val
>> PLANE_WM_LINES_SHIFT
) &
3871 PLANE_WM_LINES_MASK
;
3876 static void skl_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3878 struct drm_device
*dev
= crtc
->dev
;
3879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3880 struct skl_wm_values
*hw
= &dev_priv
->wm
.skl_hw
;
3881 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3882 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3883 struct skl_pipe_wm
*active
= &cstate
->wm
.skl
.optimal
;
3884 enum pipe pipe
= intel_crtc
->pipe
;
3885 int level
, i
, max_level
;
3888 max_level
= ilk_wm_max_level(dev
);
3890 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3892 for (level
= 0; level
<= max_level
; level
++) {
3893 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3894 hw
->plane
[pipe
][i
][level
] =
3895 I915_READ(PLANE_WM(pipe
, i
, level
));
3896 hw
->plane
[pipe
][PLANE_CURSOR
][level
] = I915_READ(CUR_WM(pipe
, level
));
3899 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++)
3900 hw
->plane_trans
[pipe
][i
] = I915_READ(PLANE_WM_TRANS(pipe
, i
));
3901 hw
->plane_trans
[pipe
][PLANE_CURSOR
] = I915_READ(CUR_WM_TRANS(pipe
));
3903 if (!intel_crtc
->active
)
3906 hw
->dirty
[pipe
] = true;
3908 active
->linetime
= hw
->wm_linetime
[pipe
];
3910 for (level
= 0; level
<= max_level
; level
++) {
3911 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3912 temp
= hw
->plane
[pipe
][i
][level
];
3913 skl_pipe_wm_active_state(temp
, active
, false,
3916 temp
= hw
->plane
[pipe
][PLANE_CURSOR
][level
];
3917 skl_pipe_wm_active_state(temp
, active
, false, true, i
, level
);
3920 for (i
= 0; i
< intel_num_planes(intel_crtc
); i
++) {
3921 temp
= hw
->plane_trans
[pipe
][i
];
3922 skl_pipe_wm_active_state(temp
, active
, true, false, i
, 0);
3925 temp
= hw
->plane_trans
[pipe
][PLANE_CURSOR
];
3926 skl_pipe_wm_active_state(temp
, active
, true, true, i
, 0);
3928 intel_crtc
->wm
.active
.skl
= *active
;
3931 void skl_wm_get_hw_state(struct drm_device
*dev
)
3933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3934 struct skl_ddb_allocation
*ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3935 struct drm_crtc
*crtc
;
3936 struct intel_crtc
*intel_crtc
;
3938 skl_ddb_get_hw_state(dev_priv
, ddb
);
3939 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
3940 skl_pipe_wm_get_hw_state(crtc
);
3942 /* Calculate plane data rates */
3943 for_each_intel_crtc(dev
, intel_crtc
) {
3944 struct intel_crtc_state
*cstate
= intel_crtc
->config
;
3945 struct intel_plane
*intel_plane
;
3947 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3948 const struct drm_plane_state
*pstate
=
3949 intel_plane
->base
.state
;
3950 int id
= skl_wm_plane_id(intel_plane
);
3952 cstate
->wm
.skl
.plane_data_rate
[id
] =
3953 skl_plane_relative_data_rate(cstate
, pstate
, 0);
3954 cstate
->wm
.skl
.plane_y_data_rate
[id
] =
3955 skl_plane_relative_data_rate(cstate
, pstate
, 1);
3960 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
3962 struct drm_device
*dev
= crtc
->dev
;
3963 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3964 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
3965 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3966 struct intel_crtc_state
*cstate
= to_intel_crtc_state(crtc
->state
);
3967 struct intel_pipe_wm
*active
= &cstate
->wm
.ilk
.optimal
;
3968 enum pipe pipe
= intel_crtc
->pipe
;
3969 static const i915_reg_t wm0_pipe_reg
[] = {
3970 [PIPE_A
] = WM0_PIPEA_ILK
,
3971 [PIPE_B
] = WM0_PIPEB_ILK
,
3972 [PIPE_C
] = WM0_PIPEC_IVB
,
3975 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
3976 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3977 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
3979 active
->pipe_enabled
= intel_crtc
->active
;
3981 if (active
->pipe_enabled
) {
3982 u32 tmp
= hw
->wm_pipe
[pipe
];
3985 * For active pipes LP0 watermark is marked as
3986 * enabled, and LP1+ watermaks as disabled since
3987 * we can't really reverse compute them in case
3988 * multiple pipes are active.
3990 active
->wm
[0].enable
= true;
3991 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
3992 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
3993 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
3994 active
->linetime
= hw
->wm_linetime
[pipe
];
3996 int level
, max_level
= ilk_wm_max_level(dev
);
3999 * For inactive pipes, all watermark levels
4000 * should be marked as enabled but zeroed,
4001 * which is what we'd compute them to.
4003 for (level
= 0; level
<= max_level
; level
++)
4004 active
->wm
[level
].enable
= true;
4007 intel_crtc
->wm
.active
.ilk
= *active
;
4010 #define _FW_WM(value, plane) \
4011 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4012 #define _FW_WM_VLV(value, plane) \
4013 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4015 static void vlv_read_wm_values(struct drm_i915_private
*dev_priv
,
4016 struct vlv_wm_values
*wm
)
4021 for_each_pipe(dev_priv
, pipe
) {
4022 tmp
= I915_READ(VLV_DDL(pipe
));
4024 wm
->ddl
[pipe
].primary
=
4025 (tmp
>> DDL_PLANE_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4026 wm
->ddl
[pipe
].cursor
=
4027 (tmp
>> DDL_CURSOR_SHIFT
) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4028 wm
->ddl
[pipe
].sprite
[0] =
4029 (tmp
>> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4030 wm
->ddl
[pipe
].sprite
[1] =
4031 (tmp
>> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH
| DRAIN_LATENCY_MASK
);
4034 tmp
= I915_READ(DSPFW1
);
4035 wm
->sr
.plane
= _FW_WM(tmp
, SR
);
4036 wm
->pipe
[PIPE_B
].cursor
= _FW_WM(tmp
, CURSORB
);
4037 wm
->pipe
[PIPE_B
].primary
= _FW_WM_VLV(tmp
, PLANEB
);
4038 wm
->pipe
[PIPE_A
].primary
= _FW_WM_VLV(tmp
, PLANEA
);
4040 tmp
= I915_READ(DSPFW2
);
4041 wm
->pipe
[PIPE_A
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEB
);
4042 wm
->pipe
[PIPE_A
].cursor
= _FW_WM(tmp
, CURSORA
);
4043 wm
->pipe
[PIPE_A
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEA
);
4045 tmp
= I915_READ(DSPFW3
);
4046 wm
->sr
.cursor
= _FW_WM(tmp
, CURSOR_SR
);
4048 if (IS_CHERRYVIEW(dev_priv
)) {
4049 tmp
= I915_READ(DSPFW7_CHV
);
4050 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
4051 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
4053 tmp
= I915_READ(DSPFW8_CHV
);
4054 wm
->pipe
[PIPE_C
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITEF
);
4055 wm
->pipe
[PIPE_C
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEE
);
4057 tmp
= I915_READ(DSPFW9_CHV
);
4058 wm
->pipe
[PIPE_C
].primary
= _FW_WM_VLV(tmp
, PLANEC
);
4059 wm
->pipe
[PIPE_C
].cursor
= _FW_WM(tmp
, CURSORC
);
4061 tmp
= I915_READ(DSPHOWM
);
4062 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4063 wm
->pipe
[PIPE_C
].sprite
[1] |= _FW_WM(tmp
, SPRITEF_HI
) << 8;
4064 wm
->pipe
[PIPE_C
].sprite
[0] |= _FW_WM(tmp
, SPRITEE_HI
) << 8;
4065 wm
->pipe
[PIPE_C
].primary
|= _FW_WM(tmp
, PLANEC_HI
) << 8;
4066 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4067 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4068 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
4069 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4070 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4071 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
4073 tmp
= I915_READ(DSPFW7
);
4074 wm
->pipe
[PIPE_B
].sprite
[1] = _FW_WM_VLV(tmp
, SPRITED
);
4075 wm
->pipe
[PIPE_B
].sprite
[0] = _FW_WM_VLV(tmp
, SPRITEC
);
4077 tmp
= I915_READ(DSPHOWM
);
4078 wm
->sr
.plane
|= _FW_WM(tmp
, SR_HI
) << 9;
4079 wm
->pipe
[PIPE_B
].sprite
[1] |= _FW_WM(tmp
, SPRITED_HI
) << 8;
4080 wm
->pipe
[PIPE_B
].sprite
[0] |= _FW_WM(tmp
, SPRITEC_HI
) << 8;
4081 wm
->pipe
[PIPE_B
].primary
|= _FW_WM(tmp
, PLANEB_HI
) << 8;
4082 wm
->pipe
[PIPE_A
].sprite
[1] |= _FW_WM(tmp
, SPRITEB_HI
) << 8;
4083 wm
->pipe
[PIPE_A
].sprite
[0] |= _FW_WM(tmp
, SPRITEA_HI
) << 8;
4084 wm
->pipe
[PIPE_A
].primary
|= _FW_WM(tmp
, PLANEA_HI
) << 8;
4091 void vlv_wm_get_hw_state(struct drm_device
*dev
)
4093 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4094 struct vlv_wm_values
*wm
= &dev_priv
->wm
.vlv
;
4095 struct intel_plane
*plane
;
4099 vlv_read_wm_values(dev_priv
, wm
);
4101 for_each_intel_plane(dev
, plane
) {
4102 switch (plane
->base
.type
) {
4104 case DRM_PLANE_TYPE_CURSOR
:
4105 plane
->wm
.fifo_size
= 63;
4107 case DRM_PLANE_TYPE_PRIMARY
:
4108 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, 0);
4110 case DRM_PLANE_TYPE_OVERLAY
:
4111 sprite
= plane
->plane
;
4112 plane
->wm
.fifo_size
= vlv_get_fifo_size(dev
, plane
->pipe
, sprite
+ 1);
4117 wm
->cxsr
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
4118 wm
->level
= VLV_WM_LEVEL_PM2
;
4120 if (IS_CHERRYVIEW(dev_priv
)) {
4121 mutex_lock(&dev_priv
->rps
.hw_lock
);
4123 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4124 if (val
& DSP_MAXFIFO_PM5_ENABLE
)
4125 wm
->level
= VLV_WM_LEVEL_PM5
;
4128 * If DDR DVFS is disabled in the BIOS, Punit
4129 * will never ack the request. So if that happens
4130 * assume we don't have to enable/disable DDR DVFS
4131 * dynamically. To test that just set the REQ_ACK
4132 * bit to poke the Punit, but don't change the
4133 * HIGH/LOW bits so that we don't actually change
4134 * the current state.
4136 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4137 val
|= FORCE_DDR_FREQ_REQ_ACK
;
4138 vlv_punit_write(dev_priv
, PUNIT_REG_DDR_SETUP2
, val
);
4140 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
) &
4141 FORCE_DDR_FREQ_REQ_ACK
) == 0, 3)) {
4142 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4143 "assuming DDR DVFS is disabled\n");
4144 dev_priv
->wm
.max_level
= VLV_WM_LEVEL_PM5
;
4146 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DDR_SETUP2
);
4147 if ((val
& FORCE_DDR_HIGH_FREQ
) == 0)
4148 wm
->level
= VLV_WM_LEVEL_DDR_DVFS
;
4151 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4154 for_each_pipe(dev_priv
, pipe
)
4155 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4156 pipe_name(pipe
), wm
->pipe
[pipe
].primary
, wm
->pipe
[pipe
].cursor
,
4157 wm
->pipe
[pipe
].sprite
[0], wm
->pipe
[pipe
].sprite
[1]);
4159 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4160 wm
->sr
.plane
, wm
->sr
.cursor
, wm
->level
, wm
->cxsr
);
4163 void ilk_wm_get_hw_state(struct drm_device
*dev
)
4165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4166 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
4167 struct drm_crtc
*crtc
;
4169 for_each_crtc(dev
, crtc
)
4170 ilk_pipe_wm_get_hw_state(crtc
);
4172 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
4173 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
4174 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
4176 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
4177 if (INTEL_INFO(dev
)->gen
>= 7) {
4178 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
4179 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
4182 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
4183 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
4184 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4185 else if (IS_IVYBRIDGE(dev
))
4186 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
4187 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
4190 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
4194 * intel_update_watermarks - update FIFO watermark values based on current modes
4196 * Calculate watermark values for the various WM regs based on current mode
4197 * and plane configuration.
4199 * There are several cases to deal with here:
4200 * - normal (i.e. non-self-refresh)
4201 * - self-refresh (SR) mode
4202 * - lines are large relative to FIFO size (buffer can hold up to 2)
4203 * - lines are small relative to FIFO size (buffer can hold more than 2
4204 * lines), so need to account for TLB latency
4206 * The normal calculation is:
4207 * watermark = dotclock * bytes per pixel * latency
4208 * where latency is platform & configuration dependent (we assume pessimal
4211 * The SR calculation is:
4212 * watermark = (trunc(latency/line time)+1) * surface width *
4215 * line time = htotal / dotclock
4216 * surface width = hdisplay for normal plane and 64 for cursor
4217 * and latency is assumed to be high, as above.
4219 * The final value programmed to the register should always be rounded up,
4220 * and include an extra 2 entries to account for clock crossings.
4222 * We don't use the sprite, so we can ignore that. And on Crestline we have
4223 * to set the non-SR watermarks to 8.
4225 void intel_update_watermarks(struct drm_crtc
*crtc
)
4227 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4229 if (dev_priv
->display
.update_wm
)
4230 dev_priv
->display
.update_wm(crtc
);
4234 * Lock protecting IPS related data structures
4236 DEFINE_SPINLOCK(mchdev_lock
);
4238 /* Global for IPS driver to get at the current i915 device. Protected by
4240 static struct drm_i915_private
*i915_mch_dev
;
4242 bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
)
4246 assert_spin_locked(&mchdev_lock
);
4248 rgvswctl
= I915_READ16(MEMSWCTL
);
4249 if (rgvswctl
& MEMCTL_CMD_STS
) {
4250 DRM_DEBUG("gpu busy, RCS change rejected\n");
4251 return false; /* still busy with another command */
4254 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
4255 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
4256 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4257 POSTING_READ16(MEMSWCTL
);
4259 rgvswctl
|= MEMCTL_CMD_STS
;
4260 I915_WRITE16(MEMSWCTL
, rgvswctl
);
4265 static void ironlake_enable_drps(struct drm_i915_private
*dev_priv
)
4268 u8 fmax
, fmin
, fstart
, vstart
;
4270 spin_lock_irq(&mchdev_lock
);
4272 rgvmodectl
= I915_READ(MEMMODECTL
);
4274 /* Enable temp reporting */
4275 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
4276 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
4278 /* 100ms RC evaluation intervals */
4279 I915_WRITE(RCUPEI
, 100000);
4280 I915_WRITE(RCDNEI
, 100000);
4282 /* Set max/min thresholds to 90ms and 80ms respectively */
4283 I915_WRITE(RCBMAXAVG
, 90000);
4284 I915_WRITE(RCBMINAVG
, 80000);
4286 I915_WRITE(MEMIHYST
, 1);
4288 /* Set up min, max, and cur for interrupt handling */
4289 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
4290 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
4291 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
4292 MEMMODE_FSTART_SHIFT
;
4294 vstart
= (I915_READ(PXVFREQ(fstart
)) & PXVFREQ_PX_MASK
) >>
4297 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
4298 dev_priv
->ips
.fstart
= fstart
;
4300 dev_priv
->ips
.max_delay
= fstart
;
4301 dev_priv
->ips
.min_delay
= fmin
;
4302 dev_priv
->ips
.cur_delay
= fstart
;
4304 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4305 fmax
, fmin
, fstart
);
4307 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
4310 * Interrupts will be enabled in ironlake_irq_postinstall
4313 I915_WRITE(VIDSTART
, vstart
);
4314 POSTING_READ(VIDSTART
);
4316 rgvmodectl
|= MEMMODE_SWMODE_EN
;
4317 I915_WRITE(MEMMODECTL
, rgvmodectl
);
4319 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
4320 DRM_ERROR("stuck trying to change perf mode\n");
4323 ironlake_set_drps(dev_priv
, fstart
);
4325 dev_priv
->ips
.last_count1
= I915_READ(DMIEC
) +
4326 I915_READ(DDREC
) + I915_READ(CSIEC
);
4327 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
4328 dev_priv
->ips
.last_count2
= I915_READ(GFXEC
);
4329 dev_priv
->ips
.last_time2
= ktime_get_raw_ns();
4331 spin_unlock_irq(&mchdev_lock
);
4334 static void ironlake_disable_drps(struct drm_i915_private
*dev_priv
)
4338 spin_lock_irq(&mchdev_lock
);
4340 rgvswctl
= I915_READ16(MEMSWCTL
);
4342 /* Ack interrupts, disable EFC interrupt */
4343 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
4344 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
4345 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
4346 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
4347 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
4349 /* Go back to the starting frequency */
4350 ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
);
4352 rgvswctl
|= MEMCTL_CMD_STS
;
4353 I915_WRITE(MEMSWCTL
, rgvswctl
);
4356 spin_unlock_irq(&mchdev_lock
);
4359 /* There's a funny hw issue where the hw returns all 0 when reading from
4360 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4361 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4362 * all limits and the gpu stuck at whatever frequency it is at atm).
4364 static u32
intel_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
4368 /* Only set the down limit when we've reached the lowest level to avoid
4369 * getting more interrupts, otherwise leave this clear. This prevents a
4370 * race in the hw when coming out of rc6: There's a tiny window where
4371 * the hw runs at the minimal clock before selecting the desired
4372 * frequency, if the down threshold expires in that window we will not
4373 * receive a down interrupt. */
4374 if (IS_GEN9(dev_priv
)) {
4375 limits
= (dev_priv
->rps
.max_freq_softlimit
) << 23;
4376 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4377 limits
|= (dev_priv
->rps
.min_freq_softlimit
) << 14;
4379 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
4380 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4381 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
4387 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
4390 u32 threshold_up
= 0, threshold_down
= 0; /* in % */
4391 u32 ei_up
= 0, ei_down
= 0;
4393 new_power
= dev_priv
->rps
.power
;
4394 switch (dev_priv
->rps
.power
) {
4396 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
4397 new_power
= BETWEEN
;
4401 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
4402 new_power
= LOW_POWER
;
4403 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
4404 new_power
= HIGH_POWER
;
4408 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
4409 new_power
= BETWEEN
;
4412 /* Max/min bins are special */
4413 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
4414 new_power
= LOW_POWER
;
4415 if (val
>= dev_priv
->rps
.max_freq_softlimit
)
4416 new_power
= HIGH_POWER
;
4417 if (new_power
== dev_priv
->rps
.power
)
4420 /* Note the units here are not exactly 1us, but 1280ns. */
4421 switch (new_power
) {
4423 /* Upclock if more than 95% busy over 16ms */
4427 /* Downclock if less than 85% busy over 32ms */
4429 threshold_down
= 85;
4433 /* Upclock if more than 90% busy over 13ms */
4437 /* Downclock if less than 75% busy over 32ms */
4439 threshold_down
= 75;
4443 /* Upclock if more than 85% busy over 10ms */
4447 /* Downclock if less than 60% busy over 32ms */
4449 threshold_down
= 60;
4453 I915_WRITE(GEN6_RP_UP_EI
,
4454 GT_INTERVAL_FROM_US(dev_priv
, ei_up
));
4455 I915_WRITE(GEN6_RP_UP_THRESHOLD
,
4456 GT_INTERVAL_FROM_US(dev_priv
, (ei_up
* threshold_up
/ 100)));
4458 I915_WRITE(GEN6_RP_DOWN_EI
,
4459 GT_INTERVAL_FROM_US(dev_priv
, ei_down
));
4460 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
,
4461 GT_INTERVAL_FROM_US(dev_priv
, (ei_down
* threshold_down
/ 100)));
4463 I915_WRITE(GEN6_RP_CONTROL
,
4464 GEN6_RP_MEDIA_TURBO
|
4465 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4466 GEN6_RP_MEDIA_IS_GFX
|
4468 GEN6_RP_UP_BUSY_AVG
|
4469 GEN6_RP_DOWN_IDLE_AVG
);
4471 dev_priv
->rps
.power
= new_power
;
4472 dev_priv
->rps
.up_threshold
= threshold_up
;
4473 dev_priv
->rps
.down_threshold
= threshold_down
;
4474 dev_priv
->rps
.last_adj
= 0;
4477 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
4481 if (val
> dev_priv
->rps
.min_freq_softlimit
)
4482 mask
|= GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
4483 if (val
< dev_priv
->rps
.max_freq_softlimit
)
4484 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
| GEN6_PM_RP_UP_THRESHOLD
;
4486 mask
&= dev_priv
->pm_rps_events
;
4488 return gen6_sanitize_rps_pm_mask(dev_priv
, ~mask
);
4491 /* gen6_set_rps is called to update the frequency request, but should also be
4492 * called when the range (min_delay and max_delay) is modified so that we can
4493 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4494 static void gen6_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4496 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4497 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
4500 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4501 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4502 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4504 /* min/max delay may still have been modified so be sure to
4505 * write the limits value.
4507 if (val
!= dev_priv
->rps
.cur_freq
) {
4508 gen6_set_rps_thresholds(dev_priv
, val
);
4510 if (IS_GEN9(dev_priv
))
4511 I915_WRITE(GEN6_RPNSWREQ
,
4512 GEN9_FREQUENCY(val
));
4513 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4514 I915_WRITE(GEN6_RPNSWREQ
,
4515 HSW_FREQUENCY(val
));
4517 I915_WRITE(GEN6_RPNSWREQ
,
4518 GEN6_FREQUENCY(val
) |
4520 GEN6_AGGRESSIVE_TURBO
);
4523 /* Make sure we continue to get interrupts
4524 * until we hit the minimum or maximum frequencies.
4526 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, intel_rps_limits(dev_priv
, val
));
4527 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4529 POSTING_READ(GEN6_RPNSWREQ
);
4531 dev_priv
->rps
.cur_freq
= val
;
4532 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4535 static void valleyview_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4537 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4538 WARN_ON(val
> dev_priv
->rps
.max_freq
);
4539 WARN_ON(val
< dev_priv
->rps
.min_freq
);
4541 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv
) && (val
& 1),
4542 "Odd GPU freq value\n"))
4545 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
4547 if (val
!= dev_priv
->rps
.cur_freq
) {
4548 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
4549 if (!IS_CHERRYVIEW(dev_priv
))
4550 gen6_set_rps_thresholds(dev_priv
, val
);
4553 dev_priv
->rps
.cur_freq
= val
;
4554 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv
, val
));
4557 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4559 * * If Gfx is Idle, then
4560 * 1. Forcewake Media well.
4561 * 2. Request idle freq.
4562 * 3. Release Forcewake of Media well.
4564 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
4566 u32 val
= dev_priv
->rps
.idle_freq
;
4568 if (dev_priv
->rps
.cur_freq
<= val
)
4571 /* Wake up the media well, as that takes a lot less
4572 * power than the Render well. */
4573 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_MEDIA
);
4574 valleyview_set_rps(dev_priv
, val
);
4575 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_MEDIA
);
4578 void gen6_rps_busy(struct drm_i915_private
*dev_priv
)
4580 mutex_lock(&dev_priv
->rps
.hw_lock
);
4581 if (dev_priv
->rps
.enabled
) {
4582 if (dev_priv
->pm_rps_events
& (GEN6_PM_RP_DOWN_EI_EXPIRED
| GEN6_PM_RP_UP_EI_EXPIRED
))
4583 gen6_rps_reset_ei(dev_priv
);
4584 I915_WRITE(GEN6_PMINTRMSK
,
4585 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
4587 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4590 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
4592 mutex_lock(&dev_priv
->rps
.hw_lock
);
4593 if (dev_priv
->rps
.enabled
) {
4594 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4595 vlv_set_rps_idle(dev_priv
);
4597 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
4598 dev_priv
->rps
.last_adj
= 0;
4599 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
4601 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4603 spin_lock(&dev_priv
->rps
.client_lock
);
4604 while (!list_empty(&dev_priv
->rps
.clients
))
4605 list_del_init(dev_priv
->rps
.clients
.next
);
4606 spin_unlock(&dev_priv
->rps
.client_lock
);
4609 void gen6_rps_boost(struct drm_i915_private
*dev_priv
,
4610 struct intel_rps_client
*rps
,
4611 unsigned long submitted
)
4613 /* This is intentionally racy! We peek at the state here, then
4614 * validate inside the RPS worker.
4616 if (!(dev_priv
->mm
.busy
&&
4617 dev_priv
->rps
.enabled
&&
4618 dev_priv
->rps
.cur_freq
< dev_priv
->rps
.max_freq_softlimit
))
4621 /* Force a RPS boost (and don't count it against the client) if
4622 * the GPU is severely congested.
4624 if (rps
&& time_after(jiffies
, submitted
+ DRM_I915_THROTTLE_JIFFIES
))
4627 spin_lock(&dev_priv
->rps
.client_lock
);
4628 if (rps
== NULL
|| list_empty(&rps
->link
)) {
4629 spin_lock_irq(&dev_priv
->irq_lock
);
4630 if (dev_priv
->rps
.interrupts_enabled
) {
4631 dev_priv
->rps
.client_boost
= true;
4632 queue_work(dev_priv
->wq
, &dev_priv
->rps
.work
);
4634 spin_unlock_irq(&dev_priv
->irq_lock
);
4637 list_add(&rps
->link
, &dev_priv
->rps
.clients
);
4640 dev_priv
->rps
.boosts
++;
4642 spin_unlock(&dev_priv
->rps
.client_lock
);
4645 void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
)
4647 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
4648 valleyview_set_rps(dev_priv
, val
);
4650 gen6_set_rps(dev_priv
, val
);
4653 static void gen9_disable_rc6(struct drm_i915_private
*dev_priv
)
4655 I915_WRITE(GEN6_RC_CONTROL
, 0);
4656 I915_WRITE(GEN9_PG_ENABLE
, 0);
4659 static void gen9_disable_rps(struct drm_i915_private
*dev_priv
)
4661 I915_WRITE(GEN6_RP_CONTROL
, 0);
4664 static void gen6_disable_rps(struct drm_i915_private
*dev_priv
)
4666 I915_WRITE(GEN6_RC_CONTROL
, 0);
4667 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
4668 I915_WRITE(GEN6_RP_CONTROL
, 0);
4671 static void cherryview_disable_rps(struct drm_i915_private
*dev_priv
)
4673 I915_WRITE(GEN6_RC_CONTROL
, 0);
4676 static void valleyview_disable_rps(struct drm_i915_private
*dev_priv
)
4678 /* we're doing forcewake before Disabling RC6,
4679 * This what the BIOS expects when going into suspend */
4680 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4682 I915_WRITE(GEN6_RC_CONTROL
, 0);
4684 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4687 static void intel_print_rc6_info(struct drm_i915_private
*dev_priv
, u32 mode
)
4689 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
4690 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
4691 mode
= GEN6_RC_CTL_RC6_ENABLE
;
4695 if (HAS_RC6p(dev_priv
))
4696 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4697 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
),
4698 onoff(mode
& GEN6_RC_CTL_RC6p_ENABLE
),
4699 onoff(mode
& GEN6_RC_CTL_RC6pp_ENABLE
));
4702 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4703 onoff(mode
& GEN6_RC_CTL_RC6_ENABLE
));
4706 static bool bxt_check_bios_rc6_setup(struct drm_i915_private
*dev_priv
)
4708 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4709 bool enable_rc6
= true;
4710 unsigned long rc6_ctx_base
;
4712 if (!(I915_READ(RC6_LOCATION
) & RC6_CTX_IN_DRAM
)) {
4713 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4718 * The exact context size is not known for BXT, so assume a page size
4721 rc6_ctx_base
= I915_READ(RC6_CTX_BASE
) & RC6_CTX_BASE_MASK
;
4722 if (!((rc6_ctx_base
>= ggtt
->stolen_reserved_base
) &&
4723 (rc6_ctx_base
+ PAGE_SIZE
<= ggtt
->stolen_reserved_base
+
4724 ggtt
->stolen_reserved_size
))) {
4725 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4729 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
4730 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0
) & IDLE_TIME_MASK
) > 1) &&
4731 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT
) & IDLE_TIME_MASK
) > 1) &&
4732 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT
) & IDLE_TIME_MASK
) > 1))) {
4733 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4737 if (!(I915_READ(GEN6_RC_CONTROL
) & (GEN6_RC_CTL_RC6_ENABLE
|
4738 GEN6_RC_CTL_HW_ENABLE
)) &&
4739 ((I915_READ(GEN6_RC_CONTROL
) & GEN6_RC_CTL_HW_ENABLE
) ||
4740 !(I915_READ(GEN6_RC_STATE
) & RC6_STATE
))) {
4741 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4748 int sanitize_rc6_option(struct drm_i915_private
*dev_priv
, int enable_rc6
)
4750 /* No RC6 before Ironlake and code is gone for ilk. */
4751 if (INTEL_INFO(dev_priv
)->gen
< 6)
4757 if (IS_BROXTON(dev_priv
) && !bxt_check_bios_rc6_setup(dev_priv
)) {
4758 DRM_INFO("RC6 disabled by BIOS\n");
4762 /* Respect the kernel parameter if it is set */
4763 if (enable_rc6
>= 0) {
4766 if (HAS_RC6p(dev_priv
))
4767 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
4770 mask
= INTEL_RC6_ENABLE
;
4772 if ((enable_rc6
& mask
) != enable_rc6
)
4773 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4774 enable_rc6
& mask
, enable_rc6
, mask
);
4776 return enable_rc6
& mask
;
4779 if (IS_IVYBRIDGE(dev_priv
))
4780 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
4782 return INTEL_RC6_ENABLE
;
4785 static void gen6_init_rps_frequencies(struct drm_i915_private
*dev_priv
)
4787 uint32_t rp_state_cap
;
4788 u32 ddcc_status
= 0;
4791 /* All of these values are in units of 50MHz */
4792 dev_priv
->rps
.cur_freq
= 0;
4793 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4794 if (IS_BROXTON(dev_priv
)) {
4795 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
4796 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 16) & 0xff;
4797 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
4798 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 0) & 0xff;
4800 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4801 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
4802 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
4803 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
4806 /* hw_max = RP0 until we check for overclocking */
4807 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
4809 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
4810 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
) ||
4811 IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
4812 ret
= sandybridge_pcode_read(dev_priv
,
4813 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL
,
4816 dev_priv
->rps
.efficient_freq
=
4818 ((ddcc_status
>> 8) & 0xff),
4819 dev_priv
->rps
.min_freq
,
4820 dev_priv
->rps
.max_freq
);
4823 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
4824 /* Store the frequency values in 16.66 MHZ units, which is
4825 the natural hardware unit for SKL */
4826 dev_priv
->rps
.rp0_freq
*= GEN9_FREQ_SCALER
;
4827 dev_priv
->rps
.rp1_freq
*= GEN9_FREQ_SCALER
;
4828 dev_priv
->rps
.min_freq
*= GEN9_FREQ_SCALER
;
4829 dev_priv
->rps
.max_freq
*= GEN9_FREQ_SCALER
;
4830 dev_priv
->rps
.efficient_freq
*= GEN9_FREQ_SCALER
;
4833 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
4835 /* Preserve min/max settings in case of re-init */
4836 if (dev_priv
->rps
.max_freq_softlimit
== 0)
4837 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
4839 if (dev_priv
->rps
.min_freq_softlimit
== 0) {
4840 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
4841 dev_priv
->rps
.min_freq_softlimit
=
4842 max_t(int, dev_priv
->rps
.efficient_freq
,
4843 intel_freq_opcode(dev_priv
, 450));
4845 dev_priv
->rps
.min_freq_softlimit
=
4846 dev_priv
->rps
.min_freq
;
4850 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4851 static void gen9_enable_rps(struct drm_i915_private
*dev_priv
)
4853 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4855 gen6_init_rps_frequencies(dev_priv
);
4857 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4858 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
4860 * BIOS could leave the Hw Turbo enabled, so need to explicitly
4861 * clear out the Control register just to avoid inconsitency
4862 * with debugfs interface, which will show Turbo as enabled
4863 * only and that is not expected by the User after adding the
4864 * WaGsvDisableTurbo. Apart from this there is no problem even
4865 * if the Turbo is left enabled in the Control register, as the
4866 * Up/Down interrupts would remain masked.
4868 gen9_disable_rps(dev_priv
);
4869 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4873 /* Program defaults and thresholds for RPS*/
4874 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
4875 GEN9_FREQUENCY(dev_priv
->rps
.rp1_freq
));
4877 /* 1 second timeout*/
4878 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,
4879 GT_INTERVAL_FROM_US(dev_priv
, 1000000));
4881 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 0xa);
4883 /* Leaning on the below call to gen6_set_rps to program/setup the
4884 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4885 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4886 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
4887 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
4889 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4892 static void gen9_enable_rc6(struct drm_i915_private
*dev_priv
)
4894 struct intel_engine_cs
*engine
;
4895 uint32_t rc6_mask
= 0;
4897 /* 1a: Software RC state - RC0 */
4898 I915_WRITE(GEN6_RC_STATE
, 0);
4900 /* 1b: Get forcewake during program sequence. Although the driver
4901 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4902 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4904 /* 2a: Disable RC states. */
4905 I915_WRITE(GEN6_RC_CONTROL
, 0);
4907 /* 2b: Program RC6 thresholds.*/
4909 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4910 if (IS_SKYLAKE(dev_priv
))
4911 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 108 << 16);
4913 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 54 << 16);
4914 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4915 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4916 for_each_engine(engine
, dev_priv
)
4917 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
4919 if (HAS_GUC_UCODE(dev_priv
))
4920 I915_WRITE(GUC_MAX_IDLE_COUNT
, 0xA);
4922 I915_WRITE(GEN6_RC_SLEEP
, 0);
4924 /* 2c: Program Coarse Power Gating Policies. */
4925 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS
, 25);
4926 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS
, 25);
4928 /* 3a: Enable RC6 */
4929 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
4930 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4931 DRM_INFO("RC6 %s\n", onoff(rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
));
4932 /* WaRsUseTimeoutMode */
4933 if (IS_SKL_REVID(dev_priv
, 0, SKL_REVID_D0
) ||
4934 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
4935 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us */
4936 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4937 GEN7_RC_CTL_TO_MODE
|
4940 I915_WRITE(GEN6_RC6_THRESHOLD
, 37500); /* 37.5/125ms per EI */
4941 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4942 GEN6_RC_CTL_EI_MODE(1) |
4947 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4948 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4950 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv
))
4951 I915_WRITE(GEN9_PG_ENABLE
, 0);
4953 I915_WRITE(GEN9_PG_ENABLE
, (rc6_mask
& GEN6_RC_CTL_RC6_ENABLE
) ?
4954 (GEN9_RENDER_PG_ENABLE
| GEN9_MEDIA_PG_ENABLE
) : 0);
4956 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4959 static void gen8_enable_rps(struct drm_i915_private
*dev_priv
)
4961 struct intel_engine_cs
*engine
;
4962 uint32_t rc6_mask
= 0;
4964 /* 1a: Software RC state - RC0 */
4965 I915_WRITE(GEN6_RC_STATE
, 0);
4967 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4968 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4969 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4971 /* 2a: Disable RC states. */
4972 I915_WRITE(GEN6_RC_CONTROL
, 0);
4974 /* Initialize rps frequencies */
4975 gen6_init_rps_frequencies(dev_priv
);
4977 /* 2b: Program RC6 thresholds.*/
4978 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
4979 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
4980 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
4981 for_each_engine(engine
, dev_priv
)
4982 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
4983 I915_WRITE(GEN6_RC_SLEEP
, 0);
4984 if (IS_BROADWELL(dev_priv
))
4985 I915_WRITE(GEN6_RC6_THRESHOLD
, 625); /* 800us/1.28 for TO */
4987 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
4990 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
4991 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
4992 intel_print_rc6_info(dev_priv
, rc6_mask
);
4993 if (IS_BROADWELL(dev_priv
))
4994 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4995 GEN7_RC_CTL_TO_MODE
|
4998 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
4999 GEN6_RC_CTL_EI_MODE(1) |
5002 /* 4 Program defaults and thresholds for RPS*/
5003 I915_WRITE(GEN6_RPNSWREQ
,
5004 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5005 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
5006 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
5007 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5008 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
5010 /* Docs recommend 900MHz, and 300 MHz respectively */
5011 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
5012 dev_priv
->rps
.max_freq_softlimit
<< 24 |
5013 dev_priv
->rps
.min_freq_softlimit
<< 16);
5015 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
5016 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5017 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
5018 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
5020 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5023 I915_WRITE(GEN6_RP_CONTROL
,
5024 GEN6_RP_MEDIA_TURBO
|
5025 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5026 GEN6_RP_MEDIA_IS_GFX
|
5028 GEN6_RP_UP_BUSY_AVG
|
5029 GEN6_RP_DOWN_IDLE_AVG
);
5031 /* 6: Ring frequency + overclocking (our driver does this later */
5033 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
5034 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5036 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5039 static void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
5041 struct intel_engine_cs
*engine
;
5042 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
5047 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5049 /* Here begins a magic sequence of register writes to enable
5050 * auto-downclocking.
5052 * Perhaps there might be some value in exposing these to
5055 I915_WRITE(GEN6_RC_STATE
, 0);
5057 /* Clear the DBG now so we don't confuse earlier errors */
5058 gtfifodbg
= I915_READ(GTFIFODBG
);
5060 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
5061 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5064 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5066 /* Initialize rps frequencies */
5067 gen6_init_rps_frequencies(dev_priv
);
5069 /* disable the counters and set deterministic thresholds */
5070 I915_WRITE(GEN6_RC_CONTROL
, 0);
5072 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
5073 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
5074 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
5075 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5076 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5078 for_each_engine(engine
, dev_priv
)
5079 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5081 I915_WRITE(GEN6_RC_SLEEP
, 0);
5082 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
5083 if (IS_IVYBRIDGE(dev_priv
))
5084 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
5086 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
5087 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
5088 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
5090 /* Check if we are enabling RC6 */
5091 rc6_mode
= intel_enable_rc6();
5092 if (rc6_mode
& INTEL_RC6_ENABLE
)
5093 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
5095 /* We don't use those on Haswell */
5096 if (!IS_HASWELL(dev_priv
)) {
5097 if (rc6_mode
& INTEL_RC6p_ENABLE
)
5098 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
5100 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
5101 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
5104 intel_print_rc6_info(dev_priv
, rc6_mask
);
5106 I915_WRITE(GEN6_RC_CONTROL
,
5108 GEN6_RC_CTL_EI_MODE(1) |
5109 GEN6_RC_CTL_HW_ENABLE
);
5111 /* Power down if completely idle for over 50ms */
5112 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
5113 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5115 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
5117 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5119 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
5120 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
5121 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5122 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
5123 (pcu_mbox
& 0xff) * 50);
5124 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
5127 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
5128 gen6_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5131 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
5132 if (IS_GEN6(dev_priv
) && ret
) {
5133 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5134 } else if (IS_GEN6(dev_priv
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
5135 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5136 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
5137 rc6vids
&= 0xffff00;
5138 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
5139 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
5141 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5144 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5147 static void __gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
5150 unsigned int gpu_freq
;
5151 unsigned int max_ia_freq
, min_ring_freq
;
5152 unsigned int max_gpu_freq
, min_gpu_freq
;
5153 int scaling_factor
= 180;
5154 struct cpufreq_policy
*policy
;
5156 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5158 policy
= cpufreq_cpu_get(0);
5160 max_ia_freq
= policy
->cpuinfo
.max_freq
;
5161 cpufreq_cpu_put(policy
);
5164 * Default to measured freq if none found, PCU will ensure we
5167 max_ia_freq
= tsc_khz
;
5170 /* Convert from kHz to MHz */
5171 max_ia_freq
/= 1000;
5173 min_ring_freq
= I915_READ(DCLK
) & 0xf;
5174 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5175 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
5177 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5178 /* Convert GT frequency to 50 HZ units */
5179 min_gpu_freq
= dev_priv
->rps
.min_freq
/ GEN9_FREQ_SCALER
;
5180 max_gpu_freq
= dev_priv
->rps
.max_freq
/ GEN9_FREQ_SCALER
;
5182 min_gpu_freq
= dev_priv
->rps
.min_freq
;
5183 max_gpu_freq
= dev_priv
->rps
.max_freq
;
5187 * For each potential GPU frequency, load a ring frequency we'd like
5188 * to use for memory access. We do this by specifying the IA frequency
5189 * the PCU should use as a reference to determine the ring frequency.
5191 for (gpu_freq
= max_gpu_freq
; gpu_freq
>= min_gpu_freq
; gpu_freq
--) {
5192 int diff
= max_gpu_freq
- gpu_freq
;
5193 unsigned int ia_freq
= 0, ring_freq
= 0;
5195 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
)) {
5197 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5198 * No floor required for ring frequency on SKL.
5200 ring_freq
= gpu_freq
;
5201 } else if (INTEL_INFO(dev_priv
)->gen
>= 8) {
5202 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5203 ring_freq
= max(min_ring_freq
, gpu_freq
);
5204 } else if (IS_HASWELL(dev_priv
)) {
5205 ring_freq
= mult_frac(gpu_freq
, 5, 4);
5206 ring_freq
= max(min_ring_freq
, ring_freq
);
5207 /* leave ia_freq as the default, chosen by cpufreq */
5209 /* On older processors, there is no separate ring
5210 * clock domain, so in order to boost the bandwidth
5211 * of the ring, we need to upclock the CPU (ia_freq).
5213 * For GPU frequencies less than 750MHz,
5214 * just use the lowest ring freq.
5216 if (gpu_freq
< min_freq
)
5219 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
5220 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
5223 sandybridge_pcode_write(dev_priv
,
5224 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
5225 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
5226 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
5231 void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
5233 if (!HAS_CORE_RING_FREQ(dev_priv
))
5236 mutex_lock(&dev_priv
->rps
.hw_lock
);
5237 __gen6_update_ring_freq(dev_priv
);
5238 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5241 static int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5245 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5247 switch (INTEL_INFO(dev_priv
)->eu_total
) {
5249 /* (2 * 4) config */
5250 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT
);
5253 /* (2 * 6) config */
5254 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT
);
5257 /* (2 * 8) config */
5259 /* Setting (2 * 8) Min RP0 for any other combination */
5260 rp0
= (val
>> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT
);
5264 rp0
= (rp0
& FB_GFX_FREQ_FUSE_MASK
);
5269 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5273 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
5274 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
5279 static int cherryview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5283 val
= vlv_punit_read(dev_priv
, FB_GFX_FMAX_AT_VMAX_FUSE
);
5284 rp1
= (val
& FB_GFX_FREQ_FUSE_MASK
);
5289 static int valleyview_rps_guar_freq(struct drm_i915_private
*dev_priv
)
5293 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5295 rp1
= (val
& FB_GFX_FGUARANTEED_FREQ_FUSE_MASK
) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT
;
5300 static int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
5304 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
5306 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
5308 rp0
= min_t(u32
, rp0
, 0xea);
5313 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
5317 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
5318 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
5319 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
5320 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
5325 static int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
5329 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
5331 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5332 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5333 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5334 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5335 * to make sure it matches what Punit accepts.
5337 return max_t(u32
, val
, 0xc0);
5340 /* Check that the pctx buffer wasn't move under us. */
5341 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
5343 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5345 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
5346 dev_priv
->vlv_pctx
->stolen
->start
);
5350 /* Check that the pcbr address is not empty. */
5351 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
5353 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
5355 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
5358 static void cherryview_setup_pctx(struct drm_i915_private
*dev_priv
)
5360 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5361 unsigned long pctx_paddr
, paddr
;
5363 int pctx_size
= 32*1024;
5365 pcbr
= I915_READ(VLV_PCBR
);
5366 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
5367 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5368 paddr
= (dev_priv
->mm
.stolen_base
+
5369 (ggtt
->stolen_size
- pctx_size
));
5371 pctx_paddr
= (paddr
& (~4095));
5372 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5375 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5378 static void valleyview_setup_pctx(struct drm_i915_private
*dev_priv
)
5380 struct drm_i915_gem_object
*pctx
;
5381 unsigned long pctx_paddr
;
5383 int pctx_size
= 24*1024;
5385 mutex_lock(&dev_priv
->dev
->struct_mutex
);
5387 pcbr
= I915_READ(VLV_PCBR
);
5389 /* BIOS set it up already, grab the pre-alloc'd space */
5392 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
5393 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
5395 I915_GTT_OFFSET_NONE
,
5400 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5403 * From the Gunit register HAS:
5404 * The Gfx driver is expected to program this register and ensure
5405 * proper allocation within Gfx stolen memory. For example, this
5406 * register should be programmed such than the PCBR range does not
5407 * overlap with other ranges, such as the frame buffer, protected
5408 * memory, or any other relevant ranges.
5410 pctx
= i915_gem_object_create_stolen(dev_priv
->dev
, pctx_size
);
5412 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5416 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
5417 I915_WRITE(VLV_PCBR
, pctx_paddr
);
5420 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR
));
5421 dev_priv
->vlv_pctx
= pctx
;
5422 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
5425 static void valleyview_cleanup_pctx(struct drm_i915_private
*dev_priv
)
5427 if (WARN_ON(!dev_priv
->vlv_pctx
))
5430 drm_gem_object_unreference_unlocked(&dev_priv
->vlv_pctx
->base
);
5431 dev_priv
->vlv_pctx
= NULL
;
5434 static void vlv_init_gpll_ref_freq(struct drm_i915_private
*dev_priv
)
5436 dev_priv
->rps
.gpll_ref_freq
=
5437 vlv_get_cck_clock(dev_priv
, "GPLL ref",
5438 CCK_GPLL_CLOCK_CONTROL
,
5439 dev_priv
->czclk_freq
);
5441 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5442 dev_priv
->rps
.gpll_ref_freq
);
5445 static void valleyview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
5449 valleyview_setup_pctx(dev_priv
);
5451 vlv_init_gpll_ref_freq(dev_priv
);
5453 mutex_lock(&dev_priv
->rps
.hw_lock
);
5455 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5456 switch ((val
>> 6) & 3) {
5459 dev_priv
->mem_freq
= 800;
5462 dev_priv
->mem_freq
= 1066;
5465 dev_priv
->mem_freq
= 1333;
5468 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5470 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
5471 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5472 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5473 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5474 dev_priv
->rps
.max_freq
);
5476 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
5477 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5478 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5479 dev_priv
->rps
.efficient_freq
);
5481 dev_priv
->rps
.rp1_freq
= valleyview_rps_guar_freq(dev_priv
);
5482 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5483 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5484 dev_priv
->rps
.rp1_freq
);
5486 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
5487 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5488 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5489 dev_priv
->rps
.min_freq
);
5491 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5493 /* Preserve min/max settings in case of re-init */
5494 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5495 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5497 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5498 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5500 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5503 static void cherryview_init_gt_powersave(struct drm_i915_private
*dev_priv
)
5507 cherryview_setup_pctx(dev_priv
);
5509 vlv_init_gpll_ref_freq(dev_priv
);
5511 mutex_lock(&dev_priv
->rps
.hw_lock
);
5513 mutex_lock(&dev_priv
->sb_lock
);
5514 val
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
);
5515 mutex_unlock(&dev_priv
->sb_lock
);
5517 switch ((val
>> 2) & 0x7) {
5519 dev_priv
->mem_freq
= 2000;
5522 dev_priv
->mem_freq
= 1600;
5525 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv
->mem_freq
);
5527 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
5528 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
5529 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5530 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
5531 dev_priv
->rps
.max_freq
);
5533 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
5534 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5535 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
5536 dev_priv
->rps
.efficient_freq
);
5538 dev_priv
->rps
.rp1_freq
= cherryview_rps_guar_freq(dev_priv
);
5539 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5540 intel_gpu_freq(dev_priv
, dev_priv
->rps
.rp1_freq
),
5541 dev_priv
->rps
.rp1_freq
);
5543 /* PUnit validated range is only [RPe, RP0] */
5544 dev_priv
->rps
.min_freq
= dev_priv
->rps
.efficient_freq
;
5545 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5546 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
5547 dev_priv
->rps
.min_freq
);
5549 WARN_ONCE((dev_priv
->rps
.max_freq
|
5550 dev_priv
->rps
.efficient_freq
|
5551 dev_priv
->rps
.rp1_freq
|
5552 dev_priv
->rps
.min_freq
) & 1,
5553 "Odd GPU freq values\n");
5555 dev_priv
->rps
.idle_freq
= dev_priv
->rps
.min_freq
;
5557 /* Preserve min/max settings in case of re-init */
5558 if (dev_priv
->rps
.max_freq_softlimit
== 0)
5559 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
5561 if (dev_priv
->rps
.min_freq_softlimit
== 0)
5562 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
5564 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5567 static void valleyview_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
5569 valleyview_cleanup_pctx(dev_priv
);
5572 static void cherryview_enable_rps(struct drm_i915_private
*dev_priv
)
5574 struct intel_engine_cs
*engine
;
5575 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
5577 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5579 gtfifodbg
= I915_READ(GTFIFODBG
) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV
|
5580 GT_FIFO_FREE_ENTRIES_CHV
);
5582 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5584 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5587 cherryview_check_pctx(dev_priv
);
5589 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5590 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5591 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5593 /* Disable RC states. */
5594 I915_WRITE(GEN6_RC_CONTROL
, 0);
5596 /* 2a: Program RC6 thresholds.*/
5597 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
5598 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
5599 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
5601 for_each_engine(engine
, dev_priv
)
5602 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5603 I915_WRITE(GEN6_RC_SLEEP
, 0);
5605 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5606 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x186);
5608 /* allows RC6 residency counter to work */
5609 I915_WRITE(VLV_COUNTER_CONTROL
,
5610 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
5611 VLV_MEDIA_RC6_COUNT_EN
|
5612 VLV_RENDER_RC6_COUNT_EN
));
5614 /* For now we assume BIOS is allocating and populating the PCBR */
5615 pcbr
= I915_READ(VLV_PCBR
);
5618 if ((intel_enable_rc6() & INTEL_RC6_ENABLE
) &&
5619 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
5620 rc6_mode
= GEN7_RC_CTL_TO_MODE
;
5622 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5624 /* 4 Program defaults and thresholds for RPS*/
5625 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5626 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5627 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5628 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5629 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5631 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5634 I915_WRITE(GEN6_RP_CONTROL
,
5635 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5636 GEN6_RP_MEDIA_IS_GFX
|
5638 GEN6_RP_UP_BUSY_AVG
|
5639 GEN6_RP_DOWN_IDLE_AVG
);
5641 /* Setting Fixed Bias */
5642 val
= VLV_OVERRIDE_EN
|
5644 CHV_BIAS_CPU_50_SOC_50
;
5645 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5647 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5649 /* RPS code assumes GPLL is used */
5650 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5652 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
5653 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5655 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5656 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5657 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5658 dev_priv
->rps
.cur_freq
);
5660 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5661 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
),
5662 dev_priv
->rps
.idle_freq
);
5664 valleyview_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5666 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5669 static void valleyview_enable_rps(struct drm_i915_private
*dev_priv
)
5671 struct intel_engine_cs
*engine
;
5672 u32 gtfifodbg
, val
, rc6_mode
= 0;
5674 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
5676 valleyview_check_pctx(dev_priv
);
5678 gtfifodbg
= I915_READ(GTFIFODBG
);
5680 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5682 I915_WRITE(GTFIFODBG
, gtfifodbg
);
5685 /* If VLV, Forcewake all wells, else re-direct to regular path */
5686 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5688 /* Disable RC states. */
5689 I915_WRITE(GEN6_RC_CONTROL
, 0);
5691 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
5692 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
5693 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
5694 I915_WRITE(GEN6_RP_UP_EI
, 66000);
5695 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
5697 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
5699 I915_WRITE(GEN6_RP_CONTROL
,
5700 GEN6_RP_MEDIA_TURBO
|
5701 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
5702 GEN6_RP_MEDIA_IS_GFX
|
5704 GEN6_RP_UP_BUSY_AVG
|
5705 GEN6_RP_DOWN_IDLE_CONT
);
5707 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
5708 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
5709 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
5711 for_each_engine(engine
, dev_priv
)
5712 I915_WRITE(RING_MAX_IDLE(engine
->mmio_base
), 10);
5714 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
5716 /* allows RC6 residency counter to work */
5717 I915_WRITE(VLV_COUNTER_CONTROL
,
5718 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN
|
5719 VLV_RENDER_RC0_COUNT_EN
|
5720 VLV_MEDIA_RC6_COUNT_EN
|
5721 VLV_RENDER_RC6_COUNT_EN
));
5723 if (intel_enable_rc6() & INTEL_RC6_ENABLE
)
5724 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
5726 intel_print_rc6_info(dev_priv
, rc6_mode
);
5728 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
5730 /* Setting Fixed Bias */
5731 val
= VLV_OVERRIDE_EN
|
5733 VLV_BIAS_CPU_125_SOC_875
;
5734 vlv_punit_write(dev_priv
, VLV_TURBO_SOC_OVERRIDE
, val
);
5736 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5738 /* RPS code assumes GPLL is used */
5739 WARN_ONCE((val
& GPLLENABLE
) == 0, "GPLL not enabled\n");
5741 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val
& GPLLENABLE
));
5742 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
5744 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
5745 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5746 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
5747 dev_priv
->rps
.cur_freq
);
5749 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5750 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
),
5751 dev_priv
->rps
.idle_freq
);
5753 valleyview_set_rps(dev_priv
, dev_priv
->rps
.idle_freq
);
5755 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5758 static unsigned long intel_pxfreq(u32 vidfreq
)
5761 int div
= (vidfreq
& 0x3f0000) >> 16;
5762 int post
= (vidfreq
& 0x3000) >> 12;
5763 int pre
= (vidfreq
& 0x7);
5768 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5773 static const struct cparams
{
5779 { 1, 1333, 301, 28664 },
5780 { 1, 1066, 294, 24460 },
5781 { 1, 800, 294, 25192 },
5782 { 0, 1333, 276, 27605 },
5783 { 0, 1066, 276, 27605 },
5784 { 0, 800, 231, 23784 },
5787 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
5789 u64 total_count
, diff
, ret
;
5790 u32 count1
, count2
, count3
, m
= 0, c
= 0;
5791 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
5794 assert_spin_locked(&mchdev_lock
);
5796 diff1
= now
- dev_priv
->ips
.last_time1
;
5798 /* Prevent division-by-zero if we are asking too fast.
5799 * Also, we don't get interesting results if we are polling
5800 * faster than once in 10ms, so just return the saved value
5804 return dev_priv
->ips
.chipset_power
;
5806 count1
= I915_READ(DMIEC
);
5807 count2
= I915_READ(DDREC
);
5808 count3
= I915_READ(CSIEC
);
5810 total_count
= count1
+ count2
+ count3
;
5812 /* FIXME: handle per-counter overflow */
5813 if (total_count
< dev_priv
->ips
.last_count1
) {
5814 diff
= ~0UL - dev_priv
->ips
.last_count1
;
5815 diff
+= total_count
;
5817 diff
= total_count
- dev_priv
->ips
.last_count1
;
5820 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
5821 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
5822 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
5829 diff
= div_u64(diff
, diff1
);
5830 ret
= ((m
* diff
) + c
);
5831 ret
= div_u64(ret
, 10);
5833 dev_priv
->ips
.last_count1
= total_count
;
5834 dev_priv
->ips
.last_time1
= now
;
5836 dev_priv
->ips
.chipset_power
= ret
;
5841 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
5845 if (INTEL_INFO(dev_priv
)->gen
!= 5)
5848 spin_lock_irq(&mchdev_lock
);
5850 val
= __i915_chipset_val(dev_priv
);
5852 spin_unlock_irq(&mchdev_lock
);
5857 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
5859 unsigned long m
, x
, b
;
5862 tsfs
= I915_READ(TSFS
);
5864 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
5865 x
= I915_READ8(TR1
);
5867 b
= tsfs
& TSFS_INTR_MASK
;
5869 return ((m
* x
) / 127) - b
;
5872 static int _pxvid_to_vd(u8 pxvid
)
5877 if (pxvid
>= 8 && pxvid
< 31)
5880 return (pxvid
+ 2) * 125;
5883 static u32
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
5885 const int vd
= _pxvid_to_vd(pxvid
);
5886 const int vm
= vd
- 1125;
5888 if (INTEL_INFO(dev_priv
)->is_mobile
)
5889 return vm
> 0 ? vm
: 0;
5894 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5896 u64 now
, diff
, diffms
;
5899 assert_spin_locked(&mchdev_lock
);
5901 now
= ktime_get_raw_ns();
5902 diffms
= now
- dev_priv
->ips
.last_time2
;
5903 do_div(diffms
, NSEC_PER_MSEC
);
5905 /* Don't divide by 0 */
5909 count
= I915_READ(GFXEC
);
5911 if (count
< dev_priv
->ips
.last_count2
) {
5912 diff
= ~0UL - dev_priv
->ips
.last_count2
;
5915 diff
= count
- dev_priv
->ips
.last_count2
;
5918 dev_priv
->ips
.last_count2
= count
;
5919 dev_priv
->ips
.last_time2
= now
;
5921 /* More magic constants... */
5923 diff
= div_u64(diff
, diffms
* 10);
5924 dev_priv
->ips
.gfx_power
= diff
;
5927 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
5929 if (INTEL_INFO(dev_priv
)->gen
!= 5)
5932 spin_lock_irq(&mchdev_lock
);
5934 __i915_update_gfx_val(dev_priv
);
5936 spin_unlock_irq(&mchdev_lock
);
5939 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
5941 unsigned long t
, corr
, state1
, corr2
, state2
;
5944 assert_spin_locked(&mchdev_lock
);
5946 pxvid
= I915_READ(PXVFREQ(dev_priv
->rps
.cur_freq
));
5947 pxvid
= (pxvid
>> 24) & 0x7f;
5948 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
5952 t
= i915_mch_val(dev_priv
);
5954 /* Revel in the empirically derived constants */
5956 /* Correction factor in 1/100000 units */
5958 corr
= ((t
* 2349) + 135940);
5960 corr
= ((t
* 964) + 29317);
5962 corr
= ((t
* 301) + 1004);
5964 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
5966 corr2
= (corr
* dev_priv
->ips
.corr
);
5968 state2
= (corr2
* state1
) / 10000;
5969 state2
/= 100; /* convert to mW */
5971 __i915_update_gfx_val(dev_priv
);
5973 return dev_priv
->ips
.gfx_power
+ state2
;
5976 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
5980 if (INTEL_INFO(dev_priv
)->gen
!= 5)
5983 spin_lock_irq(&mchdev_lock
);
5985 val
= __i915_gfx_val(dev_priv
);
5987 spin_unlock_irq(&mchdev_lock
);
5993 * i915_read_mch_val - return value for IPS use
5995 * Calculate and return a value for the IPS driver to use when deciding whether
5996 * we have thermal and power headroom to increase CPU or GPU power budget.
5998 unsigned long i915_read_mch_val(void)
6000 struct drm_i915_private
*dev_priv
;
6001 unsigned long chipset_val
, graphics_val
, ret
= 0;
6003 spin_lock_irq(&mchdev_lock
);
6006 dev_priv
= i915_mch_dev
;
6008 chipset_val
= __i915_chipset_val(dev_priv
);
6009 graphics_val
= __i915_gfx_val(dev_priv
);
6011 ret
= chipset_val
+ graphics_val
;
6014 spin_unlock_irq(&mchdev_lock
);
6018 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
6021 * i915_gpu_raise - raise GPU frequency limit
6023 * Raise the limit; IPS indicates we have thermal headroom.
6025 bool i915_gpu_raise(void)
6027 struct drm_i915_private
*dev_priv
;
6030 spin_lock_irq(&mchdev_lock
);
6031 if (!i915_mch_dev
) {
6035 dev_priv
= i915_mch_dev
;
6037 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
6038 dev_priv
->ips
.max_delay
--;
6041 spin_unlock_irq(&mchdev_lock
);
6045 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
6048 * i915_gpu_lower - lower GPU frequency limit
6050 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6051 * frequency maximum.
6053 bool i915_gpu_lower(void)
6055 struct drm_i915_private
*dev_priv
;
6058 spin_lock_irq(&mchdev_lock
);
6059 if (!i915_mch_dev
) {
6063 dev_priv
= i915_mch_dev
;
6065 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
6066 dev_priv
->ips
.max_delay
++;
6069 spin_unlock_irq(&mchdev_lock
);
6073 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
6076 * i915_gpu_busy - indicate GPU business to IPS
6078 * Tell the IPS driver whether or not the GPU is busy.
6080 bool i915_gpu_busy(void)
6082 struct drm_i915_private
*dev_priv
;
6083 struct intel_engine_cs
*engine
;
6086 spin_lock_irq(&mchdev_lock
);
6089 dev_priv
= i915_mch_dev
;
6091 for_each_engine(engine
, dev_priv
)
6092 ret
|= !list_empty(&engine
->request_list
);
6095 spin_unlock_irq(&mchdev_lock
);
6099 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
6102 * i915_gpu_turbo_disable - disable graphics turbo
6104 * Disable graphics turbo by resetting the max frequency and setting the
6105 * current frequency to the default.
6107 bool i915_gpu_turbo_disable(void)
6109 struct drm_i915_private
*dev_priv
;
6112 spin_lock_irq(&mchdev_lock
);
6113 if (!i915_mch_dev
) {
6117 dev_priv
= i915_mch_dev
;
6119 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
6121 if (!ironlake_set_drps(dev_priv
, dev_priv
->ips
.fstart
))
6125 spin_unlock_irq(&mchdev_lock
);
6129 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
6132 * Tells the intel_ips driver that the i915 driver is now loaded, if
6133 * IPS got loaded first.
6135 * This awkward dance is so that neither module has to depend on the
6136 * other in order for IPS to do the appropriate communication of
6137 * GPU turbo limits to i915.
6140 ips_ping_for_i915_load(void)
6144 link
= symbol_get(ips_link_to_i915_driver
);
6147 symbol_put(ips_link_to_i915_driver
);
6151 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
6153 /* We only register the i915 ips part with intel-ips once everything is
6154 * set up, to avoid intel-ips sneaking in and reading bogus values. */
6155 spin_lock_irq(&mchdev_lock
);
6156 i915_mch_dev
= dev_priv
;
6157 spin_unlock_irq(&mchdev_lock
);
6159 ips_ping_for_i915_load();
6162 void intel_gpu_ips_teardown(void)
6164 spin_lock_irq(&mchdev_lock
);
6165 i915_mch_dev
= NULL
;
6166 spin_unlock_irq(&mchdev_lock
);
6169 static void intel_init_emon(struct drm_i915_private
*dev_priv
)
6175 /* Disable to program */
6179 /* Program energy weights for various events */
6180 I915_WRITE(SDEW
, 0x15040d00);
6181 I915_WRITE(CSIEW0
, 0x007f0000);
6182 I915_WRITE(CSIEW1
, 0x1e220004);
6183 I915_WRITE(CSIEW2
, 0x04000004);
6185 for (i
= 0; i
< 5; i
++)
6186 I915_WRITE(PEW(i
), 0);
6187 for (i
= 0; i
< 3; i
++)
6188 I915_WRITE(DEW(i
), 0);
6190 /* Program P-state weights to account for frequency power adjustment */
6191 for (i
= 0; i
< 16; i
++) {
6192 u32 pxvidfreq
= I915_READ(PXVFREQ(i
));
6193 unsigned long freq
= intel_pxfreq(pxvidfreq
);
6194 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
6199 val
*= (freq
/ 1000);
6201 val
/= (127*127*900);
6203 DRM_ERROR("bad pxval: %ld\n", val
);
6206 /* Render standby states get 0 weight */
6210 for (i
= 0; i
< 4; i
++) {
6211 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
6212 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
6213 I915_WRITE(PXW(i
), val
);
6216 /* Adjust magic regs to magic values (more experimental results) */
6217 I915_WRITE(OGW0
, 0);
6218 I915_WRITE(OGW1
, 0);
6219 I915_WRITE(EG0
, 0x00007f00);
6220 I915_WRITE(EG1
, 0x0000000e);
6221 I915_WRITE(EG2
, 0x000e0000);
6222 I915_WRITE(EG3
, 0x68000300);
6223 I915_WRITE(EG4
, 0x42000000);
6224 I915_WRITE(EG5
, 0x00140031);
6228 for (i
= 0; i
< 8; i
++)
6229 I915_WRITE(PXWL(i
), 0);
6231 /* Enable PMON + select events */
6232 I915_WRITE(ECR
, 0x80000019);
6234 lcfuse
= I915_READ(LCFUSE02
);
6236 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
6239 void intel_init_gt_powersave(struct drm_i915_private
*dev_priv
)
6242 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6245 if (!i915
.enable_rc6
) {
6246 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6247 intel_runtime_pm_get(dev_priv
);
6250 if (IS_CHERRYVIEW(dev_priv
))
6251 cherryview_init_gt_powersave(dev_priv
);
6252 else if (IS_VALLEYVIEW(dev_priv
))
6253 valleyview_init_gt_powersave(dev_priv
);
6256 void intel_cleanup_gt_powersave(struct drm_i915_private
*dev_priv
)
6258 if (IS_CHERRYVIEW(dev_priv
))
6260 else if (IS_VALLEYVIEW(dev_priv
))
6261 valleyview_cleanup_gt_powersave(dev_priv
);
6263 if (!i915
.enable_rc6
)
6264 intel_runtime_pm_put(dev_priv
);
6267 static void gen6_suspend_rps(struct drm_i915_private
*dev_priv
)
6269 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
6271 gen6_disable_rps_interrupts(dev_priv
);
6275 * intel_suspend_gt_powersave - suspend PM work and helper threads
6276 * @dev_priv: i915 device
6278 * We don't want to disable RC6 or other features here, we just want
6279 * to make sure any work we've queued has finished and won't bother
6280 * us while we're suspended.
6282 void intel_suspend_gt_powersave(struct drm_i915_private
*dev_priv
)
6284 if (INTEL_GEN(dev_priv
) < 6)
6287 gen6_suspend_rps(dev_priv
);
6289 /* Force GPU to min freq during suspend */
6290 gen6_rps_idle(dev_priv
);
6293 void intel_disable_gt_powersave(struct drm_i915_private
*dev_priv
)
6295 if (IS_IRONLAKE_M(dev_priv
)) {
6296 ironlake_disable_drps(dev_priv
);
6297 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
6298 intel_suspend_gt_powersave(dev_priv
);
6300 mutex_lock(&dev_priv
->rps
.hw_lock
);
6301 if (INTEL_INFO(dev_priv
)->gen
>= 9) {
6302 gen9_disable_rc6(dev_priv
);
6303 gen9_disable_rps(dev_priv
);
6304 } else if (IS_CHERRYVIEW(dev_priv
))
6305 cherryview_disable_rps(dev_priv
);
6306 else if (IS_VALLEYVIEW(dev_priv
))
6307 valleyview_disable_rps(dev_priv
);
6309 gen6_disable_rps(dev_priv
);
6311 dev_priv
->rps
.enabled
= false;
6312 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6316 static void intel_gen6_powersave_work(struct work_struct
*work
)
6318 struct drm_i915_private
*dev_priv
=
6319 container_of(work
, struct drm_i915_private
,
6320 rps
.delayed_resume_work
.work
);
6322 mutex_lock(&dev_priv
->rps
.hw_lock
);
6324 gen6_reset_rps_interrupts(dev_priv
);
6326 if (IS_CHERRYVIEW(dev_priv
)) {
6327 cherryview_enable_rps(dev_priv
);
6328 } else if (IS_VALLEYVIEW(dev_priv
)) {
6329 valleyview_enable_rps(dev_priv
);
6330 } else if (INTEL_INFO(dev_priv
)->gen
>= 9) {
6331 gen9_enable_rc6(dev_priv
);
6332 gen9_enable_rps(dev_priv
);
6333 if (IS_SKYLAKE(dev_priv
) || IS_KABYLAKE(dev_priv
))
6334 __gen6_update_ring_freq(dev_priv
);
6335 } else if (IS_BROADWELL(dev_priv
)) {
6336 gen8_enable_rps(dev_priv
);
6337 __gen6_update_ring_freq(dev_priv
);
6339 gen6_enable_rps(dev_priv
);
6340 __gen6_update_ring_freq(dev_priv
);
6343 WARN_ON(dev_priv
->rps
.max_freq
< dev_priv
->rps
.min_freq
);
6344 WARN_ON(dev_priv
->rps
.idle_freq
> dev_priv
->rps
.max_freq
);
6346 WARN_ON(dev_priv
->rps
.efficient_freq
< dev_priv
->rps
.min_freq
);
6347 WARN_ON(dev_priv
->rps
.efficient_freq
> dev_priv
->rps
.max_freq
);
6349 dev_priv
->rps
.enabled
= true;
6351 gen6_enable_rps_interrupts(dev_priv
);
6353 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6355 intel_runtime_pm_put(dev_priv
);
6358 void intel_enable_gt_powersave(struct drm_i915_private
*dev_priv
)
6360 /* Powersaving is controlled by the host when inside a VM */
6361 if (intel_vgpu_active(dev_priv
))
6364 if (IS_IRONLAKE_M(dev_priv
)) {
6365 ironlake_enable_drps(dev_priv
);
6366 mutex_lock(&dev_priv
->dev
->struct_mutex
);
6367 intel_init_emon(dev_priv
);
6368 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
6369 } else if (INTEL_INFO(dev_priv
)->gen
>= 6) {
6371 * PCU communication is slow and this doesn't need to be
6372 * done at any specific time, so do this out of our fast path
6373 * to make resume and init faster.
6375 * We depend on the HW RC6 power context save/restore
6376 * mechanism when entering D3 through runtime PM suspend. So
6377 * disable RPM until RPS/RC6 is properly setup. We can only
6378 * get here via the driver load/system resume/runtime resume
6379 * paths, so the _noresume version is enough (and in case of
6380 * runtime resume it's necessary).
6382 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
6383 round_jiffies_up_relative(HZ
)))
6384 intel_runtime_pm_get_noresume(dev_priv
);
6388 void intel_reset_gt_powersave(struct drm_i915_private
*dev_priv
)
6390 if (INTEL_INFO(dev_priv
)->gen
< 6)
6393 gen6_suspend_rps(dev_priv
);
6394 dev_priv
->rps
.enabled
= false;
6397 static void ibx_init_clock_gating(struct drm_device
*dev
)
6399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6402 * On Ibex Peak and Cougar Point, we need to disable clock
6403 * gating for the panel power sequencer or it will fail to
6404 * start up when no ports are active.
6406 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
6409 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
6411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6414 for_each_pipe(dev_priv
, pipe
) {
6415 I915_WRITE(DSPCNTR(pipe
),
6416 I915_READ(DSPCNTR(pipe
)) |
6417 DISPPLANE_TRICKLE_FEED_DISABLE
);
6419 I915_WRITE(DSPSURF(pipe
), I915_READ(DSPSURF(pipe
)));
6420 POSTING_READ(DSPSURF(pipe
));
6424 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
6426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6428 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
6429 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
6430 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
6433 * Don't touch WM1S_LP_EN here.
6434 * Doing so could cause underruns.
6438 static void ironlake_init_clock_gating(struct drm_device
*dev
)
6440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6441 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6445 * WaFbcDisableDpfcClockGating:ilk
6447 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
6448 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
6449 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
6451 I915_WRITE(PCH_3DCGDIS0
,
6452 MARIUNIT_CLOCK_GATE_DISABLE
|
6453 SVSMUNIT_CLOCK_GATE_DISABLE
);
6454 I915_WRITE(PCH_3DCGDIS1
,
6455 VFMUNIT_CLOCK_GATE_DISABLE
);
6458 * According to the spec the following bits should be set in
6459 * order to enable memory self-refresh
6460 * The bit 22/21 of 0x42004
6461 * The bit 5 of 0x42020
6462 * The bit 15 of 0x45000
6464 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6465 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
6466 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
6467 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
6468 I915_WRITE(DISP_ARB_CTL
,
6469 (I915_READ(DISP_ARB_CTL
) |
6472 ilk_init_lp_watermarks(dev
);
6475 * Based on the document from hardware guys the following bits
6476 * should be set unconditionally in order to enable FBC.
6477 * The bit 22 of 0x42000
6478 * The bit 22 of 0x42004
6479 * The bit 7,8,9 of 0x42020.
6481 if (IS_IRONLAKE_M(dev
)) {
6482 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6483 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6484 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6486 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6487 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6491 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6493 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6494 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6495 ILK_ELPIN_409_SELECT
);
6496 I915_WRITE(_3D_CHICKEN2
,
6497 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
6498 _3D_CHICKEN2_WM_READ_PIPELINED
);
6500 /* WaDisableRenderCachePipelinedFlush:ilk */
6501 I915_WRITE(CACHE_MODE_0
,
6502 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
6504 /* WaDisable_RenderCache_OperationalFlush:ilk */
6505 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6507 g4x_disable_trickle_feed(dev
);
6509 ibx_init_clock_gating(dev
);
6512 static void cpt_init_clock_gating(struct drm_device
*dev
)
6514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6519 * On Ibex Peak and Cougar Point, we need to disable clock
6520 * gating for the panel power sequencer or it will fail to
6521 * start up when no ports are active.
6523 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
6524 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
6525 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
6526 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
6527 DPLS_EDP_PPS_FIX_DIS
);
6528 /* The below fixes the weird display corruption, a few pixels shifted
6529 * downward, on (only) LVDS of some HP laptops with IVY.
6531 for_each_pipe(dev_priv
, pipe
) {
6532 val
= I915_READ(TRANS_CHICKEN2(pipe
));
6533 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
6534 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6535 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
6536 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
6537 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
6538 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
6539 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
6540 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
6542 /* WADP0ClockGatingDisable */
6543 for_each_pipe(dev_priv
, pipe
) {
6544 I915_WRITE(TRANS_CHICKEN1(pipe
),
6545 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6549 static void gen6_check_mch_setup(struct drm_device
*dev
)
6551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6554 tmp
= I915_READ(MCH_SSKPD
);
6555 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
)
6556 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6560 static void gen6_init_clock_gating(struct drm_device
*dev
)
6562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6563 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
6565 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
6567 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6568 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6569 ILK_ELPIN_409_SELECT
);
6571 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6572 I915_WRITE(_3D_CHICKEN
,
6573 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
6575 /* WaDisable_RenderCache_OperationalFlush:snb */
6576 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6579 * BSpec recoomends 8x4 when MSAA is used,
6580 * however in practice 16x4 seems fastest.
6582 * Note that PS/WM thread counts depend on the WIZ hashing
6583 * disable bit, which we don't touch here, but it's good
6584 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6586 I915_WRITE(GEN6_GT_MODE
,
6587 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6589 ilk_init_lp_watermarks(dev
);
6591 I915_WRITE(CACHE_MODE_0
,
6592 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
6594 I915_WRITE(GEN6_UCGCTL1
,
6595 I915_READ(GEN6_UCGCTL1
) |
6596 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
6597 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
6599 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6600 * gating disable must be set. Failure to set it results in
6601 * flickering pixels due to Z write ordering failures after
6602 * some amount of runtime in the Mesa "fire" demo, and Unigine
6603 * Sanctuary and Tropics, and apparently anything else with
6604 * alpha test or pixel discard.
6606 * According to the spec, bit 11 (RCCUNIT) must also be set,
6607 * but we didn't debug actual testcases to find it out.
6609 * WaDisableRCCUnitClockGating:snb
6610 * WaDisableRCPBUnitClockGating:snb
6612 I915_WRITE(GEN6_UCGCTL2
,
6613 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
6614 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
6616 /* WaStripsFansDisableFastClipPerformanceFix:snb */
6617 I915_WRITE(_3D_CHICKEN3
,
6618 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
6622 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6623 * 3DSTATE_SF number of SF output attributes is more than 16."
6625 I915_WRITE(_3D_CHICKEN3
,
6626 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
6629 * According to the spec the following bits should be
6630 * set in order to enable memory self-refresh and fbc:
6631 * The bit21 and bit22 of 0x42000
6632 * The bit21 and bit22 of 0x42004
6633 * The bit5 and bit7 of 0x42020
6634 * The bit14 of 0x70180
6635 * The bit14 of 0x71180
6637 * WaFbcAsynchFlipDisableFbcQueue:snb
6639 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
6640 I915_READ(ILK_DISPLAY_CHICKEN1
) |
6641 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
6642 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
6643 I915_READ(ILK_DISPLAY_CHICKEN2
) |
6644 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
6645 I915_WRITE(ILK_DSPCLK_GATE_D
,
6646 I915_READ(ILK_DSPCLK_GATE_D
) |
6647 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
6648 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
6650 g4x_disable_trickle_feed(dev
);
6652 cpt_init_clock_gating(dev
);
6654 gen6_check_mch_setup(dev
);
6657 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
6659 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
6662 * WaVSThreadDispatchOverride:ivb,vlv
6664 * This actually overrides the dispatch
6665 * mode for all thread types.
6667 reg
&= ~GEN7_FF_SCHED_MASK
;
6668 reg
|= GEN7_FF_TS_SCHED_HW
;
6669 reg
|= GEN7_FF_VS_SCHED_HW
;
6670 reg
|= GEN7_FF_DS_SCHED_HW
;
6672 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
6675 static void lpt_init_clock_gating(struct drm_device
*dev
)
6677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6680 * TODO: this bit should only be enabled when really needed, then
6681 * disabled when not needed anymore in order to save power.
6683 if (HAS_PCH_LPT_LP(dev
))
6684 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
6685 I915_READ(SOUTH_DSPCLK_GATE_D
) |
6686 PCH_LP_PARTITION_LEVEL_DISABLE
);
6688 /* WADPOClockGatingDisable:hsw */
6689 I915_WRITE(TRANS_CHICKEN1(PIPE_A
),
6690 I915_READ(TRANS_CHICKEN1(PIPE_A
)) |
6691 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
6694 static void lpt_suspend_hw(struct drm_device
*dev
)
6696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6698 if (HAS_PCH_LPT_LP(dev
)) {
6699 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6701 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6702 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6706 static void gen8_set_l3sqc_credits(struct drm_i915_private
*dev_priv
,
6707 int general_prio_credits
,
6708 int high_prio_credits
)
6712 /* WaTempDisableDOPClkGating:bdw */
6713 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
6714 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
6716 I915_WRITE(GEN8_L3SQCREG1
,
6717 L3_GENERAL_PRIO_CREDITS(general_prio_credits
) |
6718 L3_HIGH_PRIO_CREDITS(high_prio_credits
));
6721 * Wait at least 100 clocks before re-enabling clock gating.
6722 * See the definition of L3SQCREG1 in BSpec.
6724 POSTING_READ(GEN8_L3SQCREG1
);
6726 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
6729 static void broadwell_init_clock_gating(struct drm_device
*dev
)
6731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6734 ilk_init_lp_watermarks(dev
);
6736 /* WaSwitchSolVfFArbitrationPriority:bdw */
6737 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
6739 /* WaPsrDPAMaskVBlankInSRD:bdw */
6740 I915_WRITE(CHICKEN_PAR1_1
,
6741 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
6743 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6744 for_each_pipe(dev_priv
, pipe
) {
6745 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
6746 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
6747 BDW_DPRS_MASK_VBLANK_SRD
);
6750 /* WaVSRefCountFullforceMissDisable:bdw */
6751 /* WaDSRefCountFullforceMissDisable:bdw */
6752 I915_WRITE(GEN7_FF_THREAD_MODE
,
6753 I915_READ(GEN7_FF_THREAD_MODE
) &
6754 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
6756 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
6757 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
6759 /* WaDisableSDEUnitClockGating:bdw */
6760 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
6761 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
6763 /* WaProgramL3SqcReg1Default:bdw */
6764 gen8_set_l3sqc_credits(dev_priv
, 30, 2);
6767 * WaGttCachingOffByDefault:bdw
6768 * GTT cache may not work with big pages, so if those
6769 * are ever enabled GTT cache may need to be disabled.
6771 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
6773 lpt_init_clock_gating(dev
);
6776 static void haswell_init_clock_gating(struct drm_device
*dev
)
6778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6780 ilk_init_lp_watermarks(dev
);
6782 /* L3 caching of data atomics doesn't work -- disable it. */
6783 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
6784 I915_WRITE(HSW_ROW_CHICKEN3
,
6785 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
6787 /* This is required by WaCatErrorRejectionIssue:hsw */
6788 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6789 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6790 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6792 /* WaVSRefCountFullforceMissDisable:hsw */
6793 I915_WRITE(GEN7_FF_THREAD_MODE
,
6794 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
6796 /* WaDisable_RenderCache_OperationalFlush:hsw */
6797 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6799 /* enable HiZ Raw Stall Optimization */
6800 I915_WRITE(CACHE_MODE_0_GEN7
,
6801 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6803 /* WaDisable4x2SubspanOptimization:hsw */
6804 I915_WRITE(CACHE_MODE_1
,
6805 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6808 * BSpec recommends 8x4 when MSAA is used,
6809 * however in practice 16x4 seems fastest.
6811 * Note that PS/WM thread counts depend on the WIZ hashing
6812 * disable bit, which we don't touch here, but it's good
6813 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6815 I915_WRITE(GEN7_GT_MODE
,
6816 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6818 /* WaSampleCChickenBitEnable:hsw */
6819 I915_WRITE(HALF_SLICE_CHICKEN3
,
6820 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE
));
6822 /* WaSwitchSolVfFArbitrationPriority:hsw */
6823 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
6825 /* WaRsPkgCStateDisplayPMReq:hsw */
6826 I915_WRITE(CHICKEN_PAR1_1
,
6827 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
6829 lpt_init_clock_gating(dev
);
6832 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
6834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6837 ilk_init_lp_watermarks(dev
);
6839 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
6841 /* WaDisableEarlyCull:ivb */
6842 I915_WRITE(_3D_CHICKEN3
,
6843 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6845 /* WaDisableBackToBackFlipFix:ivb */
6846 I915_WRITE(IVB_CHICKEN3
,
6847 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6848 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6850 /* WaDisablePSDDualDispatchEnable:ivb */
6851 if (IS_IVB_GT1(dev
))
6852 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6853 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6855 /* WaDisable_RenderCache_OperationalFlush:ivb */
6856 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6858 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6859 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
6860 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
6862 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6863 I915_WRITE(GEN7_L3CNTLREG1
,
6864 GEN7_WA_FOR_GEN7_L3_CONTROL
);
6865 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
6866 GEN7_WA_L3_CHICKEN_MODE
);
6867 if (IS_IVB_GT1(dev
))
6868 I915_WRITE(GEN7_ROW_CHICKEN2
,
6869 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6871 /* must write both registers */
6872 I915_WRITE(GEN7_ROW_CHICKEN2
,
6873 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6874 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
6875 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6878 /* WaForceL3Serialization:ivb */
6879 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6880 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6883 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6884 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6886 I915_WRITE(GEN6_UCGCTL2
,
6887 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6889 /* This is required by WaCatErrorRejectionIssue:ivb */
6890 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6891 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6892 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6894 g4x_disable_trickle_feed(dev
);
6896 gen7_setup_fixed_func_scheduler(dev_priv
);
6898 if (0) { /* causes HiZ corruption on ivb:gt1 */
6899 /* enable HiZ Raw Stall Optimization */
6900 I915_WRITE(CACHE_MODE_0_GEN7
,
6901 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
6904 /* WaDisable4x2SubspanOptimization:ivb */
6905 I915_WRITE(CACHE_MODE_1
,
6906 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6909 * BSpec recommends 8x4 when MSAA is used,
6910 * however in practice 16x4 seems fastest.
6912 * Note that PS/WM thread counts depend on the WIZ hashing
6913 * disable bit, which we don't touch here, but it's good
6914 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6916 I915_WRITE(GEN7_GT_MODE
,
6917 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6919 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
6920 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
6921 snpcr
|= GEN6_MBC_SNPCR_MED
;
6922 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
6924 if (!HAS_PCH_NOP(dev
))
6925 cpt_init_clock_gating(dev
);
6927 gen6_check_mch_setup(dev
);
6930 static void valleyview_init_clock_gating(struct drm_device
*dev
)
6932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6934 /* WaDisableEarlyCull:vlv */
6935 I915_WRITE(_3D_CHICKEN3
,
6936 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
6938 /* WaDisableBackToBackFlipFix:vlv */
6939 I915_WRITE(IVB_CHICKEN3
,
6940 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
6941 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
6943 /* WaPsdDispatchEnable:vlv */
6944 /* WaDisablePSDDualDispatchEnable:vlv */
6945 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
6946 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
6947 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
6949 /* WaDisable_RenderCache_OperationalFlush:vlv */
6950 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
6952 /* WaForceL3Serialization:vlv */
6953 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
6954 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
6956 /* WaDisableDopClockGating:vlv */
6957 I915_WRITE(GEN7_ROW_CHICKEN2
,
6958 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
6960 /* This is required by WaCatErrorRejectionIssue:vlv */
6961 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
6962 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
6963 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
6965 gen7_setup_fixed_func_scheduler(dev_priv
);
6968 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6969 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6971 I915_WRITE(GEN6_UCGCTL2
,
6972 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
6974 /* WaDisableL3Bank2xClockGate:vlv
6975 * Disabling L3 clock gating- MMIO 940c[25] = 1
6976 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6977 I915_WRITE(GEN7_UCGCTL4
,
6978 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
6981 * BSpec says this must be set, even though
6982 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6984 I915_WRITE(CACHE_MODE_1
,
6985 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
6988 * BSpec recommends 8x4 when MSAA is used,
6989 * however in practice 16x4 seems fastest.
6991 * Note that PS/WM thread counts depend on the WIZ hashing
6992 * disable bit, which we don't touch here, but it's good
6993 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6995 I915_WRITE(GEN7_GT_MODE
,
6996 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK
, GEN6_WIZ_HASHING_16x4
));
6999 * WaIncreaseL3CreditsForVLVB0:vlv
7000 * This is the hardware default actually.
7002 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
7005 * WaDisableVLVClockGating_VBIIssue:vlv
7006 * Disable clock gating on th GCFG unit to prevent a delay
7007 * in the reporting of vblank events.
7009 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
7012 static void cherryview_init_clock_gating(struct drm_device
*dev
)
7014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7016 /* WaVSRefCountFullforceMissDisable:chv */
7017 /* WaDSRefCountFullforceMissDisable:chv */
7018 I915_WRITE(GEN7_FF_THREAD_MODE
,
7019 I915_READ(GEN7_FF_THREAD_MODE
) &
7020 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
7022 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7023 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
7024 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
7026 /* WaDisableCSUnitClockGating:chv */
7027 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
7028 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
7030 /* WaDisableSDEUnitClockGating:chv */
7031 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
7032 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
7035 * WaProgramL3SqcReg1Default:chv
7036 * See gfxspecs/Related Documents/Performance Guide/
7037 * LSQC Setting Recommendations.
7039 gen8_set_l3sqc_credits(dev_priv
, 38, 2);
7042 * GTT cache may not work with big pages, so if those
7043 * are ever enabled GTT cache may need to be disabled.
7045 I915_WRITE(HSW_GTT_CACHE_EN
, GTT_CACHE_EN_ALL
);
7048 static void g4x_init_clock_gating(struct drm_device
*dev
)
7050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7051 uint32_t dspclk_gate
;
7053 I915_WRITE(RENCLK_GATE_D1
, 0);
7054 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
7055 GS_UNIT_CLOCK_GATE_DISABLE
|
7056 CL_UNIT_CLOCK_GATE_DISABLE
);
7057 I915_WRITE(RAMCLK_GATE_D
, 0);
7058 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
7059 OVRUNIT_CLOCK_GATE_DISABLE
|
7060 OVCUNIT_CLOCK_GATE_DISABLE
;
7062 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
7063 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
7065 /* WaDisableRenderCachePipelinedFlush */
7066 I915_WRITE(CACHE_MODE_0
,
7067 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
7069 /* WaDisable_RenderCache_OperationalFlush:g4x */
7070 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7072 g4x_disable_trickle_feed(dev
);
7075 static void crestline_init_clock_gating(struct drm_device
*dev
)
7077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7079 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
7080 I915_WRITE(RENCLK_GATE_D2
, 0);
7081 I915_WRITE(DSPCLK_GATE_D
, 0);
7082 I915_WRITE(RAMCLK_GATE_D
, 0);
7083 I915_WRITE16(DEUC
, 0);
7084 I915_WRITE(MI_ARB_STATE
,
7085 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7087 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7088 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7091 static void broadwater_init_clock_gating(struct drm_device
*dev
)
7093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7095 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
7096 I965_RCC_CLOCK_GATE_DISABLE
|
7097 I965_RCPB_CLOCK_GATE_DISABLE
|
7098 I965_ISC_CLOCK_GATE_DISABLE
|
7099 I965_FBC_CLOCK_GATE_DISABLE
);
7100 I915_WRITE(RENCLK_GATE_D2
, 0);
7101 I915_WRITE(MI_ARB_STATE
,
7102 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7104 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7105 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
7108 static void gen3_init_clock_gating(struct drm_device
*dev
)
7110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7111 u32 dstate
= I915_READ(D_STATE
);
7113 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
7114 DSTATE_DOT_CLOCK_GATING
;
7115 I915_WRITE(D_STATE
, dstate
);
7117 if (IS_PINEVIEW(dev
))
7118 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
7120 /* IIR "flip pending" means done if this bit is set */
7121 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
7123 /* interrupts should cause a wake up from C3 */
7124 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
7126 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7127 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
7129 I915_WRITE(MI_ARB_STATE
,
7130 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
7133 static void i85x_init_clock_gating(struct drm_device
*dev
)
7135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7137 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
7139 /* interrupts should cause a wake up from C3 */
7140 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
7141 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
7143 I915_WRITE(MEM_MODE
,
7144 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE
));
7147 static void i830_init_clock_gating(struct drm_device
*dev
)
7149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7151 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
7153 I915_WRITE(MEM_MODE
,
7154 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE
) |
7155 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE
));
7158 void intel_init_clock_gating(struct drm_device
*dev
)
7160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7162 dev_priv
->display
.init_clock_gating(dev
);
7165 void intel_suspend_hw(struct drm_device
*dev
)
7167 if (HAS_PCH_LPT(dev
))
7168 lpt_suspend_hw(dev
);
7171 static void nop_init_clock_gating(struct drm_device
*dev
)
7173 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7177 * intel_init_clock_gating_hooks - setup the clock gating hooks
7178 * @dev_priv: device private
7180 * Setup the hooks that configure which clocks of a given platform can be
7181 * gated and also apply various GT and display specific workarounds for these
7182 * platforms. Note that some GT specific workarounds are applied separately
7183 * when GPU contexts or batchbuffers start their execution.
7185 void intel_init_clock_gating_hooks(struct drm_i915_private
*dev_priv
)
7187 if (IS_SKYLAKE(dev_priv
))
7188 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
7189 else if (IS_KABYLAKE(dev_priv
))
7190 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
7191 else if (IS_BROXTON(dev_priv
))
7192 dev_priv
->display
.init_clock_gating
= bxt_init_clock_gating
;
7193 else if (IS_BROADWELL(dev_priv
))
7194 dev_priv
->display
.init_clock_gating
= broadwell_init_clock_gating
;
7195 else if (IS_CHERRYVIEW(dev_priv
))
7196 dev_priv
->display
.init_clock_gating
= cherryview_init_clock_gating
;
7197 else if (IS_HASWELL(dev_priv
))
7198 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
7199 else if (IS_IVYBRIDGE(dev_priv
))
7200 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
7201 else if (IS_VALLEYVIEW(dev_priv
))
7202 dev_priv
->display
.init_clock_gating
= valleyview_init_clock_gating
;
7203 else if (IS_GEN6(dev_priv
))
7204 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
7205 else if (IS_GEN5(dev_priv
))
7206 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
7207 else if (IS_G4X(dev_priv
))
7208 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
7209 else if (IS_CRESTLINE(dev_priv
))
7210 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
7211 else if (IS_BROADWATER(dev_priv
))
7212 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
7213 else if (IS_GEN3(dev_priv
))
7214 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
7215 else if (IS_I85X(dev_priv
) || IS_I865G(dev_priv
))
7216 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
7217 else if (IS_GEN2(dev_priv
))
7218 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
7220 MISSING_CASE(INTEL_DEVID(dev_priv
));
7221 dev_priv
->display
.init_clock_gating
= nop_init_clock_gating
;
7225 /* Set up chip specific power management-related functions */
7226 void intel_init_pm(struct drm_device
*dev
)
7228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7230 intel_fbc_init(dev_priv
);
7233 if (IS_PINEVIEW(dev
))
7234 i915_pineview_get_mem_freq(dev
);
7235 else if (IS_GEN5(dev
))
7236 i915_ironlake_get_mem_freq(dev
);
7238 /* For FIFO watermark updates */
7239 if (INTEL_INFO(dev
)->gen
>= 9) {
7240 skl_setup_wm_latency(dev
);
7241 dev_priv
->display
.update_wm
= skl_update_wm
;
7242 } else if (HAS_PCH_SPLIT(dev
)) {
7243 ilk_setup_wm_latency(dev
);
7245 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
7246 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
7247 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
7248 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
7249 dev_priv
->display
.compute_pipe_wm
= ilk_compute_pipe_wm
;
7250 dev_priv
->display
.compute_intermediate_wm
=
7251 ilk_compute_intermediate_wm
;
7252 dev_priv
->display
.initial_watermarks
=
7253 ilk_initial_watermarks
;
7254 dev_priv
->display
.optimize_watermarks
=
7255 ilk_optimize_watermarks
;
7257 DRM_DEBUG_KMS("Failed to read display plane latency. "
7260 } else if (IS_CHERRYVIEW(dev
)) {
7261 vlv_setup_wm_latency(dev
);
7262 dev_priv
->display
.update_wm
= vlv_update_wm
;
7263 } else if (IS_VALLEYVIEW(dev
)) {
7264 vlv_setup_wm_latency(dev
);
7265 dev_priv
->display
.update_wm
= vlv_update_wm
;
7266 } else if (IS_PINEVIEW(dev
)) {
7267 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
7270 dev_priv
->mem_freq
)) {
7271 DRM_INFO("failed to find known CxSR latency "
7272 "(found ddr%s fsb freq %d, mem freq %d), "
7274 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
7275 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
7276 /* Disable CxSR and never update its watermark again */
7277 intel_set_memory_cxsr(dev_priv
, false);
7278 dev_priv
->display
.update_wm
= NULL
;
7280 dev_priv
->display
.update_wm
= pineview_update_wm
;
7281 } else if (IS_G4X(dev
)) {
7282 dev_priv
->display
.update_wm
= g4x_update_wm
;
7283 } else if (IS_GEN4(dev
)) {
7284 dev_priv
->display
.update_wm
= i965_update_wm
;
7285 } else if (IS_GEN3(dev
)) {
7286 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7287 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
7288 } else if (IS_GEN2(dev
)) {
7289 if (INTEL_INFO(dev
)->num_pipes
== 1) {
7290 dev_priv
->display
.update_wm
= i845_update_wm
;
7291 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
7293 dev_priv
->display
.update_wm
= i9xx_update_wm
;
7294 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
7297 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7301 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
)
7303 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7305 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7306 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7310 I915_WRITE(GEN6_PCODE_DATA
, *val
);
7311 I915_WRITE(GEN6_PCODE_DATA1
, 0);
7312 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7314 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7316 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
7320 *val
= I915_READ(GEN6_PCODE_DATA
);
7321 I915_WRITE(GEN6_PCODE_DATA
, 0);
7326 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
)
7328 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
7330 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
7331 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7335 I915_WRITE(GEN6_PCODE_DATA
, val
);
7336 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
7338 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
7340 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
7344 I915_WRITE(GEN6_PCODE_DATA
, 0);
7349 static int byt_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7353 * Slow = Fast = GPLL ref * N
7355 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* (val
- 0xb7), 1000);
7358 static int byt_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7360 return DIV_ROUND_CLOSEST(1000 * val
, dev_priv
->rps
.gpll_ref_freq
) + 0xb7;
7363 static int chv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7367 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7369 return DIV_ROUND_CLOSEST(dev_priv
->rps
.gpll_ref_freq
* val
, 2 * 2 * 1000);
7372 static int chv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7374 /* CHV needs even values */
7375 return DIV_ROUND_CLOSEST(2 * 1000 * val
, dev_priv
->rps
.gpll_ref_freq
) * 2;
7378 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
7380 if (IS_GEN9(dev_priv
))
7381 return DIV_ROUND_CLOSEST(val
* GT_FREQUENCY_MULTIPLIER
,
7383 else if (IS_CHERRYVIEW(dev_priv
))
7384 return chv_gpu_freq(dev_priv
, val
);
7385 else if (IS_VALLEYVIEW(dev_priv
))
7386 return byt_gpu_freq(dev_priv
, val
);
7388 return val
* GT_FREQUENCY_MULTIPLIER
;
7391 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
7393 if (IS_GEN9(dev_priv
))
7394 return DIV_ROUND_CLOSEST(val
* GEN9_FREQ_SCALER
,
7395 GT_FREQUENCY_MULTIPLIER
);
7396 else if (IS_CHERRYVIEW(dev_priv
))
7397 return chv_freq_opcode(dev_priv
, val
);
7398 else if (IS_VALLEYVIEW(dev_priv
))
7399 return byt_freq_opcode(dev_priv
, val
);
7401 return DIV_ROUND_CLOSEST(val
, GT_FREQUENCY_MULTIPLIER
);
7404 struct request_boost
{
7405 struct work_struct work
;
7406 struct drm_i915_gem_request
*req
;
7409 static void __intel_rps_boost_work(struct work_struct
*work
)
7411 struct request_boost
*boost
= container_of(work
, struct request_boost
, work
);
7412 struct drm_i915_gem_request
*req
= boost
->req
;
7414 if (!i915_gem_request_completed(req
, true))
7415 gen6_rps_boost(req
->i915
, NULL
, req
->emitted_jiffies
);
7417 i915_gem_request_unreference(req
);
7421 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request
*req
)
7423 struct request_boost
*boost
;
7425 if (req
== NULL
|| INTEL_GEN(req
->i915
) < 6)
7428 if (i915_gem_request_completed(req
, true))
7431 boost
= kmalloc(sizeof(*boost
), GFP_ATOMIC
);
7435 i915_gem_request_reference(req
);
7438 INIT_WORK(&boost
->work
, __intel_rps_boost_work
);
7439 queue_work(req
->i915
->wq
, &boost
->work
);
7442 void intel_pm_setup(struct drm_device
*dev
)
7444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7446 mutex_init(&dev_priv
->rps
.hw_lock
);
7447 spin_lock_init(&dev_priv
->rps
.client_lock
);
7449 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
7450 intel_gen6_powersave_work
);
7451 INIT_LIST_HEAD(&dev_priv
->rps
.clients
);
7452 INIT_LIST_HEAD(&dev_priv
->rps
.semaphores
.link
);
7453 INIT_LIST_HEAD(&dev_priv
->rps
.mmioflips
.link
);
7455 dev_priv
->pm
.suspended
= false;
7456 atomic_set(&dev_priv
->pm
.wakeref_count
, 0);
7457 atomic_set(&dev_priv
->pm
.atomic_seq
, 0);