2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
42 struct drm_i915_gem_object
*obj
;
43 volatile u32
*cpu_page
;
47 static inline int ring_space(struct intel_ring_buffer
*ring
)
49 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ 8);
55 static u32
i915_gem_get_seqno(struct drm_device
*dev
)
57 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
60 seqno
= dev_priv
->next_seqno
;
62 /* reserve 0 for non-seqno */
63 if (++dev_priv
->next_seqno
== 0)
64 dev_priv
->next_seqno
= 1;
70 render_ring_flush(struct intel_ring_buffer
*ring
,
71 u32 invalidate_domains
,
74 struct drm_device
*dev
= ring
->dev
;
81 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
82 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
83 * also flushed at 2d versus 3d pipeline switches.
87 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
88 * MI_READ_FLUSH is set, and is always flushed on 965.
90 * I915_GEM_DOMAIN_COMMAND may not exist?
92 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
93 * invalidated when MI_EXE_FLUSH is set.
95 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
96 * invalidated with every MI_FLUSH.
100 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
101 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
102 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
103 * are flushed at any MI_FLUSH.
106 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
107 if ((invalidate_domains
|flush_domains
) &
108 I915_GEM_DOMAIN_RENDER
)
109 cmd
&= ~MI_NO_WRITE_FLUSH
;
110 if (INTEL_INFO(dev
)->gen
< 4) {
112 * On the 965, the sampler cache always gets flushed
113 * and this bit is reserved.
115 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
116 cmd
|= MI_READ_FLUSH
;
118 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
121 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
122 (IS_G4X(dev
) || IS_GEN5(dev
)))
123 cmd
|= MI_INVALIDATE_ISP
;
125 ret
= intel_ring_begin(ring
, 2);
129 intel_ring_emit(ring
, cmd
);
130 intel_ring_emit(ring
, MI_NOOP
);
131 intel_ring_advance(ring
);
137 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
138 * implementing two workarounds on gen6. From section 1.4.7.1
139 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
141 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
142 * produced by non-pipelined state commands), software needs to first
143 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
147 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
149 * And the workaround for these two requires this workaround first:
151 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
152 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * And this last workaround is tricky because of the requirements on
156 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * "1 of the following must also be set:
160 * - Render Target Cache Flush Enable ([12] of DW1)
161 * - Depth Cache Flush Enable ([0] of DW1)
162 * - Stall at Pixel Scoreboard ([1] of DW1)
163 * - Depth Stall ([13] of DW1)
164 * - Post-Sync Operation ([13] of DW1)
165 * - Notify Enable ([8] of DW1)"
167 * The cache flushes require the workaround flush that triggered this
168 * one, so we can't use it. Depth stall would trigger the same.
169 * Post-sync nonzero is what triggered this second workaround, so we
170 * can't use that one either. Notify enable is IRQs, which aren't
171 * really our business. That leaves only stall at scoreboard.
174 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
176 struct pipe_control
*pc
= ring
->private;
177 u32 scratch_addr
= pc
->gtt_offset
+ 128;
181 ret
= intel_ring_begin(ring
, 6);
185 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
186 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
187 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
188 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
189 intel_ring_emit(ring
, 0); /* low dword */
190 intel_ring_emit(ring
, 0); /* high dword */
191 intel_ring_emit(ring
, MI_NOOP
);
192 intel_ring_advance(ring
);
194 ret
= intel_ring_begin(ring
, 6);
198 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
199 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
200 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
201 intel_ring_emit(ring
, 0);
202 intel_ring_emit(ring
, 0);
203 intel_ring_emit(ring
, MI_NOOP
);
204 intel_ring_advance(ring
);
210 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
211 u32 invalidate_domains
, u32 flush_domains
)
214 struct pipe_control
*pc
= ring
->private;
215 u32 scratch_addr
= pc
->gtt_offset
+ 128;
218 /* Force SNB workarounds for PIPE_CONTROL flushes */
219 intel_emit_post_sync_nonzero_flush(ring
);
221 /* Just flush everything. Experiments have shown that reducing the
222 * number of bits based on the write domains has little performance
225 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
226 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
227 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
228 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
229 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
230 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
231 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
233 ret
= intel_ring_begin(ring
, 6);
237 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
238 intel_ring_emit(ring
, flags
);
239 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
240 intel_ring_emit(ring
, 0); /* lower dword */
241 intel_ring_emit(ring
, 0); /* uppwer dword */
242 intel_ring_emit(ring
, MI_NOOP
);
243 intel_ring_advance(ring
);
248 static void ring_write_tail(struct intel_ring_buffer
*ring
,
251 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
252 I915_WRITE_TAIL(ring
, value
);
255 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
257 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
258 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
259 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
261 return I915_READ(acthd_reg
);
264 static int init_ring_common(struct intel_ring_buffer
*ring
)
266 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
267 struct drm_i915_gem_object
*obj
= ring
->obj
;
270 /* Stop the ring if it's running. */
271 I915_WRITE_CTL(ring
, 0);
272 I915_WRITE_HEAD(ring
, 0);
273 ring
->write_tail(ring
, 0);
275 /* Initialize the ring. */
276 I915_WRITE_START(ring
, obj
->gtt_offset
);
277 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
279 /* G45 ring initialization fails to reset head to zero */
281 DRM_DEBUG_KMS("%s head not reset to zero "
282 "ctl %08x head %08x tail %08x start %08x\n",
285 I915_READ_HEAD(ring
),
286 I915_READ_TAIL(ring
),
287 I915_READ_START(ring
));
289 I915_WRITE_HEAD(ring
, 0);
291 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
292 DRM_ERROR("failed to set %s head to zero "
293 "ctl %08x head %08x tail %08x start %08x\n",
296 I915_READ_HEAD(ring
),
297 I915_READ_TAIL(ring
),
298 I915_READ_START(ring
));
303 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
304 | RING_REPORT_64K
| RING_VALID
);
306 /* If the head is still not zero, the ring is dead */
307 if ((I915_READ_CTL(ring
) & RING_VALID
) == 0 ||
308 I915_READ_START(ring
) != obj
->gtt_offset
||
309 (I915_READ_HEAD(ring
) & HEAD_ADDR
) != 0) {
310 DRM_ERROR("%s initialization failed "
311 "ctl %08x head %08x tail %08x start %08x\n",
314 I915_READ_HEAD(ring
),
315 I915_READ_TAIL(ring
),
316 I915_READ_START(ring
));
320 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
321 i915_kernel_lost_context(ring
->dev
);
323 ring
->head
= I915_READ_HEAD(ring
);
324 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
325 ring
->space
= ring_space(ring
);
332 init_pipe_control(struct intel_ring_buffer
*ring
)
334 struct pipe_control
*pc
;
335 struct drm_i915_gem_object
*obj
;
341 pc
= kmalloc(sizeof(*pc
), GFP_KERNEL
);
345 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
347 DRM_ERROR("Failed to allocate seqno page\n");
352 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
354 ret
= i915_gem_object_pin(obj
, 4096, true);
358 pc
->gtt_offset
= obj
->gtt_offset
;
359 pc
->cpu_page
= kmap(obj
->pages
[0]);
360 if (pc
->cpu_page
== NULL
)
368 i915_gem_object_unpin(obj
);
370 drm_gem_object_unreference(&obj
->base
);
377 cleanup_pipe_control(struct intel_ring_buffer
*ring
)
379 struct pipe_control
*pc
= ring
->private;
380 struct drm_i915_gem_object
*obj
;
386 kunmap(obj
->pages
[0]);
387 i915_gem_object_unpin(obj
);
388 drm_gem_object_unreference(&obj
->base
);
391 ring
->private = NULL
;
394 static int init_render_ring(struct intel_ring_buffer
*ring
)
396 struct drm_device
*dev
= ring
->dev
;
397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
398 int ret
= init_ring_common(ring
);
400 if (INTEL_INFO(dev
)->gen
> 3) {
401 int mode
= VS_TIMER_DISPATCH
<< 16 | VS_TIMER_DISPATCH
;
402 I915_WRITE(MI_MODE
, mode
);
404 I915_WRITE(GFX_MODE_GEN7
,
405 GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
406 GFX_MODE_ENABLE(GFX_REPLAY_MODE
));
409 if (INTEL_INFO(dev
)->gen
>= 5) {
410 ret
= init_pipe_control(ring
);
415 if (INTEL_INFO(dev
)->gen
>= 6) {
417 INSTPM_FORCE_ORDERING
<< 16 | INSTPM_FORCE_ORDERING
);
423 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
428 cleanup_pipe_control(ring
);
432 update_mboxes(struct intel_ring_buffer
*ring
,
436 intel_ring_emit(ring
, MI_SEMAPHORE_MBOX
|
437 MI_SEMAPHORE_GLOBAL_GTT
|
438 MI_SEMAPHORE_REGISTER
|
439 MI_SEMAPHORE_UPDATE
);
440 intel_ring_emit(ring
, seqno
);
441 intel_ring_emit(ring
, mmio_offset
);
445 * gen6_add_request - Update the semaphore mailbox registers
447 * @ring - ring that is adding a request
448 * @seqno - return seqno stuck into the ring
450 * Update the mailbox registers in the *other* rings with the current seqno.
451 * This acts like a signal in the canonical semaphore.
454 gen6_add_request(struct intel_ring_buffer
*ring
,
461 ret
= intel_ring_begin(ring
, 10);
465 mbox1_reg
= ring
->signal_mbox
[0];
466 mbox2_reg
= ring
->signal_mbox
[1];
468 *seqno
= i915_gem_get_seqno(ring
->dev
);
470 update_mboxes(ring
, *seqno
, mbox1_reg
);
471 update_mboxes(ring
, *seqno
, mbox2_reg
);
472 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
473 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
474 intel_ring_emit(ring
, *seqno
);
475 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
476 intel_ring_advance(ring
);
482 * intel_ring_sync - sync the waiter to the signaller on seqno
484 * @waiter - ring that is waiting
485 * @signaller - ring which has, or will signal
486 * @seqno - seqno which the waiter will block on
489 intel_ring_sync(struct intel_ring_buffer
*waiter
,
490 struct intel_ring_buffer
*signaller
,
495 u32 dw1
= MI_SEMAPHORE_MBOX
|
496 MI_SEMAPHORE_COMPARE
|
497 MI_SEMAPHORE_REGISTER
;
499 ret
= intel_ring_begin(waiter
, 4);
503 intel_ring_emit(waiter
, dw1
| signaller
->semaphore_register
[ring
]);
504 intel_ring_emit(waiter
, seqno
);
505 intel_ring_emit(waiter
, 0);
506 intel_ring_emit(waiter
, MI_NOOP
);
507 intel_ring_advance(waiter
);
512 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
514 render_ring_sync_to(struct intel_ring_buffer
*waiter
,
515 struct intel_ring_buffer
*signaller
,
518 WARN_ON(signaller
->semaphore_register
[RCS
] == MI_SEMAPHORE_SYNC_INVALID
);
519 return intel_ring_sync(waiter
,
525 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
527 gen6_bsd_ring_sync_to(struct intel_ring_buffer
*waiter
,
528 struct intel_ring_buffer
*signaller
,
531 WARN_ON(signaller
->semaphore_register
[VCS
] == MI_SEMAPHORE_SYNC_INVALID
);
532 return intel_ring_sync(waiter
,
538 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
540 gen6_blt_ring_sync_to(struct intel_ring_buffer
*waiter
,
541 struct intel_ring_buffer
*signaller
,
544 WARN_ON(signaller
->semaphore_register
[BCS
] == MI_SEMAPHORE_SYNC_INVALID
);
545 return intel_ring_sync(waiter
,
553 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
555 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
556 PIPE_CONTROL_DEPTH_STALL); \
557 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
558 intel_ring_emit(ring__, 0); \
559 intel_ring_emit(ring__, 0); \
563 pc_render_add_request(struct intel_ring_buffer
*ring
,
566 struct drm_device
*dev
= ring
->dev
;
567 u32 seqno
= i915_gem_get_seqno(dev
);
568 struct pipe_control
*pc
= ring
->private;
569 u32 scratch_addr
= pc
->gtt_offset
+ 128;
572 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
573 * incoherent with writes to memory, i.e. completely fubar,
574 * so we need to use PIPE_NOTIFY instead.
576 * However, we also need to workaround the qword write
577 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
578 * memory before requesting an interrupt.
580 ret
= intel_ring_begin(ring
, 32);
584 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
585 PIPE_CONTROL_WRITE_FLUSH
|
586 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
587 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
588 intel_ring_emit(ring
, seqno
);
589 intel_ring_emit(ring
, 0);
590 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
591 scratch_addr
+= 128; /* write to separate cachelines */
592 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
594 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
596 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
598 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
600 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
601 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
602 PIPE_CONTROL_WRITE_FLUSH
|
603 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
604 PIPE_CONTROL_NOTIFY
);
605 intel_ring_emit(ring
, pc
->gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
606 intel_ring_emit(ring
, seqno
);
607 intel_ring_emit(ring
, 0);
608 intel_ring_advance(ring
);
615 render_ring_add_request(struct intel_ring_buffer
*ring
,
618 struct drm_device
*dev
= ring
->dev
;
619 u32 seqno
= i915_gem_get_seqno(dev
);
622 ret
= intel_ring_begin(ring
, 4);
626 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
627 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
628 intel_ring_emit(ring
, seqno
);
629 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
630 intel_ring_advance(ring
);
637 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
)
639 struct drm_device
*dev
= ring
->dev
;
641 /* Workaround to force correct ordering between irq and seqno writes on
642 * ivb (and maybe also on snb) by reading from a CS register (like
643 * ACTHD) before reading the status page. */
645 intel_ring_get_active_head(ring
);
646 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
650 ring_get_seqno(struct intel_ring_buffer
*ring
)
652 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
656 pc_render_get_seqno(struct intel_ring_buffer
*ring
)
658 struct pipe_control
*pc
= ring
->private;
659 return pc
->cpu_page
[0];
663 ironlake_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
665 dev_priv
->gt_irq_mask
&= ~mask
;
666 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
671 ironlake_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
673 dev_priv
->gt_irq_mask
|= mask
;
674 I915_WRITE(GTIMR
, dev_priv
->gt_irq_mask
);
679 i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
681 dev_priv
->irq_mask
&= ~mask
;
682 I915_WRITE(IMR
, dev_priv
->irq_mask
);
687 i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
)
689 dev_priv
->irq_mask
|= mask
;
690 I915_WRITE(IMR
, dev_priv
->irq_mask
);
695 render_ring_get_irq(struct intel_ring_buffer
*ring
)
697 struct drm_device
*dev
= ring
->dev
;
698 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
700 if (!dev
->irq_enabled
)
703 spin_lock(&ring
->irq_lock
);
704 if (ring
->irq_refcount
++ == 0) {
705 if (HAS_PCH_SPLIT(dev
))
706 ironlake_enable_irq(dev_priv
,
707 GT_PIPE_NOTIFY
| GT_USER_INTERRUPT
);
709 i915_enable_irq(dev_priv
, I915_USER_INTERRUPT
);
711 spin_unlock(&ring
->irq_lock
);
717 render_ring_put_irq(struct intel_ring_buffer
*ring
)
719 struct drm_device
*dev
= ring
->dev
;
720 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
722 spin_lock(&ring
->irq_lock
);
723 if (--ring
->irq_refcount
== 0) {
724 if (HAS_PCH_SPLIT(dev
))
725 ironlake_disable_irq(dev_priv
,
729 i915_disable_irq(dev_priv
, I915_USER_INTERRUPT
);
731 spin_unlock(&ring
->irq_lock
);
734 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
736 struct drm_device
*dev
= ring
->dev
;
737 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
740 /* The ring status page addresses are no longer next to the rest of
741 * the ring registers as of gen7.
746 mmio
= RENDER_HWS_PGA_GEN7
;
749 mmio
= BLT_HWS_PGA_GEN7
;
752 mmio
= BSD_HWS_PGA_GEN7
;
755 } else if (IS_GEN6(ring
->dev
)) {
756 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
758 mmio
= RING_HWS_PGA(ring
->mmio_base
);
761 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
766 bsd_ring_flush(struct intel_ring_buffer
*ring
,
767 u32 invalidate_domains
,
772 ret
= intel_ring_begin(ring
, 2);
776 intel_ring_emit(ring
, MI_FLUSH
);
777 intel_ring_emit(ring
, MI_NOOP
);
778 intel_ring_advance(ring
);
783 ring_add_request(struct intel_ring_buffer
*ring
,
789 ret
= intel_ring_begin(ring
, 4);
793 seqno
= i915_gem_get_seqno(ring
->dev
);
795 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
796 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
797 intel_ring_emit(ring
, seqno
);
798 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
799 intel_ring_advance(ring
);
806 gen6_ring_get_irq(struct intel_ring_buffer
*ring
, u32 gflag
, u32 rflag
)
808 struct drm_device
*dev
= ring
->dev
;
809 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
811 if (!dev
->irq_enabled
)
814 /* It looks like we need to prevent the gt from suspending while waiting
815 * for an notifiy irq, otherwise irqs seem to get lost on at least the
816 * blt/bsd rings on ivb. */
818 gen6_gt_force_wake_get(dev_priv
);
820 spin_lock(&ring
->irq_lock
);
821 if (ring
->irq_refcount
++ == 0) {
822 ring
->irq_mask
&= ~rflag
;
823 I915_WRITE_IMR(ring
, ring
->irq_mask
);
824 ironlake_enable_irq(dev_priv
, gflag
);
826 spin_unlock(&ring
->irq_lock
);
832 gen6_ring_put_irq(struct intel_ring_buffer
*ring
, u32 gflag
, u32 rflag
)
834 struct drm_device
*dev
= ring
->dev
;
835 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
837 spin_lock(&ring
->irq_lock
);
838 if (--ring
->irq_refcount
== 0) {
839 ring
->irq_mask
|= rflag
;
840 I915_WRITE_IMR(ring
, ring
->irq_mask
);
841 ironlake_disable_irq(dev_priv
, gflag
);
843 spin_unlock(&ring
->irq_lock
);
846 gen6_gt_force_wake_put(dev_priv
);
850 bsd_ring_get_irq(struct intel_ring_buffer
*ring
)
852 struct drm_device
*dev
= ring
->dev
;
853 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
855 if (!dev
->irq_enabled
)
858 spin_lock(&ring
->irq_lock
);
859 if (ring
->irq_refcount
++ == 0) {
861 i915_enable_irq(dev_priv
, I915_BSD_USER_INTERRUPT
);
863 ironlake_enable_irq(dev_priv
, GT_BSD_USER_INTERRUPT
);
865 spin_unlock(&ring
->irq_lock
);
870 bsd_ring_put_irq(struct intel_ring_buffer
*ring
)
872 struct drm_device
*dev
= ring
->dev
;
873 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
875 spin_lock(&ring
->irq_lock
);
876 if (--ring
->irq_refcount
== 0) {
878 i915_disable_irq(dev_priv
, I915_BSD_USER_INTERRUPT
);
880 ironlake_disable_irq(dev_priv
, GT_BSD_USER_INTERRUPT
);
882 spin_unlock(&ring
->irq_lock
);
886 ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
, u32 offset
, u32 length
)
890 ret
= intel_ring_begin(ring
, 2);
894 intel_ring_emit(ring
,
895 MI_BATCH_BUFFER_START
| (2 << 6) |
896 MI_BATCH_NON_SECURE_I965
);
897 intel_ring_emit(ring
, offset
);
898 intel_ring_advance(ring
);
904 render_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
907 struct drm_device
*dev
= ring
->dev
;
910 if (IS_I830(dev
) || IS_845G(dev
)) {
911 ret
= intel_ring_begin(ring
, 4);
915 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
916 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
917 intel_ring_emit(ring
, offset
+ len
- 8);
918 intel_ring_emit(ring
, 0);
920 ret
= intel_ring_begin(ring
, 2);
924 if (INTEL_INFO(dev
)->gen
>= 4) {
925 intel_ring_emit(ring
,
926 MI_BATCH_BUFFER_START
| (2 << 6) |
927 MI_BATCH_NON_SECURE_I965
);
928 intel_ring_emit(ring
, offset
);
930 intel_ring_emit(ring
,
931 MI_BATCH_BUFFER_START
| (2 << 6));
932 intel_ring_emit(ring
, offset
| MI_BATCH_NON_SECURE
);
935 intel_ring_advance(ring
);
940 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
942 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
943 struct drm_i915_gem_object
*obj
;
945 obj
= ring
->status_page
.obj
;
949 kunmap(obj
->pages
[0]);
950 i915_gem_object_unpin(obj
);
951 drm_gem_object_unreference(&obj
->base
);
952 ring
->status_page
.obj
= NULL
;
954 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
957 static int init_status_page(struct intel_ring_buffer
*ring
)
959 struct drm_device
*dev
= ring
->dev
;
960 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
961 struct drm_i915_gem_object
*obj
;
964 obj
= i915_gem_alloc_object(dev
, 4096);
966 DRM_ERROR("Failed to allocate status page\n");
971 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
973 ret
= i915_gem_object_pin(obj
, 4096, true);
978 ring
->status_page
.gfx_addr
= obj
->gtt_offset
;
979 ring
->status_page
.page_addr
= kmap(obj
->pages
[0]);
980 if (ring
->status_page
.page_addr
== NULL
) {
981 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
984 ring
->status_page
.obj
= obj
;
985 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
987 intel_ring_setup_status_page(ring
);
988 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
989 ring
->name
, ring
->status_page
.gfx_addr
);
994 i915_gem_object_unpin(obj
);
996 drm_gem_object_unreference(&obj
->base
);
1001 int intel_init_ring_buffer(struct drm_device
*dev
,
1002 struct intel_ring_buffer
*ring
)
1004 struct drm_i915_gem_object
*obj
;
1008 INIT_LIST_HEAD(&ring
->active_list
);
1009 INIT_LIST_HEAD(&ring
->request_list
);
1010 INIT_LIST_HEAD(&ring
->gpu_write_list
);
1012 init_waitqueue_head(&ring
->irq_queue
);
1013 spin_lock_init(&ring
->irq_lock
);
1014 ring
->irq_mask
= ~0;
1016 if (I915_NEED_GFX_HWS(dev
)) {
1017 ret
= init_status_page(ring
);
1022 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1024 DRM_ERROR("Failed to allocate ringbuffer\n");
1031 ret
= i915_gem_object_pin(obj
, PAGE_SIZE
, true);
1035 ring
->map
.size
= ring
->size
;
1036 ring
->map
.offset
= dev
->agp
->base
+ obj
->gtt_offset
;
1038 ring
->map
.flags
= 0;
1041 drm_core_ioremap_wc(&ring
->map
, dev
);
1042 if (ring
->map
.handle
== NULL
) {
1043 DRM_ERROR("Failed to map ringbuffer.\n");
1048 ring
->virtual_start
= ring
->map
.handle
;
1049 ret
= ring
->init(ring
);
1053 /* Workaround an erratum on the i830 which causes a hang if
1054 * the TAIL pointer points to within the last 2 cachelines
1057 ring
->effective_size
= ring
->size
;
1058 if (IS_I830(ring
->dev
))
1059 ring
->effective_size
-= 128;
1064 drm_core_ioremapfree(&ring
->map
, dev
);
1066 i915_gem_object_unpin(obj
);
1068 drm_gem_object_unreference(&obj
->base
);
1071 cleanup_status_page(ring
);
1075 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1077 struct drm_i915_private
*dev_priv
;
1080 if (ring
->obj
== NULL
)
1083 /* Disable the ring buffer. The ring must be idle at this point */
1084 dev_priv
= ring
->dev
->dev_private
;
1085 ret
= intel_wait_ring_idle(ring
);
1087 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1090 I915_WRITE_CTL(ring
, 0);
1092 drm_core_ioremapfree(&ring
->map
, ring
->dev
);
1094 i915_gem_object_unpin(ring
->obj
);
1095 drm_gem_object_unreference(&ring
->obj
->base
);
1099 ring
->cleanup(ring
);
1101 cleanup_status_page(ring
);
1104 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1107 int rem
= ring
->size
- ring
->tail
;
1109 if (ring
->space
< rem
) {
1110 int ret
= intel_wait_ring_buffer(ring
, rem
);
1115 virt
= (unsigned int *)(ring
->virtual_start
+ ring
->tail
);
1123 ring
->space
= ring_space(ring
);
1128 int intel_wait_ring_buffer(struct intel_ring_buffer
*ring
, int n
)
1130 struct drm_device
*dev
= ring
->dev
;
1131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1135 /* If the reported head position has wrapped or hasn't advanced,
1136 * fallback to the slow and accurate path.
1138 head
= intel_read_status_page(ring
, 4);
1139 if (head
> ring
->head
) {
1141 ring
->space
= ring_space(ring
);
1142 if (ring
->space
>= n
)
1146 trace_i915_ring_wait_begin(ring
);
1147 if (drm_core_check_feature(dev
, DRIVER_GEM
))
1148 /* With GEM the hangcheck timer should kick us out of the loop,
1149 * leaving it early runs the risk of corrupting GEM state (due
1150 * to running on almost untested codepaths). But on resume
1151 * timers don't work yet, so prevent a complete hang in that
1152 * case by choosing an insanely large timeout. */
1153 end
= jiffies
+ 60 * HZ
;
1155 end
= jiffies
+ 3 * HZ
;
1158 ring
->head
= I915_READ_HEAD(ring
);
1159 ring
->space
= ring_space(ring
);
1160 if (ring
->space
>= n
) {
1161 trace_i915_ring_wait_end(ring
);
1165 if (dev
->primary
->master
) {
1166 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1167 if (master_priv
->sarea_priv
)
1168 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1172 if (atomic_read(&dev_priv
->mm
.wedged
))
1174 } while (!time_after(jiffies
, end
));
1175 trace_i915_ring_wait_end(ring
);
1179 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1182 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1183 int n
= 4*num_dwords
;
1186 if (unlikely(atomic_read(&dev_priv
->mm
.wedged
)))
1189 if (unlikely(ring
->tail
+ n
> ring
->effective_size
)) {
1190 ret
= intel_wrap_ring_buffer(ring
);
1195 if (unlikely(ring
->space
< n
)) {
1196 ret
= intel_wait_ring_buffer(ring
, n
);
1205 void intel_ring_advance(struct intel_ring_buffer
*ring
)
1207 ring
->tail
&= ring
->size
- 1;
1208 ring
->write_tail(ring
, ring
->tail
);
1211 static const struct intel_ring_buffer render_ring
= {
1212 .name
= "render ring",
1214 .mmio_base
= RENDER_RING_BASE
,
1215 .size
= 32 * PAGE_SIZE
,
1216 .init
= init_render_ring
,
1217 .write_tail
= ring_write_tail
,
1218 .flush
= render_ring_flush
,
1219 .add_request
= render_ring_add_request
,
1220 .get_seqno
= ring_get_seqno
,
1221 .irq_get
= render_ring_get_irq
,
1222 .irq_put
= render_ring_put_irq
,
1223 .dispatch_execbuffer
= render_ring_dispatch_execbuffer
,
1224 .cleanup
= render_ring_cleanup
,
1225 .sync_to
= render_ring_sync_to
,
1226 .semaphore_register
= {MI_SEMAPHORE_SYNC_INVALID
,
1227 MI_SEMAPHORE_SYNC_RV
,
1228 MI_SEMAPHORE_SYNC_RB
},
1229 .signal_mbox
= {GEN6_VRSYNC
, GEN6_BRSYNC
},
1232 /* ring buffer for bit-stream decoder */
1234 static const struct intel_ring_buffer bsd_ring
= {
1237 .mmio_base
= BSD_RING_BASE
,
1238 .size
= 32 * PAGE_SIZE
,
1239 .init
= init_ring_common
,
1240 .write_tail
= ring_write_tail
,
1241 .flush
= bsd_ring_flush
,
1242 .add_request
= ring_add_request
,
1243 .get_seqno
= ring_get_seqno
,
1244 .irq_get
= bsd_ring_get_irq
,
1245 .irq_put
= bsd_ring_put_irq
,
1246 .dispatch_execbuffer
= ring_dispatch_execbuffer
,
1250 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1253 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1255 /* Every tail move must follow the sequence below */
1256 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1257 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
1258 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE
);
1259 I915_WRITE(GEN6_BSD_RNCID
, 0x0);
1261 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1262 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR
) == 0,
1264 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1266 I915_WRITE_TAIL(ring
, value
);
1267 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1268 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK
|
1269 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE
);
1272 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1273 u32 invalidate
, u32 flush
)
1278 ret
= intel_ring_begin(ring
, 4);
1283 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1284 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
1285 intel_ring_emit(ring
, cmd
);
1286 intel_ring_emit(ring
, 0);
1287 intel_ring_emit(ring
, 0);
1288 intel_ring_emit(ring
, MI_NOOP
);
1289 intel_ring_advance(ring
);
1294 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1295 u32 offset
, u32 len
)
1299 ret
= intel_ring_begin(ring
, 2);
1303 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_NON_SECURE_I965
);
1304 /* bit0-7 is the length on GEN6+ */
1305 intel_ring_emit(ring
, offset
);
1306 intel_ring_advance(ring
);
1312 gen6_render_ring_get_irq(struct intel_ring_buffer
*ring
)
1314 return gen6_ring_get_irq(ring
,
1316 GEN6_RENDER_USER_INTERRUPT
);
1320 gen6_render_ring_put_irq(struct intel_ring_buffer
*ring
)
1322 return gen6_ring_put_irq(ring
,
1324 GEN6_RENDER_USER_INTERRUPT
);
1328 gen6_bsd_ring_get_irq(struct intel_ring_buffer
*ring
)
1330 return gen6_ring_get_irq(ring
,
1331 GT_GEN6_BSD_USER_INTERRUPT
,
1332 GEN6_BSD_USER_INTERRUPT
);
1336 gen6_bsd_ring_put_irq(struct intel_ring_buffer
*ring
)
1338 return gen6_ring_put_irq(ring
,
1339 GT_GEN6_BSD_USER_INTERRUPT
,
1340 GEN6_BSD_USER_INTERRUPT
);
1343 /* ring buffer for Video Codec for Gen6+ */
1344 static const struct intel_ring_buffer gen6_bsd_ring
= {
1345 .name
= "gen6 bsd ring",
1347 .mmio_base
= GEN6_BSD_RING_BASE
,
1348 .size
= 32 * PAGE_SIZE
,
1349 .init
= init_ring_common
,
1350 .write_tail
= gen6_bsd_ring_write_tail
,
1351 .flush
= gen6_ring_flush
,
1352 .add_request
= gen6_add_request
,
1353 .get_seqno
= gen6_ring_get_seqno
,
1354 .irq_get
= gen6_bsd_ring_get_irq
,
1355 .irq_put
= gen6_bsd_ring_put_irq
,
1356 .dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
,
1357 .sync_to
= gen6_bsd_ring_sync_to
,
1358 .semaphore_register
= {MI_SEMAPHORE_SYNC_VR
,
1359 MI_SEMAPHORE_SYNC_INVALID
,
1360 MI_SEMAPHORE_SYNC_VB
},
1361 .signal_mbox
= {GEN6_RVSYNC
, GEN6_BVSYNC
},
1364 /* Blitter support (SandyBridge+) */
1367 blt_ring_get_irq(struct intel_ring_buffer
*ring
)
1369 return gen6_ring_get_irq(ring
,
1370 GT_BLT_USER_INTERRUPT
,
1371 GEN6_BLITTER_USER_INTERRUPT
);
1375 blt_ring_put_irq(struct intel_ring_buffer
*ring
)
1377 gen6_ring_put_irq(ring
,
1378 GT_BLT_USER_INTERRUPT
,
1379 GEN6_BLITTER_USER_INTERRUPT
);
1382 static int blt_ring_flush(struct intel_ring_buffer
*ring
,
1383 u32 invalidate
, u32 flush
)
1388 ret
= intel_ring_begin(ring
, 4);
1393 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1394 cmd
|= MI_INVALIDATE_TLB
;
1395 intel_ring_emit(ring
, cmd
);
1396 intel_ring_emit(ring
, 0);
1397 intel_ring_emit(ring
, 0);
1398 intel_ring_emit(ring
, MI_NOOP
);
1399 intel_ring_advance(ring
);
1403 static const struct intel_ring_buffer gen6_blt_ring
= {
1406 .mmio_base
= BLT_RING_BASE
,
1407 .size
= 32 * PAGE_SIZE
,
1408 .init
= init_ring_common
,
1409 .write_tail
= ring_write_tail
,
1410 .flush
= blt_ring_flush
,
1411 .add_request
= gen6_add_request
,
1412 .get_seqno
= gen6_ring_get_seqno
,
1413 .irq_get
= blt_ring_get_irq
,
1414 .irq_put
= blt_ring_put_irq
,
1415 .dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
,
1416 .sync_to
= gen6_blt_ring_sync_to
,
1417 .semaphore_register
= {MI_SEMAPHORE_SYNC_BR
,
1418 MI_SEMAPHORE_SYNC_BV
,
1419 MI_SEMAPHORE_SYNC_INVALID
},
1420 .signal_mbox
= {GEN6_RBSYNC
, GEN6_VBSYNC
},
1423 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1425 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1426 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1428 *ring
= render_ring
;
1429 if (INTEL_INFO(dev
)->gen
>= 6) {
1430 ring
->add_request
= gen6_add_request
;
1431 ring
->flush
= gen6_render_ring_flush
;
1432 ring
->irq_get
= gen6_render_ring_get_irq
;
1433 ring
->irq_put
= gen6_render_ring_put_irq
;
1434 ring
->get_seqno
= gen6_ring_get_seqno
;
1435 } else if (IS_GEN5(dev
)) {
1436 ring
->add_request
= pc_render_add_request
;
1437 ring
->get_seqno
= pc_render_get_seqno
;
1440 if (!I915_NEED_GFX_HWS(dev
)) {
1441 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1442 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1445 return intel_init_ring_buffer(dev
, ring
);
1448 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1450 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1451 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1453 *ring
= render_ring
;
1454 if (INTEL_INFO(dev
)->gen
>= 6) {
1455 ring
->add_request
= gen6_add_request
;
1456 ring
->irq_get
= gen6_render_ring_get_irq
;
1457 ring
->irq_put
= gen6_render_ring_put_irq
;
1458 } else if (IS_GEN5(dev
)) {
1459 ring
->add_request
= pc_render_add_request
;
1460 ring
->get_seqno
= pc_render_get_seqno
;
1463 if (!I915_NEED_GFX_HWS(dev
))
1464 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1467 INIT_LIST_HEAD(&ring
->active_list
);
1468 INIT_LIST_HEAD(&ring
->request_list
);
1469 INIT_LIST_HEAD(&ring
->gpu_write_list
);
1472 ring
->effective_size
= ring
->size
;
1473 if (IS_I830(ring
->dev
))
1474 ring
->effective_size
-= 128;
1476 ring
->map
.offset
= start
;
1477 ring
->map
.size
= size
;
1479 ring
->map
.flags
= 0;
1482 drm_core_ioremap_wc(&ring
->map
, dev
);
1483 if (ring
->map
.handle
== NULL
) {
1484 DRM_ERROR("can not ioremap virtual address for"
1489 ring
->virtual_start
= (void __force __iomem
*)ring
->map
.handle
;
1493 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
1495 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1496 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
1498 if (IS_GEN6(dev
) || IS_GEN7(dev
))
1499 *ring
= gen6_bsd_ring
;
1503 return intel_init_ring_buffer(dev
, ring
);
1506 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
1508 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1509 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
1511 *ring
= gen6_blt_ring
;
1513 return intel_init_ring_buffer(dev
, ring
);