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drm/i915: Rename local struct intel_engine_cs variables
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <linux/log2.h>
31 #include <drm/drmP.h>
32 #include "i915_drv.h"
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 int __intel_ring_space(int head, int tail, int size)
38 {
39 int space = head - tail;
40 if (space <= 0)
41 space += size;
42 return space - I915_RING_FREE_SPACE;
43 }
44
45 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
46 {
47 if (ringbuf->last_retired_head != -1) {
48 ringbuf->head = ringbuf->last_retired_head;
49 ringbuf->last_retired_head = -1;
50 }
51
52 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
53 ringbuf->tail, ringbuf->size);
54 }
55
56 int intel_ring_space(struct intel_ringbuffer *ringbuf)
57 {
58 intel_ring_update_space(ringbuf);
59 return ringbuf->space;
60 }
61
62 bool intel_ring_stopped(struct intel_engine_cs *ring)
63 {
64 struct drm_i915_private *dev_priv = ring->dev->dev_private;
65 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
66 }
67
68 static void __intel_ring_advance(struct intel_engine_cs *ring)
69 {
70 struct intel_ringbuffer *ringbuf = ring->buffer;
71 ringbuf->tail &= ringbuf->size - 1;
72 if (intel_ring_stopped(ring))
73 return;
74 ring->write_tail(ring, ringbuf->tail);
75 }
76
77 static int
78 gen2_render_ring_flush(struct drm_i915_gem_request *req,
79 u32 invalidate_domains,
80 u32 flush_domains)
81 {
82 struct intel_engine_cs *engine = req->ring;
83 u32 cmd;
84 int ret;
85
86 cmd = MI_FLUSH;
87 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
88 cmd |= MI_NO_WRITE_FLUSH;
89
90 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
91 cmd |= MI_READ_FLUSH;
92
93 ret = intel_ring_begin(req, 2);
94 if (ret)
95 return ret;
96
97 intel_ring_emit(engine, cmd);
98 intel_ring_emit(engine, MI_NOOP);
99 intel_ring_advance(engine);
100
101 return 0;
102 }
103
104 static int
105 gen4_render_ring_flush(struct drm_i915_gem_request *req,
106 u32 invalidate_domains,
107 u32 flush_domains)
108 {
109 struct intel_engine_cs *engine = req->ring;
110 struct drm_device *dev = engine->dev;
111 u32 cmd;
112 int ret;
113
114 /*
115 * read/write caches:
116 *
117 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
118 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
119 * also flushed at 2d versus 3d pipeline switches.
120 *
121 * read-only caches:
122 *
123 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
124 * MI_READ_FLUSH is set, and is always flushed on 965.
125 *
126 * I915_GEM_DOMAIN_COMMAND may not exist?
127 *
128 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
129 * invalidated when MI_EXE_FLUSH is set.
130 *
131 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
132 * invalidated with every MI_FLUSH.
133 *
134 * TLBs:
135 *
136 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
137 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
138 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
139 * are flushed at any MI_FLUSH.
140 */
141
142 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
143 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
144 cmd &= ~MI_NO_WRITE_FLUSH;
145 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
146 cmd |= MI_EXE_FLUSH;
147
148 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
149 (IS_G4X(dev) || IS_GEN5(dev)))
150 cmd |= MI_INVALIDATE_ISP;
151
152 ret = intel_ring_begin(req, 2);
153 if (ret)
154 return ret;
155
156 intel_ring_emit(engine, cmd);
157 intel_ring_emit(engine, MI_NOOP);
158 intel_ring_advance(engine);
159
160 return 0;
161 }
162
163 /**
164 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
165 * implementing two workarounds on gen6. From section 1.4.7.1
166 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
167 *
168 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
169 * produced by non-pipelined state commands), software needs to first
170 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
171 * 0.
172 *
173 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
174 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
175 *
176 * And the workaround for these two requires this workaround first:
177 *
178 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
179 * BEFORE the pipe-control with a post-sync op and no write-cache
180 * flushes.
181 *
182 * And this last workaround is tricky because of the requirements on
183 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
184 * volume 2 part 1:
185 *
186 * "1 of the following must also be set:
187 * - Render Target Cache Flush Enable ([12] of DW1)
188 * - Depth Cache Flush Enable ([0] of DW1)
189 * - Stall at Pixel Scoreboard ([1] of DW1)
190 * - Depth Stall ([13] of DW1)
191 * - Post-Sync Operation ([13] of DW1)
192 * - Notify Enable ([8] of DW1)"
193 *
194 * The cache flushes require the workaround flush that triggered this
195 * one, so we can't use it. Depth stall would trigger the same.
196 * Post-sync nonzero is what triggered this second workaround, so we
197 * can't use that one either. Notify enable is IRQs, which aren't
198 * really our business. That leaves only stall at scoreboard.
199 */
200 static int
201 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
202 {
203 struct intel_engine_cs *engine = req->ring;
204 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
205 int ret;
206
207 ret = intel_ring_begin(req, 6);
208 if (ret)
209 return ret;
210
211 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
212 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
213 PIPE_CONTROL_STALL_AT_SCOREBOARD);
214 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
215 intel_ring_emit(engine, 0); /* low dword */
216 intel_ring_emit(engine, 0); /* high dword */
217 intel_ring_emit(engine, MI_NOOP);
218 intel_ring_advance(engine);
219
220 ret = intel_ring_begin(req, 6);
221 if (ret)
222 return ret;
223
224 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
225 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
226 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
227 intel_ring_emit(engine, 0);
228 intel_ring_emit(engine, 0);
229 intel_ring_emit(engine, MI_NOOP);
230 intel_ring_advance(engine);
231
232 return 0;
233 }
234
235 static int
236 gen6_render_ring_flush(struct drm_i915_gem_request *req,
237 u32 invalidate_domains, u32 flush_domains)
238 {
239 struct intel_engine_cs *engine = req->ring;
240 u32 flags = 0;
241 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
242 int ret;
243
244 /* Force SNB workarounds for PIPE_CONTROL flushes */
245 ret = intel_emit_post_sync_nonzero_flush(req);
246 if (ret)
247 return ret;
248
249 /* Just flush everything. Experiments have shown that reducing the
250 * number of bits based on the write domains has little performance
251 * impact.
252 */
253 if (flush_domains) {
254 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
255 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
256 /*
257 * Ensure that any following seqno writes only happen
258 * when the render cache is indeed flushed.
259 */
260 flags |= PIPE_CONTROL_CS_STALL;
261 }
262 if (invalidate_domains) {
263 flags |= PIPE_CONTROL_TLB_INVALIDATE;
264 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
269 /*
270 * TLB invalidate requires a post-sync write.
271 */
272 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
273 }
274
275 ret = intel_ring_begin(req, 4);
276 if (ret)
277 return ret;
278
279 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
280 intel_ring_emit(engine, flags);
281 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
282 intel_ring_emit(engine, 0);
283 intel_ring_advance(engine);
284
285 return 0;
286 }
287
288 static int
289 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
290 {
291 struct intel_engine_cs *engine = req->ring;
292 int ret;
293
294 ret = intel_ring_begin(req, 4);
295 if (ret)
296 return ret;
297
298 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
299 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
300 PIPE_CONTROL_STALL_AT_SCOREBOARD);
301 intel_ring_emit(engine, 0);
302 intel_ring_emit(engine, 0);
303 intel_ring_advance(engine);
304
305 return 0;
306 }
307
308 static int
309 gen7_render_ring_flush(struct drm_i915_gem_request *req,
310 u32 invalidate_domains, u32 flush_domains)
311 {
312 struct intel_engine_cs *engine = req->ring;
313 u32 flags = 0;
314 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
315 int ret;
316
317 /*
318 * Ensure that any following seqno writes only happen when the render
319 * cache is indeed flushed.
320 *
321 * Workaround: 4th PIPE_CONTROL command (except the ones with only
322 * read-cache invalidate bits set) must have the CS_STALL bit set. We
323 * don't try to be clever and just set it unconditionally.
324 */
325 flags |= PIPE_CONTROL_CS_STALL;
326
327 /* Just flush everything. Experiments have shown that reducing the
328 * number of bits based on the write domains has little performance
329 * impact.
330 */
331 if (flush_domains) {
332 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
333 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
334 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
335 flags |= PIPE_CONTROL_FLUSH_ENABLE;
336 }
337 if (invalidate_domains) {
338 flags |= PIPE_CONTROL_TLB_INVALIDATE;
339 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
342 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
343 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
344 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
345 /*
346 * TLB invalidate requires a post-sync write.
347 */
348 flags |= PIPE_CONTROL_QW_WRITE;
349 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
350
351 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
352
353 /* Workaround: we must issue a pipe_control with CS-stall bit
354 * set before a pipe_control command that has the state cache
355 * invalidate bit set. */
356 gen7_render_ring_cs_stall_wa(req);
357 }
358
359 ret = intel_ring_begin(req, 4);
360 if (ret)
361 return ret;
362
363 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
364 intel_ring_emit(engine, flags);
365 intel_ring_emit(engine, scratch_addr);
366 intel_ring_emit(engine, 0);
367 intel_ring_advance(engine);
368
369 return 0;
370 }
371
372 static int
373 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
374 u32 flags, u32 scratch_addr)
375 {
376 struct intel_engine_cs *engine = req->ring;
377 int ret;
378
379 ret = intel_ring_begin(req, 6);
380 if (ret)
381 return ret;
382
383 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
384 intel_ring_emit(engine, flags);
385 intel_ring_emit(engine, scratch_addr);
386 intel_ring_emit(engine, 0);
387 intel_ring_emit(engine, 0);
388 intel_ring_emit(engine, 0);
389 intel_ring_advance(engine);
390
391 return 0;
392 }
393
394 static int
395 gen8_render_ring_flush(struct drm_i915_gem_request *req,
396 u32 invalidate_domains, u32 flush_domains)
397 {
398 u32 flags = 0;
399 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
400 int ret;
401
402 flags |= PIPE_CONTROL_CS_STALL;
403
404 if (flush_domains) {
405 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
406 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
407 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
408 flags |= PIPE_CONTROL_FLUSH_ENABLE;
409 }
410 if (invalidate_domains) {
411 flags |= PIPE_CONTROL_TLB_INVALIDATE;
412 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
416 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
417 flags |= PIPE_CONTROL_QW_WRITE;
418 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
419
420 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
421 ret = gen8_emit_pipe_control(req,
422 PIPE_CONTROL_CS_STALL |
423 PIPE_CONTROL_STALL_AT_SCOREBOARD,
424 0);
425 if (ret)
426 return ret;
427 }
428
429 return gen8_emit_pipe_control(req, flags, scratch_addr);
430 }
431
432 static void ring_write_tail(struct intel_engine_cs *ring,
433 u32 value)
434 {
435 struct drm_i915_private *dev_priv = ring->dev->dev_private;
436 I915_WRITE_TAIL(ring, value);
437 }
438
439 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
440 {
441 struct drm_i915_private *dev_priv = ring->dev->dev_private;
442 u64 acthd;
443
444 if (INTEL_INFO(ring->dev)->gen >= 8)
445 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
446 RING_ACTHD_UDW(ring->mmio_base));
447 else if (INTEL_INFO(ring->dev)->gen >= 4)
448 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
449 else
450 acthd = I915_READ(ACTHD);
451
452 return acthd;
453 }
454
455 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
456 {
457 struct drm_i915_private *dev_priv = ring->dev->dev_private;
458 u32 addr;
459
460 addr = dev_priv->status_page_dmah->busaddr;
461 if (INTEL_INFO(ring->dev)->gen >= 4)
462 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
463 I915_WRITE(HWS_PGA, addr);
464 }
465
466 static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
467 {
468 struct drm_device *dev = ring->dev;
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 i915_reg_t mmio;
471
472 /* The ring status page addresses are no longer next to the rest of
473 * the ring registers as of gen7.
474 */
475 if (IS_GEN7(dev)) {
476 switch (ring->id) {
477 case RCS:
478 mmio = RENDER_HWS_PGA_GEN7;
479 break;
480 case BCS:
481 mmio = BLT_HWS_PGA_GEN7;
482 break;
483 /*
484 * VCS2 actually doesn't exist on Gen7. Only shut up
485 * gcc switch check warning
486 */
487 case VCS2:
488 case VCS:
489 mmio = BSD_HWS_PGA_GEN7;
490 break;
491 case VECS:
492 mmio = VEBOX_HWS_PGA_GEN7;
493 break;
494 }
495 } else if (IS_GEN6(ring->dev)) {
496 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
497 } else {
498 /* XXX: gen8 returns to sanity */
499 mmio = RING_HWS_PGA(ring->mmio_base);
500 }
501
502 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
503 POSTING_READ(mmio);
504
505 /*
506 * Flush the TLB for this page
507 *
508 * FIXME: These two bits have disappeared on gen8, so a question
509 * arises: do we still need this and if so how should we go about
510 * invalidating the TLB?
511 */
512 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
513 i915_reg_t reg = RING_INSTPM(ring->mmio_base);
514
515 /* ring should be idle before issuing a sync flush*/
516 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
517
518 I915_WRITE(reg,
519 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
520 INSTPM_SYNC_FLUSH));
521 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
522 1000))
523 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
524 ring->name);
525 }
526 }
527
528 static bool stop_ring(struct intel_engine_cs *ring)
529 {
530 struct drm_i915_private *dev_priv = to_i915(ring->dev);
531
532 if (!IS_GEN2(ring->dev)) {
533 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
534 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
535 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
536 /* Sometimes we observe that the idle flag is not
537 * set even though the ring is empty. So double
538 * check before giving up.
539 */
540 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
541 return false;
542 }
543 }
544
545 I915_WRITE_CTL(ring, 0);
546 I915_WRITE_HEAD(ring, 0);
547 ring->write_tail(ring, 0);
548
549 if (!IS_GEN2(ring->dev)) {
550 (void)I915_READ_CTL(ring);
551 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
552 }
553
554 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
555 }
556
557 static int init_ring_common(struct intel_engine_cs *ring)
558 {
559 struct drm_device *dev = ring->dev;
560 struct drm_i915_private *dev_priv = dev->dev_private;
561 struct intel_ringbuffer *ringbuf = ring->buffer;
562 struct drm_i915_gem_object *obj = ringbuf->obj;
563 int ret = 0;
564
565 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
566
567 if (!stop_ring(ring)) {
568 /* G45 ring initialization often fails to reset head to zero */
569 DRM_DEBUG_KMS("%s head not reset to zero "
570 "ctl %08x head %08x tail %08x start %08x\n",
571 ring->name,
572 I915_READ_CTL(ring),
573 I915_READ_HEAD(ring),
574 I915_READ_TAIL(ring),
575 I915_READ_START(ring));
576
577 if (!stop_ring(ring)) {
578 DRM_ERROR("failed to set %s head to zero "
579 "ctl %08x head %08x tail %08x start %08x\n",
580 ring->name,
581 I915_READ_CTL(ring),
582 I915_READ_HEAD(ring),
583 I915_READ_TAIL(ring),
584 I915_READ_START(ring));
585 ret = -EIO;
586 goto out;
587 }
588 }
589
590 if (I915_NEED_GFX_HWS(dev))
591 intel_ring_setup_status_page(ring);
592 else
593 ring_setup_phys_status_page(ring);
594
595 /* Enforce ordering by reading HEAD register back */
596 I915_READ_HEAD(ring);
597
598 /* Initialize the ring. This must happen _after_ we've cleared the ring
599 * registers with the above sequence (the readback of the HEAD registers
600 * also enforces ordering), otherwise the hw might lose the new ring
601 * register values. */
602 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
603
604 /* WaClearRingBufHeadRegAtInit:ctg,elk */
605 if (I915_READ_HEAD(ring))
606 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
607 ring->name, I915_READ_HEAD(ring));
608 I915_WRITE_HEAD(ring, 0);
609 (void)I915_READ_HEAD(ring);
610
611 I915_WRITE_CTL(ring,
612 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
613 | RING_VALID);
614
615 /* If the head is still not zero, the ring is dead */
616 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
617 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
618 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
619 DRM_ERROR("%s initialization failed "
620 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
621 ring->name,
622 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
623 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
624 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
625 ret = -EIO;
626 goto out;
627 }
628
629 ringbuf->last_retired_head = -1;
630 ringbuf->head = I915_READ_HEAD(ring);
631 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
632 intel_ring_update_space(ringbuf);
633
634 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
635
636 out:
637 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
638
639 return ret;
640 }
641
642 void
643 intel_fini_pipe_control(struct intel_engine_cs *ring)
644 {
645 struct drm_device *dev = ring->dev;
646
647 if (ring->scratch.obj == NULL)
648 return;
649
650 if (INTEL_INFO(dev)->gen >= 5) {
651 kunmap(sg_page(ring->scratch.obj->pages->sgl));
652 i915_gem_object_ggtt_unpin(ring->scratch.obj);
653 }
654
655 drm_gem_object_unreference(&ring->scratch.obj->base);
656 ring->scratch.obj = NULL;
657 }
658
659 int
660 intel_init_pipe_control(struct intel_engine_cs *ring)
661 {
662 int ret;
663
664 WARN_ON(ring->scratch.obj);
665
666 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
667 if (ring->scratch.obj == NULL) {
668 DRM_ERROR("Failed to allocate seqno page\n");
669 ret = -ENOMEM;
670 goto err;
671 }
672
673 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
674 if (ret)
675 goto err_unref;
676
677 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
678 if (ret)
679 goto err_unref;
680
681 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
682 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
683 if (ring->scratch.cpu_page == NULL) {
684 ret = -ENOMEM;
685 goto err_unpin;
686 }
687
688 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
689 ring->name, ring->scratch.gtt_offset);
690 return 0;
691
692 err_unpin:
693 i915_gem_object_ggtt_unpin(ring->scratch.obj);
694 err_unref:
695 drm_gem_object_unreference(&ring->scratch.obj->base);
696 err:
697 return ret;
698 }
699
700 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
701 {
702 int ret, i;
703 struct intel_engine_cs *engine = req->ring;
704 struct drm_device *dev = engine->dev;
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 struct i915_workarounds *w = &dev_priv->workarounds;
707
708 if (w->count == 0)
709 return 0;
710
711 engine->gpu_caches_dirty = true;
712 ret = intel_ring_flush_all_caches(req);
713 if (ret)
714 return ret;
715
716 ret = intel_ring_begin(req, (w->count * 2 + 2));
717 if (ret)
718 return ret;
719
720 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
721 for (i = 0; i < w->count; i++) {
722 intel_ring_emit_reg(engine, w->reg[i].addr);
723 intel_ring_emit(engine, w->reg[i].value);
724 }
725 intel_ring_emit(engine, MI_NOOP);
726
727 intel_ring_advance(engine);
728
729 engine->gpu_caches_dirty = true;
730 ret = intel_ring_flush_all_caches(req);
731 if (ret)
732 return ret;
733
734 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
735
736 return 0;
737 }
738
739 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
740 {
741 int ret;
742
743 ret = intel_ring_workarounds_emit(req);
744 if (ret != 0)
745 return ret;
746
747 ret = i915_gem_render_state_init(req);
748 if (ret)
749 return ret;
750
751 return 0;
752 }
753
754 static int wa_add(struct drm_i915_private *dev_priv,
755 i915_reg_t addr,
756 const u32 mask, const u32 val)
757 {
758 const u32 idx = dev_priv->workarounds.count;
759
760 if (WARN_ON(idx >= I915_MAX_WA_REGS))
761 return -ENOSPC;
762
763 dev_priv->workarounds.reg[idx].addr = addr;
764 dev_priv->workarounds.reg[idx].value = val;
765 dev_priv->workarounds.reg[idx].mask = mask;
766
767 dev_priv->workarounds.count++;
768
769 return 0;
770 }
771
772 #define WA_REG(addr, mask, val) do { \
773 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
774 if (r) \
775 return r; \
776 } while (0)
777
778 #define WA_SET_BIT_MASKED(addr, mask) \
779 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
780
781 #define WA_CLR_BIT_MASKED(addr, mask) \
782 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
783
784 #define WA_SET_FIELD_MASKED(addr, mask, value) \
785 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
786
787 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
788 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
789
790 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
791
792 static int wa_ring_whitelist_reg(struct intel_engine_cs *ring, i915_reg_t reg)
793 {
794 struct drm_i915_private *dev_priv = ring->dev->dev_private;
795 struct i915_workarounds *wa = &dev_priv->workarounds;
796 const uint32_t index = wa->hw_whitelist_count[ring->id];
797
798 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
799 return -EINVAL;
800
801 WA_WRITE(RING_FORCE_TO_NONPRIV(ring->mmio_base, index),
802 i915_mmio_reg_offset(reg));
803 wa->hw_whitelist_count[ring->id]++;
804
805 return 0;
806 }
807
808 static int gen8_init_workarounds(struct intel_engine_cs *ring)
809 {
810 struct drm_device *dev = ring->dev;
811 struct drm_i915_private *dev_priv = dev->dev_private;
812
813 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
814
815 /* WaDisableAsyncFlipPerfMode:bdw,chv */
816 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
817
818 /* WaDisablePartialInstShootdown:bdw,chv */
819 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
820 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
821
822 /* Use Force Non-Coherent whenever executing a 3D context. This is a
823 * workaround for for a possible hang in the unlikely event a TLB
824 * invalidation occurs during a PSD flush.
825 */
826 /* WaForceEnableNonCoherent:bdw,chv */
827 /* WaHdcDisableFetchWhenMasked:bdw,chv */
828 WA_SET_BIT_MASKED(HDC_CHICKEN0,
829 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
830 HDC_FORCE_NON_COHERENT);
831
832 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
833 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
834 * polygons in the same 8x4 pixel/sample area to be processed without
835 * stalling waiting for the earlier ones to write to Hierarchical Z
836 * buffer."
837 *
838 * This optimization is off by default for BDW and CHV; turn it on.
839 */
840 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
841
842 /* Wa4x4STCOptimizationDisable:bdw,chv */
843 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
844
845 /*
846 * BSpec recommends 8x4 when MSAA is used,
847 * however in practice 16x4 seems fastest.
848 *
849 * Note that PS/WM thread counts depend on the WIZ hashing
850 * disable bit, which we don't touch here, but it's good
851 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
852 */
853 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
854 GEN6_WIZ_HASHING_MASK,
855 GEN6_WIZ_HASHING_16x4);
856
857 return 0;
858 }
859
860 static int bdw_init_workarounds(struct intel_engine_cs *ring)
861 {
862 int ret;
863 struct drm_device *dev = ring->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865
866 ret = gen8_init_workarounds(ring);
867 if (ret)
868 return ret;
869
870 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
871 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
872
873 /* WaDisableDopClockGating:bdw */
874 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
875 DOP_CLOCK_GATING_DISABLE);
876
877 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
878 GEN8_SAMPLER_POWER_BYPASS_DIS);
879
880 WA_SET_BIT_MASKED(HDC_CHICKEN0,
881 /* WaForceContextSaveRestoreNonCoherent:bdw */
882 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
883 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
884 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
885
886 return 0;
887 }
888
889 static int chv_init_workarounds(struct intel_engine_cs *ring)
890 {
891 int ret;
892 struct drm_device *dev = ring->dev;
893 struct drm_i915_private *dev_priv = dev->dev_private;
894
895 ret = gen8_init_workarounds(ring);
896 if (ret)
897 return ret;
898
899 /* WaDisableThreadStallDopClockGating:chv */
900 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
901
902 /* Improve HiZ throughput on CHV. */
903 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
904
905 return 0;
906 }
907
908 static int gen9_init_workarounds(struct intel_engine_cs *ring)
909 {
910 struct drm_device *dev = ring->dev;
911 struct drm_i915_private *dev_priv = dev->dev_private;
912 uint32_t tmp;
913 int ret;
914
915 /* WaEnableLbsSlaRetryTimerDecrement:skl */
916 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
917 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
918
919 /* WaDisableKillLogic:bxt,skl */
920 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
921 ECOCHK_DIS_TLB);
922
923 /* WaDisablePartialInstShootdown:skl,bxt */
924 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
925 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
926
927 /* Syncing dependencies between camera and graphics:skl,bxt */
928 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
929 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
930
931 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
932 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
933 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
934 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
935 GEN9_DG_MIRROR_FIX_ENABLE);
936
937 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
938 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
939 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
940 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
941 GEN9_RHWO_OPTIMIZATION_DISABLE);
942 /*
943 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
944 * but we do that in per ctx batchbuffer as there is an issue
945 * with this register not getting restored on ctx restore
946 */
947 }
948
949 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
950 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
951 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
952 GEN9_ENABLE_YV12_BUGFIX);
953
954 /* Wa4x4STCOptimizationDisable:skl,bxt */
955 /* WaDisablePartialResolveInVc:skl,bxt */
956 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
957 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
958
959 /* WaCcsTlbPrefetchDisable:skl,bxt */
960 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
961 GEN9_CCS_TLB_PREFETCH_ENABLE);
962
963 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
964 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
965 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
966 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
967 PIXEL_MASK_CAMMING_DISABLE);
968
969 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
970 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
971 if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
972 IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
973 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
974 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
975
976 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
977 if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
978 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
979 GEN8_SAMPLER_POWER_BYPASS_DIS);
980
981 /* WaDisableSTUnitPowerOptimization:skl,bxt */
982 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
983
984 /* WaOCLCoherentLineFlush:skl,bxt */
985 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
986 GEN8_LQSC_FLUSH_COHERENT_LINES));
987
988 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
989 ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1);
990 if (ret)
991 return ret;
992
993 /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
994 ret = wa_ring_whitelist_reg(ring, GEN8_HDC_CHICKEN1);
995 if (ret)
996 return ret;
997
998 return 0;
999 }
1000
1001 static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
1002 {
1003 struct drm_device *dev = ring->dev;
1004 struct drm_i915_private *dev_priv = dev->dev_private;
1005 u8 vals[3] = { 0, 0, 0 };
1006 unsigned int i;
1007
1008 for (i = 0; i < 3; i++) {
1009 u8 ss;
1010
1011 /*
1012 * Only consider slices where one, and only one, subslice has 7
1013 * EUs
1014 */
1015 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1016 continue;
1017
1018 /*
1019 * subslice_7eu[i] != 0 (because of the check above) and
1020 * ss_max == 4 (maximum number of subslices possible per slice)
1021 *
1022 * -> 0 <= ss <= 3;
1023 */
1024 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1025 vals[i] = 3 - ss;
1026 }
1027
1028 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1029 return 0;
1030
1031 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1032 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1033 GEN9_IZ_HASHING_MASK(2) |
1034 GEN9_IZ_HASHING_MASK(1) |
1035 GEN9_IZ_HASHING_MASK(0),
1036 GEN9_IZ_HASHING(2, vals[2]) |
1037 GEN9_IZ_HASHING(1, vals[1]) |
1038 GEN9_IZ_HASHING(0, vals[0]));
1039
1040 return 0;
1041 }
1042
1043 static int skl_init_workarounds(struct intel_engine_cs *ring)
1044 {
1045 int ret;
1046 struct drm_device *dev = ring->dev;
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1048
1049 ret = gen9_init_workarounds(ring);
1050 if (ret)
1051 return ret;
1052
1053 /*
1054 * Actual WA is to disable percontext preemption granularity control
1055 * until D0 which is the default case so this is equivalent to
1056 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1057 */
1058 if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1059 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1060 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1061 }
1062
1063 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1064 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1065 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1066 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1067 }
1068
1069 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1070 * involving this register should also be added to WA batch as required.
1071 */
1072 if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1073 /* WaDisableLSQCROPERFforOCL:skl */
1074 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1075 GEN8_LQSC_RO_PERF_DIS);
1076
1077 /* WaEnableGapsTsvCreditFix:skl */
1078 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1079 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1080 GEN9_GAPS_TSV_CREDIT_DISABLE));
1081 }
1082
1083 /* WaDisablePowerCompilerClockGating:skl */
1084 if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1085 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1086 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1087
1088 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
1089 /*
1090 *Use Force Non-Coherent whenever executing a 3D context. This
1091 * is a workaround for a possible hang in the unlikely event
1092 * a TLB invalidation occurs during a PSD flush.
1093 */
1094 /* WaForceEnableNonCoherent:skl */
1095 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1096 HDC_FORCE_NON_COHERENT);
1097
1098 /* WaDisableHDCInvalidation:skl */
1099 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1100 BDW_DISABLE_HDC_INVALIDATION);
1101 }
1102
1103 /* WaBarrierPerformanceFixDisable:skl */
1104 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1105 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1106 HDC_FENCE_DEST_SLM_DISABLE |
1107 HDC_BARRIER_PERFORMANCE_DISABLE);
1108
1109 /* WaDisableSbeCacheDispatchPortSharing:skl */
1110 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1111 WA_SET_BIT_MASKED(
1112 GEN7_HALF_SLICE_CHICKEN1,
1113 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1114
1115 /* WaDisableLSQCROPERFforOCL:skl */
1116 ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
1117 if (ret)
1118 return ret;
1119
1120 return skl_tune_iz_hashing(ring);
1121 }
1122
1123 static int bxt_init_workarounds(struct intel_engine_cs *ring)
1124 {
1125 int ret;
1126 struct drm_device *dev = ring->dev;
1127 struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129 ret = gen9_init_workarounds(ring);
1130 if (ret)
1131 return ret;
1132
1133 /* WaStoreMultiplePTEenable:bxt */
1134 /* This is a requirement according to Hardware specification */
1135 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1136 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1137
1138 /* WaSetClckGatingDisableMedia:bxt */
1139 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1140 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1141 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1142 }
1143
1144 /* WaDisableThreadStallDopClockGating:bxt */
1145 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1146 STALL_DOP_GATING_DISABLE);
1147
1148 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1149 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1150 WA_SET_BIT_MASKED(
1151 GEN7_HALF_SLICE_CHICKEN1,
1152 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1153 }
1154
1155 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1156 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1157 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1158 /* WaDisableLSQCROPERFforOCL:bxt */
1159 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1160 ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1);
1161 if (ret)
1162 return ret;
1163
1164 ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
1165 if (ret)
1166 return ret;
1167 }
1168
1169 return 0;
1170 }
1171
1172 int init_workarounds_ring(struct intel_engine_cs *ring)
1173 {
1174 struct drm_device *dev = ring->dev;
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176
1177 WARN_ON(ring->id != RCS);
1178
1179 dev_priv->workarounds.count = 0;
1180 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1181
1182 if (IS_BROADWELL(dev))
1183 return bdw_init_workarounds(ring);
1184
1185 if (IS_CHERRYVIEW(dev))
1186 return chv_init_workarounds(ring);
1187
1188 if (IS_SKYLAKE(dev))
1189 return skl_init_workarounds(ring);
1190
1191 if (IS_BROXTON(dev))
1192 return bxt_init_workarounds(ring);
1193
1194 return 0;
1195 }
1196
1197 static int init_render_ring(struct intel_engine_cs *ring)
1198 {
1199 struct drm_device *dev = ring->dev;
1200 struct drm_i915_private *dev_priv = dev->dev_private;
1201 int ret = init_ring_common(ring);
1202 if (ret)
1203 return ret;
1204
1205 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1206 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1207 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1208
1209 /* We need to disable the AsyncFlip performance optimisations in order
1210 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1211 * programmed to '1' on all products.
1212 *
1213 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1214 */
1215 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1216 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1217
1218 /* Required for the hardware to program scanline values for waiting */
1219 /* WaEnableFlushTlbInvalidationMode:snb */
1220 if (INTEL_INFO(dev)->gen == 6)
1221 I915_WRITE(GFX_MODE,
1222 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1223
1224 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1225 if (IS_GEN7(dev))
1226 I915_WRITE(GFX_MODE_GEN7,
1227 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1228 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1229
1230 if (IS_GEN6(dev)) {
1231 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1232 * "If this bit is set, STCunit will have LRA as replacement
1233 * policy. [...] This bit must be reset. LRA replacement
1234 * policy is not supported."
1235 */
1236 I915_WRITE(CACHE_MODE_0,
1237 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1238 }
1239
1240 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1241 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1242
1243 if (HAS_L3_DPF(dev))
1244 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1245
1246 return init_workarounds_ring(ring);
1247 }
1248
1249 static void render_ring_cleanup(struct intel_engine_cs *ring)
1250 {
1251 struct drm_device *dev = ring->dev;
1252 struct drm_i915_private *dev_priv = dev->dev_private;
1253
1254 if (dev_priv->semaphore_obj) {
1255 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1256 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1257 dev_priv->semaphore_obj = NULL;
1258 }
1259
1260 intel_fini_pipe_control(ring);
1261 }
1262
1263 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1264 unsigned int num_dwords)
1265 {
1266 #define MBOX_UPDATE_DWORDS 8
1267 struct intel_engine_cs *signaller = signaller_req->ring;
1268 struct drm_device *dev = signaller->dev;
1269 struct drm_i915_private *dev_priv = dev->dev_private;
1270 struct intel_engine_cs *waiter;
1271 int i, ret, num_rings;
1272
1273 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1274 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1275 #undef MBOX_UPDATE_DWORDS
1276
1277 ret = intel_ring_begin(signaller_req, num_dwords);
1278 if (ret)
1279 return ret;
1280
1281 for_each_ring(waiter, dev_priv, i) {
1282 u32 seqno;
1283 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1284 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1285 continue;
1286
1287 seqno = i915_gem_request_get_seqno(signaller_req);
1288 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1289 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1290 PIPE_CONTROL_QW_WRITE |
1291 PIPE_CONTROL_FLUSH_ENABLE);
1292 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1293 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1294 intel_ring_emit(signaller, seqno);
1295 intel_ring_emit(signaller, 0);
1296 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1297 MI_SEMAPHORE_TARGET(waiter->id));
1298 intel_ring_emit(signaller, 0);
1299 }
1300
1301 return 0;
1302 }
1303
1304 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1305 unsigned int num_dwords)
1306 {
1307 #define MBOX_UPDATE_DWORDS 6
1308 struct intel_engine_cs *signaller = signaller_req->ring;
1309 struct drm_device *dev = signaller->dev;
1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 struct intel_engine_cs *waiter;
1312 int i, ret, num_rings;
1313
1314 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1315 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1316 #undef MBOX_UPDATE_DWORDS
1317
1318 ret = intel_ring_begin(signaller_req, num_dwords);
1319 if (ret)
1320 return ret;
1321
1322 for_each_ring(waiter, dev_priv, i) {
1323 u32 seqno;
1324 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1325 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1326 continue;
1327
1328 seqno = i915_gem_request_get_seqno(signaller_req);
1329 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1330 MI_FLUSH_DW_OP_STOREDW);
1331 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1332 MI_FLUSH_DW_USE_GTT);
1333 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1334 intel_ring_emit(signaller, seqno);
1335 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1336 MI_SEMAPHORE_TARGET(waiter->id));
1337 intel_ring_emit(signaller, 0);
1338 }
1339
1340 return 0;
1341 }
1342
1343 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1344 unsigned int num_dwords)
1345 {
1346 struct intel_engine_cs *signaller = signaller_req->ring;
1347 struct drm_device *dev = signaller->dev;
1348 struct drm_i915_private *dev_priv = dev->dev_private;
1349 struct intel_engine_cs *useless;
1350 int i, ret, num_rings;
1351
1352 #define MBOX_UPDATE_DWORDS 3
1353 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1354 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1355 #undef MBOX_UPDATE_DWORDS
1356
1357 ret = intel_ring_begin(signaller_req, num_dwords);
1358 if (ret)
1359 return ret;
1360
1361 for_each_ring(useless, dev_priv, i) {
1362 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
1363
1364 if (i915_mmio_reg_valid(mbox_reg)) {
1365 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1366
1367 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1368 intel_ring_emit_reg(signaller, mbox_reg);
1369 intel_ring_emit(signaller, seqno);
1370 }
1371 }
1372
1373 /* If num_dwords was rounded, make sure the tail pointer is correct */
1374 if (num_rings % 2 == 0)
1375 intel_ring_emit(signaller, MI_NOOP);
1376
1377 return 0;
1378 }
1379
1380 /**
1381 * gen6_add_request - Update the semaphore mailbox registers
1382 *
1383 * @request - request to write to the ring
1384 *
1385 * Update the mailbox registers in the *other* rings with the current seqno.
1386 * This acts like a signal in the canonical semaphore.
1387 */
1388 static int
1389 gen6_add_request(struct drm_i915_gem_request *req)
1390 {
1391 struct intel_engine_cs *engine = req->ring;
1392 int ret;
1393
1394 if (engine->semaphore.signal)
1395 ret = engine->semaphore.signal(req, 4);
1396 else
1397 ret = intel_ring_begin(req, 4);
1398
1399 if (ret)
1400 return ret;
1401
1402 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1403 intel_ring_emit(engine,
1404 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1405 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1406 intel_ring_emit(engine, MI_USER_INTERRUPT);
1407 __intel_ring_advance(engine);
1408
1409 return 0;
1410 }
1411
1412 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1413 u32 seqno)
1414 {
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416 return dev_priv->last_seqno < seqno;
1417 }
1418
1419 /**
1420 * intel_ring_sync - sync the waiter to the signaller on seqno
1421 *
1422 * @waiter - ring that is waiting
1423 * @signaller - ring which has, or will signal
1424 * @seqno - seqno which the waiter will block on
1425 */
1426
1427 static int
1428 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1429 struct intel_engine_cs *signaller,
1430 u32 seqno)
1431 {
1432 struct intel_engine_cs *waiter = waiter_req->ring;
1433 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1434 int ret;
1435
1436 ret = intel_ring_begin(waiter_req, 4);
1437 if (ret)
1438 return ret;
1439
1440 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1441 MI_SEMAPHORE_GLOBAL_GTT |
1442 MI_SEMAPHORE_POLL |
1443 MI_SEMAPHORE_SAD_GTE_SDD);
1444 intel_ring_emit(waiter, seqno);
1445 intel_ring_emit(waiter,
1446 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1447 intel_ring_emit(waiter,
1448 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1449 intel_ring_advance(waiter);
1450 return 0;
1451 }
1452
1453 static int
1454 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1455 struct intel_engine_cs *signaller,
1456 u32 seqno)
1457 {
1458 struct intel_engine_cs *waiter = waiter_req->ring;
1459 u32 dw1 = MI_SEMAPHORE_MBOX |
1460 MI_SEMAPHORE_COMPARE |
1461 MI_SEMAPHORE_REGISTER;
1462 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1463 int ret;
1464
1465 /* Throughout all of the GEM code, seqno passed implies our current
1466 * seqno is >= the last seqno executed. However for hardware the
1467 * comparison is strictly greater than.
1468 */
1469 seqno -= 1;
1470
1471 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1472
1473 ret = intel_ring_begin(waiter_req, 4);
1474 if (ret)
1475 return ret;
1476
1477 /* If seqno wrap happened, omit the wait with no-ops */
1478 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1479 intel_ring_emit(waiter, dw1 | wait_mbox);
1480 intel_ring_emit(waiter, seqno);
1481 intel_ring_emit(waiter, 0);
1482 intel_ring_emit(waiter, MI_NOOP);
1483 } else {
1484 intel_ring_emit(waiter, MI_NOOP);
1485 intel_ring_emit(waiter, MI_NOOP);
1486 intel_ring_emit(waiter, MI_NOOP);
1487 intel_ring_emit(waiter, MI_NOOP);
1488 }
1489 intel_ring_advance(waiter);
1490
1491 return 0;
1492 }
1493
1494 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1495 do { \
1496 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1497 PIPE_CONTROL_DEPTH_STALL); \
1498 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1499 intel_ring_emit(ring__, 0); \
1500 intel_ring_emit(ring__, 0); \
1501 } while (0)
1502
1503 static int
1504 pc_render_add_request(struct drm_i915_gem_request *req)
1505 {
1506 struct intel_engine_cs *engine = req->ring;
1507 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1508 int ret;
1509
1510 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1511 * incoherent with writes to memory, i.e. completely fubar,
1512 * so we need to use PIPE_NOTIFY instead.
1513 *
1514 * However, we also need to workaround the qword write
1515 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1516 * memory before requesting an interrupt.
1517 */
1518 ret = intel_ring_begin(req, 32);
1519 if (ret)
1520 return ret;
1521
1522 intel_ring_emit(engine,
1523 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1524 PIPE_CONTROL_WRITE_FLUSH |
1525 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1526 intel_ring_emit(engine,
1527 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1528 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1529 intel_ring_emit(engine, 0);
1530 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1531 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1532 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1533 scratch_addr += 2 * CACHELINE_BYTES;
1534 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1535 scratch_addr += 2 * CACHELINE_BYTES;
1536 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1537 scratch_addr += 2 * CACHELINE_BYTES;
1538 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1539 scratch_addr += 2 * CACHELINE_BYTES;
1540 PIPE_CONTROL_FLUSH(engine, scratch_addr);
1541
1542 intel_ring_emit(engine,
1543 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1544 PIPE_CONTROL_WRITE_FLUSH |
1545 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1546 PIPE_CONTROL_NOTIFY);
1547 intel_ring_emit(engine,
1548 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1549 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1550 intel_ring_emit(engine, 0);
1551 __intel_ring_advance(engine);
1552
1553 return 0;
1554 }
1555
1556 static u32
1557 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1558 {
1559 /* Workaround to force correct ordering between irq and seqno writes on
1560 * ivb (and maybe also on snb) by reading from a CS register (like
1561 * ACTHD) before reading the status page. */
1562 if (!lazy_coherency) {
1563 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1564 POSTING_READ(RING_ACTHD(ring->mmio_base));
1565 }
1566
1567 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1568 }
1569
1570 static u32
1571 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1572 {
1573 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1574 }
1575
1576 static void
1577 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1578 {
1579 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1580 }
1581
1582 static u32
1583 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1584 {
1585 return ring->scratch.cpu_page[0];
1586 }
1587
1588 static void
1589 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1590 {
1591 ring->scratch.cpu_page[0] = seqno;
1592 }
1593
1594 static bool
1595 gen5_ring_get_irq(struct intel_engine_cs *ring)
1596 {
1597 struct drm_device *dev = ring->dev;
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1599 unsigned long flags;
1600
1601 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1602 return false;
1603
1604 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1605 if (ring->irq_refcount++ == 0)
1606 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1607 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1608
1609 return true;
1610 }
1611
1612 static void
1613 gen5_ring_put_irq(struct intel_engine_cs *ring)
1614 {
1615 struct drm_device *dev = ring->dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 unsigned long flags;
1618
1619 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1620 if (--ring->irq_refcount == 0)
1621 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1622 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1623 }
1624
1625 static bool
1626 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1627 {
1628 struct drm_device *dev = ring->dev;
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 unsigned long flags;
1631
1632 if (!intel_irqs_enabled(dev_priv))
1633 return false;
1634
1635 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1636 if (ring->irq_refcount++ == 0) {
1637 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1638 I915_WRITE(IMR, dev_priv->irq_mask);
1639 POSTING_READ(IMR);
1640 }
1641 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1642
1643 return true;
1644 }
1645
1646 static void
1647 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1648 {
1649 struct drm_device *dev = ring->dev;
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 unsigned long flags;
1652
1653 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1654 if (--ring->irq_refcount == 0) {
1655 dev_priv->irq_mask |= ring->irq_enable_mask;
1656 I915_WRITE(IMR, dev_priv->irq_mask);
1657 POSTING_READ(IMR);
1658 }
1659 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1660 }
1661
1662 static bool
1663 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1664 {
1665 struct drm_device *dev = ring->dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 unsigned long flags;
1668
1669 if (!intel_irqs_enabled(dev_priv))
1670 return false;
1671
1672 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1673 if (ring->irq_refcount++ == 0) {
1674 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1675 I915_WRITE16(IMR, dev_priv->irq_mask);
1676 POSTING_READ16(IMR);
1677 }
1678 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1679
1680 return true;
1681 }
1682
1683 static void
1684 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1685 {
1686 struct drm_device *dev = ring->dev;
1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688 unsigned long flags;
1689
1690 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1691 if (--ring->irq_refcount == 0) {
1692 dev_priv->irq_mask |= ring->irq_enable_mask;
1693 I915_WRITE16(IMR, dev_priv->irq_mask);
1694 POSTING_READ16(IMR);
1695 }
1696 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1697 }
1698
1699 static int
1700 bsd_ring_flush(struct drm_i915_gem_request *req,
1701 u32 invalidate_domains,
1702 u32 flush_domains)
1703 {
1704 struct intel_engine_cs *engine = req->ring;
1705 int ret;
1706
1707 ret = intel_ring_begin(req, 2);
1708 if (ret)
1709 return ret;
1710
1711 intel_ring_emit(engine, MI_FLUSH);
1712 intel_ring_emit(engine, MI_NOOP);
1713 intel_ring_advance(engine);
1714 return 0;
1715 }
1716
1717 static int
1718 i9xx_add_request(struct drm_i915_gem_request *req)
1719 {
1720 struct intel_engine_cs *engine = req->ring;
1721 int ret;
1722
1723 ret = intel_ring_begin(req, 4);
1724 if (ret)
1725 return ret;
1726
1727 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1728 intel_ring_emit(engine,
1729 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1730 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1731 intel_ring_emit(engine, MI_USER_INTERRUPT);
1732 __intel_ring_advance(engine);
1733
1734 return 0;
1735 }
1736
1737 static bool
1738 gen6_ring_get_irq(struct intel_engine_cs *ring)
1739 {
1740 struct drm_device *dev = ring->dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
1742 unsigned long flags;
1743
1744 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1745 return false;
1746
1747 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1748 if (ring->irq_refcount++ == 0) {
1749 if (HAS_L3_DPF(dev) && ring->id == RCS)
1750 I915_WRITE_IMR(ring,
1751 ~(ring->irq_enable_mask |
1752 GT_PARITY_ERROR(dev)));
1753 else
1754 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1755 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1756 }
1757 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1758
1759 return true;
1760 }
1761
1762 static void
1763 gen6_ring_put_irq(struct intel_engine_cs *ring)
1764 {
1765 struct drm_device *dev = ring->dev;
1766 struct drm_i915_private *dev_priv = dev->dev_private;
1767 unsigned long flags;
1768
1769 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1770 if (--ring->irq_refcount == 0) {
1771 if (HAS_L3_DPF(dev) && ring->id == RCS)
1772 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1773 else
1774 I915_WRITE_IMR(ring, ~0);
1775 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1776 }
1777 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1778 }
1779
1780 static bool
1781 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1782 {
1783 struct drm_device *dev = ring->dev;
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1785 unsigned long flags;
1786
1787 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1788 return false;
1789
1790 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1791 if (ring->irq_refcount++ == 0) {
1792 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1793 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1794 }
1795 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1796
1797 return true;
1798 }
1799
1800 static void
1801 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1802 {
1803 struct drm_device *dev = ring->dev;
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805 unsigned long flags;
1806
1807 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1808 if (--ring->irq_refcount == 0) {
1809 I915_WRITE_IMR(ring, ~0);
1810 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1811 }
1812 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1813 }
1814
1815 static bool
1816 gen8_ring_get_irq(struct intel_engine_cs *ring)
1817 {
1818 struct drm_device *dev = ring->dev;
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1820 unsigned long flags;
1821
1822 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1823 return false;
1824
1825 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1826 if (ring->irq_refcount++ == 0) {
1827 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1828 I915_WRITE_IMR(ring,
1829 ~(ring->irq_enable_mask |
1830 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1831 } else {
1832 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1833 }
1834 POSTING_READ(RING_IMR(ring->mmio_base));
1835 }
1836 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1837
1838 return true;
1839 }
1840
1841 static void
1842 gen8_ring_put_irq(struct intel_engine_cs *ring)
1843 {
1844 struct drm_device *dev = ring->dev;
1845 struct drm_i915_private *dev_priv = dev->dev_private;
1846 unsigned long flags;
1847
1848 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1849 if (--ring->irq_refcount == 0) {
1850 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1851 I915_WRITE_IMR(ring,
1852 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1853 } else {
1854 I915_WRITE_IMR(ring, ~0);
1855 }
1856 POSTING_READ(RING_IMR(ring->mmio_base));
1857 }
1858 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1859 }
1860
1861 static int
1862 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1863 u64 offset, u32 length,
1864 unsigned dispatch_flags)
1865 {
1866 struct intel_engine_cs *engine = req->ring;
1867 int ret;
1868
1869 ret = intel_ring_begin(req, 2);
1870 if (ret)
1871 return ret;
1872
1873 intel_ring_emit(engine,
1874 MI_BATCH_BUFFER_START |
1875 MI_BATCH_GTT |
1876 (dispatch_flags & I915_DISPATCH_SECURE ?
1877 0 : MI_BATCH_NON_SECURE_I965));
1878 intel_ring_emit(engine, offset);
1879 intel_ring_advance(engine);
1880
1881 return 0;
1882 }
1883
1884 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1885 #define I830_BATCH_LIMIT (256*1024)
1886 #define I830_TLB_ENTRIES (2)
1887 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1888 static int
1889 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1890 u64 offset, u32 len,
1891 unsigned dispatch_flags)
1892 {
1893 struct intel_engine_cs *engine = req->ring;
1894 u32 cs_offset = engine->scratch.gtt_offset;
1895 int ret;
1896
1897 ret = intel_ring_begin(req, 6);
1898 if (ret)
1899 return ret;
1900
1901 /* Evict the invalid PTE TLBs */
1902 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1903 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1904 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1905 intel_ring_emit(engine, cs_offset);
1906 intel_ring_emit(engine, 0xdeadbeef);
1907 intel_ring_emit(engine, MI_NOOP);
1908 intel_ring_advance(engine);
1909
1910 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1911 if (len > I830_BATCH_LIMIT)
1912 return -ENOSPC;
1913
1914 ret = intel_ring_begin(req, 6 + 2);
1915 if (ret)
1916 return ret;
1917
1918 /* Blit the batch (which has now all relocs applied) to the
1919 * stable batch scratch bo area (so that the CS never
1920 * stumbles over its tlb invalidation bug) ...
1921 */
1922 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1923 intel_ring_emit(engine,
1924 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1925 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1926 intel_ring_emit(engine, cs_offset);
1927 intel_ring_emit(engine, 4096);
1928 intel_ring_emit(engine, offset);
1929
1930 intel_ring_emit(engine, MI_FLUSH);
1931 intel_ring_emit(engine, MI_NOOP);
1932 intel_ring_advance(engine);
1933
1934 /* ... and execute it. */
1935 offset = cs_offset;
1936 }
1937
1938 ret = intel_ring_begin(req, 2);
1939 if (ret)
1940 return ret;
1941
1942 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1943 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1944 0 : MI_BATCH_NON_SECURE));
1945 intel_ring_advance(engine);
1946
1947 return 0;
1948 }
1949
1950 static int
1951 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1952 u64 offset, u32 len,
1953 unsigned dispatch_flags)
1954 {
1955 struct intel_engine_cs *engine = req->ring;
1956 int ret;
1957
1958 ret = intel_ring_begin(req, 2);
1959 if (ret)
1960 return ret;
1961
1962 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1963 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1964 0 : MI_BATCH_NON_SECURE));
1965 intel_ring_advance(engine);
1966
1967 return 0;
1968 }
1969
1970 static void cleanup_phys_status_page(struct intel_engine_cs *ring)
1971 {
1972 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1973
1974 if (!dev_priv->status_page_dmah)
1975 return;
1976
1977 drm_pci_free(ring->dev, dev_priv->status_page_dmah);
1978 ring->status_page.page_addr = NULL;
1979 }
1980
1981 static void cleanup_status_page(struct intel_engine_cs *ring)
1982 {
1983 struct drm_i915_gem_object *obj;
1984
1985 obj = ring->status_page.obj;
1986 if (obj == NULL)
1987 return;
1988
1989 kunmap(sg_page(obj->pages->sgl));
1990 i915_gem_object_ggtt_unpin(obj);
1991 drm_gem_object_unreference(&obj->base);
1992 ring->status_page.obj = NULL;
1993 }
1994
1995 static int init_status_page(struct intel_engine_cs *ring)
1996 {
1997 struct drm_i915_gem_object *obj = ring->status_page.obj;
1998
1999 if (obj == NULL) {
2000 unsigned flags;
2001 int ret;
2002
2003 obj = i915_gem_alloc_object(ring->dev, 4096);
2004 if (obj == NULL) {
2005 DRM_ERROR("Failed to allocate status page\n");
2006 return -ENOMEM;
2007 }
2008
2009 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2010 if (ret)
2011 goto err_unref;
2012
2013 flags = 0;
2014 if (!HAS_LLC(ring->dev))
2015 /* On g33, we cannot place HWS above 256MiB, so
2016 * restrict its pinning to the low mappable arena.
2017 * Though this restriction is not documented for
2018 * gen4, gen5, or byt, they also behave similarly
2019 * and hang if the HWS is placed at the top of the
2020 * GTT. To generalise, it appears that all !llc
2021 * platforms have issues with us placing the HWS
2022 * above the mappable region (even though we never
2023 * actualy map it).
2024 */
2025 flags |= PIN_MAPPABLE;
2026 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2027 if (ret) {
2028 err_unref:
2029 drm_gem_object_unreference(&obj->base);
2030 return ret;
2031 }
2032
2033 ring->status_page.obj = obj;
2034 }
2035
2036 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2037 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2038 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
2039
2040 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2041 ring->name, ring->status_page.gfx_addr);
2042
2043 return 0;
2044 }
2045
2046 static int init_phys_status_page(struct intel_engine_cs *ring)
2047 {
2048 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2049
2050 if (!dev_priv->status_page_dmah) {
2051 dev_priv->status_page_dmah =
2052 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
2053 if (!dev_priv->status_page_dmah)
2054 return -ENOMEM;
2055 }
2056
2057 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2058 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
2059
2060 return 0;
2061 }
2062
2063 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2064 {
2065 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2066 vunmap(ringbuf->virtual_start);
2067 else
2068 iounmap(ringbuf->virtual_start);
2069 ringbuf->virtual_start = NULL;
2070 ringbuf->vma = NULL;
2071 i915_gem_object_ggtt_unpin(ringbuf->obj);
2072 }
2073
2074 static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2075 {
2076 struct sg_page_iter sg_iter;
2077 struct page **pages;
2078 void *addr;
2079 int i;
2080
2081 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2082 if (pages == NULL)
2083 return NULL;
2084
2085 i = 0;
2086 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2087 pages[i++] = sg_page_iter_page(&sg_iter);
2088
2089 addr = vmap(pages, i, 0, PAGE_KERNEL);
2090 drm_free_large(pages);
2091
2092 return addr;
2093 }
2094
2095 int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2096 struct intel_ringbuffer *ringbuf)
2097 {
2098 struct drm_i915_private *dev_priv = to_i915(dev);
2099 struct drm_i915_gem_object *obj = ringbuf->obj;
2100 int ret;
2101
2102 if (HAS_LLC(dev_priv) && !obj->stolen) {
2103 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2104 if (ret)
2105 return ret;
2106
2107 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2108 if (ret) {
2109 i915_gem_object_ggtt_unpin(obj);
2110 return ret;
2111 }
2112
2113 ringbuf->virtual_start = vmap_obj(obj);
2114 if (ringbuf->virtual_start == NULL) {
2115 i915_gem_object_ggtt_unpin(obj);
2116 return -ENOMEM;
2117 }
2118 } else {
2119 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2120 if (ret)
2121 return ret;
2122
2123 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2124 if (ret) {
2125 i915_gem_object_ggtt_unpin(obj);
2126 return ret;
2127 }
2128
2129 /* Access through the GTT requires the device to be awake. */
2130 assert_rpm_wakelock_held(dev_priv);
2131
2132 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2133 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2134 if (ringbuf->virtual_start == NULL) {
2135 i915_gem_object_ggtt_unpin(obj);
2136 return -EINVAL;
2137 }
2138 }
2139
2140 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2141
2142 return 0;
2143 }
2144
2145 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2146 {
2147 drm_gem_object_unreference(&ringbuf->obj->base);
2148 ringbuf->obj = NULL;
2149 }
2150
2151 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2152 struct intel_ringbuffer *ringbuf)
2153 {
2154 struct drm_i915_gem_object *obj;
2155
2156 obj = NULL;
2157 if (!HAS_LLC(dev))
2158 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2159 if (obj == NULL)
2160 obj = i915_gem_alloc_object(dev, ringbuf->size);
2161 if (obj == NULL)
2162 return -ENOMEM;
2163
2164 /* mark ring buffers as read-only from GPU side by default */
2165 obj->gt_ro = 1;
2166
2167 ringbuf->obj = obj;
2168
2169 return 0;
2170 }
2171
2172 struct intel_ringbuffer *
2173 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2174 {
2175 struct intel_ringbuffer *ring;
2176 int ret;
2177
2178 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2179 if (ring == NULL) {
2180 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2181 engine->name);
2182 return ERR_PTR(-ENOMEM);
2183 }
2184
2185 ring->ring = engine;
2186 list_add(&ring->link, &engine->buffers);
2187
2188 ring->size = size;
2189 /* Workaround an erratum on the i830 which causes a hang if
2190 * the TAIL pointer points to within the last 2 cachelines
2191 * of the buffer.
2192 */
2193 ring->effective_size = size;
2194 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2195 ring->effective_size -= 2 * CACHELINE_BYTES;
2196
2197 ring->last_retired_head = -1;
2198 intel_ring_update_space(ring);
2199
2200 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2201 if (ret) {
2202 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2203 engine->name, ret);
2204 list_del(&ring->link);
2205 kfree(ring);
2206 return ERR_PTR(ret);
2207 }
2208
2209 return ring;
2210 }
2211
2212 void
2213 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2214 {
2215 intel_destroy_ringbuffer_obj(ring);
2216 list_del(&ring->link);
2217 kfree(ring);
2218 }
2219
2220 static int intel_init_ring_buffer(struct drm_device *dev,
2221 struct intel_engine_cs *ring)
2222 {
2223 struct intel_ringbuffer *ringbuf;
2224 int ret;
2225
2226 WARN_ON(ring->buffer);
2227
2228 ring->dev = dev;
2229 INIT_LIST_HEAD(&ring->active_list);
2230 INIT_LIST_HEAD(&ring->request_list);
2231 INIT_LIST_HEAD(&ring->execlist_queue);
2232 INIT_LIST_HEAD(&ring->buffers);
2233 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2234 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2235
2236 init_waitqueue_head(&ring->irq_queue);
2237
2238 ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2239 if (IS_ERR(ringbuf)) {
2240 ret = PTR_ERR(ringbuf);
2241 goto error;
2242 }
2243 ring->buffer = ringbuf;
2244
2245 if (I915_NEED_GFX_HWS(dev)) {
2246 ret = init_status_page(ring);
2247 if (ret)
2248 goto error;
2249 } else {
2250 WARN_ON(ring->id != RCS);
2251 ret = init_phys_status_page(ring);
2252 if (ret)
2253 goto error;
2254 }
2255
2256 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2257 if (ret) {
2258 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2259 ring->name, ret);
2260 intel_destroy_ringbuffer_obj(ringbuf);
2261 goto error;
2262 }
2263
2264 ret = i915_cmd_parser_init_ring(ring);
2265 if (ret)
2266 goto error;
2267
2268 return 0;
2269
2270 error:
2271 intel_cleanup_ring_buffer(ring);
2272 return ret;
2273 }
2274
2275 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2276 {
2277 struct drm_i915_private *dev_priv;
2278
2279 if (!intel_ring_initialized(ring))
2280 return;
2281
2282 dev_priv = to_i915(ring->dev);
2283
2284 if (ring->buffer) {
2285 intel_stop_ring_buffer(ring);
2286 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2287
2288 intel_unpin_ringbuffer_obj(ring->buffer);
2289 intel_ringbuffer_free(ring->buffer);
2290 ring->buffer = NULL;
2291 }
2292
2293 if (ring->cleanup)
2294 ring->cleanup(ring);
2295
2296 if (I915_NEED_GFX_HWS(ring->dev)) {
2297 cleanup_status_page(ring);
2298 } else {
2299 WARN_ON(ring->id != RCS);
2300 cleanup_phys_status_page(ring);
2301 }
2302
2303 i915_cmd_parser_fini_ring(ring);
2304 i915_gem_batch_pool_fini(&ring->batch_pool);
2305 ring->dev = NULL;
2306 }
2307
2308 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2309 {
2310 struct intel_ringbuffer *ringbuf = ring->buffer;
2311 struct drm_i915_gem_request *request;
2312 unsigned space;
2313 int ret;
2314
2315 if (intel_ring_space(ringbuf) >= n)
2316 return 0;
2317
2318 /* The whole point of reserving space is to not wait! */
2319 WARN_ON(ringbuf->reserved_in_use);
2320
2321 list_for_each_entry(request, &ring->request_list, list) {
2322 space = __intel_ring_space(request->postfix, ringbuf->tail,
2323 ringbuf->size);
2324 if (space >= n)
2325 break;
2326 }
2327
2328 if (WARN_ON(&request->list == &ring->request_list))
2329 return -ENOSPC;
2330
2331 ret = i915_wait_request(request);
2332 if (ret)
2333 return ret;
2334
2335 ringbuf->space = space;
2336 return 0;
2337 }
2338
2339 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2340 {
2341 uint32_t __iomem *virt;
2342 int rem = ringbuf->size - ringbuf->tail;
2343
2344 virt = ringbuf->virtual_start + ringbuf->tail;
2345 rem /= 4;
2346 while (rem--)
2347 iowrite32(MI_NOOP, virt++);
2348
2349 ringbuf->tail = 0;
2350 intel_ring_update_space(ringbuf);
2351 }
2352
2353 int intel_ring_idle(struct intel_engine_cs *ring)
2354 {
2355 struct drm_i915_gem_request *req;
2356
2357 /* Wait upon the last request to be completed */
2358 if (list_empty(&ring->request_list))
2359 return 0;
2360
2361 req = list_entry(ring->request_list.prev,
2362 struct drm_i915_gem_request,
2363 list);
2364
2365 /* Make sure we do not trigger any retires */
2366 return __i915_wait_request(req,
2367 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2368 to_i915(ring->dev)->mm.interruptible,
2369 NULL, NULL);
2370 }
2371
2372 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2373 {
2374 request->ringbuf = request->ring->buffer;
2375 return 0;
2376 }
2377
2378 int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2379 {
2380 /*
2381 * The first call merely notes the reserve request and is common for
2382 * all back ends. The subsequent localised _begin() call actually
2383 * ensures that the reservation is available. Without the begin, if
2384 * the request creator immediately submitted the request without
2385 * adding any commands to it then there might not actually be
2386 * sufficient room for the submission commands.
2387 */
2388 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2389
2390 return intel_ring_begin(request, 0);
2391 }
2392
2393 void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2394 {
2395 WARN_ON(ringbuf->reserved_size);
2396 WARN_ON(ringbuf->reserved_in_use);
2397
2398 ringbuf->reserved_size = size;
2399 }
2400
2401 void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2402 {
2403 WARN_ON(ringbuf->reserved_in_use);
2404
2405 ringbuf->reserved_size = 0;
2406 ringbuf->reserved_in_use = false;
2407 }
2408
2409 void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2410 {
2411 WARN_ON(ringbuf->reserved_in_use);
2412
2413 ringbuf->reserved_in_use = true;
2414 ringbuf->reserved_tail = ringbuf->tail;
2415 }
2416
2417 void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2418 {
2419 WARN_ON(!ringbuf->reserved_in_use);
2420 if (ringbuf->tail > ringbuf->reserved_tail) {
2421 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2422 "request reserved size too small: %d vs %d!\n",
2423 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2424 } else {
2425 /*
2426 * The ring was wrapped while the reserved space was in use.
2427 * That means that some unknown amount of the ring tail was
2428 * no-op filled and skipped. Thus simply adding the ring size
2429 * to the tail and doing the above space check will not work.
2430 * Rather than attempt to track how much tail was skipped,
2431 * it is much simpler to say that also skipping the sanity
2432 * check every once in a while is not a big issue.
2433 */
2434 }
2435
2436 ringbuf->reserved_size = 0;
2437 ringbuf->reserved_in_use = false;
2438 }
2439
2440 static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2441 {
2442 struct intel_ringbuffer *ringbuf = ring->buffer;
2443 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2444 int remain_actual = ringbuf->size - ringbuf->tail;
2445 int ret, total_bytes, wait_bytes = 0;
2446 bool need_wrap = false;
2447
2448 if (ringbuf->reserved_in_use)
2449 total_bytes = bytes;
2450 else
2451 total_bytes = bytes + ringbuf->reserved_size;
2452
2453 if (unlikely(bytes > remain_usable)) {
2454 /*
2455 * Not enough space for the basic request. So need to flush
2456 * out the remainder and then wait for base + reserved.
2457 */
2458 wait_bytes = remain_actual + total_bytes;
2459 need_wrap = true;
2460 } else {
2461 if (unlikely(total_bytes > remain_usable)) {
2462 /*
2463 * The base request will fit but the reserved space
2464 * falls off the end. So only need to to wait for the
2465 * reserved size after flushing out the remainder.
2466 */
2467 wait_bytes = remain_actual + ringbuf->reserved_size;
2468 need_wrap = true;
2469 } else if (total_bytes > ringbuf->space) {
2470 /* No wrapping required, just waiting. */
2471 wait_bytes = total_bytes;
2472 }
2473 }
2474
2475 if (wait_bytes) {
2476 ret = ring_wait_for_space(ring, wait_bytes);
2477 if (unlikely(ret))
2478 return ret;
2479
2480 if (need_wrap)
2481 __wrap_ring_buffer(ringbuf);
2482 }
2483
2484 return 0;
2485 }
2486
2487 int intel_ring_begin(struct drm_i915_gem_request *req,
2488 int num_dwords)
2489 {
2490 struct intel_engine_cs *engine;
2491 struct drm_i915_private *dev_priv;
2492 int ret;
2493
2494 WARN_ON(req == NULL);
2495 engine = req->ring;
2496 dev_priv = engine->dev->dev_private;
2497
2498 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2499 dev_priv->mm.interruptible);
2500 if (ret)
2501 return ret;
2502
2503 ret = __intel_ring_prepare(engine, num_dwords * sizeof(uint32_t));
2504 if (ret)
2505 return ret;
2506
2507 engine->buffer->space -= num_dwords * sizeof(uint32_t);
2508 return 0;
2509 }
2510
2511 /* Align the ring tail to a cacheline boundary */
2512 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2513 {
2514 struct intel_engine_cs *engine = req->ring;
2515 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2516 int ret;
2517
2518 if (num_dwords == 0)
2519 return 0;
2520
2521 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2522 ret = intel_ring_begin(req, num_dwords);
2523 if (ret)
2524 return ret;
2525
2526 while (num_dwords--)
2527 intel_ring_emit(engine, MI_NOOP);
2528
2529 intel_ring_advance(engine);
2530
2531 return 0;
2532 }
2533
2534 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2535 {
2536 struct drm_device *dev = ring->dev;
2537 struct drm_i915_private *dev_priv = dev->dev_private;
2538
2539 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2540 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2541 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2542 if (HAS_VEBOX(dev))
2543 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2544 }
2545
2546 ring->set_seqno(ring, seqno);
2547 ring->hangcheck.seqno = seqno;
2548 }
2549
2550 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2551 u32 value)
2552 {
2553 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2554
2555 /* Every tail move must follow the sequence below */
2556
2557 /* Disable notification that the ring is IDLE. The GT
2558 * will then assume that it is busy and bring it out of rc6.
2559 */
2560 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2561 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2562
2563 /* Clear the context id. Here be magic! */
2564 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2565
2566 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2567 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2568 GEN6_BSD_SLEEP_INDICATOR) == 0,
2569 50))
2570 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2571
2572 /* Now that the ring is fully powered up, update the tail */
2573 I915_WRITE_TAIL(ring, value);
2574 POSTING_READ(RING_TAIL(ring->mmio_base));
2575
2576 /* Let the ring send IDLE messages to the GT again,
2577 * and so let it sleep to conserve power when idle.
2578 */
2579 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2580 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2581 }
2582
2583 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2584 u32 invalidate, u32 flush)
2585 {
2586 struct intel_engine_cs *engine = req->ring;
2587 uint32_t cmd;
2588 int ret;
2589
2590 ret = intel_ring_begin(req, 4);
2591 if (ret)
2592 return ret;
2593
2594 cmd = MI_FLUSH_DW;
2595 if (INTEL_INFO(engine->dev)->gen >= 8)
2596 cmd += 1;
2597
2598 /* We always require a command barrier so that subsequent
2599 * commands, such as breadcrumb interrupts, are strictly ordered
2600 * wrt the contents of the write cache being flushed to memory
2601 * (and thus being coherent from the CPU).
2602 */
2603 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2604
2605 /*
2606 * Bspec vol 1c.5 - video engine command streamer:
2607 * "If ENABLED, all TLBs will be invalidated once the flush
2608 * operation is complete. This bit is only valid when the
2609 * Post-Sync Operation field is a value of 1h or 3h."
2610 */
2611 if (invalidate & I915_GEM_GPU_DOMAINS)
2612 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2613
2614 intel_ring_emit(engine, cmd);
2615 intel_ring_emit(engine,
2616 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2617 if (INTEL_INFO(engine->dev)->gen >= 8) {
2618 intel_ring_emit(engine, 0); /* upper addr */
2619 intel_ring_emit(engine, 0); /* value */
2620 } else {
2621 intel_ring_emit(engine, 0);
2622 intel_ring_emit(engine, MI_NOOP);
2623 }
2624 intel_ring_advance(engine);
2625 return 0;
2626 }
2627
2628 static int
2629 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2630 u64 offset, u32 len,
2631 unsigned dispatch_flags)
2632 {
2633 struct intel_engine_cs *engine = req->ring;
2634 bool ppgtt = USES_PPGTT(engine->dev) &&
2635 !(dispatch_flags & I915_DISPATCH_SECURE);
2636 int ret;
2637
2638 ret = intel_ring_begin(req, 4);
2639 if (ret)
2640 return ret;
2641
2642 /* FIXME(BDW): Address space and security selectors. */
2643 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2644 (dispatch_flags & I915_DISPATCH_RS ?
2645 MI_BATCH_RESOURCE_STREAMER : 0));
2646 intel_ring_emit(engine, lower_32_bits(offset));
2647 intel_ring_emit(engine, upper_32_bits(offset));
2648 intel_ring_emit(engine, MI_NOOP);
2649 intel_ring_advance(engine);
2650
2651 return 0;
2652 }
2653
2654 static int
2655 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2656 u64 offset, u32 len,
2657 unsigned dispatch_flags)
2658 {
2659 struct intel_engine_cs *engine = req->ring;
2660 int ret;
2661
2662 ret = intel_ring_begin(req, 2);
2663 if (ret)
2664 return ret;
2665
2666 intel_ring_emit(engine,
2667 MI_BATCH_BUFFER_START |
2668 (dispatch_flags & I915_DISPATCH_SECURE ?
2669 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2670 (dispatch_flags & I915_DISPATCH_RS ?
2671 MI_BATCH_RESOURCE_STREAMER : 0));
2672 /* bit0-7 is the length on GEN6+ */
2673 intel_ring_emit(engine, offset);
2674 intel_ring_advance(engine);
2675
2676 return 0;
2677 }
2678
2679 static int
2680 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2681 u64 offset, u32 len,
2682 unsigned dispatch_flags)
2683 {
2684 struct intel_engine_cs *engine = req->ring;
2685 int ret;
2686
2687 ret = intel_ring_begin(req, 2);
2688 if (ret)
2689 return ret;
2690
2691 intel_ring_emit(engine,
2692 MI_BATCH_BUFFER_START |
2693 (dispatch_flags & I915_DISPATCH_SECURE ?
2694 0 : MI_BATCH_NON_SECURE_I965));
2695 /* bit0-7 is the length on GEN6+ */
2696 intel_ring_emit(engine, offset);
2697 intel_ring_advance(engine);
2698
2699 return 0;
2700 }
2701
2702 /* Blitter support (SandyBridge+) */
2703
2704 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2705 u32 invalidate, u32 flush)
2706 {
2707 struct intel_engine_cs *engine = req->ring;
2708 struct drm_device *dev = engine->dev;
2709 uint32_t cmd;
2710 int ret;
2711
2712 ret = intel_ring_begin(req, 4);
2713 if (ret)
2714 return ret;
2715
2716 cmd = MI_FLUSH_DW;
2717 if (INTEL_INFO(dev)->gen >= 8)
2718 cmd += 1;
2719
2720 /* We always require a command barrier so that subsequent
2721 * commands, such as breadcrumb interrupts, are strictly ordered
2722 * wrt the contents of the write cache being flushed to memory
2723 * (and thus being coherent from the CPU).
2724 */
2725 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2726
2727 /*
2728 * Bspec vol 1c.3 - blitter engine command streamer:
2729 * "If ENABLED, all TLBs will be invalidated once the flush
2730 * operation is complete. This bit is only valid when the
2731 * Post-Sync Operation field is a value of 1h or 3h."
2732 */
2733 if (invalidate & I915_GEM_DOMAIN_RENDER)
2734 cmd |= MI_INVALIDATE_TLB;
2735 intel_ring_emit(engine, cmd);
2736 intel_ring_emit(engine,
2737 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2738 if (INTEL_INFO(dev)->gen >= 8) {
2739 intel_ring_emit(engine, 0); /* upper addr */
2740 intel_ring_emit(engine, 0); /* value */
2741 } else {
2742 intel_ring_emit(engine, 0);
2743 intel_ring_emit(engine, MI_NOOP);
2744 }
2745 intel_ring_advance(engine);
2746
2747 return 0;
2748 }
2749
2750 int intel_init_render_ring_buffer(struct drm_device *dev)
2751 {
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 struct intel_engine_cs *engine = &dev_priv->ring[RCS];
2754 struct drm_i915_gem_object *obj;
2755 int ret;
2756
2757 engine->name = "render ring";
2758 engine->id = RCS;
2759 engine->exec_id = I915_EXEC_RENDER;
2760 engine->mmio_base = RENDER_RING_BASE;
2761
2762 if (INTEL_INFO(dev)->gen >= 8) {
2763 if (i915_semaphore_is_enabled(dev)) {
2764 obj = i915_gem_alloc_object(dev, 4096);
2765 if (obj == NULL) {
2766 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2767 i915.semaphores = 0;
2768 } else {
2769 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2770 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2771 if (ret != 0) {
2772 drm_gem_object_unreference(&obj->base);
2773 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2774 i915.semaphores = 0;
2775 } else
2776 dev_priv->semaphore_obj = obj;
2777 }
2778 }
2779
2780 engine->init_context = intel_rcs_ctx_init;
2781 engine->add_request = gen6_add_request;
2782 engine->flush = gen8_render_ring_flush;
2783 engine->irq_get = gen8_ring_get_irq;
2784 engine->irq_put = gen8_ring_put_irq;
2785 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2786 engine->get_seqno = gen6_ring_get_seqno;
2787 engine->set_seqno = ring_set_seqno;
2788 if (i915_semaphore_is_enabled(dev)) {
2789 WARN_ON(!dev_priv->semaphore_obj);
2790 engine->semaphore.sync_to = gen8_ring_sync;
2791 engine->semaphore.signal = gen8_rcs_signal;
2792 GEN8_RING_SEMAPHORE_INIT(engine);
2793 }
2794 } else if (INTEL_INFO(dev)->gen >= 6) {
2795 engine->init_context = intel_rcs_ctx_init;
2796 engine->add_request = gen6_add_request;
2797 engine->flush = gen7_render_ring_flush;
2798 if (INTEL_INFO(dev)->gen == 6)
2799 engine->flush = gen6_render_ring_flush;
2800 engine->irq_get = gen6_ring_get_irq;
2801 engine->irq_put = gen6_ring_put_irq;
2802 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2803 engine->get_seqno = gen6_ring_get_seqno;
2804 engine->set_seqno = ring_set_seqno;
2805 if (i915_semaphore_is_enabled(dev)) {
2806 engine->semaphore.sync_to = gen6_ring_sync;
2807 engine->semaphore.signal = gen6_signal;
2808 /*
2809 * The current semaphore is only applied on pre-gen8
2810 * platform. And there is no VCS2 ring on the pre-gen8
2811 * platform. So the semaphore between RCS and VCS2 is
2812 * initialized as INVALID. Gen8 will initialize the
2813 * sema between VCS2 and RCS later.
2814 */
2815 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2816 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2817 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2818 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2819 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2820 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2821 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2822 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2823 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2824 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2825 }
2826 } else if (IS_GEN5(dev)) {
2827 engine->add_request = pc_render_add_request;
2828 engine->flush = gen4_render_ring_flush;
2829 engine->get_seqno = pc_render_get_seqno;
2830 engine->set_seqno = pc_render_set_seqno;
2831 engine->irq_get = gen5_ring_get_irq;
2832 engine->irq_put = gen5_ring_put_irq;
2833 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2834 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2835 } else {
2836 engine->add_request = i9xx_add_request;
2837 if (INTEL_INFO(dev)->gen < 4)
2838 engine->flush = gen2_render_ring_flush;
2839 else
2840 engine->flush = gen4_render_ring_flush;
2841 engine->get_seqno = ring_get_seqno;
2842 engine->set_seqno = ring_set_seqno;
2843 if (IS_GEN2(dev)) {
2844 engine->irq_get = i8xx_ring_get_irq;
2845 engine->irq_put = i8xx_ring_put_irq;
2846 } else {
2847 engine->irq_get = i9xx_ring_get_irq;
2848 engine->irq_put = i9xx_ring_put_irq;
2849 }
2850 engine->irq_enable_mask = I915_USER_INTERRUPT;
2851 }
2852 engine->write_tail = ring_write_tail;
2853
2854 if (IS_HASWELL(dev))
2855 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2856 else if (IS_GEN8(dev))
2857 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2858 else if (INTEL_INFO(dev)->gen >= 6)
2859 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2860 else if (INTEL_INFO(dev)->gen >= 4)
2861 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2862 else if (IS_I830(dev) || IS_845G(dev))
2863 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2864 else
2865 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2866 engine->init_hw = init_render_ring;
2867 engine->cleanup = render_ring_cleanup;
2868
2869 /* Workaround batchbuffer to combat CS tlb bug. */
2870 if (HAS_BROKEN_CS_TLB(dev)) {
2871 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2872 if (obj == NULL) {
2873 DRM_ERROR("Failed to allocate batch bo\n");
2874 return -ENOMEM;
2875 }
2876
2877 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2878 if (ret != 0) {
2879 drm_gem_object_unreference(&obj->base);
2880 DRM_ERROR("Failed to ping batch bo\n");
2881 return ret;
2882 }
2883
2884 engine->scratch.obj = obj;
2885 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2886 }
2887
2888 ret = intel_init_ring_buffer(dev, engine);
2889 if (ret)
2890 return ret;
2891
2892 if (INTEL_INFO(dev)->gen >= 5) {
2893 ret = intel_init_pipe_control(engine);
2894 if (ret)
2895 return ret;
2896 }
2897
2898 return 0;
2899 }
2900
2901 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2902 {
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904 struct intel_engine_cs *engine = &dev_priv->ring[VCS];
2905
2906 engine->name = "bsd ring";
2907 engine->id = VCS;
2908 engine->exec_id = I915_EXEC_BSD;
2909
2910 engine->write_tail = ring_write_tail;
2911 if (INTEL_INFO(dev)->gen >= 6) {
2912 engine->mmio_base = GEN6_BSD_RING_BASE;
2913 /* gen6 bsd needs a special wa for tail updates */
2914 if (IS_GEN6(dev))
2915 engine->write_tail = gen6_bsd_ring_write_tail;
2916 engine->flush = gen6_bsd_ring_flush;
2917 engine->add_request = gen6_add_request;
2918 engine->get_seqno = gen6_ring_get_seqno;
2919 engine->set_seqno = ring_set_seqno;
2920 if (INTEL_INFO(dev)->gen >= 8) {
2921 engine->irq_enable_mask =
2922 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2923 engine->irq_get = gen8_ring_get_irq;
2924 engine->irq_put = gen8_ring_put_irq;
2925 engine->dispatch_execbuffer =
2926 gen8_ring_dispatch_execbuffer;
2927 if (i915_semaphore_is_enabled(dev)) {
2928 engine->semaphore.sync_to = gen8_ring_sync;
2929 engine->semaphore.signal = gen8_xcs_signal;
2930 GEN8_RING_SEMAPHORE_INIT(engine);
2931 }
2932 } else {
2933 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2934 engine->irq_get = gen6_ring_get_irq;
2935 engine->irq_put = gen6_ring_put_irq;
2936 engine->dispatch_execbuffer =
2937 gen6_ring_dispatch_execbuffer;
2938 if (i915_semaphore_is_enabled(dev)) {
2939 engine->semaphore.sync_to = gen6_ring_sync;
2940 engine->semaphore.signal = gen6_signal;
2941 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2942 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2943 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2944 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2945 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2946 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2947 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2948 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2949 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2950 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2951 }
2952 }
2953 } else {
2954 engine->mmio_base = BSD_RING_BASE;
2955 engine->flush = bsd_ring_flush;
2956 engine->add_request = i9xx_add_request;
2957 engine->get_seqno = ring_get_seqno;
2958 engine->set_seqno = ring_set_seqno;
2959 if (IS_GEN5(dev)) {
2960 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2961 engine->irq_get = gen5_ring_get_irq;
2962 engine->irq_put = gen5_ring_put_irq;
2963 } else {
2964 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2965 engine->irq_get = i9xx_ring_get_irq;
2966 engine->irq_put = i9xx_ring_put_irq;
2967 }
2968 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2969 }
2970 engine->init_hw = init_ring_common;
2971
2972 return intel_init_ring_buffer(dev, engine);
2973 }
2974
2975 /**
2976 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2977 */
2978 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2979 {
2980 struct drm_i915_private *dev_priv = dev->dev_private;
2981 struct intel_engine_cs *engine = &dev_priv->ring[VCS2];
2982
2983 engine->name = "bsd2 ring";
2984 engine->id = VCS2;
2985 engine->exec_id = I915_EXEC_BSD;
2986
2987 engine->write_tail = ring_write_tail;
2988 engine->mmio_base = GEN8_BSD2_RING_BASE;
2989 engine->flush = gen6_bsd_ring_flush;
2990 engine->add_request = gen6_add_request;
2991 engine->get_seqno = gen6_ring_get_seqno;
2992 engine->set_seqno = ring_set_seqno;
2993 engine->irq_enable_mask =
2994 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2995 engine->irq_get = gen8_ring_get_irq;
2996 engine->irq_put = gen8_ring_put_irq;
2997 engine->dispatch_execbuffer =
2998 gen8_ring_dispatch_execbuffer;
2999 if (i915_semaphore_is_enabled(dev)) {
3000 engine->semaphore.sync_to = gen8_ring_sync;
3001 engine->semaphore.signal = gen8_xcs_signal;
3002 GEN8_RING_SEMAPHORE_INIT(engine);
3003 }
3004 engine->init_hw = init_ring_common;
3005
3006 return intel_init_ring_buffer(dev, engine);
3007 }
3008
3009 int intel_init_blt_ring_buffer(struct drm_device *dev)
3010 {
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 struct intel_engine_cs *engine = &dev_priv->ring[BCS];
3013
3014 engine->name = "blitter ring";
3015 engine->id = BCS;
3016 engine->exec_id = I915_EXEC_BLT;
3017
3018 engine->mmio_base = BLT_RING_BASE;
3019 engine->write_tail = ring_write_tail;
3020 engine->flush = gen6_ring_flush;
3021 engine->add_request = gen6_add_request;
3022 engine->get_seqno = gen6_ring_get_seqno;
3023 engine->set_seqno = ring_set_seqno;
3024 if (INTEL_INFO(dev)->gen >= 8) {
3025 engine->irq_enable_mask =
3026 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3027 engine->irq_get = gen8_ring_get_irq;
3028 engine->irq_put = gen8_ring_put_irq;
3029 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3030 if (i915_semaphore_is_enabled(dev)) {
3031 engine->semaphore.sync_to = gen8_ring_sync;
3032 engine->semaphore.signal = gen8_xcs_signal;
3033 GEN8_RING_SEMAPHORE_INIT(engine);
3034 }
3035 } else {
3036 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3037 engine->irq_get = gen6_ring_get_irq;
3038 engine->irq_put = gen6_ring_put_irq;
3039 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3040 if (i915_semaphore_is_enabled(dev)) {
3041 engine->semaphore.signal = gen6_signal;
3042 engine->semaphore.sync_to = gen6_ring_sync;
3043 /*
3044 * The current semaphore is only applied on pre-gen8
3045 * platform. And there is no VCS2 ring on the pre-gen8
3046 * platform. So the semaphore between BCS and VCS2 is
3047 * initialized as INVALID. Gen8 will initialize the
3048 * sema between BCS and VCS2 later.
3049 */
3050 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3051 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3052 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3053 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3054 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3055 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3056 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3057 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3058 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3059 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3060 }
3061 }
3062 engine->init_hw = init_ring_common;
3063
3064 return intel_init_ring_buffer(dev, engine);
3065 }
3066
3067 int intel_init_vebox_ring_buffer(struct drm_device *dev)
3068 {
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct intel_engine_cs *engine = &dev_priv->ring[VECS];
3071
3072 engine->name = "video enhancement ring";
3073 engine->id = VECS;
3074 engine->exec_id = I915_EXEC_VEBOX;
3075
3076 engine->mmio_base = VEBOX_RING_BASE;
3077 engine->write_tail = ring_write_tail;
3078 engine->flush = gen6_ring_flush;
3079 engine->add_request = gen6_add_request;
3080 engine->get_seqno = gen6_ring_get_seqno;
3081 engine->set_seqno = ring_set_seqno;
3082
3083 if (INTEL_INFO(dev)->gen >= 8) {
3084 engine->irq_enable_mask =
3085 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3086 engine->irq_get = gen8_ring_get_irq;
3087 engine->irq_put = gen8_ring_put_irq;
3088 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3089 if (i915_semaphore_is_enabled(dev)) {
3090 engine->semaphore.sync_to = gen8_ring_sync;
3091 engine->semaphore.signal = gen8_xcs_signal;
3092 GEN8_RING_SEMAPHORE_INIT(engine);
3093 }
3094 } else {
3095 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3096 engine->irq_get = hsw_vebox_get_irq;
3097 engine->irq_put = hsw_vebox_put_irq;
3098 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3099 if (i915_semaphore_is_enabled(dev)) {
3100 engine->semaphore.sync_to = gen6_ring_sync;
3101 engine->semaphore.signal = gen6_signal;
3102 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3103 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3104 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3105 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3106 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3107 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3108 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3109 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3110 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3111 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3112 }
3113 }
3114 engine->init_hw = init_ring_common;
3115
3116 return intel_init_ring_buffer(dev, engine);
3117 }
3118
3119 int
3120 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3121 {
3122 struct intel_engine_cs *engine = req->ring;
3123 int ret;
3124
3125 if (!engine->gpu_caches_dirty)
3126 return 0;
3127
3128 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3129 if (ret)
3130 return ret;
3131
3132 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3133
3134 engine->gpu_caches_dirty = false;
3135 return 0;
3136 }
3137
3138 int
3139 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3140 {
3141 struct intel_engine_cs *engine = req->ring;
3142 uint32_t flush_domains;
3143 int ret;
3144
3145 flush_domains = 0;
3146 if (engine->gpu_caches_dirty)
3147 flush_domains = I915_GEM_GPU_DOMAINS;
3148
3149 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3150 if (ret)
3151 return ret;
3152
3153 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3154
3155 engine->gpu_caches_dirty = false;
3156 return 0;
3157 }
3158
3159 void
3160 intel_stop_ring_buffer(struct intel_engine_cs *ring)
3161 {
3162 int ret;
3163
3164 if (!intel_ring_initialized(ring))
3165 return;
3166
3167 ret = intel_ring_idle(ring);
3168 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3169 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3170 ring->name, ret);
3171
3172 stop_ring(ring);
3173 }
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