2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
36 static inline int ring_space(struct intel_ring_buffer
*ring
)
38 int space
= (ring
->head
& HEAD_ADDR
) - (ring
->tail
+ I915_RING_FREE_SPACE
);
44 void __intel_ring_advance(struct intel_ring_buffer
*ring
)
46 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
48 ring
->tail
&= ring
->size
- 1;
49 if (dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
))
51 ring
->write_tail(ring
, ring
->tail
);
55 gen2_render_ring_flush(struct intel_ring_buffer
*ring
,
56 u32 invalidate_domains
,
63 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
64 cmd
|= MI_NO_WRITE_FLUSH
;
66 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
69 ret
= intel_ring_begin(ring
, 2);
73 intel_ring_emit(ring
, cmd
);
74 intel_ring_emit(ring
, MI_NOOP
);
75 intel_ring_advance(ring
);
81 gen4_render_ring_flush(struct intel_ring_buffer
*ring
,
82 u32 invalidate_domains
,
85 struct drm_device
*dev
= ring
->dev
;
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
101 * I915_GEM_DOMAIN_COMMAND may not exist?
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
117 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
118 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
119 cmd
&= ~MI_NO_WRITE_FLUSH
;
120 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
123 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
124 (IS_G4X(dev
) || IS_GEN5(dev
)))
125 cmd
|= MI_INVALIDATE_ISP
;
127 ret
= intel_ring_begin(ring
, 2);
131 intel_ring_emit(ring
, cmd
);
132 intel_ring_emit(ring
, MI_NOOP
);
133 intel_ring_advance(ring
);
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
151 * And the workaround for these two requires this workaround first:
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer
*ring
)
178 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 128;
182 ret
= intel_ring_begin(ring
, 6);
186 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
188 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
189 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
190 intel_ring_emit(ring
, 0); /* low dword */
191 intel_ring_emit(ring
, 0); /* high dword */
192 intel_ring_emit(ring
, MI_NOOP
);
193 intel_ring_advance(ring
);
195 ret
= intel_ring_begin(ring
, 6);
199 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
201 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
202 intel_ring_emit(ring
, 0);
203 intel_ring_emit(ring
, 0);
204 intel_ring_emit(ring
, MI_NOOP
);
205 intel_ring_advance(ring
);
211 gen6_render_ring_flush(struct intel_ring_buffer
*ring
,
212 u32 invalidate_domains
, u32 flush_domains
)
215 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 128;
218 /* Force SNB workarounds for PIPE_CONTROL flushes */
219 ret
= intel_emit_post_sync_nonzero_flush(ring
);
223 /* Just flush everything. Experiments have shown that reducing the
224 * number of bits based on the write domains has little performance
228 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
229 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
231 * Ensure that any following seqno writes only happen
232 * when the render cache is indeed flushed.
234 flags
|= PIPE_CONTROL_CS_STALL
;
236 if (invalidate_domains
) {
237 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
238 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
239 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
240 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
241 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
242 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
244 * TLB invalidate requires a post-sync write.
246 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
249 ret
= intel_ring_begin(ring
, 4);
253 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
254 intel_ring_emit(ring
, flags
);
255 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
256 intel_ring_emit(ring
, 0);
257 intel_ring_advance(ring
);
263 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer
*ring
)
267 ret
= intel_ring_begin(ring
, 4);
271 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
272 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
273 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
274 intel_ring_emit(ring
, 0);
275 intel_ring_emit(ring
, 0);
276 intel_ring_advance(ring
);
281 static int gen7_ring_fbc_flush(struct intel_ring_buffer
*ring
, u32 value
)
285 if (!ring
->fbc_dirty
)
288 ret
= intel_ring_begin(ring
, 6);
291 /* WaFbcNukeOn3DBlt:ivb/hsw */
292 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
293 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
294 intel_ring_emit(ring
, value
);
295 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT
);
296 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
297 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
298 intel_ring_advance(ring
);
300 ring
->fbc_dirty
= false;
305 gen7_render_ring_flush(struct intel_ring_buffer
*ring
,
306 u32 invalidate_domains
, u32 flush_domains
)
309 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 128;
313 * Ensure that any following seqno writes only happen when the render
314 * cache is indeed flushed.
316 * Workaround: 4th PIPE_CONTROL command (except the ones with only
317 * read-cache invalidate bits set) must have the CS_STALL bit set. We
318 * don't try to be clever and just set it unconditionally.
320 flags
|= PIPE_CONTROL_CS_STALL
;
322 /* Just flush everything. Experiments have shown that reducing the
323 * number of bits based on the write domains has little performance
327 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
328 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
330 if (invalidate_domains
) {
331 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
332 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
333 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
334 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
335 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
336 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
338 * TLB invalidate requires a post-sync write.
340 flags
|= PIPE_CONTROL_QW_WRITE
;
341 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
343 /* Workaround: we must issue a pipe_control with CS-stall bit
344 * set before a pipe_control command that has the state cache
345 * invalidate bit set. */
346 gen7_render_ring_cs_stall_wa(ring
);
349 ret
= intel_ring_begin(ring
, 4);
353 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
354 intel_ring_emit(ring
, flags
);
355 intel_ring_emit(ring
, scratch_addr
);
356 intel_ring_emit(ring
, 0);
357 intel_ring_advance(ring
);
359 if (!invalidate_domains
&& flush_domains
)
360 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
366 gen8_render_ring_flush(struct intel_ring_buffer
*ring
,
367 u32 invalidate_domains
, u32 flush_domains
)
370 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 128;
373 flags
|= PIPE_CONTROL_CS_STALL
;
376 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
377 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
379 if (invalidate_domains
) {
380 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
381 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
382 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
383 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
384 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
385 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
386 flags
|= PIPE_CONTROL_QW_WRITE
;
387 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
390 ret
= intel_ring_begin(ring
, 6);
394 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
395 intel_ring_emit(ring
, flags
);
396 intel_ring_emit(ring
, scratch_addr
);
397 intel_ring_emit(ring
, 0);
398 intel_ring_emit(ring
, 0);
399 intel_ring_emit(ring
, 0);
400 intel_ring_advance(ring
);
406 static void ring_write_tail(struct intel_ring_buffer
*ring
,
409 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
410 I915_WRITE_TAIL(ring
, value
);
413 u32
intel_ring_get_active_head(struct intel_ring_buffer
*ring
)
415 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
416 u32 acthd_reg
= INTEL_INFO(ring
->dev
)->gen
>= 4 ?
417 RING_ACTHD(ring
->mmio_base
) : ACTHD
;
419 return I915_READ(acthd_reg
);
422 static void ring_setup_phys_status_page(struct intel_ring_buffer
*ring
)
424 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
427 addr
= dev_priv
->status_page_dmah
->busaddr
;
428 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
429 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
430 I915_WRITE(HWS_PGA
, addr
);
433 static int init_ring_common(struct intel_ring_buffer
*ring
)
435 struct drm_device
*dev
= ring
->dev
;
436 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
437 struct drm_i915_gem_object
*obj
= ring
->obj
;
441 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
443 if (I915_NEED_GFX_HWS(dev
))
444 intel_ring_setup_status_page(ring
);
446 ring_setup_phys_status_page(ring
);
448 /* Stop the ring if it's running. */
449 I915_WRITE_CTL(ring
, 0);
450 I915_WRITE_HEAD(ring
, 0);
451 ring
->write_tail(ring
, 0);
453 head
= I915_READ_HEAD(ring
) & HEAD_ADDR
;
455 /* G45 ring initialization fails to reset head to zero */
457 DRM_DEBUG_KMS("%s head not reset to zero "
458 "ctl %08x head %08x tail %08x start %08x\n",
461 I915_READ_HEAD(ring
),
462 I915_READ_TAIL(ring
),
463 I915_READ_START(ring
));
465 I915_WRITE_HEAD(ring
, 0);
467 if (I915_READ_HEAD(ring
) & HEAD_ADDR
) {
468 DRM_ERROR("failed to set %s head to zero "
469 "ctl %08x head %08x tail %08x start %08x\n",
472 I915_READ_HEAD(ring
),
473 I915_READ_TAIL(ring
),
474 I915_READ_START(ring
));
478 /* Initialize the ring. This must happen _after_ we've cleared the ring
479 * registers with the above sequence (the readback of the HEAD registers
480 * also enforces ordering), otherwise the hw might lose the new ring
481 * register values. */
482 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
484 ((ring
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
487 /* If the head is still not zero, the ring is dead */
488 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
489 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
490 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
491 DRM_ERROR("%s initialization failed "
492 "ctl %08x head %08x tail %08x start %08x\n",
495 I915_READ_HEAD(ring
),
496 I915_READ_TAIL(ring
),
497 I915_READ_START(ring
));
502 if (!drm_core_check_feature(ring
->dev
, DRIVER_MODESET
))
503 i915_kernel_lost_context(ring
->dev
);
505 ring
->head
= I915_READ_HEAD(ring
);
506 ring
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
507 ring
->space
= ring_space(ring
);
508 ring
->last_retired_head
= -1;
511 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
514 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
520 init_pipe_control(struct intel_ring_buffer
*ring
)
524 if (ring
->scratch
.obj
)
527 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
528 if (ring
->scratch
.obj
== NULL
) {
529 DRM_ERROR("Failed to allocate seqno page\n");
534 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
538 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
542 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
543 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
544 if (ring
->scratch
.cpu_page
== NULL
) {
549 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
550 ring
->name
, ring
->scratch
.gtt_offset
);
554 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
556 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
561 static int init_render_ring(struct intel_ring_buffer
*ring
)
563 struct drm_device
*dev
= ring
->dev
;
564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
565 int ret
= init_ring_common(ring
);
567 if (INTEL_INFO(dev
)->gen
> 3)
568 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
570 /* We need to disable the AsyncFlip performance optimisations in order
571 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
572 * programmed to '1' on all products.
574 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
576 if (INTEL_INFO(dev
)->gen
>= 6)
577 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
579 /* Required for the hardware to program scanline values for waiting */
580 if (INTEL_INFO(dev
)->gen
== 6)
582 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS
));
585 I915_WRITE(GFX_MODE_GEN7
,
586 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS
) |
587 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
589 if (INTEL_INFO(dev
)->gen
>= 5) {
590 ret
= init_pipe_control(ring
);
596 /* From the Sandybridge PRM, volume 1 part 3, page 24:
597 * "If this bit is set, STCunit will have LRA as replacement
598 * policy. [...] This bit must be reset. LRA replacement
599 * policy is not supported."
601 I915_WRITE(CACHE_MODE_0
,
602 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
604 /* This is not explicitly set for GEN6, so read the register.
605 * see intel_ring_mi_set_context() for why we care.
606 * TODO: consider explicitly setting the bit for GEN5
608 ring
->itlb_before_ctx_switch
=
609 !!(I915_READ(GFX_MODE
) & GFX_TLB_INVALIDATE_ALWAYS
);
612 if (INTEL_INFO(dev
)->gen
>= 6)
613 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
616 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
621 static void render_ring_cleanup(struct intel_ring_buffer
*ring
)
623 struct drm_device
*dev
= ring
->dev
;
625 if (ring
->scratch
.obj
== NULL
)
628 if (INTEL_INFO(dev
)->gen
>= 5) {
629 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
630 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
633 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
634 ring
->scratch
.obj
= NULL
;
638 update_mboxes(struct intel_ring_buffer
*ring
,
641 /* NB: In order to be able to do semaphore MBOX updates for varying number
642 * of rings, it's easiest if we round up each individual update to a
643 * multiple of 2 (since ring updates must always be a multiple of 2)
644 * even though the actual update only requires 3 dwords.
646 #define MBOX_UPDATE_DWORDS 4
647 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
648 intel_ring_emit(ring
, mmio_offset
);
649 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
650 intel_ring_emit(ring
, MI_NOOP
);
654 * gen6_add_request - Update the semaphore mailbox registers
656 * @ring - ring that is adding a request
657 * @seqno - return seqno stuck into the ring
659 * Update the mailbox registers in the *other* rings with the current seqno.
660 * This acts like a signal in the canonical semaphore.
663 gen6_add_request(struct intel_ring_buffer
*ring
)
665 struct drm_device
*dev
= ring
->dev
;
666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
667 struct intel_ring_buffer
*useless
;
668 int i
, ret
, num_dwords
= 4;
670 if (i915_semaphore_is_enabled(dev
))
671 num_dwords
+= ((I915_NUM_RINGS
-1) * MBOX_UPDATE_DWORDS
);
672 #undef MBOX_UPDATE_DWORDS
674 ret
= intel_ring_begin(ring
, num_dwords
);
678 if (i915_semaphore_is_enabled(dev
)) {
679 for_each_ring(useless
, dev_priv
, i
) {
680 u32 mbox_reg
= ring
->signal_mbox
[i
];
681 if (mbox_reg
!= GEN6_NOSYNC
)
682 update_mboxes(ring
, mbox_reg
);
686 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
687 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
688 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
689 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
690 __intel_ring_advance(ring
);
695 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
699 return dev_priv
->last_seqno
< seqno
;
703 * intel_ring_sync - sync the waiter to the signaller on seqno
705 * @waiter - ring that is waiting
706 * @signaller - ring which has, or will signal
707 * @seqno - seqno which the waiter will block on
710 gen6_ring_sync(struct intel_ring_buffer
*waiter
,
711 struct intel_ring_buffer
*signaller
,
715 u32 dw1
= MI_SEMAPHORE_MBOX
|
716 MI_SEMAPHORE_COMPARE
|
717 MI_SEMAPHORE_REGISTER
;
719 /* Throughout all of the GEM code, seqno passed implies our current
720 * seqno is >= the last seqno executed. However for hardware the
721 * comparison is strictly greater than.
725 WARN_ON(signaller
->semaphore_register
[waiter
->id
] ==
726 MI_SEMAPHORE_SYNC_INVALID
);
728 ret
= intel_ring_begin(waiter
, 4);
732 /* If seqno wrap happened, omit the wait with no-ops */
733 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
734 intel_ring_emit(waiter
,
736 signaller
->semaphore_register
[waiter
->id
]);
737 intel_ring_emit(waiter
, seqno
);
738 intel_ring_emit(waiter
, 0);
739 intel_ring_emit(waiter
, MI_NOOP
);
741 intel_ring_emit(waiter
, MI_NOOP
);
742 intel_ring_emit(waiter
, MI_NOOP
);
743 intel_ring_emit(waiter
, MI_NOOP
);
744 intel_ring_emit(waiter
, MI_NOOP
);
746 intel_ring_advance(waiter
);
751 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
753 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
754 PIPE_CONTROL_DEPTH_STALL); \
755 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
756 intel_ring_emit(ring__, 0); \
757 intel_ring_emit(ring__, 0); \
761 pc_render_add_request(struct intel_ring_buffer
*ring
)
763 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 128;
766 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
767 * incoherent with writes to memory, i.e. completely fubar,
768 * so we need to use PIPE_NOTIFY instead.
770 * However, we also need to workaround the qword write
771 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
772 * memory before requesting an interrupt.
774 ret
= intel_ring_begin(ring
, 32);
778 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
779 PIPE_CONTROL_WRITE_FLUSH
|
780 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
781 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
782 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
783 intel_ring_emit(ring
, 0);
784 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
785 scratch_addr
+= 128; /* write to separate cachelines */
786 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
788 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
790 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
792 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
794 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
796 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
797 PIPE_CONTROL_WRITE_FLUSH
|
798 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
799 PIPE_CONTROL_NOTIFY
);
800 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
801 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
802 intel_ring_emit(ring
, 0);
803 __intel_ring_advance(ring
);
809 gen6_ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
811 /* Workaround to force correct ordering between irq and seqno writes on
812 * ivb (and maybe also on snb) by reading from a CS register (like
813 * ACTHD) before reading the status page. */
815 intel_ring_get_active_head(ring
);
816 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
820 ring_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
822 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
826 ring_set_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
828 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
832 pc_render_get_seqno(struct intel_ring_buffer
*ring
, bool lazy_coherency
)
834 return ring
->scratch
.cpu_page
[0];
838 pc_render_set_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
840 ring
->scratch
.cpu_page
[0] = seqno
;
844 gen5_ring_get_irq(struct intel_ring_buffer
*ring
)
846 struct drm_device
*dev
= ring
->dev
;
847 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
850 if (!dev
->irq_enabled
)
853 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
854 if (ring
->irq_refcount
++ == 0)
855 ilk_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
856 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
862 gen5_ring_put_irq(struct intel_ring_buffer
*ring
)
864 struct drm_device
*dev
= ring
->dev
;
865 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
868 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
869 if (--ring
->irq_refcount
== 0)
870 ilk_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
871 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
875 i9xx_ring_get_irq(struct intel_ring_buffer
*ring
)
877 struct drm_device
*dev
= ring
->dev
;
878 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
881 if (!dev
->irq_enabled
)
884 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
885 if (ring
->irq_refcount
++ == 0) {
886 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
887 I915_WRITE(IMR
, dev_priv
->irq_mask
);
890 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
896 i9xx_ring_put_irq(struct intel_ring_buffer
*ring
)
898 struct drm_device
*dev
= ring
->dev
;
899 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
902 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
903 if (--ring
->irq_refcount
== 0) {
904 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
905 I915_WRITE(IMR
, dev_priv
->irq_mask
);
908 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
912 i8xx_ring_get_irq(struct intel_ring_buffer
*ring
)
914 struct drm_device
*dev
= ring
->dev
;
915 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
918 if (!dev
->irq_enabled
)
921 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
922 if (ring
->irq_refcount
++ == 0) {
923 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
924 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
927 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
933 i8xx_ring_put_irq(struct intel_ring_buffer
*ring
)
935 struct drm_device
*dev
= ring
->dev
;
936 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
939 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
940 if (--ring
->irq_refcount
== 0) {
941 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
942 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
945 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
948 void intel_ring_setup_status_page(struct intel_ring_buffer
*ring
)
950 struct drm_device
*dev
= ring
->dev
;
951 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
954 /* The ring status page addresses are no longer next to the rest of
955 * the ring registers as of gen7.
960 mmio
= RENDER_HWS_PGA_GEN7
;
963 mmio
= BLT_HWS_PGA_GEN7
;
966 mmio
= BSD_HWS_PGA_GEN7
;
969 mmio
= VEBOX_HWS_PGA_GEN7
;
972 } else if (IS_GEN6(ring
->dev
)) {
973 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
975 /* XXX: gen8 returns to sanity */
976 mmio
= RING_HWS_PGA(ring
->mmio_base
);
979 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
982 /* Flush the TLB for this page */
983 if (INTEL_INFO(dev
)->gen
>= 6) {
984 u32 reg
= RING_INSTPM(ring
->mmio_base
);
986 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
988 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
990 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
996 bsd_ring_flush(struct intel_ring_buffer
*ring
,
997 u32 invalidate_domains
,
1002 ret
= intel_ring_begin(ring
, 2);
1006 intel_ring_emit(ring
, MI_FLUSH
);
1007 intel_ring_emit(ring
, MI_NOOP
);
1008 intel_ring_advance(ring
);
1013 i9xx_add_request(struct intel_ring_buffer
*ring
)
1017 ret
= intel_ring_begin(ring
, 4);
1021 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1022 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1023 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1024 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1025 __intel_ring_advance(ring
);
1031 gen6_ring_get_irq(struct intel_ring_buffer
*ring
)
1033 struct drm_device
*dev
= ring
->dev
;
1034 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1035 unsigned long flags
;
1037 if (!dev
->irq_enabled
)
1040 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1041 if (ring
->irq_refcount
++ == 0) {
1042 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1043 I915_WRITE_IMR(ring
,
1044 ~(ring
->irq_enable_mask
|
1045 GT_PARITY_ERROR(dev
)));
1047 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1048 ilk_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1050 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1056 gen6_ring_put_irq(struct intel_ring_buffer
*ring
)
1058 struct drm_device
*dev
= ring
->dev
;
1059 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1060 unsigned long flags
;
1062 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1063 if (--ring
->irq_refcount
== 0) {
1064 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1065 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1067 I915_WRITE_IMR(ring
, ~0);
1068 ilk_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1070 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1074 hsw_vebox_get_irq(struct intel_ring_buffer
*ring
)
1076 struct drm_device
*dev
= ring
->dev
;
1077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1078 unsigned long flags
;
1080 if (!dev
->irq_enabled
)
1083 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1084 if (ring
->irq_refcount
++ == 0) {
1085 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1086 snb_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1088 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1094 hsw_vebox_put_irq(struct intel_ring_buffer
*ring
)
1096 struct drm_device
*dev
= ring
->dev
;
1097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1098 unsigned long flags
;
1100 if (!dev
->irq_enabled
)
1103 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1104 if (--ring
->irq_refcount
== 0) {
1105 I915_WRITE_IMR(ring
, ~0);
1106 snb_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1108 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1112 gen8_ring_get_irq(struct intel_ring_buffer
*ring
)
1114 struct drm_device
*dev
= ring
->dev
;
1115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1116 unsigned long flags
;
1118 if (!dev
->irq_enabled
)
1121 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1122 if (ring
->irq_refcount
++ == 0) {
1123 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1124 I915_WRITE_IMR(ring
,
1125 ~(ring
->irq_enable_mask
|
1126 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1128 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1130 POSTING_READ(RING_IMR(ring
->mmio_base
));
1132 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1138 gen8_ring_put_irq(struct intel_ring_buffer
*ring
)
1140 struct drm_device
*dev
= ring
->dev
;
1141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1142 unsigned long flags
;
1144 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1145 if (--ring
->irq_refcount
== 0) {
1146 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1147 I915_WRITE_IMR(ring
,
1148 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1150 I915_WRITE_IMR(ring
, ~0);
1152 POSTING_READ(RING_IMR(ring
->mmio_base
));
1154 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1158 i965_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1159 u32 offset
, u32 length
,
1164 ret
= intel_ring_begin(ring
, 2);
1168 intel_ring_emit(ring
,
1169 MI_BATCH_BUFFER_START
|
1171 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1172 intel_ring_emit(ring
, offset
);
1173 intel_ring_advance(ring
);
1178 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1179 #define I830_BATCH_LIMIT (256*1024)
1181 i830_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1182 u32 offset
, u32 len
,
1187 if (flags
& I915_DISPATCH_PINNED
) {
1188 ret
= intel_ring_begin(ring
, 4);
1192 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1193 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1194 intel_ring_emit(ring
, offset
+ len
- 8);
1195 intel_ring_emit(ring
, MI_NOOP
);
1196 intel_ring_advance(ring
);
1198 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1200 if (len
> I830_BATCH_LIMIT
)
1203 ret
= intel_ring_begin(ring
, 9+3);
1206 /* Blit the batch (which has now all relocs applied) to the stable batch
1207 * scratch bo area (so that the CS never stumbles over its tlb
1208 * invalidation bug) ... */
1209 intel_ring_emit(ring
, XY_SRC_COPY_BLT_CMD
|
1210 XY_SRC_COPY_BLT_WRITE_ALPHA
|
1211 XY_SRC_COPY_BLT_WRITE_RGB
);
1212 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_GXCOPY
| 4096);
1213 intel_ring_emit(ring
, 0);
1214 intel_ring_emit(ring
, (DIV_ROUND_UP(len
, 4096) << 16) | 1024);
1215 intel_ring_emit(ring
, cs_offset
);
1216 intel_ring_emit(ring
, 0);
1217 intel_ring_emit(ring
, 4096);
1218 intel_ring_emit(ring
, offset
);
1219 intel_ring_emit(ring
, MI_FLUSH
);
1221 /* ... and execute it. */
1222 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1223 intel_ring_emit(ring
, cs_offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1224 intel_ring_emit(ring
, cs_offset
+ len
- 8);
1225 intel_ring_advance(ring
);
1232 i915_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1233 u32 offset
, u32 len
,
1238 ret
= intel_ring_begin(ring
, 2);
1242 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1243 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1244 intel_ring_advance(ring
);
1249 static void cleanup_status_page(struct intel_ring_buffer
*ring
)
1251 struct drm_i915_gem_object
*obj
;
1253 obj
= ring
->status_page
.obj
;
1257 kunmap(sg_page(obj
->pages
->sgl
));
1258 i915_gem_object_ggtt_unpin(obj
);
1259 drm_gem_object_unreference(&obj
->base
);
1260 ring
->status_page
.obj
= NULL
;
1263 static int init_status_page(struct intel_ring_buffer
*ring
)
1265 struct drm_device
*dev
= ring
->dev
;
1266 struct drm_i915_gem_object
*obj
;
1269 obj
= i915_gem_alloc_object(dev
, 4096);
1271 DRM_ERROR("Failed to allocate status page\n");
1276 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1280 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, 0);
1284 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1285 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1286 if (ring
->status_page
.page_addr
== NULL
) {
1290 ring
->status_page
.obj
= obj
;
1291 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1293 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1294 ring
->name
, ring
->status_page
.gfx_addr
);
1299 i915_gem_object_ggtt_unpin(obj
);
1301 drm_gem_object_unreference(&obj
->base
);
1306 static int init_phys_status_page(struct intel_ring_buffer
*ring
)
1308 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1310 if (!dev_priv
->status_page_dmah
) {
1311 dev_priv
->status_page_dmah
=
1312 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1313 if (!dev_priv
->status_page_dmah
)
1317 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1318 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1323 static int intel_init_ring_buffer(struct drm_device
*dev
,
1324 struct intel_ring_buffer
*ring
)
1326 struct drm_i915_gem_object
*obj
;
1327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1331 INIT_LIST_HEAD(&ring
->active_list
);
1332 INIT_LIST_HEAD(&ring
->request_list
);
1333 ring
->size
= 32 * PAGE_SIZE
;
1334 memset(ring
->sync_seqno
, 0, sizeof(ring
->sync_seqno
));
1336 init_waitqueue_head(&ring
->irq_queue
);
1338 if (I915_NEED_GFX_HWS(dev
)) {
1339 ret
= init_status_page(ring
);
1343 BUG_ON(ring
->id
!= RCS
);
1344 ret
= init_phys_status_page(ring
);
1351 obj
= i915_gem_object_create_stolen(dev
, ring
->size
);
1353 obj
= i915_gem_alloc_object(dev
, ring
->size
);
1355 DRM_ERROR("Failed to allocate ringbuffer\n");
1362 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
1366 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1370 ring
->virtual_start
=
1371 ioremap_wc(dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
),
1373 if (ring
->virtual_start
== NULL
) {
1374 DRM_ERROR("Failed to map ringbuffer.\n");
1379 ret
= ring
->init(ring
);
1383 /* Workaround an erratum on the i830 which causes a hang if
1384 * the TAIL pointer points to within the last 2 cachelines
1387 ring
->effective_size
= ring
->size
;
1388 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
1389 ring
->effective_size
-= 128;
1391 i915_cmd_parser_init_ring(ring
);
1396 iounmap(ring
->virtual_start
);
1398 i915_gem_object_ggtt_unpin(obj
);
1400 drm_gem_object_unreference(&obj
->base
);
1403 cleanup_status_page(ring
);
1407 void intel_cleanup_ring_buffer(struct intel_ring_buffer
*ring
)
1409 struct drm_i915_private
*dev_priv
;
1412 if (ring
->obj
== NULL
)
1415 /* Disable the ring buffer. The ring must be idle at this point */
1416 dev_priv
= ring
->dev
->dev_private
;
1417 ret
= intel_ring_idle(ring
);
1418 if (ret
&& !i915_reset_in_progress(&dev_priv
->gpu_error
))
1419 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1422 I915_WRITE_CTL(ring
, 0);
1424 iounmap(ring
->virtual_start
);
1426 i915_gem_object_ggtt_unpin(ring
->obj
);
1427 drm_gem_object_unreference(&ring
->obj
->base
);
1429 ring
->preallocated_lazy_request
= NULL
;
1430 ring
->outstanding_lazy_seqno
= 0;
1433 ring
->cleanup(ring
);
1435 cleanup_status_page(ring
);
1438 static int intel_ring_wait_request(struct intel_ring_buffer
*ring
, int n
)
1440 struct drm_i915_gem_request
*request
;
1441 u32 seqno
= 0, tail
;
1444 if (ring
->last_retired_head
!= -1) {
1445 ring
->head
= ring
->last_retired_head
;
1446 ring
->last_retired_head
= -1;
1448 ring
->space
= ring_space(ring
);
1449 if (ring
->space
>= n
)
1453 list_for_each_entry(request
, &ring
->request_list
, list
) {
1456 if (request
->tail
== -1)
1459 space
= request
->tail
- (ring
->tail
+ I915_RING_FREE_SPACE
);
1461 space
+= ring
->size
;
1463 seqno
= request
->seqno
;
1464 tail
= request
->tail
;
1468 /* Consume this request in case we need more space than
1469 * is available and so need to prevent a race between
1470 * updating last_retired_head and direct reads of
1471 * I915_RING_HEAD. It also provides a nice sanity check.
1479 ret
= i915_wait_seqno(ring
, seqno
);
1484 ring
->space
= ring_space(ring
);
1485 if (WARN_ON(ring
->space
< n
))
1491 static int ring_wait_for_space(struct intel_ring_buffer
*ring
, int n
)
1493 struct drm_device
*dev
= ring
->dev
;
1494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1498 ret
= intel_ring_wait_request(ring
, n
);
1502 /* force the tail write in case we have been skipping them */
1503 __intel_ring_advance(ring
);
1505 trace_i915_ring_wait_begin(ring
);
1506 /* With GEM the hangcheck timer should kick us out of the loop,
1507 * leaving it early runs the risk of corrupting GEM state (due
1508 * to running on almost untested codepaths). But on resume
1509 * timers don't work yet, so prevent a complete hang in that
1510 * case by choosing an insanely large timeout. */
1511 end
= jiffies
+ 60 * HZ
;
1514 ring
->head
= I915_READ_HEAD(ring
);
1515 ring
->space
= ring_space(ring
);
1516 if (ring
->space
>= n
) {
1517 trace_i915_ring_wait_end(ring
);
1521 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) &&
1522 dev
->primary
->master
) {
1523 struct drm_i915_master_private
*master_priv
= dev
->primary
->master
->driver_priv
;
1524 if (master_priv
->sarea_priv
)
1525 master_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
1530 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1531 dev_priv
->mm
.interruptible
);
1534 } while (!time_after(jiffies
, end
));
1535 trace_i915_ring_wait_end(ring
);
1539 static int intel_wrap_ring_buffer(struct intel_ring_buffer
*ring
)
1541 uint32_t __iomem
*virt
;
1542 int rem
= ring
->size
- ring
->tail
;
1544 if (ring
->space
< rem
) {
1545 int ret
= ring_wait_for_space(ring
, rem
);
1550 virt
= ring
->virtual_start
+ ring
->tail
;
1553 iowrite32(MI_NOOP
, virt
++);
1556 ring
->space
= ring_space(ring
);
1561 int intel_ring_idle(struct intel_ring_buffer
*ring
)
1566 /* We need to add any requests required to flush the objects and ring */
1567 if (ring
->outstanding_lazy_seqno
) {
1568 ret
= i915_add_request(ring
, NULL
);
1573 /* Wait upon the last request to be completed */
1574 if (list_empty(&ring
->request_list
))
1577 seqno
= list_entry(ring
->request_list
.prev
,
1578 struct drm_i915_gem_request
,
1581 return i915_wait_seqno(ring
, seqno
);
1585 intel_ring_alloc_seqno(struct intel_ring_buffer
*ring
)
1587 if (ring
->outstanding_lazy_seqno
)
1590 if (ring
->preallocated_lazy_request
== NULL
) {
1591 struct drm_i915_gem_request
*request
;
1593 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
1594 if (request
== NULL
)
1597 ring
->preallocated_lazy_request
= request
;
1600 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_seqno
);
1603 static int __intel_ring_prepare(struct intel_ring_buffer
*ring
,
1608 if (unlikely(ring
->tail
+ bytes
> ring
->effective_size
)) {
1609 ret
= intel_wrap_ring_buffer(ring
);
1614 if (unlikely(ring
->space
< bytes
)) {
1615 ret
= ring_wait_for_space(ring
, bytes
);
1623 int intel_ring_begin(struct intel_ring_buffer
*ring
,
1626 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1629 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1630 dev_priv
->mm
.interruptible
);
1634 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
1638 /* Preallocate the olr before touching the ring */
1639 ret
= intel_ring_alloc_seqno(ring
);
1643 ring
->space
-= num_dwords
* sizeof(uint32_t);
1647 /* Align the ring tail to a cacheline boundary */
1648 int intel_ring_cacheline_align(struct intel_ring_buffer
*ring
)
1650 int num_dwords
= (64 - (ring
->tail
& 63)) / sizeof(uint32_t);
1653 if (num_dwords
== 0)
1656 ret
= intel_ring_begin(ring
, num_dwords
);
1660 while (num_dwords
--)
1661 intel_ring_emit(ring
, MI_NOOP
);
1663 intel_ring_advance(ring
);
1668 void intel_ring_init_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
1670 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1672 BUG_ON(ring
->outstanding_lazy_seqno
);
1674 if (INTEL_INFO(ring
->dev
)->gen
>= 6) {
1675 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
1676 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
1677 if (HAS_VEBOX(ring
->dev
))
1678 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
1681 ring
->set_seqno(ring
, seqno
);
1682 ring
->hangcheck
.seqno
= seqno
;
1685 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer
*ring
,
1688 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1690 /* Every tail move must follow the sequence below */
1692 /* Disable notification that the ring is IDLE. The GT
1693 * will then assume that it is busy and bring it out of rc6.
1695 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1696 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1698 /* Clear the context id. Here be magic! */
1699 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
1701 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1702 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
1703 GEN6_BSD_SLEEP_INDICATOR
) == 0,
1705 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1707 /* Now that the ring is fully powered up, update the tail */
1708 I915_WRITE_TAIL(ring
, value
);
1709 POSTING_READ(RING_TAIL(ring
->mmio_base
));
1711 /* Let the ring send IDLE messages to the GT again,
1712 * and so let it sleep to conserve power when idle.
1714 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
1715 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
1718 static int gen6_bsd_ring_flush(struct intel_ring_buffer
*ring
,
1719 u32 invalidate
, u32 flush
)
1724 ret
= intel_ring_begin(ring
, 4);
1729 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
1732 * Bspec vol 1c.5 - video engine command streamer:
1733 * "If ENABLED, all TLBs will be invalidated once the flush
1734 * operation is complete. This bit is only valid when the
1735 * Post-Sync Operation field is a value of 1h or 3h."
1737 if (invalidate
& I915_GEM_GPU_DOMAINS
)
1738 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
1739 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
1740 intel_ring_emit(ring
, cmd
);
1741 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1742 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
1743 intel_ring_emit(ring
, 0); /* upper addr */
1744 intel_ring_emit(ring
, 0); /* value */
1746 intel_ring_emit(ring
, 0);
1747 intel_ring_emit(ring
, MI_NOOP
);
1749 intel_ring_advance(ring
);
1754 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1755 u32 offset
, u32 len
,
1758 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1759 bool ppgtt
= dev_priv
->mm
.aliasing_ppgtt
!= NULL
&&
1760 !(flags
& I915_DISPATCH_SECURE
);
1763 ret
= intel_ring_begin(ring
, 4);
1767 /* FIXME(BDW): Address space and security selectors. */
1768 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
1769 intel_ring_emit(ring
, offset
);
1770 intel_ring_emit(ring
, 0);
1771 intel_ring_emit(ring
, MI_NOOP
);
1772 intel_ring_advance(ring
);
1778 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1779 u32 offset
, u32 len
,
1784 ret
= intel_ring_begin(ring
, 2);
1788 intel_ring_emit(ring
,
1789 MI_BATCH_BUFFER_START
| MI_BATCH_PPGTT_HSW
|
1790 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_HSW
));
1791 /* bit0-7 is the length on GEN6+ */
1792 intel_ring_emit(ring
, offset
);
1793 intel_ring_advance(ring
);
1799 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer
*ring
,
1800 u32 offset
, u32 len
,
1805 ret
= intel_ring_begin(ring
, 2);
1809 intel_ring_emit(ring
,
1810 MI_BATCH_BUFFER_START
|
1811 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1812 /* bit0-7 is the length on GEN6+ */
1813 intel_ring_emit(ring
, offset
);
1814 intel_ring_advance(ring
);
1819 /* Blitter support (SandyBridge+) */
1821 static int gen6_ring_flush(struct intel_ring_buffer
*ring
,
1822 u32 invalidate
, u32 flush
)
1824 struct drm_device
*dev
= ring
->dev
;
1828 ret
= intel_ring_begin(ring
, 4);
1833 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
1836 * Bspec vol 1c.3 - blitter engine command streamer:
1837 * "If ENABLED, all TLBs will be invalidated once the flush
1838 * operation is complete. This bit is only valid when the
1839 * Post-Sync Operation field is a value of 1h or 3h."
1841 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
1842 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
1843 MI_FLUSH_DW_OP_STOREDW
;
1844 intel_ring_emit(ring
, cmd
);
1845 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
1846 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
1847 intel_ring_emit(ring
, 0); /* upper addr */
1848 intel_ring_emit(ring
, 0); /* value */
1850 intel_ring_emit(ring
, 0);
1851 intel_ring_emit(ring
, MI_NOOP
);
1853 intel_ring_advance(ring
);
1855 if (IS_GEN7(dev
) && !invalidate
&& flush
)
1856 return gen7_ring_fbc_flush(ring
, FBC_REND_CACHE_CLEAN
);
1861 int intel_init_render_ring_buffer(struct drm_device
*dev
)
1863 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1864 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1866 ring
->name
= "render ring";
1868 ring
->mmio_base
= RENDER_RING_BASE
;
1870 if (INTEL_INFO(dev
)->gen
>= 6) {
1871 ring
->add_request
= gen6_add_request
;
1872 ring
->flush
= gen7_render_ring_flush
;
1873 if (INTEL_INFO(dev
)->gen
== 6)
1874 ring
->flush
= gen6_render_ring_flush
;
1875 if (INTEL_INFO(dev
)->gen
>= 8) {
1876 ring
->flush
= gen8_render_ring_flush
;
1877 ring
->irq_get
= gen8_ring_get_irq
;
1878 ring
->irq_put
= gen8_ring_put_irq
;
1880 ring
->irq_get
= gen6_ring_get_irq
;
1881 ring
->irq_put
= gen6_ring_put_irq
;
1883 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
1884 ring
->get_seqno
= gen6_ring_get_seqno
;
1885 ring
->set_seqno
= ring_set_seqno
;
1886 ring
->sync_to
= gen6_ring_sync
;
1887 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
1888 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
1889 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
1890 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
1891 ring
->signal_mbox
[RCS
] = GEN6_NOSYNC
;
1892 ring
->signal_mbox
[VCS
] = GEN6_VRSYNC
;
1893 ring
->signal_mbox
[BCS
] = GEN6_BRSYNC
;
1894 ring
->signal_mbox
[VECS
] = GEN6_VERSYNC
;
1895 } else if (IS_GEN5(dev
)) {
1896 ring
->add_request
= pc_render_add_request
;
1897 ring
->flush
= gen4_render_ring_flush
;
1898 ring
->get_seqno
= pc_render_get_seqno
;
1899 ring
->set_seqno
= pc_render_set_seqno
;
1900 ring
->irq_get
= gen5_ring_get_irq
;
1901 ring
->irq_put
= gen5_ring_put_irq
;
1902 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
1903 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
1905 ring
->add_request
= i9xx_add_request
;
1906 if (INTEL_INFO(dev
)->gen
< 4)
1907 ring
->flush
= gen2_render_ring_flush
;
1909 ring
->flush
= gen4_render_ring_flush
;
1910 ring
->get_seqno
= ring_get_seqno
;
1911 ring
->set_seqno
= ring_set_seqno
;
1913 ring
->irq_get
= i8xx_ring_get_irq
;
1914 ring
->irq_put
= i8xx_ring_put_irq
;
1916 ring
->irq_get
= i9xx_ring_get_irq
;
1917 ring
->irq_put
= i9xx_ring_put_irq
;
1919 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1921 ring
->write_tail
= ring_write_tail
;
1922 if (IS_HASWELL(dev
))
1923 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
1924 else if (IS_GEN8(dev
))
1925 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
1926 else if (INTEL_INFO(dev
)->gen
>= 6)
1927 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
1928 else if (INTEL_INFO(dev
)->gen
>= 4)
1929 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1930 else if (IS_I830(dev
) || IS_845G(dev
))
1931 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
1933 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
1934 ring
->init
= init_render_ring
;
1935 ring
->cleanup
= render_ring_cleanup
;
1937 /* Workaround batchbuffer to combat CS tlb bug. */
1938 if (HAS_BROKEN_CS_TLB(dev
)) {
1939 struct drm_i915_gem_object
*obj
;
1942 obj
= i915_gem_alloc_object(dev
, I830_BATCH_LIMIT
);
1944 DRM_ERROR("Failed to allocate batch bo\n");
1948 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
1950 drm_gem_object_unreference(&obj
->base
);
1951 DRM_ERROR("Failed to ping batch bo\n");
1955 ring
->scratch
.obj
= obj
;
1956 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
1959 return intel_init_ring_buffer(dev
, ring
);
1962 int intel_render_ring_init_dri(struct drm_device
*dev
, u64 start
, u32 size
)
1964 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1965 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
1968 ring
->name
= "render ring";
1970 ring
->mmio_base
= RENDER_RING_BASE
;
1972 if (INTEL_INFO(dev
)->gen
>= 6) {
1973 /* non-kms not supported on gen6+ */
1977 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1978 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1979 * the special gen5 functions. */
1980 ring
->add_request
= i9xx_add_request
;
1981 if (INTEL_INFO(dev
)->gen
< 4)
1982 ring
->flush
= gen2_render_ring_flush
;
1984 ring
->flush
= gen4_render_ring_flush
;
1985 ring
->get_seqno
= ring_get_seqno
;
1986 ring
->set_seqno
= ring_set_seqno
;
1988 ring
->irq_get
= i8xx_ring_get_irq
;
1989 ring
->irq_put
= i8xx_ring_put_irq
;
1991 ring
->irq_get
= i9xx_ring_get_irq
;
1992 ring
->irq_put
= i9xx_ring_put_irq
;
1994 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
1995 ring
->write_tail
= ring_write_tail
;
1996 if (INTEL_INFO(dev
)->gen
>= 4)
1997 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
1998 else if (IS_I830(dev
) || IS_845G(dev
))
1999 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2001 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2002 ring
->init
= init_render_ring
;
2003 ring
->cleanup
= render_ring_cleanup
;
2006 INIT_LIST_HEAD(&ring
->active_list
);
2007 INIT_LIST_HEAD(&ring
->request_list
);
2010 ring
->effective_size
= ring
->size
;
2011 if (IS_I830(ring
->dev
) || IS_845G(ring
->dev
))
2012 ring
->effective_size
-= 128;
2014 ring
->virtual_start
= ioremap_wc(start
, size
);
2015 if (ring
->virtual_start
== NULL
) {
2016 DRM_ERROR("can not ioremap virtual address for"
2021 if (!I915_NEED_GFX_HWS(dev
)) {
2022 ret
= init_phys_status_page(ring
);
2030 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2032 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2033 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VCS
];
2035 ring
->name
= "bsd ring";
2038 ring
->write_tail
= ring_write_tail
;
2039 if (INTEL_INFO(dev
)->gen
>= 6) {
2040 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2041 /* gen6 bsd needs a special wa for tail updates */
2043 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2044 ring
->flush
= gen6_bsd_ring_flush
;
2045 ring
->add_request
= gen6_add_request
;
2046 ring
->get_seqno
= gen6_ring_get_seqno
;
2047 ring
->set_seqno
= ring_set_seqno
;
2048 if (INTEL_INFO(dev
)->gen
>= 8) {
2049 ring
->irq_enable_mask
=
2050 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2051 ring
->irq_get
= gen8_ring_get_irq
;
2052 ring
->irq_put
= gen8_ring_put_irq
;
2053 ring
->dispatch_execbuffer
=
2054 gen8_ring_dispatch_execbuffer
;
2056 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2057 ring
->irq_get
= gen6_ring_get_irq
;
2058 ring
->irq_put
= gen6_ring_put_irq
;
2059 ring
->dispatch_execbuffer
=
2060 gen6_ring_dispatch_execbuffer
;
2062 ring
->sync_to
= gen6_ring_sync
;
2063 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2064 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2065 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2066 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2067 ring
->signal_mbox
[RCS
] = GEN6_RVSYNC
;
2068 ring
->signal_mbox
[VCS
] = GEN6_NOSYNC
;
2069 ring
->signal_mbox
[BCS
] = GEN6_BVSYNC
;
2070 ring
->signal_mbox
[VECS
] = GEN6_VEVSYNC
;
2072 ring
->mmio_base
= BSD_RING_BASE
;
2073 ring
->flush
= bsd_ring_flush
;
2074 ring
->add_request
= i9xx_add_request
;
2075 ring
->get_seqno
= ring_get_seqno
;
2076 ring
->set_seqno
= ring_set_seqno
;
2078 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2079 ring
->irq_get
= gen5_ring_get_irq
;
2080 ring
->irq_put
= gen5_ring_put_irq
;
2082 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2083 ring
->irq_get
= i9xx_ring_get_irq
;
2084 ring
->irq_put
= i9xx_ring_put_irq
;
2086 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2088 ring
->init
= init_ring_common
;
2090 return intel_init_ring_buffer(dev
, ring
);
2093 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2095 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2096 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
2098 ring
->name
= "blitter ring";
2101 ring
->mmio_base
= BLT_RING_BASE
;
2102 ring
->write_tail
= ring_write_tail
;
2103 ring
->flush
= gen6_ring_flush
;
2104 ring
->add_request
= gen6_add_request
;
2105 ring
->get_seqno
= gen6_ring_get_seqno
;
2106 ring
->set_seqno
= ring_set_seqno
;
2107 if (INTEL_INFO(dev
)->gen
>= 8) {
2108 ring
->irq_enable_mask
=
2109 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2110 ring
->irq_get
= gen8_ring_get_irq
;
2111 ring
->irq_put
= gen8_ring_put_irq
;
2112 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2114 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2115 ring
->irq_get
= gen6_ring_get_irq
;
2116 ring
->irq_put
= gen6_ring_put_irq
;
2117 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2119 ring
->sync_to
= gen6_ring_sync
;
2120 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2121 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2122 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2123 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2124 ring
->signal_mbox
[RCS
] = GEN6_RBSYNC
;
2125 ring
->signal_mbox
[VCS
] = GEN6_VBSYNC
;
2126 ring
->signal_mbox
[BCS
] = GEN6_NOSYNC
;
2127 ring
->signal_mbox
[VECS
] = GEN6_VEBSYNC
;
2128 ring
->init
= init_ring_common
;
2130 return intel_init_ring_buffer(dev
, ring
);
2133 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2135 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2136 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[VECS
];
2138 ring
->name
= "video enhancement ring";
2141 ring
->mmio_base
= VEBOX_RING_BASE
;
2142 ring
->write_tail
= ring_write_tail
;
2143 ring
->flush
= gen6_ring_flush
;
2144 ring
->add_request
= gen6_add_request
;
2145 ring
->get_seqno
= gen6_ring_get_seqno
;
2146 ring
->set_seqno
= ring_set_seqno
;
2148 if (INTEL_INFO(dev
)->gen
>= 8) {
2149 ring
->irq_enable_mask
=
2150 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2151 ring
->irq_get
= gen8_ring_get_irq
;
2152 ring
->irq_put
= gen8_ring_put_irq
;
2153 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2155 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2156 ring
->irq_get
= hsw_vebox_get_irq
;
2157 ring
->irq_put
= hsw_vebox_put_irq
;
2158 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2160 ring
->sync_to
= gen6_ring_sync
;
2161 ring
->semaphore_register
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2162 ring
->semaphore_register
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2163 ring
->semaphore_register
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2164 ring
->semaphore_register
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2165 ring
->signal_mbox
[RCS
] = GEN6_RVESYNC
;
2166 ring
->signal_mbox
[VCS
] = GEN6_VVESYNC
;
2167 ring
->signal_mbox
[BCS
] = GEN6_BVESYNC
;
2168 ring
->signal_mbox
[VECS
] = GEN6_NOSYNC
;
2169 ring
->init
= init_ring_common
;
2171 return intel_init_ring_buffer(dev
, ring
);
2175 intel_ring_flush_all_caches(struct intel_ring_buffer
*ring
)
2179 if (!ring
->gpu_caches_dirty
)
2182 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2186 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2188 ring
->gpu_caches_dirty
= false;
2193 intel_ring_invalidate_all_caches(struct intel_ring_buffer
*ring
)
2195 uint32_t flush_domains
;
2199 if (ring
->gpu_caches_dirty
)
2200 flush_domains
= I915_GEM_GPU_DOMAINS
;
2202 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2206 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2208 ring
->gpu_caches_dirty
= false;