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Merge tag 'drm-intel-next-2014-02-14' of ssh://git.freedesktop.org/git/drm-intel...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30 #include <drm/drmP.h>
31 #include "i915_drv.h"
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35
36 static inline int ring_space(struct intel_ring_buffer *ring)
37 {
38 int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
39 if (space < 0)
40 space += ring->size;
41 return space;
42 }
43
44 void __intel_ring_advance(struct intel_ring_buffer *ring)
45 {
46 struct drm_i915_private *dev_priv = ring->dev->dev_private;
47
48 ring->tail &= ring->size - 1;
49 if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
50 return;
51 ring->write_tail(ring, ring->tail);
52 }
53
54 static int
55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
56 u32 invalidate_domains,
57 u32 flush_domains)
58 {
59 u32 cmd;
60 int ret;
61
62 cmd = MI_FLUSH;
63 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
64 cmd |= MI_NO_WRITE_FLUSH;
65
66 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
67 cmd |= MI_READ_FLUSH;
68
69 ret = intel_ring_begin(ring, 2);
70 if (ret)
71 return ret;
72
73 intel_ring_emit(ring, cmd);
74 intel_ring_emit(ring, MI_NOOP);
75 intel_ring_advance(ring);
76
77 return 0;
78 }
79
80 static int
81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
82 u32 invalidate_domains,
83 u32 flush_domains)
84 {
85 struct drm_device *dev = ring->dev;
86 u32 cmd;
87 int ret;
88
89 /*
90 * read/write caches:
91 *
92 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
93 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
94 * also flushed at 2d versus 3d pipeline switches.
95 *
96 * read-only caches:
97 *
98 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
99 * MI_READ_FLUSH is set, and is always flushed on 965.
100 *
101 * I915_GEM_DOMAIN_COMMAND may not exist?
102 *
103 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
104 * invalidated when MI_EXE_FLUSH is set.
105 *
106 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
107 * invalidated with every MI_FLUSH.
108 *
109 * TLBs:
110 *
111 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
112 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
113 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
114 * are flushed at any MI_FLUSH.
115 */
116
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
118 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
119 cmd &= ~MI_NO_WRITE_FLUSH;
120 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
121 cmd |= MI_EXE_FLUSH;
122
123 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
124 (IS_G4X(dev) || IS_GEN5(dev)))
125 cmd |= MI_INVALIDATE_ISP;
126
127 ret = intel_ring_begin(ring, 2);
128 if (ret)
129 return ret;
130
131 intel_ring_emit(ring, cmd);
132 intel_ring_emit(ring, MI_NOOP);
133 intel_ring_advance(ring);
134
135 return 0;
136 }
137
138 /**
139 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
140 * implementing two workarounds on gen6. From section 1.4.7.1
141 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 *
143 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
144 * produced by non-pipelined state commands), software needs to first
145 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
146 * 0.
147 *
148 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
149 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 *
151 * And the workaround for these two requires this workaround first:
152 *
153 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
154 * BEFORE the pipe-control with a post-sync op and no write-cache
155 * flushes.
156 *
157 * And this last workaround is tricky because of the requirements on
158 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
159 * volume 2 part 1:
160 *
161 * "1 of the following must also be set:
162 * - Render Target Cache Flush Enable ([12] of DW1)
163 * - Depth Cache Flush Enable ([0] of DW1)
164 * - Stall at Pixel Scoreboard ([1] of DW1)
165 * - Depth Stall ([13] of DW1)
166 * - Post-Sync Operation ([13] of DW1)
167 * - Notify Enable ([8] of DW1)"
168 *
169 * The cache flushes require the workaround flush that triggered this
170 * one, so we can't use it. Depth stall would trigger the same.
171 * Post-sync nonzero is what triggered this second workaround, so we
172 * can't use that one either. Notify enable is IRQs, which aren't
173 * really our business. That leaves only stall at scoreboard.
174 */
175 static int
176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
177 {
178 u32 scratch_addr = ring->scratch.gtt_offset + 128;
179 int ret;
180
181
182 ret = intel_ring_begin(ring, 6);
183 if (ret)
184 return ret;
185
186 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
188 PIPE_CONTROL_STALL_AT_SCOREBOARD);
189 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
190 intel_ring_emit(ring, 0); /* low dword */
191 intel_ring_emit(ring, 0); /* high dword */
192 intel_ring_emit(ring, MI_NOOP);
193 intel_ring_advance(ring);
194
195 ret = intel_ring_begin(ring, 6);
196 if (ret)
197 return ret;
198
199 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
201 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
202 intel_ring_emit(ring, 0);
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, MI_NOOP);
205 intel_ring_advance(ring);
206
207 return 0;
208 }
209
210 static int
211 gen6_render_ring_flush(struct intel_ring_buffer *ring,
212 u32 invalidate_domains, u32 flush_domains)
213 {
214 u32 flags = 0;
215 u32 scratch_addr = ring->scratch.gtt_offset + 128;
216 int ret;
217
218 /* Force SNB workarounds for PIPE_CONTROL flushes */
219 ret = intel_emit_post_sync_nonzero_flush(ring);
220 if (ret)
221 return ret;
222
223 /* Just flush everything. Experiments have shown that reducing the
224 * number of bits based on the write domains has little performance
225 * impact.
226 */
227 if (flush_domains) {
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
230 /*
231 * Ensure that any following seqno writes only happen
232 * when the render cache is indeed flushed.
233 */
234 flags |= PIPE_CONTROL_CS_STALL;
235 }
236 if (invalidate_domains) {
237 flags |= PIPE_CONTROL_TLB_INVALIDATE;
238 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
239 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
243 /*
244 * TLB invalidate requires a post-sync write.
245 */
246 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
247 }
248
249 ret = intel_ring_begin(ring, 4);
250 if (ret)
251 return ret;
252
253 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
254 intel_ring_emit(ring, flags);
255 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
256 intel_ring_emit(ring, 0);
257 intel_ring_advance(ring);
258
259 return 0;
260 }
261
262 static int
263 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
264 {
265 int ret;
266
267 ret = intel_ring_begin(ring, 4);
268 if (ret)
269 return ret;
270
271 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
272 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
273 PIPE_CONTROL_STALL_AT_SCOREBOARD);
274 intel_ring_emit(ring, 0);
275 intel_ring_emit(ring, 0);
276 intel_ring_advance(ring);
277
278 return 0;
279 }
280
281 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
282 {
283 int ret;
284
285 if (!ring->fbc_dirty)
286 return 0;
287
288 ret = intel_ring_begin(ring, 6);
289 if (ret)
290 return ret;
291 /* WaFbcNukeOn3DBlt:ivb/hsw */
292 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
293 intel_ring_emit(ring, MSG_FBC_REND_STATE);
294 intel_ring_emit(ring, value);
295 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
296 intel_ring_emit(ring, MSG_FBC_REND_STATE);
297 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
298 intel_ring_advance(ring);
299
300 ring->fbc_dirty = false;
301 return 0;
302 }
303
304 static int
305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
306 u32 invalidate_domains, u32 flush_domains)
307 {
308 u32 flags = 0;
309 u32 scratch_addr = ring->scratch.gtt_offset + 128;
310 int ret;
311
312 /*
313 * Ensure that any following seqno writes only happen when the render
314 * cache is indeed flushed.
315 *
316 * Workaround: 4th PIPE_CONTROL command (except the ones with only
317 * read-cache invalidate bits set) must have the CS_STALL bit set. We
318 * don't try to be clever and just set it unconditionally.
319 */
320 flags |= PIPE_CONTROL_CS_STALL;
321
322 /* Just flush everything. Experiments have shown that reducing the
323 * number of bits based on the write domains has little performance
324 * impact.
325 */
326 if (flush_domains) {
327 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
328 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
329 }
330 if (invalidate_domains) {
331 flags |= PIPE_CONTROL_TLB_INVALIDATE;
332 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
333 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
334 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
335 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
336 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
337 /*
338 * TLB invalidate requires a post-sync write.
339 */
340 flags |= PIPE_CONTROL_QW_WRITE;
341 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
342
343 /* Workaround: we must issue a pipe_control with CS-stall bit
344 * set before a pipe_control command that has the state cache
345 * invalidate bit set. */
346 gen7_render_ring_cs_stall_wa(ring);
347 }
348
349 ret = intel_ring_begin(ring, 4);
350 if (ret)
351 return ret;
352
353 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
354 intel_ring_emit(ring, flags);
355 intel_ring_emit(ring, scratch_addr);
356 intel_ring_emit(ring, 0);
357 intel_ring_advance(ring);
358
359 if (!invalidate_domains && flush_domains)
360 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
361
362 return 0;
363 }
364
365 static int
366 gen8_render_ring_flush(struct intel_ring_buffer *ring,
367 u32 invalidate_domains, u32 flush_domains)
368 {
369 u32 flags = 0;
370 u32 scratch_addr = ring->scratch.gtt_offset + 128;
371 int ret;
372
373 flags |= PIPE_CONTROL_CS_STALL;
374
375 if (flush_domains) {
376 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
377 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
378 }
379 if (invalidate_domains) {
380 flags |= PIPE_CONTROL_TLB_INVALIDATE;
381 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
382 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
383 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
384 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
385 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
386 flags |= PIPE_CONTROL_QW_WRITE;
387 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
388 }
389
390 ret = intel_ring_begin(ring, 6);
391 if (ret)
392 return ret;
393
394 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
395 intel_ring_emit(ring, flags);
396 intel_ring_emit(ring, scratch_addr);
397 intel_ring_emit(ring, 0);
398 intel_ring_emit(ring, 0);
399 intel_ring_emit(ring, 0);
400 intel_ring_advance(ring);
401
402 return 0;
403
404 }
405
406 static void ring_write_tail(struct intel_ring_buffer *ring,
407 u32 value)
408 {
409 drm_i915_private_t *dev_priv = ring->dev->dev_private;
410 I915_WRITE_TAIL(ring, value);
411 }
412
413 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
414 {
415 drm_i915_private_t *dev_priv = ring->dev->dev_private;
416 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
417 RING_ACTHD(ring->mmio_base) : ACTHD;
418
419 return I915_READ(acthd_reg);
420 }
421
422 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
423 {
424 struct drm_i915_private *dev_priv = ring->dev->dev_private;
425 u32 addr;
426
427 addr = dev_priv->status_page_dmah->busaddr;
428 if (INTEL_INFO(ring->dev)->gen >= 4)
429 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
430 I915_WRITE(HWS_PGA, addr);
431 }
432
433 static int init_ring_common(struct intel_ring_buffer *ring)
434 {
435 struct drm_device *dev = ring->dev;
436 drm_i915_private_t *dev_priv = dev->dev_private;
437 struct drm_i915_gem_object *obj = ring->obj;
438 int ret = 0;
439 u32 head;
440
441 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
442
443 if (I915_NEED_GFX_HWS(dev))
444 intel_ring_setup_status_page(ring);
445 else
446 ring_setup_phys_status_page(ring);
447
448 /* Stop the ring if it's running. */
449 I915_WRITE_CTL(ring, 0);
450 I915_WRITE_HEAD(ring, 0);
451 ring->write_tail(ring, 0);
452
453 head = I915_READ_HEAD(ring) & HEAD_ADDR;
454
455 /* G45 ring initialization fails to reset head to zero */
456 if (head != 0) {
457 DRM_DEBUG_KMS("%s head not reset to zero "
458 "ctl %08x head %08x tail %08x start %08x\n",
459 ring->name,
460 I915_READ_CTL(ring),
461 I915_READ_HEAD(ring),
462 I915_READ_TAIL(ring),
463 I915_READ_START(ring));
464
465 I915_WRITE_HEAD(ring, 0);
466
467 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
468 DRM_ERROR("failed to set %s head to zero "
469 "ctl %08x head %08x tail %08x start %08x\n",
470 ring->name,
471 I915_READ_CTL(ring),
472 I915_READ_HEAD(ring),
473 I915_READ_TAIL(ring),
474 I915_READ_START(ring));
475 }
476 }
477
478 /* Initialize the ring. This must happen _after_ we've cleared the ring
479 * registers with the above sequence (the readback of the HEAD registers
480 * also enforces ordering), otherwise the hw might lose the new ring
481 * register values. */
482 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
483 I915_WRITE_CTL(ring,
484 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
485 | RING_VALID);
486
487 /* If the head is still not zero, the ring is dead */
488 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
489 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
490 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
491 DRM_ERROR("%s initialization failed "
492 "ctl %08x head %08x tail %08x start %08x\n",
493 ring->name,
494 I915_READ_CTL(ring),
495 I915_READ_HEAD(ring),
496 I915_READ_TAIL(ring),
497 I915_READ_START(ring));
498 ret = -EIO;
499 goto out;
500 }
501
502 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
503 i915_kernel_lost_context(ring->dev);
504 else {
505 ring->head = I915_READ_HEAD(ring);
506 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
507 ring->space = ring_space(ring);
508 ring->last_retired_head = -1;
509 }
510
511 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
512
513 out:
514 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
515
516 return ret;
517 }
518
519 static int
520 init_pipe_control(struct intel_ring_buffer *ring)
521 {
522 int ret;
523
524 if (ring->scratch.obj)
525 return 0;
526
527 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
528 if (ring->scratch.obj == NULL) {
529 DRM_ERROR("Failed to allocate seqno page\n");
530 ret = -ENOMEM;
531 goto err;
532 }
533
534 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
535 if (ret)
536 goto err_unref;
537
538 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
539 if (ret)
540 goto err_unref;
541
542 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
543 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
544 if (ring->scratch.cpu_page == NULL) {
545 ret = -ENOMEM;
546 goto err_unpin;
547 }
548
549 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
550 ring->name, ring->scratch.gtt_offset);
551 return 0;
552
553 err_unpin:
554 i915_gem_object_ggtt_unpin(ring->scratch.obj);
555 err_unref:
556 drm_gem_object_unreference(&ring->scratch.obj->base);
557 err:
558 return ret;
559 }
560
561 static int init_render_ring(struct intel_ring_buffer *ring)
562 {
563 struct drm_device *dev = ring->dev;
564 struct drm_i915_private *dev_priv = dev->dev_private;
565 int ret = init_ring_common(ring);
566
567 if (INTEL_INFO(dev)->gen > 3)
568 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
569
570 /* We need to disable the AsyncFlip performance optimisations in order
571 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
572 * programmed to '1' on all products.
573 *
574 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
575 */
576 if (INTEL_INFO(dev)->gen >= 6)
577 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
578
579 /* Required for the hardware to program scanline values for waiting */
580 if (INTEL_INFO(dev)->gen == 6)
581 I915_WRITE(GFX_MODE,
582 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
583
584 if (IS_GEN7(dev))
585 I915_WRITE(GFX_MODE_GEN7,
586 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
587 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
588
589 if (INTEL_INFO(dev)->gen >= 5) {
590 ret = init_pipe_control(ring);
591 if (ret)
592 return ret;
593 }
594
595 if (IS_GEN6(dev)) {
596 /* From the Sandybridge PRM, volume 1 part 3, page 24:
597 * "If this bit is set, STCunit will have LRA as replacement
598 * policy. [...] This bit must be reset. LRA replacement
599 * policy is not supported."
600 */
601 I915_WRITE(CACHE_MODE_0,
602 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
603
604 /* This is not explicitly set for GEN6, so read the register.
605 * see intel_ring_mi_set_context() for why we care.
606 * TODO: consider explicitly setting the bit for GEN5
607 */
608 ring->itlb_before_ctx_switch =
609 !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
610 }
611
612 if (INTEL_INFO(dev)->gen >= 6)
613 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
614
615 if (HAS_L3_DPF(dev))
616 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
617
618 return ret;
619 }
620
621 static void render_ring_cleanup(struct intel_ring_buffer *ring)
622 {
623 struct drm_device *dev = ring->dev;
624
625 if (ring->scratch.obj == NULL)
626 return;
627
628 if (INTEL_INFO(dev)->gen >= 5) {
629 kunmap(sg_page(ring->scratch.obj->pages->sgl));
630 i915_gem_object_ggtt_unpin(ring->scratch.obj);
631 }
632
633 drm_gem_object_unreference(&ring->scratch.obj->base);
634 ring->scratch.obj = NULL;
635 }
636
637 static void
638 update_mboxes(struct intel_ring_buffer *ring,
639 u32 mmio_offset)
640 {
641 /* NB: In order to be able to do semaphore MBOX updates for varying number
642 * of rings, it's easiest if we round up each individual update to a
643 * multiple of 2 (since ring updates must always be a multiple of 2)
644 * even though the actual update only requires 3 dwords.
645 */
646 #define MBOX_UPDATE_DWORDS 4
647 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
648 intel_ring_emit(ring, mmio_offset);
649 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
650 intel_ring_emit(ring, MI_NOOP);
651 }
652
653 /**
654 * gen6_add_request - Update the semaphore mailbox registers
655 *
656 * @ring - ring that is adding a request
657 * @seqno - return seqno stuck into the ring
658 *
659 * Update the mailbox registers in the *other* rings with the current seqno.
660 * This acts like a signal in the canonical semaphore.
661 */
662 static int
663 gen6_add_request(struct intel_ring_buffer *ring)
664 {
665 struct drm_device *dev = ring->dev;
666 struct drm_i915_private *dev_priv = dev->dev_private;
667 struct intel_ring_buffer *useless;
668 int i, ret, num_dwords = 4;
669
670 if (i915_semaphore_is_enabled(dev))
671 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
672 #undef MBOX_UPDATE_DWORDS
673
674 ret = intel_ring_begin(ring, num_dwords);
675 if (ret)
676 return ret;
677
678 if (i915_semaphore_is_enabled(dev)) {
679 for_each_ring(useless, dev_priv, i) {
680 u32 mbox_reg = ring->signal_mbox[i];
681 if (mbox_reg != GEN6_NOSYNC)
682 update_mboxes(ring, mbox_reg);
683 }
684 }
685
686 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
687 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
688 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
689 intel_ring_emit(ring, MI_USER_INTERRUPT);
690 __intel_ring_advance(ring);
691
692 return 0;
693 }
694
695 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
696 u32 seqno)
697 {
698 struct drm_i915_private *dev_priv = dev->dev_private;
699 return dev_priv->last_seqno < seqno;
700 }
701
702 /**
703 * intel_ring_sync - sync the waiter to the signaller on seqno
704 *
705 * @waiter - ring that is waiting
706 * @signaller - ring which has, or will signal
707 * @seqno - seqno which the waiter will block on
708 */
709 static int
710 gen6_ring_sync(struct intel_ring_buffer *waiter,
711 struct intel_ring_buffer *signaller,
712 u32 seqno)
713 {
714 int ret;
715 u32 dw1 = MI_SEMAPHORE_MBOX |
716 MI_SEMAPHORE_COMPARE |
717 MI_SEMAPHORE_REGISTER;
718
719 /* Throughout all of the GEM code, seqno passed implies our current
720 * seqno is >= the last seqno executed. However for hardware the
721 * comparison is strictly greater than.
722 */
723 seqno -= 1;
724
725 WARN_ON(signaller->semaphore_register[waiter->id] ==
726 MI_SEMAPHORE_SYNC_INVALID);
727
728 ret = intel_ring_begin(waiter, 4);
729 if (ret)
730 return ret;
731
732 /* If seqno wrap happened, omit the wait with no-ops */
733 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
734 intel_ring_emit(waiter,
735 dw1 |
736 signaller->semaphore_register[waiter->id]);
737 intel_ring_emit(waiter, seqno);
738 intel_ring_emit(waiter, 0);
739 intel_ring_emit(waiter, MI_NOOP);
740 } else {
741 intel_ring_emit(waiter, MI_NOOP);
742 intel_ring_emit(waiter, MI_NOOP);
743 intel_ring_emit(waiter, MI_NOOP);
744 intel_ring_emit(waiter, MI_NOOP);
745 }
746 intel_ring_advance(waiter);
747
748 return 0;
749 }
750
751 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
752 do { \
753 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
754 PIPE_CONTROL_DEPTH_STALL); \
755 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
756 intel_ring_emit(ring__, 0); \
757 intel_ring_emit(ring__, 0); \
758 } while (0)
759
760 static int
761 pc_render_add_request(struct intel_ring_buffer *ring)
762 {
763 u32 scratch_addr = ring->scratch.gtt_offset + 128;
764 int ret;
765
766 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
767 * incoherent with writes to memory, i.e. completely fubar,
768 * so we need to use PIPE_NOTIFY instead.
769 *
770 * However, we also need to workaround the qword write
771 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
772 * memory before requesting an interrupt.
773 */
774 ret = intel_ring_begin(ring, 32);
775 if (ret)
776 return ret;
777
778 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
779 PIPE_CONTROL_WRITE_FLUSH |
780 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
781 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
782 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
783 intel_ring_emit(ring, 0);
784 PIPE_CONTROL_FLUSH(ring, scratch_addr);
785 scratch_addr += 128; /* write to separate cachelines */
786 PIPE_CONTROL_FLUSH(ring, scratch_addr);
787 scratch_addr += 128;
788 PIPE_CONTROL_FLUSH(ring, scratch_addr);
789 scratch_addr += 128;
790 PIPE_CONTROL_FLUSH(ring, scratch_addr);
791 scratch_addr += 128;
792 PIPE_CONTROL_FLUSH(ring, scratch_addr);
793 scratch_addr += 128;
794 PIPE_CONTROL_FLUSH(ring, scratch_addr);
795
796 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
797 PIPE_CONTROL_WRITE_FLUSH |
798 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
799 PIPE_CONTROL_NOTIFY);
800 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
801 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
802 intel_ring_emit(ring, 0);
803 __intel_ring_advance(ring);
804
805 return 0;
806 }
807
808 static u32
809 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
810 {
811 /* Workaround to force correct ordering between irq and seqno writes on
812 * ivb (and maybe also on snb) by reading from a CS register (like
813 * ACTHD) before reading the status page. */
814 if (!lazy_coherency)
815 intel_ring_get_active_head(ring);
816 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
817 }
818
819 static u32
820 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
821 {
822 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
823 }
824
825 static void
826 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
827 {
828 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
829 }
830
831 static u32
832 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
833 {
834 return ring->scratch.cpu_page[0];
835 }
836
837 static void
838 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
839 {
840 ring->scratch.cpu_page[0] = seqno;
841 }
842
843 static bool
844 gen5_ring_get_irq(struct intel_ring_buffer *ring)
845 {
846 struct drm_device *dev = ring->dev;
847 drm_i915_private_t *dev_priv = dev->dev_private;
848 unsigned long flags;
849
850 if (!dev->irq_enabled)
851 return false;
852
853 spin_lock_irqsave(&dev_priv->irq_lock, flags);
854 if (ring->irq_refcount++ == 0)
855 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
856 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
857
858 return true;
859 }
860
861 static void
862 gen5_ring_put_irq(struct intel_ring_buffer *ring)
863 {
864 struct drm_device *dev = ring->dev;
865 drm_i915_private_t *dev_priv = dev->dev_private;
866 unsigned long flags;
867
868 spin_lock_irqsave(&dev_priv->irq_lock, flags);
869 if (--ring->irq_refcount == 0)
870 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
871 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
872 }
873
874 static bool
875 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
876 {
877 struct drm_device *dev = ring->dev;
878 drm_i915_private_t *dev_priv = dev->dev_private;
879 unsigned long flags;
880
881 if (!dev->irq_enabled)
882 return false;
883
884 spin_lock_irqsave(&dev_priv->irq_lock, flags);
885 if (ring->irq_refcount++ == 0) {
886 dev_priv->irq_mask &= ~ring->irq_enable_mask;
887 I915_WRITE(IMR, dev_priv->irq_mask);
888 POSTING_READ(IMR);
889 }
890 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
891
892 return true;
893 }
894
895 static void
896 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
897 {
898 struct drm_device *dev = ring->dev;
899 drm_i915_private_t *dev_priv = dev->dev_private;
900 unsigned long flags;
901
902 spin_lock_irqsave(&dev_priv->irq_lock, flags);
903 if (--ring->irq_refcount == 0) {
904 dev_priv->irq_mask |= ring->irq_enable_mask;
905 I915_WRITE(IMR, dev_priv->irq_mask);
906 POSTING_READ(IMR);
907 }
908 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
909 }
910
911 static bool
912 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
913 {
914 struct drm_device *dev = ring->dev;
915 drm_i915_private_t *dev_priv = dev->dev_private;
916 unsigned long flags;
917
918 if (!dev->irq_enabled)
919 return false;
920
921 spin_lock_irqsave(&dev_priv->irq_lock, flags);
922 if (ring->irq_refcount++ == 0) {
923 dev_priv->irq_mask &= ~ring->irq_enable_mask;
924 I915_WRITE16(IMR, dev_priv->irq_mask);
925 POSTING_READ16(IMR);
926 }
927 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
928
929 return true;
930 }
931
932 static void
933 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
934 {
935 struct drm_device *dev = ring->dev;
936 drm_i915_private_t *dev_priv = dev->dev_private;
937 unsigned long flags;
938
939 spin_lock_irqsave(&dev_priv->irq_lock, flags);
940 if (--ring->irq_refcount == 0) {
941 dev_priv->irq_mask |= ring->irq_enable_mask;
942 I915_WRITE16(IMR, dev_priv->irq_mask);
943 POSTING_READ16(IMR);
944 }
945 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
946 }
947
948 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
949 {
950 struct drm_device *dev = ring->dev;
951 drm_i915_private_t *dev_priv = ring->dev->dev_private;
952 u32 mmio = 0;
953
954 /* The ring status page addresses are no longer next to the rest of
955 * the ring registers as of gen7.
956 */
957 if (IS_GEN7(dev)) {
958 switch (ring->id) {
959 case RCS:
960 mmio = RENDER_HWS_PGA_GEN7;
961 break;
962 case BCS:
963 mmio = BLT_HWS_PGA_GEN7;
964 break;
965 case VCS:
966 mmio = BSD_HWS_PGA_GEN7;
967 break;
968 case VECS:
969 mmio = VEBOX_HWS_PGA_GEN7;
970 break;
971 }
972 } else if (IS_GEN6(ring->dev)) {
973 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
974 } else {
975 /* XXX: gen8 returns to sanity */
976 mmio = RING_HWS_PGA(ring->mmio_base);
977 }
978
979 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
980 POSTING_READ(mmio);
981
982 /* Flush the TLB for this page */
983 if (INTEL_INFO(dev)->gen >= 6) {
984 u32 reg = RING_INSTPM(ring->mmio_base);
985 I915_WRITE(reg,
986 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
987 INSTPM_SYNC_FLUSH));
988 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
989 1000))
990 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
991 ring->name);
992 }
993 }
994
995 static int
996 bsd_ring_flush(struct intel_ring_buffer *ring,
997 u32 invalidate_domains,
998 u32 flush_domains)
999 {
1000 int ret;
1001
1002 ret = intel_ring_begin(ring, 2);
1003 if (ret)
1004 return ret;
1005
1006 intel_ring_emit(ring, MI_FLUSH);
1007 intel_ring_emit(ring, MI_NOOP);
1008 intel_ring_advance(ring);
1009 return 0;
1010 }
1011
1012 static int
1013 i9xx_add_request(struct intel_ring_buffer *ring)
1014 {
1015 int ret;
1016
1017 ret = intel_ring_begin(ring, 4);
1018 if (ret)
1019 return ret;
1020
1021 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1022 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1023 intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1024 intel_ring_emit(ring, MI_USER_INTERRUPT);
1025 __intel_ring_advance(ring);
1026
1027 return 0;
1028 }
1029
1030 static bool
1031 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1032 {
1033 struct drm_device *dev = ring->dev;
1034 drm_i915_private_t *dev_priv = dev->dev_private;
1035 unsigned long flags;
1036
1037 if (!dev->irq_enabled)
1038 return false;
1039
1040 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1041 if (ring->irq_refcount++ == 0) {
1042 if (HAS_L3_DPF(dev) && ring->id == RCS)
1043 I915_WRITE_IMR(ring,
1044 ~(ring->irq_enable_mask |
1045 GT_PARITY_ERROR(dev)));
1046 else
1047 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1048 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1049 }
1050 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1051
1052 return true;
1053 }
1054
1055 static void
1056 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1057 {
1058 struct drm_device *dev = ring->dev;
1059 drm_i915_private_t *dev_priv = dev->dev_private;
1060 unsigned long flags;
1061
1062 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1063 if (--ring->irq_refcount == 0) {
1064 if (HAS_L3_DPF(dev) && ring->id == RCS)
1065 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1066 else
1067 I915_WRITE_IMR(ring, ~0);
1068 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1069 }
1070 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1071 }
1072
1073 static bool
1074 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1075 {
1076 struct drm_device *dev = ring->dev;
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 unsigned long flags;
1079
1080 if (!dev->irq_enabled)
1081 return false;
1082
1083 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1084 if (ring->irq_refcount++ == 0) {
1085 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1086 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1087 }
1088 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1089
1090 return true;
1091 }
1092
1093 static void
1094 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1095 {
1096 struct drm_device *dev = ring->dev;
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 unsigned long flags;
1099
1100 if (!dev->irq_enabled)
1101 return;
1102
1103 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1104 if (--ring->irq_refcount == 0) {
1105 I915_WRITE_IMR(ring, ~0);
1106 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1107 }
1108 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1109 }
1110
1111 static bool
1112 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1113 {
1114 struct drm_device *dev = ring->dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1116 unsigned long flags;
1117
1118 if (!dev->irq_enabled)
1119 return false;
1120
1121 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1122 if (ring->irq_refcount++ == 0) {
1123 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1124 I915_WRITE_IMR(ring,
1125 ~(ring->irq_enable_mask |
1126 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1127 } else {
1128 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1129 }
1130 POSTING_READ(RING_IMR(ring->mmio_base));
1131 }
1132 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1133
1134 return true;
1135 }
1136
1137 static void
1138 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1139 {
1140 struct drm_device *dev = ring->dev;
1141 struct drm_i915_private *dev_priv = dev->dev_private;
1142 unsigned long flags;
1143
1144 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1145 if (--ring->irq_refcount == 0) {
1146 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1147 I915_WRITE_IMR(ring,
1148 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1149 } else {
1150 I915_WRITE_IMR(ring, ~0);
1151 }
1152 POSTING_READ(RING_IMR(ring->mmio_base));
1153 }
1154 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1155 }
1156
1157 static int
1158 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1159 u32 offset, u32 length,
1160 unsigned flags)
1161 {
1162 int ret;
1163
1164 ret = intel_ring_begin(ring, 2);
1165 if (ret)
1166 return ret;
1167
1168 intel_ring_emit(ring,
1169 MI_BATCH_BUFFER_START |
1170 MI_BATCH_GTT |
1171 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1172 intel_ring_emit(ring, offset);
1173 intel_ring_advance(ring);
1174
1175 return 0;
1176 }
1177
1178 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1179 #define I830_BATCH_LIMIT (256*1024)
1180 static int
1181 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1182 u32 offset, u32 len,
1183 unsigned flags)
1184 {
1185 int ret;
1186
1187 if (flags & I915_DISPATCH_PINNED) {
1188 ret = intel_ring_begin(ring, 4);
1189 if (ret)
1190 return ret;
1191
1192 intel_ring_emit(ring, MI_BATCH_BUFFER);
1193 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1194 intel_ring_emit(ring, offset + len - 8);
1195 intel_ring_emit(ring, MI_NOOP);
1196 intel_ring_advance(ring);
1197 } else {
1198 u32 cs_offset = ring->scratch.gtt_offset;
1199
1200 if (len > I830_BATCH_LIMIT)
1201 return -ENOSPC;
1202
1203 ret = intel_ring_begin(ring, 9+3);
1204 if (ret)
1205 return ret;
1206 /* Blit the batch (which has now all relocs applied) to the stable batch
1207 * scratch bo area (so that the CS never stumbles over its tlb
1208 * invalidation bug) ... */
1209 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1210 XY_SRC_COPY_BLT_WRITE_ALPHA |
1211 XY_SRC_COPY_BLT_WRITE_RGB);
1212 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1213 intel_ring_emit(ring, 0);
1214 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1215 intel_ring_emit(ring, cs_offset);
1216 intel_ring_emit(ring, 0);
1217 intel_ring_emit(ring, 4096);
1218 intel_ring_emit(ring, offset);
1219 intel_ring_emit(ring, MI_FLUSH);
1220
1221 /* ... and execute it. */
1222 intel_ring_emit(ring, MI_BATCH_BUFFER);
1223 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1224 intel_ring_emit(ring, cs_offset + len - 8);
1225 intel_ring_advance(ring);
1226 }
1227
1228 return 0;
1229 }
1230
1231 static int
1232 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1233 u32 offset, u32 len,
1234 unsigned flags)
1235 {
1236 int ret;
1237
1238 ret = intel_ring_begin(ring, 2);
1239 if (ret)
1240 return ret;
1241
1242 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1243 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1244 intel_ring_advance(ring);
1245
1246 return 0;
1247 }
1248
1249 static void cleanup_status_page(struct intel_ring_buffer *ring)
1250 {
1251 struct drm_i915_gem_object *obj;
1252
1253 obj = ring->status_page.obj;
1254 if (obj == NULL)
1255 return;
1256
1257 kunmap(sg_page(obj->pages->sgl));
1258 i915_gem_object_ggtt_unpin(obj);
1259 drm_gem_object_unreference(&obj->base);
1260 ring->status_page.obj = NULL;
1261 }
1262
1263 static int init_status_page(struct intel_ring_buffer *ring)
1264 {
1265 struct drm_device *dev = ring->dev;
1266 struct drm_i915_gem_object *obj;
1267 int ret;
1268
1269 obj = i915_gem_alloc_object(dev, 4096);
1270 if (obj == NULL) {
1271 DRM_ERROR("Failed to allocate status page\n");
1272 ret = -ENOMEM;
1273 goto err;
1274 }
1275
1276 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1277 if (ret)
1278 goto err_unref;
1279
1280 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1281 if (ret)
1282 goto err_unref;
1283
1284 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1285 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1286 if (ring->status_page.page_addr == NULL) {
1287 ret = -ENOMEM;
1288 goto err_unpin;
1289 }
1290 ring->status_page.obj = obj;
1291 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1292
1293 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1294 ring->name, ring->status_page.gfx_addr);
1295
1296 return 0;
1297
1298 err_unpin:
1299 i915_gem_object_ggtt_unpin(obj);
1300 err_unref:
1301 drm_gem_object_unreference(&obj->base);
1302 err:
1303 return ret;
1304 }
1305
1306 static int init_phys_status_page(struct intel_ring_buffer *ring)
1307 {
1308 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1309
1310 if (!dev_priv->status_page_dmah) {
1311 dev_priv->status_page_dmah =
1312 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1313 if (!dev_priv->status_page_dmah)
1314 return -ENOMEM;
1315 }
1316
1317 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1318 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1319
1320 return 0;
1321 }
1322
1323 static int intel_init_ring_buffer(struct drm_device *dev,
1324 struct intel_ring_buffer *ring)
1325 {
1326 struct drm_i915_gem_object *obj;
1327 struct drm_i915_private *dev_priv = dev->dev_private;
1328 int ret;
1329
1330 ring->dev = dev;
1331 INIT_LIST_HEAD(&ring->active_list);
1332 INIT_LIST_HEAD(&ring->request_list);
1333 ring->size = 32 * PAGE_SIZE;
1334 memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1335
1336 init_waitqueue_head(&ring->irq_queue);
1337
1338 if (I915_NEED_GFX_HWS(dev)) {
1339 ret = init_status_page(ring);
1340 if (ret)
1341 return ret;
1342 } else {
1343 BUG_ON(ring->id != RCS);
1344 ret = init_phys_status_page(ring);
1345 if (ret)
1346 return ret;
1347 }
1348
1349 obj = NULL;
1350 if (!HAS_LLC(dev))
1351 obj = i915_gem_object_create_stolen(dev, ring->size);
1352 if (obj == NULL)
1353 obj = i915_gem_alloc_object(dev, ring->size);
1354 if (obj == NULL) {
1355 DRM_ERROR("Failed to allocate ringbuffer\n");
1356 ret = -ENOMEM;
1357 goto err_hws;
1358 }
1359
1360 ring->obj = obj;
1361
1362 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1363 if (ret)
1364 goto err_unref;
1365
1366 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1367 if (ret)
1368 goto err_unpin;
1369
1370 ring->virtual_start =
1371 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1372 ring->size);
1373 if (ring->virtual_start == NULL) {
1374 DRM_ERROR("Failed to map ringbuffer.\n");
1375 ret = -EINVAL;
1376 goto err_unpin;
1377 }
1378
1379 ret = ring->init(ring);
1380 if (ret)
1381 goto err_unmap;
1382
1383 /* Workaround an erratum on the i830 which causes a hang if
1384 * the TAIL pointer points to within the last 2 cachelines
1385 * of the buffer.
1386 */
1387 ring->effective_size = ring->size;
1388 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1389 ring->effective_size -= 128;
1390
1391 return 0;
1392
1393 err_unmap:
1394 iounmap(ring->virtual_start);
1395 err_unpin:
1396 i915_gem_object_ggtt_unpin(obj);
1397 err_unref:
1398 drm_gem_object_unreference(&obj->base);
1399 ring->obj = NULL;
1400 err_hws:
1401 cleanup_status_page(ring);
1402 return ret;
1403 }
1404
1405 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1406 {
1407 struct drm_i915_private *dev_priv;
1408 int ret;
1409
1410 if (ring->obj == NULL)
1411 return;
1412
1413 /* Disable the ring buffer. The ring must be idle at this point */
1414 dev_priv = ring->dev->dev_private;
1415 ret = intel_ring_idle(ring);
1416 if (ret && !i915_reset_in_progress(&dev_priv->gpu_error))
1417 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1418 ring->name, ret);
1419
1420 I915_WRITE_CTL(ring, 0);
1421
1422 iounmap(ring->virtual_start);
1423
1424 i915_gem_object_ggtt_unpin(ring->obj);
1425 drm_gem_object_unreference(&ring->obj->base);
1426 ring->obj = NULL;
1427 ring->preallocated_lazy_request = NULL;
1428 ring->outstanding_lazy_seqno = 0;
1429
1430 if (ring->cleanup)
1431 ring->cleanup(ring);
1432
1433 cleanup_status_page(ring);
1434 }
1435
1436 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1437 {
1438 struct drm_i915_gem_request *request;
1439 u32 seqno = 0, tail;
1440 int ret;
1441
1442 if (ring->last_retired_head != -1) {
1443 ring->head = ring->last_retired_head;
1444 ring->last_retired_head = -1;
1445
1446 ring->space = ring_space(ring);
1447 if (ring->space >= n)
1448 return 0;
1449 }
1450
1451 list_for_each_entry(request, &ring->request_list, list) {
1452 int space;
1453
1454 if (request->tail == -1)
1455 continue;
1456
1457 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1458 if (space < 0)
1459 space += ring->size;
1460 if (space >= n) {
1461 seqno = request->seqno;
1462 tail = request->tail;
1463 break;
1464 }
1465
1466 /* Consume this request in case we need more space than
1467 * is available and so need to prevent a race between
1468 * updating last_retired_head and direct reads of
1469 * I915_RING_HEAD. It also provides a nice sanity check.
1470 */
1471 request->tail = -1;
1472 }
1473
1474 if (seqno == 0)
1475 return -ENOSPC;
1476
1477 ret = i915_wait_seqno(ring, seqno);
1478 if (ret)
1479 return ret;
1480
1481 ring->head = tail;
1482 ring->space = ring_space(ring);
1483 if (WARN_ON(ring->space < n))
1484 return -ENOSPC;
1485
1486 return 0;
1487 }
1488
1489 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1490 {
1491 struct drm_device *dev = ring->dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 unsigned long end;
1494 int ret;
1495
1496 ret = intel_ring_wait_request(ring, n);
1497 if (ret != -ENOSPC)
1498 return ret;
1499
1500 /* force the tail write in case we have been skipping them */
1501 __intel_ring_advance(ring);
1502
1503 trace_i915_ring_wait_begin(ring);
1504 /* With GEM the hangcheck timer should kick us out of the loop,
1505 * leaving it early runs the risk of corrupting GEM state (due
1506 * to running on almost untested codepaths). But on resume
1507 * timers don't work yet, so prevent a complete hang in that
1508 * case by choosing an insanely large timeout. */
1509 end = jiffies + 60 * HZ;
1510
1511 do {
1512 ring->head = I915_READ_HEAD(ring);
1513 ring->space = ring_space(ring);
1514 if (ring->space >= n) {
1515 trace_i915_ring_wait_end(ring);
1516 return 0;
1517 }
1518
1519 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1520 dev->primary->master) {
1521 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1522 if (master_priv->sarea_priv)
1523 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1524 }
1525
1526 msleep(1);
1527
1528 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1529 dev_priv->mm.interruptible);
1530 if (ret)
1531 return ret;
1532 } while (!time_after(jiffies, end));
1533 trace_i915_ring_wait_end(ring);
1534 return -EBUSY;
1535 }
1536
1537 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1538 {
1539 uint32_t __iomem *virt;
1540 int rem = ring->size - ring->tail;
1541
1542 if (ring->space < rem) {
1543 int ret = ring_wait_for_space(ring, rem);
1544 if (ret)
1545 return ret;
1546 }
1547
1548 virt = ring->virtual_start + ring->tail;
1549 rem /= 4;
1550 while (rem--)
1551 iowrite32(MI_NOOP, virt++);
1552
1553 ring->tail = 0;
1554 ring->space = ring_space(ring);
1555
1556 return 0;
1557 }
1558
1559 int intel_ring_idle(struct intel_ring_buffer *ring)
1560 {
1561 u32 seqno;
1562 int ret;
1563
1564 /* We need to add any requests required to flush the objects and ring */
1565 if (ring->outstanding_lazy_seqno) {
1566 ret = i915_add_request(ring, NULL);
1567 if (ret)
1568 return ret;
1569 }
1570
1571 /* Wait upon the last request to be completed */
1572 if (list_empty(&ring->request_list))
1573 return 0;
1574
1575 seqno = list_entry(ring->request_list.prev,
1576 struct drm_i915_gem_request,
1577 list)->seqno;
1578
1579 return i915_wait_seqno(ring, seqno);
1580 }
1581
1582 static int
1583 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1584 {
1585 if (ring->outstanding_lazy_seqno)
1586 return 0;
1587
1588 if (ring->preallocated_lazy_request == NULL) {
1589 struct drm_i915_gem_request *request;
1590
1591 request = kmalloc(sizeof(*request), GFP_KERNEL);
1592 if (request == NULL)
1593 return -ENOMEM;
1594
1595 ring->preallocated_lazy_request = request;
1596 }
1597
1598 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1599 }
1600
1601 static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1602 int bytes)
1603 {
1604 int ret;
1605
1606 if (unlikely(ring->tail + bytes > ring->effective_size)) {
1607 ret = intel_wrap_ring_buffer(ring);
1608 if (unlikely(ret))
1609 return ret;
1610 }
1611
1612 if (unlikely(ring->space < bytes)) {
1613 ret = ring_wait_for_space(ring, bytes);
1614 if (unlikely(ret))
1615 return ret;
1616 }
1617
1618 return 0;
1619 }
1620
1621 int intel_ring_begin(struct intel_ring_buffer *ring,
1622 int num_dwords)
1623 {
1624 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1625 int ret;
1626
1627 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1628 dev_priv->mm.interruptible);
1629 if (ret)
1630 return ret;
1631
1632 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
1633 if (ret)
1634 return ret;
1635
1636 /* Preallocate the olr before touching the ring */
1637 ret = intel_ring_alloc_seqno(ring);
1638 if (ret)
1639 return ret;
1640
1641 ring->space -= num_dwords * sizeof(uint32_t);
1642 return 0;
1643 }
1644
1645 /* Align the ring tail to a cacheline boundary */
1646 int intel_ring_cacheline_align(struct intel_ring_buffer *ring)
1647 {
1648 int num_dwords = (64 - (ring->tail & 63)) / sizeof(uint32_t);
1649 int ret;
1650
1651 if (num_dwords == 0)
1652 return 0;
1653
1654 ret = intel_ring_begin(ring, num_dwords);
1655 if (ret)
1656 return ret;
1657
1658 while (num_dwords--)
1659 intel_ring_emit(ring, MI_NOOP);
1660
1661 intel_ring_advance(ring);
1662
1663 return 0;
1664 }
1665
1666 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1667 {
1668 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1669
1670 BUG_ON(ring->outstanding_lazy_seqno);
1671
1672 if (INTEL_INFO(ring->dev)->gen >= 6) {
1673 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1674 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1675 if (HAS_VEBOX(ring->dev))
1676 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1677 }
1678
1679 ring->set_seqno(ring, seqno);
1680 ring->hangcheck.seqno = seqno;
1681 }
1682
1683 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1684 u32 value)
1685 {
1686 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1687
1688 /* Every tail move must follow the sequence below */
1689
1690 /* Disable notification that the ring is IDLE. The GT
1691 * will then assume that it is busy and bring it out of rc6.
1692 */
1693 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1694 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1695
1696 /* Clear the context id. Here be magic! */
1697 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1698
1699 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1700 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1701 GEN6_BSD_SLEEP_INDICATOR) == 0,
1702 50))
1703 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1704
1705 /* Now that the ring is fully powered up, update the tail */
1706 I915_WRITE_TAIL(ring, value);
1707 POSTING_READ(RING_TAIL(ring->mmio_base));
1708
1709 /* Let the ring send IDLE messages to the GT again,
1710 * and so let it sleep to conserve power when idle.
1711 */
1712 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1713 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1714 }
1715
1716 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1717 u32 invalidate, u32 flush)
1718 {
1719 uint32_t cmd;
1720 int ret;
1721
1722 ret = intel_ring_begin(ring, 4);
1723 if (ret)
1724 return ret;
1725
1726 cmd = MI_FLUSH_DW;
1727 if (INTEL_INFO(ring->dev)->gen >= 8)
1728 cmd += 1;
1729 /*
1730 * Bspec vol 1c.5 - video engine command streamer:
1731 * "If ENABLED, all TLBs will be invalidated once the flush
1732 * operation is complete. This bit is only valid when the
1733 * Post-Sync Operation field is a value of 1h or 3h."
1734 */
1735 if (invalidate & I915_GEM_GPU_DOMAINS)
1736 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1737 MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1738 intel_ring_emit(ring, cmd);
1739 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1740 if (INTEL_INFO(ring->dev)->gen >= 8) {
1741 intel_ring_emit(ring, 0); /* upper addr */
1742 intel_ring_emit(ring, 0); /* value */
1743 } else {
1744 intel_ring_emit(ring, 0);
1745 intel_ring_emit(ring, MI_NOOP);
1746 }
1747 intel_ring_advance(ring);
1748 return 0;
1749 }
1750
1751 static int
1752 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1753 u32 offset, u32 len,
1754 unsigned flags)
1755 {
1756 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1757 bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1758 !(flags & I915_DISPATCH_SECURE);
1759 int ret;
1760
1761 ret = intel_ring_begin(ring, 4);
1762 if (ret)
1763 return ret;
1764
1765 /* FIXME(BDW): Address space and security selectors. */
1766 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1767 intel_ring_emit(ring, offset);
1768 intel_ring_emit(ring, 0);
1769 intel_ring_emit(ring, MI_NOOP);
1770 intel_ring_advance(ring);
1771
1772 return 0;
1773 }
1774
1775 static int
1776 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1777 u32 offset, u32 len,
1778 unsigned flags)
1779 {
1780 int ret;
1781
1782 ret = intel_ring_begin(ring, 2);
1783 if (ret)
1784 return ret;
1785
1786 intel_ring_emit(ring,
1787 MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1788 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1789 /* bit0-7 is the length on GEN6+ */
1790 intel_ring_emit(ring, offset);
1791 intel_ring_advance(ring);
1792
1793 return 0;
1794 }
1795
1796 static int
1797 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1798 u32 offset, u32 len,
1799 unsigned flags)
1800 {
1801 int ret;
1802
1803 ret = intel_ring_begin(ring, 2);
1804 if (ret)
1805 return ret;
1806
1807 intel_ring_emit(ring,
1808 MI_BATCH_BUFFER_START |
1809 (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1810 /* bit0-7 is the length on GEN6+ */
1811 intel_ring_emit(ring, offset);
1812 intel_ring_advance(ring);
1813
1814 return 0;
1815 }
1816
1817 /* Blitter support (SandyBridge+) */
1818
1819 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1820 u32 invalidate, u32 flush)
1821 {
1822 struct drm_device *dev = ring->dev;
1823 uint32_t cmd;
1824 int ret;
1825
1826 ret = intel_ring_begin(ring, 4);
1827 if (ret)
1828 return ret;
1829
1830 cmd = MI_FLUSH_DW;
1831 if (INTEL_INFO(ring->dev)->gen >= 8)
1832 cmd += 1;
1833 /*
1834 * Bspec vol 1c.3 - blitter engine command streamer:
1835 * "If ENABLED, all TLBs will be invalidated once the flush
1836 * operation is complete. This bit is only valid when the
1837 * Post-Sync Operation field is a value of 1h or 3h."
1838 */
1839 if (invalidate & I915_GEM_DOMAIN_RENDER)
1840 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1841 MI_FLUSH_DW_OP_STOREDW;
1842 intel_ring_emit(ring, cmd);
1843 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1844 if (INTEL_INFO(ring->dev)->gen >= 8) {
1845 intel_ring_emit(ring, 0); /* upper addr */
1846 intel_ring_emit(ring, 0); /* value */
1847 } else {
1848 intel_ring_emit(ring, 0);
1849 intel_ring_emit(ring, MI_NOOP);
1850 }
1851 intel_ring_advance(ring);
1852
1853 if (IS_GEN7(dev) && !invalidate && flush)
1854 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1855
1856 return 0;
1857 }
1858
1859 int intel_init_render_ring_buffer(struct drm_device *dev)
1860 {
1861 drm_i915_private_t *dev_priv = dev->dev_private;
1862 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1863
1864 ring->name = "render ring";
1865 ring->id = RCS;
1866 ring->mmio_base = RENDER_RING_BASE;
1867
1868 if (INTEL_INFO(dev)->gen >= 6) {
1869 ring->add_request = gen6_add_request;
1870 ring->flush = gen7_render_ring_flush;
1871 if (INTEL_INFO(dev)->gen == 6)
1872 ring->flush = gen6_render_ring_flush;
1873 if (INTEL_INFO(dev)->gen >= 8) {
1874 ring->flush = gen8_render_ring_flush;
1875 ring->irq_get = gen8_ring_get_irq;
1876 ring->irq_put = gen8_ring_put_irq;
1877 } else {
1878 ring->irq_get = gen6_ring_get_irq;
1879 ring->irq_put = gen6_ring_put_irq;
1880 }
1881 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1882 ring->get_seqno = gen6_ring_get_seqno;
1883 ring->set_seqno = ring_set_seqno;
1884 ring->sync_to = gen6_ring_sync;
1885 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1886 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1887 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1888 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1889 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1890 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1891 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1892 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1893 } else if (IS_GEN5(dev)) {
1894 ring->add_request = pc_render_add_request;
1895 ring->flush = gen4_render_ring_flush;
1896 ring->get_seqno = pc_render_get_seqno;
1897 ring->set_seqno = pc_render_set_seqno;
1898 ring->irq_get = gen5_ring_get_irq;
1899 ring->irq_put = gen5_ring_put_irq;
1900 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1901 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1902 } else {
1903 ring->add_request = i9xx_add_request;
1904 if (INTEL_INFO(dev)->gen < 4)
1905 ring->flush = gen2_render_ring_flush;
1906 else
1907 ring->flush = gen4_render_ring_flush;
1908 ring->get_seqno = ring_get_seqno;
1909 ring->set_seqno = ring_set_seqno;
1910 if (IS_GEN2(dev)) {
1911 ring->irq_get = i8xx_ring_get_irq;
1912 ring->irq_put = i8xx_ring_put_irq;
1913 } else {
1914 ring->irq_get = i9xx_ring_get_irq;
1915 ring->irq_put = i9xx_ring_put_irq;
1916 }
1917 ring->irq_enable_mask = I915_USER_INTERRUPT;
1918 }
1919 ring->write_tail = ring_write_tail;
1920 if (IS_HASWELL(dev))
1921 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1922 else if (IS_GEN8(dev))
1923 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1924 else if (INTEL_INFO(dev)->gen >= 6)
1925 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1926 else if (INTEL_INFO(dev)->gen >= 4)
1927 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1928 else if (IS_I830(dev) || IS_845G(dev))
1929 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1930 else
1931 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1932 ring->init = init_render_ring;
1933 ring->cleanup = render_ring_cleanup;
1934
1935 /* Workaround batchbuffer to combat CS tlb bug. */
1936 if (HAS_BROKEN_CS_TLB(dev)) {
1937 struct drm_i915_gem_object *obj;
1938 int ret;
1939
1940 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1941 if (obj == NULL) {
1942 DRM_ERROR("Failed to allocate batch bo\n");
1943 return -ENOMEM;
1944 }
1945
1946 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
1947 if (ret != 0) {
1948 drm_gem_object_unreference(&obj->base);
1949 DRM_ERROR("Failed to ping batch bo\n");
1950 return ret;
1951 }
1952
1953 ring->scratch.obj = obj;
1954 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
1955 }
1956
1957 return intel_init_ring_buffer(dev, ring);
1958 }
1959
1960 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1961 {
1962 drm_i915_private_t *dev_priv = dev->dev_private;
1963 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1964 int ret;
1965
1966 ring->name = "render ring";
1967 ring->id = RCS;
1968 ring->mmio_base = RENDER_RING_BASE;
1969
1970 if (INTEL_INFO(dev)->gen >= 6) {
1971 /* non-kms not supported on gen6+ */
1972 return -ENODEV;
1973 }
1974
1975 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1976 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1977 * the special gen5 functions. */
1978 ring->add_request = i9xx_add_request;
1979 if (INTEL_INFO(dev)->gen < 4)
1980 ring->flush = gen2_render_ring_flush;
1981 else
1982 ring->flush = gen4_render_ring_flush;
1983 ring->get_seqno = ring_get_seqno;
1984 ring->set_seqno = ring_set_seqno;
1985 if (IS_GEN2(dev)) {
1986 ring->irq_get = i8xx_ring_get_irq;
1987 ring->irq_put = i8xx_ring_put_irq;
1988 } else {
1989 ring->irq_get = i9xx_ring_get_irq;
1990 ring->irq_put = i9xx_ring_put_irq;
1991 }
1992 ring->irq_enable_mask = I915_USER_INTERRUPT;
1993 ring->write_tail = ring_write_tail;
1994 if (INTEL_INFO(dev)->gen >= 4)
1995 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1996 else if (IS_I830(dev) || IS_845G(dev))
1997 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1998 else
1999 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2000 ring->init = init_render_ring;
2001 ring->cleanup = render_ring_cleanup;
2002
2003 ring->dev = dev;
2004 INIT_LIST_HEAD(&ring->active_list);
2005 INIT_LIST_HEAD(&ring->request_list);
2006
2007 ring->size = size;
2008 ring->effective_size = ring->size;
2009 if (IS_I830(ring->dev) || IS_845G(ring->dev))
2010 ring->effective_size -= 128;
2011
2012 ring->virtual_start = ioremap_wc(start, size);
2013 if (ring->virtual_start == NULL) {
2014 DRM_ERROR("can not ioremap virtual address for"
2015 " ring buffer\n");
2016 return -ENOMEM;
2017 }
2018
2019 if (!I915_NEED_GFX_HWS(dev)) {
2020 ret = init_phys_status_page(ring);
2021 if (ret)
2022 return ret;
2023 }
2024
2025 return 0;
2026 }
2027
2028 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2029 {
2030 drm_i915_private_t *dev_priv = dev->dev_private;
2031 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2032
2033 ring->name = "bsd ring";
2034 ring->id = VCS;
2035
2036 ring->write_tail = ring_write_tail;
2037 if (INTEL_INFO(dev)->gen >= 6) {
2038 ring->mmio_base = GEN6_BSD_RING_BASE;
2039 /* gen6 bsd needs a special wa for tail updates */
2040 if (IS_GEN6(dev))
2041 ring->write_tail = gen6_bsd_ring_write_tail;
2042 ring->flush = gen6_bsd_ring_flush;
2043 ring->add_request = gen6_add_request;
2044 ring->get_seqno = gen6_ring_get_seqno;
2045 ring->set_seqno = ring_set_seqno;
2046 if (INTEL_INFO(dev)->gen >= 8) {
2047 ring->irq_enable_mask =
2048 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2049 ring->irq_get = gen8_ring_get_irq;
2050 ring->irq_put = gen8_ring_put_irq;
2051 ring->dispatch_execbuffer =
2052 gen8_ring_dispatch_execbuffer;
2053 } else {
2054 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2055 ring->irq_get = gen6_ring_get_irq;
2056 ring->irq_put = gen6_ring_put_irq;
2057 ring->dispatch_execbuffer =
2058 gen6_ring_dispatch_execbuffer;
2059 }
2060 ring->sync_to = gen6_ring_sync;
2061 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
2062 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2063 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
2064 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
2065 ring->signal_mbox[RCS] = GEN6_RVSYNC;
2066 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2067 ring->signal_mbox[BCS] = GEN6_BVSYNC;
2068 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
2069 } else {
2070 ring->mmio_base = BSD_RING_BASE;
2071 ring->flush = bsd_ring_flush;
2072 ring->add_request = i9xx_add_request;
2073 ring->get_seqno = ring_get_seqno;
2074 ring->set_seqno = ring_set_seqno;
2075 if (IS_GEN5(dev)) {
2076 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2077 ring->irq_get = gen5_ring_get_irq;
2078 ring->irq_put = gen5_ring_put_irq;
2079 } else {
2080 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2081 ring->irq_get = i9xx_ring_get_irq;
2082 ring->irq_put = i9xx_ring_put_irq;
2083 }
2084 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2085 }
2086 ring->init = init_ring_common;
2087
2088 return intel_init_ring_buffer(dev, ring);
2089 }
2090
2091 int intel_init_blt_ring_buffer(struct drm_device *dev)
2092 {
2093 drm_i915_private_t *dev_priv = dev->dev_private;
2094 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2095
2096 ring->name = "blitter ring";
2097 ring->id = BCS;
2098
2099 ring->mmio_base = BLT_RING_BASE;
2100 ring->write_tail = ring_write_tail;
2101 ring->flush = gen6_ring_flush;
2102 ring->add_request = gen6_add_request;
2103 ring->get_seqno = gen6_ring_get_seqno;
2104 ring->set_seqno = ring_set_seqno;
2105 if (INTEL_INFO(dev)->gen >= 8) {
2106 ring->irq_enable_mask =
2107 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2108 ring->irq_get = gen8_ring_get_irq;
2109 ring->irq_put = gen8_ring_put_irq;
2110 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2111 } else {
2112 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2113 ring->irq_get = gen6_ring_get_irq;
2114 ring->irq_put = gen6_ring_put_irq;
2115 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2116 }
2117 ring->sync_to = gen6_ring_sync;
2118 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2119 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2120 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2121 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
2122 ring->signal_mbox[RCS] = GEN6_RBSYNC;
2123 ring->signal_mbox[VCS] = GEN6_VBSYNC;
2124 ring->signal_mbox[BCS] = GEN6_NOSYNC;
2125 ring->signal_mbox[VECS] = GEN6_VEBSYNC;
2126 ring->init = init_ring_common;
2127
2128 return intel_init_ring_buffer(dev, ring);
2129 }
2130
2131 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2132 {
2133 drm_i915_private_t *dev_priv = dev->dev_private;
2134 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2135
2136 ring->name = "video enhancement ring";
2137 ring->id = VECS;
2138
2139 ring->mmio_base = VEBOX_RING_BASE;
2140 ring->write_tail = ring_write_tail;
2141 ring->flush = gen6_ring_flush;
2142 ring->add_request = gen6_add_request;
2143 ring->get_seqno = gen6_ring_get_seqno;
2144 ring->set_seqno = ring_set_seqno;
2145
2146 if (INTEL_INFO(dev)->gen >= 8) {
2147 ring->irq_enable_mask =
2148 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2149 ring->irq_get = gen8_ring_get_irq;
2150 ring->irq_put = gen8_ring_put_irq;
2151 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2152 } else {
2153 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2154 ring->irq_get = hsw_vebox_get_irq;
2155 ring->irq_put = hsw_vebox_put_irq;
2156 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2157 }
2158 ring->sync_to = gen6_ring_sync;
2159 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2160 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2161 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2162 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2163 ring->signal_mbox[RCS] = GEN6_RVESYNC;
2164 ring->signal_mbox[VCS] = GEN6_VVESYNC;
2165 ring->signal_mbox[BCS] = GEN6_BVESYNC;
2166 ring->signal_mbox[VECS] = GEN6_NOSYNC;
2167 ring->init = init_ring_common;
2168
2169 return intel_init_ring_buffer(dev, ring);
2170 }
2171
2172 int
2173 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2174 {
2175 int ret;
2176
2177 if (!ring->gpu_caches_dirty)
2178 return 0;
2179
2180 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2181 if (ret)
2182 return ret;
2183
2184 trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2185
2186 ring->gpu_caches_dirty = false;
2187 return 0;
2188 }
2189
2190 int
2191 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2192 {
2193 uint32_t flush_domains;
2194 int ret;
2195
2196 flush_domains = 0;
2197 if (ring->gpu_caches_dirty)
2198 flush_domains = I915_GEM_GPU_DOMAINS;
2199
2200 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2201 if (ret)
2202 return ret;
2203
2204 trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2205
2206 ring->gpu_caches_dirty = false;
2207 return 0;
2208 }
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