2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
32 #include <drm/i915_drm.h>
33 #include "i915_trace.h"
34 #include "intel_drv.h"
37 intel_ring_initialized(struct intel_engine_cs
*ring
)
39 struct drm_device
*dev
= ring
->dev
;
44 if (i915
.enable_execlists
) {
45 struct intel_context
*dctx
= ring
->default_context
;
46 struct intel_ringbuffer
*ringbuf
= dctx
->engine
[ring
->id
].ringbuf
;
50 return ring
->buffer
&& ring
->buffer
->obj
;
53 int __intel_ring_space(int head
, int tail
, int size
)
55 int space
= head
- (tail
+ I915_RING_FREE_SPACE
);
61 int intel_ring_space(struct intel_ringbuffer
*ringbuf
)
63 return __intel_ring_space(ringbuf
->head
& HEAD_ADDR
,
64 ringbuf
->tail
, ringbuf
->size
);
67 bool intel_ring_stopped(struct intel_engine_cs
*ring
)
69 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
70 return dev_priv
->gpu_error
.stop_rings
& intel_ring_flag(ring
);
73 void __intel_ring_advance(struct intel_engine_cs
*ring
)
75 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
76 ringbuf
->tail
&= ringbuf
->size
- 1;
77 if (intel_ring_stopped(ring
))
79 ring
->write_tail(ring
, ringbuf
->tail
);
83 gen2_render_ring_flush(struct intel_engine_cs
*ring
,
84 u32 invalidate_domains
,
91 if (((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
) == 0)
92 cmd
|= MI_NO_WRITE_FLUSH
;
94 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
97 ret
= intel_ring_begin(ring
, 2);
101 intel_ring_emit(ring
, cmd
);
102 intel_ring_emit(ring
, MI_NOOP
);
103 intel_ring_advance(ring
);
109 gen4_render_ring_flush(struct intel_engine_cs
*ring
,
110 u32 invalidate_domains
,
113 struct drm_device
*dev
= ring
->dev
;
120 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
121 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
122 * also flushed at 2d versus 3d pipeline switches.
126 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
127 * MI_READ_FLUSH is set, and is always flushed on 965.
129 * I915_GEM_DOMAIN_COMMAND may not exist?
131 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
132 * invalidated when MI_EXE_FLUSH is set.
134 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
135 * invalidated with every MI_FLUSH.
139 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
140 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
141 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
142 * are flushed at any MI_FLUSH.
145 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
146 if ((invalidate_domains
|flush_domains
) & I915_GEM_DOMAIN_RENDER
)
147 cmd
&= ~MI_NO_WRITE_FLUSH
;
148 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
151 if (invalidate_domains
& I915_GEM_DOMAIN_COMMAND
&&
152 (IS_G4X(dev
) || IS_GEN5(dev
)))
153 cmd
|= MI_INVALIDATE_ISP
;
155 ret
= intel_ring_begin(ring
, 2);
159 intel_ring_emit(ring
, cmd
);
160 intel_ring_emit(ring
, MI_NOOP
);
161 intel_ring_advance(ring
);
167 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
168 * implementing two workarounds on gen6. From section 1.4.7.1
169 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
171 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
172 * produced by non-pipelined state commands), software needs to first
173 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
176 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
177 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
179 * And the workaround for these two requires this workaround first:
181 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
182 * BEFORE the pipe-control with a post-sync op and no write-cache
185 * And this last workaround is tricky because of the requirements on
186 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
189 * "1 of the following must also be set:
190 * - Render Target Cache Flush Enable ([12] of DW1)
191 * - Depth Cache Flush Enable ([0] of DW1)
192 * - Stall at Pixel Scoreboard ([1] of DW1)
193 * - Depth Stall ([13] of DW1)
194 * - Post-Sync Operation ([13] of DW1)
195 * - Notify Enable ([8] of DW1)"
197 * The cache flushes require the workaround flush that triggered this
198 * one, so we can't use it. Depth stall would trigger the same.
199 * Post-sync nonzero is what triggered this second workaround, so we
200 * can't use that one either. Notify enable is IRQs, which aren't
201 * really our business. That leaves only stall at scoreboard.
204 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs
*ring
)
206 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
210 ret
= intel_ring_begin(ring
, 6);
214 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
215 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
216 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
217 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
218 intel_ring_emit(ring
, 0); /* low dword */
219 intel_ring_emit(ring
, 0); /* high dword */
220 intel_ring_emit(ring
, MI_NOOP
);
221 intel_ring_advance(ring
);
223 ret
= intel_ring_begin(ring
, 6);
227 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
228 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
229 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
); /* address */
230 intel_ring_emit(ring
, 0);
231 intel_ring_emit(ring
, 0);
232 intel_ring_emit(ring
, MI_NOOP
);
233 intel_ring_advance(ring
);
239 gen6_render_ring_flush(struct intel_engine_cs
*ring
,
240 u32 invalidate_domains
, u32 flush_domains
)
243 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
246 /* Force SNB workarounds for PIPE_CONTROL flushes */
247 ret
= intel_emit_post_sync_nonzero_flush(ring
);
251 /* Just flush everything. Experiments have shown that reducing the
252 * number of bits based on the write domains has little performance
256 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
257 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
259 * Ensure that any following seqno writes only happen
260 * when the render cache is indeed flushed.
262 flags
|= PIPE_CONTROL_CS_STALL
;
264 if (invalidate_domains
) {
265 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
266 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
267 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
268 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
269 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
270 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
272 * TLB invalidate requires a post-sync write.
274 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
277 ret
= intel_ring_begin(ring
, 4);
281 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
282 intel_ring_emit(ring
, flags
);
283 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
284 intel_ring_emit(ring
, 0);
285 intel_ring_advance(ring
);
291 gen7_render_ring_cs_stall_wa(struct intel_engine_cs
*ring
)
295 ret
= intel_ring_begin(ring
, 4);
299 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
300 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
301 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
302 intel_ring_emit(ring
, 0);
303 intel_ring_emit(ring
, 0);
304 intel_ring_advance(ring
);
309 static int gen7_ring_fbc_flush(struct intel_engine_cs
*ring
, u32 value
)
313 if (!ring
->fbc_dirty
)
316 ret
= intel_ring_begin(ring
, 6);
319 /* WaFbcNukeOn3DBlt:ivb/hsw */
320 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
321 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
322 intel_ring_emit(ring
, value
);
323 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT
);
324 intel_ring_emit(ring
, MSG_FBC_REND_STATE
);
325 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
326 intel_ring_advance(ring
);
328 ring
->fbc_dirty
= false;
333 gen7_render_ring_flush(struct intel_engine_cs
*ring
,
334 u32 invalidate_domains
, u32 flush_domains
)
337 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
341 * Ensure that any following seqno writes only happen when the render
342 * cache is indeed flushed.
344 * Workaround: 4th PIPE_CONTROL command (except the ones with only
345 * read-cache invalidate bits set) must have the CS_STALL bit set. We
346 * don't try to be clever and just set it unconditionally.
348 flags
|= PIPE_CONTROL_CS_STALL
;
350 /* Just flush everything. Experiments have shown that reducing the
351 * number of bits based on the write domains has little performance
355 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
356 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
358 if (invalidate_domains
) {
359 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
360 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
361 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
362 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
363 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
364 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
365 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
367 * TLB invalidate requires a post-sync write.
369 flags
|= PIPE_CONTROL_QW_WRITE
;
370 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
372 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
374 /* Workaround: we must issue a pipe_control with CS-stall bit
375 * set before a pipe_control command that has the state cache
376 * invalidate bit set. */
377 gen7_render_ring_cs_stall_wa(ring
);
380 ret
= intel_ring_begin(ring
, 4);
384 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
385 intel_ring_emit(ring
, flags
);
386 intel_ring_emit(ring
, scratch_addr
);
387 intel_ring_emit(ring
, 0);
388 intel_ring_advance(ring
);
390 if (!invalidate_domains
&& flush_domains
)
391 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
397 gen8_emit_pipe_control(struct intel_engine_cs
*ring
,
398 u32 flags
, u32 scratch_addr
)
402 ret
= intel_ring_begin(ring
, 6);
406 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
407 intel_ring_emit(ring
, flags
);
408 intel_ring_emit(ring
, scratch_addr
);
409 intel_ring_emit(ring
, 0);
410 intel_ring_emit(ring
, 0);
411 intel_ring_emit(ring
, 0);
412 intel_ring_advance(ring
);
418 gen8_render_ring_flush(struct intel_engine_cs
*ring
,
419 u32 invalidate_domains
, u32 flush_domains
)
422 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
425 flags
|= PIPE_CONTROL_CS_STALL
;
428 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
429 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
431 if (invalidate_domains
) {
432 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
433 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
434 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
435 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
436 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
437 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
438 flags
|= PIPE_CONTROL_QW_WRITE
;
439 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
441 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
442 ret
= gen8_emit_pipe_control(ring
,
443 PIPE_CONTROL_CS_STALL
|
444 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
450 ret
= gen8_emit_pipe_control(ring
, flags
, scratch_addr
);
454 if (!invalidate_domains
&& flush_domains
)
455 return gen7_ring_fbc_flush(ring
, FBC_REND_NUKE
);
460 static void ring_write_tail(struct intel_engine_cs
*ring
,
463 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
464 I915_WRITE_TAIL(ring
, value
);
467 u64
intel_ring_get_active_head(struct intel_engine_cs
*ring
)
469 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
472 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
473 acthd
= I915_READ64_2x32(RING_ACTHD(ring
->mmio_base
),
474 RING_ACTHD_UDW(ring
->mmio_base
));
475 else if (INTEL_INFO(ring
->dev
)->gen
>= 4)
476 acthd
= I915_READ(RING_ACTHD(ring
->mmio_base
));
478 acthd
= I915_READ(ACTHD
);
483 static void ring_setup_phys_status_page(struct intel_engine_cs
*ring
)
485 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
488 addr
= dev_priv
->status_page_dmah
->busaddr
;
489 if (INTEL_INFO(ring
->dev
)->gen
>= 4)
490 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
491 I915_WRITE(HWS_PGA
, addr
);
494 static bool stop_ring(struct intel_engine_cs
*ring
)
496 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
498 if (!IS_GEN2(ring
->dev
)) {
499 I915_WRITE_MODE(ring
, _MASKED_BIT_ENABLE(STOP_RING
));
500 if (wait_for((I915_READ_MODE(ring
) & MODE_IDLE
) != 0, 1000)) {
501 DRM_ERROR("%s : timed out trying to stop ring\n", ring
->name
);
502 /* Sometimes we observe that the idle flag is not
503 * set even though the ring is empty. So double
504 * check before giving up.
506 if (I915_READ_HEAD(ring
) != I915_READ_TAIL(ring
))
511 I915_WRITE_CTL(ring
, 0);
512 I915_WRITE_HEAD(ring
, 0);
513 ring
->write_tail(ring
, 0);
515 if (!IS_GEN2(ring
->dev
)) {
516 (void)I915_READ_CTL(ring
);
517 I915_WRITE_MODE(ring
, _MASKED_BIT_DISABLE(STOP_RING
));
520 return (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0;
523 static int init_ring_common(struct intel_engine_cs
*ring
)
525 struct drm_device
*dev
= ring
->dev
;
526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
527 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
528 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
531 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
533 if (!stop_ring(ring
)) {
534 /* G45 ring initialization often fails to reset head to zero */
535 DRM_DEBUG_KMS("%s head not reset to zero "
536 "ctl %08x head %08x tail %08x start %08x\n",
539 I915_READ_HEAD(ring
),
540 I915_READ_TAIL(ring
),
541 I915_READ_START(ring
));
543 if (!stop_ring(ring
)) {
544 DRM_ERROR("failed to set %s head to zero "
545 "ctl %08x head %08x tail %08x start %08x\n",
548 I915_READ_HEAD(ring
),
549 I915_READ_TAIL(ring
),
550 I915_READ_START(ring
));
556 if (I915_NEED_GFX_HWS(dev
))
557 intel_ring_setup_status_page(ring
);
559 ring_setup_phys_status_page(ring
);
561 /* Enforce ordering by reading HEAD register back */
562 I915_READ_HEAD(ring
);
564 /* Initialize the ring. This must happen _after_ we've cleared the ring
565 * registers with the above sequence (the readback of the HEAD registers
566 * also enforces ordering), otherwise the hw might lose the new ring
567 * register values. */
568 I915_WRITE_START(ring
, i915_gem_obj_ggtt_offset(obj
));
570 /* WaClearRingBufHeadRegAtInit:ctg,elk */
571 if (I915_READ_HEAD(ring
))
572 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
573 ring
->name
, I915_READ_HEAD(ring
));
574 I915_WRITE_HEAD(ring
, 0);
575 (void)I915_READ_HEAD(ring
);
578 ((ringbuf
->size
- PAGE_SIZE
) & RING_NR_PAGES
)
581 /* If the head is still not zero, the ring is dead */
582 if (wait_for((I915_READ_CTL(ring
) & RING_VALID
) != 0 &&
583 I915_READ_START(ring
) == i915_gem_obj_ggtt_offset(obj
) &&
584 (I915_READ_HEAD(ring
) & HEAD_ADDR
) == 0, 50)) {
585 DRM_ERROR("%s initialization failed "
586 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
588 I915_READ_CTL(ring
), I915_READ_CTL(ring
) & RING_VALID
,
589 I915_READ_HEAD(ring
), I915_READ_TAIL(ring
),
590 I915_READ_START(ring
), (unsigned long)i915_gem_obj_ggtt_offset(obj
));
595 ringbuf
->head
= I915_READ_HEAD(ring
);
596 ringbuf
->tail
= I915_READ_TAIL(ring
) & TAIL_ADDR
;
597 ringbuf
->space
= intel_ring_space(ringbuf
);
598 ringbuf
->last_retired_head
= -1;
600 memset(&ring
->hangcheck
, 0, sizeof(ring
->hangcheck
));
603 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
609 intel_fini_pipe_control(struct intel_engine_cs
*ring
)
611 struct drm_device
*dev
= ring
->dev
;
613 if (ring
->scratch
.obj
== NULL
)
616 if (INTEL_INFO(dev
)->gen
>= 5) {
617 kunmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
618 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
621 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
622 ring
->scratch
.obj
= NULL
;
626 intel_init_pipe_control(struct intel_engine_cs
*ring
)
630 if (ring
->scratch
.obj
)
633 ring
->scratch
.obj
= i915_gem_alloc_object(ring
->dev
, 4096);
634 if (ring
->scratch
.obj
== NULL
) {
635 DRM_ERROR("Failed to allocate seqno page\n");
640 ret
= i915_gem_object_set_cache_level(ring
->scratch
.obj
, I915_CACHE_LLC
);
644 ret
= i915_gem_obj_ggtt_pin(ring
->scratch
.obj
, 4096, 0);
648 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(ring
->scratch
.obj
);
649 ring
->scratch
.cpu_page
= kmap(sg_page(ring
->scratch
.obj
->pages
->sgl
));
650 if (ring
->scratch
.cpu_page
== NULL
) {
655 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
656 ring
->name
, ring
->scratch
.gtt_offset
);
660 i915_gem_object_ggtt_unpin(ring
->scratch
.obj
);
662 drm_gem_object_unreference(&ring
->scratch
.obj
->base
);
667 static int intel_ring_workarounds_emit(struct intel_engine_cs
*ring
,
668 struct intel_context
*ctx
)
671 struct drm_device
*dev
= ring
->dev
;
672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
673 struct i915_workarounds
*w
= &dev_priv
->workarounds
;
675 if (WARN_ON(w
->count
== 0))
678 ring
->gpu_caches_dirty
= true;
679 ret
= intel_ring_flush_all_caches(ring
);
683 ret
= intel_ring_begin(ring
, (w
->count
* 2 + 2));
687 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
688 for (i
= 0; i
< w
->count
; i
++) {
689 intel_ring_emit(ring
, w
->reg
[i
].addr
);
690 intel_ring_emit(ring
, w
->reg
[i
].value
);
692 intel_ring_emit(ring
, MI_NOOP
);
694 intel_ring_advance(ring
);
696 ring
->gpu_caches_dirty
= true;
697 ret
= intel_ring_flush_all_caches(ring
);
701 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
706 static int wa_add(struct drm_i915_private
*dev_priv
,
707 const u32 addr
, const u32 mask
, const u32 val
)
709 const u32 idx
= dev_priv
->workarounds
.count
;
711 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
714 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
715 dev_priv
->workarounds
.reg
[idx
].value
= val
;
716 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
718 dev_priv
->workarounds
.count
++;
723 #define WA_REG(addr, mask, val) { \
724 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
729 #define WA_SET_BIT_MASKED(addr, mask) \
730 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
732 #define WA_CLR_BIT_MASKED(addr, mask) \
733 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
735 #define WA_SET_FIELD_MASKED(addr, mask, value) \
736 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
738 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
739 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
741 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
743 static int bdw_init_workarounds(struct intel_engine_cs
*ring
)
745 struct drm_device
*dev
= ring
->dev
;
746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
748 /* WaDisablePartialInstShootdown:bdw */
749 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
750 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
751 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
752 STALL_DOP_GATING_DISABLE
);
754 /* WaDisableDopClockGating:bdw */
755 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
756 DOP_CLOCK_GATING_DISABLE
);
758 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
759 GEN8_SAMPLER_POWER_BYPASS_DIS
);
761 /* Use Force Non-Coherent whenever executing a 3D context. This is a
762 * workaround for for a possible hang in the unlikely event a TLB
763 * invalidation occurs during a PSD flush.
765 /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
766 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
767 HDC_FORCE_NON_COHERENT
|
768 (IS_BDW_GT3(dev
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
770 /* Wa4x4STCOptimizationDisable:bdw */
771 WA_SET_BIT_MASKED(CACHE_MODE_1
,
772 GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
775 * BSpec recommends 8x4 when MSAA is used,
776 * however in practice 16x4 seems fastest.
778 * Note that PS/WM thread counts depend on the WIZ hashing
779 * disable bit, which we don't touch here, but it's good
780 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
782 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
783 GEN6_WIZ_HASHING_MASK
,
784 GEN6_WIZ_HASHING_16x4
);
789 static int chv_init_workarounds(struct intel_engine_cs
*ring
)
791 struct drm_device
*dev
= ring
->dev
;
792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
794 /* WaDisablePartialInstShootdown:chv */
795 /* WaDisableThreadStallDopClockGating:chv */
796 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
797 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
|
798 STALL_DOP_GATING_DISABLE
);
800 /* Use Force Non-Coherent whenever executing a 3D context. This is a
801 * workaround for a possible hang in the unlikely event a TLB
802 * invalidation occurs during a PSD flush.
804 /* WaForceEnableNonCoherent:chv */
805 /* WaHdcDisableFetchWhenMasked:chv */
806 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
807 HDC_FORCE_NON_COHERENT
|
808 HDC_DONOT_FETCH_MEM_WHEN_MASKED
);
813 int init_workarounds_ring(struct intel_engine_cs
*ring
)
815 struct drm_device
*dev
= ring
->dev
;
816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
818 WARN_ON(ring
->id
!= RCS
);
820 dev_priv
->workarounds
.count
= 0;
822 if (IS_BROADWELL(dev
))
823 return bdw_init_workarounds(ring
);
825 if (IS_CHERRYVIEW(dev
))
826 return chv_init_workarounds(ring
);
831 static int init_render_ring(struct intel_engine_cs
*ring
)
833 struct drm_device
*dev
= ring
->dev
;
834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
835 int ret
= init_ring_common(ring
);
839 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
840 if (INTEL_INFO(dev
)->gen
>= 4 && INTEL_INFO(dev
)->gen
< 7)
841 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
843 /* We need to disable the AsyncFlip performance optimisations in order
844 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
845 * programmed to '1' on all products.
847 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
849 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 9)
850 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
852 /* Required for the hardware to program scanline values for waiting */
853 /* WaEnableFlushTlbInvalidationMode:snb */
854 if (INTEL_INFO(dev
)->gen
== 6)
856 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
858 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
860 I915_WRITE(GFX_MODE_GEN7
,
861 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
862 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
864 if (INTEL_INFO(dev
)->gen
>= 5) {
865 ret
= intel_init_pipe_control(ring
);
871 /* From the Sandybridge PRM, volume 1 part 3, page 24:
872 * "If this bit is set, STCunit will have LRA as replacement
873 * policy. [...] This bit must be reset. LRA replacement
874 * policy is not supported."
876 I915_WRITE(CACHE_MODE_0
,
877 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
880 if (INTEL_INFO(dev
)->gen
>= 6)
881 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
884 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
886 return init_workarounds_ring(ring
);
889 static void render_ring_cleanup(struct intel_engine_cs
*ring
)
891 struct drm_device
*dev
= ring
->dev
;
892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
894 if (dev_priv
->semaphore_obj
) {
895 i915_gem_object_ggtt_unpin(dev_priv
->semaphore_obj
);
896 drm_gem_object_unreference(&dev_priv
->semaphore_obj
->base
);
897 dev_priv
->semaphore_obj
= NULL
;
900 intel_fini_pipe_control(ring
);
903 static int gen8_rcs_signal(struct intel_engine_cs
*signaller
,
904 unsigned int num_dwords
)
906 #define MBOX_UPDATE_DWORDS 8
907 struct drm_device
*dev
= signaller
->dev
;
908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
909 struct intel_engine_cs
*waiter
;
910 int i
, ret
, num_rings
;
912 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
913 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
914 #undef MBOX_UPDATE_DWORDS
916 ret
= intel_ring_begin(signaller
, num_dwords
);
920 for_each_ring(waiter
, dev_priv
, i
) {
921 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
922 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
925 intel_ring_emit(signaller
, GFX_OP_PIPE_CONTROL(6));
926 intel_ring_emit(signaller
, PIPE_CONTROL_GLOBAL_GTT_IVB
|
927 PIPE_CONTROL_QW_WRITE
|
928 PIPE_CONTROL_FLUSH_ENABLE
);
929 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
));
930 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
931 intel_ring_emit(signaller
, signaller
->outstanding_lazy_seqno
);
932 intel_ring_emit(signaller
, 0);
933 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
934 MI_SEMAPHORE_TARGET(waiter
->id
));
935 intel_ring_emit(signaller
, 0);
941 static int gen8_xcs_signal(struct intel_engine_cs
*signaller
,
942 unsigned int num_dwords
)
944 #define MBOX_UPDATE_DWORDS 6
945 struct drm_device
*dev
= signaller
->dev
;
946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
947 struct intel_engine_cs
*waiter
;
948 int i
, ret
, num_rings
;
950 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
951 num_dwords
+= (num_rings
-1) * MBOX_UPDATE_DWORDS
;
952 #undef MBOX_UPDATE_DWORDS
954 ret
= intel_ring_begin(signaller
, num_dwords
);
958 for_each_ring(waiter
, dev_priv
, i
) {
959 u64 gtt_offset
= signaller
->semaphore
.signal_ggtt
[i
];
960 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
963 intel_ring_emit(signaller
, (MI_FLUSH_DW
+ 1) |
964 MI_FLUSH_DW_OP_STOREDW
);
965 intel_ring_emit(signaller
, lower_32_bits(gtt_offset
) |
966 MI_FLUSH_DW_USE_GTT
);
967 intel_ring_emit(signaller
, upper_32_bits(gtt_offset
));
968 intel_ring_emit(signaller
, signaller
->outstanding_lazy_seqno
);
969 intel_ring_emit(signaller
, MI_SEMAPHORE_SIGNAL
|
970 MI_SEMAPHORE_TARGET(waiter
->id
));
971 intel_ring_emit(signaller
, 0);
977 static int gen6_signal(struct intel_engine_cs
*signaller
,
978 unsigned int num_dwords
)
980 struct drm_device
*dev
= signaller
->dev
;
981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
982 struct intel_engine_cs
*useless
;
983 int i
, ret
, num_rings
;
985 #define MBOX_UPDATE_DWORDS 3
986 num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
987 num_dwords
+= round_up((num_rings
-1) * MBOX_UPDATE_DWORDS
, 2);
988 #undef MBOX_UPDATE_DWORDS
990 ret
= intel_ring_begin(signaller
, num_dwords
);
994 for_each_ring(useless
, dev_priv
, i
) {
995 u32 mbox_reg
= signaller
->semaphore
.mbox
.signal
[i
];
996 if (mbox_reg
!= GEN6_NOSYNC
) {
997 intel_ring_emit(signaller
, MI_LOAD_REGISTER_IMM(1));
998 intel_ring_emit(signaller
, mbox_reg
);
999 intel_ring_emit(signaller
, signaller
->outstanding_lazy_seqno
);
1003 /* If num_dwords was rounded, make sure the tail pointer is correct */
1004 if (num_rings
% 2 == 0)
1005 intel_ring_emit(signaller
, MI_NOOP
);
1011 * gen6_add_request - Update the semaphore mailbox registers
1013 * @ring - ring that is adding a request
1014 * @seqno - return seqno stuck into the ring
1016 * Update the mailbox registers in the *other* rings with the current seqno.
1017 * This acts like a signal in the canonical semaphore.
1020 gen6_add_request(struct intel_engine_cs
*ring
)
1024 if (ring
->semaphore
.signal
)
1025 ret
= ring
->semaphore
.signal(ring
, 4);
1027 ret
= intel_ring_begin(ring
, 4);
1032 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1033 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1034 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1035 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1036 __intel_ring_advance(ring
);
1041 static inline bool i915_gem_has_seqno_wrapped(struct drm_device
*dev
,
1044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1045 return dev_priv
->last_seqno
< seqno
;
1049 * intel_ring_sync - sync the waiter to the signaller on seqno
1051 * @waiter - ring that is waiting
1052 * @signaller - ring which has, or will signal
1053 * @seqno - seqno which the waiter will block on
1057 gen8_ring_sync(struct intel_engine_cs
*waiter
,
1058 struct intel_engine_cs
*signaller
,
1061 struct drm_i915_private
*dev_priv
= waiter
->dev
->dev_private
;
1064 ret
= intel_ring_begin(waiter
, 4);
1068 intel_ring_emit(waiter
, MI_SEMAPHORE_WAIT
|
1069 MI_SEMAPHORE_GLOBAL_GTT
|
1071 MI_SEMAPHORE_SAD_GTE_SDD
);
1072 intel_ring_emit(waiter
, seqno
);
1073 intel_ring_emit(waiter
,
1074 lower_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1075 intel_ring_emit(waiter
,
1076 upper_32_bits(GEN8_WAIT_OFFSET(waiter
, signaller
->id
)));
1077 intel_ring_advance(waiter
);
1082 gen6_ring_sync(struct intel_engine_cs
*waiter
,
1083 struct intel_engine_cs
*signaller
,
1086 u32 dw1
= MI_SEMAPHORE_MBOX
|
1087 MI_SEMAPHORE_COMPARE
|
1088 MI_SEMAPHORE_REGISTER
;
1089 u32 wait_mbox
= signaller
->semaphore
.mbox
.wait
[waiter
->id
];
1092 /* Throughout all of the GEM code, seqno passed implies our current
1093 * seqno is >= the last seqno executed. However for hardware the
1094 * comparison is strictly greater than.
1098 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1100 ret
= intel_ring_begin(waiter
, 4);
1104 /* If seqno wrap happened, omit the wait with no-ops */
1105 if (likely(!i915_gem_has_seqno_wrapped(waiter
->dev
, seqno
))) {
1106 intel_ring_emit(waiter
, dw1
| wait_mbox
);
1107 intel_ring_emit(waiter
, seqno
);
1108 intel_ring_emit(waiter
, 0);
1109 intel_ring_emit(waiter
, MI_NOOP
);
1111 intel_ring_emit(waiter
, MI_NOOP
);
1112 intel_ring_emit(waiter
, MI_NOOP
);
1113 intel_ring_emit(waiter
, MI_NOOP
);
1114 intel_ring_emit(waiter
, MI_NOOP
);
1116 intel_ring_advance(waiter
);
1121 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
1123 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1124 PIPE_CONTROL_DEPTH_STALL); \
1125 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1126 intel_ring_emit(ring__, 0); \
1127 intel_ring_emit(ring__, 0); \
1131 pc_render_add_request(struct intel_engine_cs
*ring
)
1133 u32 scratch_addr
= ring
->scratch
.gtt_offset
+ 2 * CACHELINE_BYTES
;
1136 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1137 * incoherent with writes to memory, i.e. completely fubar,
1138 * so we need to use PIPE_NOTIFY instead.
1140 * However, we also need to workaround the qword write
1141 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1142 * memory before requesting an interrupt.
1144 ret
= intel_ring_begin(ring
, 32);
1148 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1149 PIPE_CONTROL_WRITE_FLUSH
|
1150 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
1151 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1152 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1153 intel_ring_emit(ring
, 0);
1154 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1155 scratch_addr
+= 2 * CACHELINE_BYTES
; /* write to separate cachelines */
1156 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1157 scratch_addr
+= 2 * CACHELINE_BYTES
;
1158 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1159 scratch_addr
+= 2 * CACHELINE_BYTES
;
1160 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1161 scratch_addr
+= 2 * CACHELINE_BYTES
;
1162 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1163 scratch_addr
+= 2 * CACHELINE_BYTES
;
1164 PIPE_CONTROL_FLUSH(ring
, scratch_addr
);
1166 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE
|
1167 PIPE_CONTROL_WRITE_FLUSH
|
1168 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
|
1169 PIPE_CONTROL_NOTIFY
);
1170 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
| PIPE_CONTROL_GLOBAL_GTT
);
1171 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1172 intel_ring_emit(ring
, 0);
1173 __intel_ring_advance(ring
);
1179 gen6_ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1181 /* Workaround to force correct ordering between irq and seqno writes on
1182 * ivb (and maybe also on snb) by reading from a CS register (like
1183 * ACTHD) before reading the status page. */
1184 if (!lazy_coherency
) {
1185 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1186 POSTING_READ(RING_ACTHD(ring
->mmio_base
));
1189 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1193 ring_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1195 return intel_read_status_page(ring
, I915_GEM_HWS_INDEX
);
1199 ring_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1201 intel_write_status_page(ring
, I915_GEM_HWS_INDEX
, seqno
);
1205 pc_render_get_seqno(struct intel_engine_cs
*ring
, bool lazy_coherency
)
1207 return ring
->scratch
.cpu_page
[0];
1211 pc_render_set_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
1213 ring
->scratch
.cpu_page
[0] = seqno
;
1217 gen5_ring_get_irq(struct intel_engine_cs
*ring
)
1219 struct drm_device
*dev
= ring
->dev
;
1220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1221 unsigned long flags
;
1223 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1226 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1227 if (ring
->irq_refcount
++ == 0)
1228 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1229 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1235 gen5_ring_put_irq(struct intel_engine_cs
*ring
)
1237 struct drm_device
*dev
= ring
->dev
;
1238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1239 unsigned long flags
;
1241 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1242 if (--ring
->irq_refcount
== 0)
1243 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1244 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1248 i9xx_ring_get_irq(struct intel_engine_cs
*ring
)
1250 struct drm_device
*dev
= ring
->dev
;
1251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1252 unsigned long flags
;
1254 if (!intel_irqs_enabled(dev_priv
))
1257 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1258 if (ring
->irq_refcount
++ == 0) {
1259 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1260 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1263 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1269 i9xx_ring_put_irq(struct intel_engine_cs
*ring
)
1271 struct drm_device
*dev
= ring
->dev
;
1272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1273 unsigned long flags
;
1275 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1276 if (--ring
->irq_refcount
== 0) {
1277 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1278 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1281 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1285 i8xx_ring_get_irq(struct intel_engine_cs
*ring
)
1287 struct drm_device
*dev
= ring
->dev
;
1288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1289 unsigned long flags
;
1291 if (!intel_irqs_enabled(dev_priv
))
1294 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1295 if (ring
->irq_refcount
++ == 0) {
1296 dev_priv
->irq_mask
&= ~ring
->irq_enable_mask
;
1297 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1298 POSTING_READ16(IMR
);
1300 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1306 i8xx_ring_put_irq(struct intel_engine_cs
*ring
)
1308 struct drm_device
*dev
= ring
->dev
;
1309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1310 unsigned long flags
;
1312 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1313 if (--ring
->irq_refcount
== 0) {
1314 dev_priv
->irq_mask
|= ring
->irq_enable_mask
;
1315 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1316 POSTING_READ16(IMR
);
1318 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1321 void intel_ring_setup_status_page(struct intel_engine_cs
*ring
)
1323 struct drm_device
*dev
= ring
->dev
;
1324 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1327 /* The ring status page addresses are no longer next to the rest of
1328 * the ring registers as of gen7.
1333 mmio
= RENDER_HWS_PGA_GEN7
;
1336 mmio
= BLT_HWS_PGA_GEN7
;
1339 * VCS2 actually doesn't exist on Gen7. Only shut up
1340 * gcc switch check warning
1344 mmio
= BSD_HWS_PGA_GEN7
;
1347 mmio
= VEBOX_HWS_PGA_GEN7
;
1350 } else if (IS_GEN6(ring
->dev
)) {
1351 mmio
= RING_HWS_PGA_GEN6(ring
->mmio_base
);
1353 /* XXX: gen8 returns to sanity */
1354 mmio
= RING_HWS_PGA(ring
->mmio_base
);
1357 I915_WRITE(mmio
, (u32
)ring
->status_page
.gfx_addr
);
1361 * Flush the TLB for this page
1363 * FIXME: These two bits have disappeared on gen8, so a question
1364 * arises: do we still need this and if so how should we go about
1365 * invalidating the TLB?
1367 if (INTEL_INFO(dev
)->gen
>= 6 && INTEL_INFO(dev
)->gen
< 8) {
1368 u32 reg
= RING_INSTPM(ring
->mmio_base
);
1370 /* ring should be idle before issuing a sync flush*/
1371 WARN_ON((I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1374 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
1375 INSTPM_SYNC_FLUSH
));
1376 if (wait_for((I915_READ(reg
) & INSTPM_SYNC_FLUSH
) == 0,
1378 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1384 bsd_ring_flush(struct intel_engine_cs
*ring
,
1385 u32 invalidate_domains
,
1390 ret
= intel_ring_begin(ring
, 2);
1394 intel_ring_emit(ring
, MI_FLUSH
);
1395 intel_ring_emit(ring
, MI_NOOP
);
1396 intel_ring_advance(ring
);
1401 i9xx_add_request(struct intel_engine_cs
*ring
)
1405 ret
= intel_ring_begin(ring
, 4);
1409 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1410 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1411 intel_ring_emit(ring
, ring
->outstanding_lazy_seqno
);
1412 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1413 __intel_ring_advance(ring
);
1419 gen6_ring_get_irq(struct intel_engine_cs
*ring
)
1421 struct drm_device
*dev
= ring
->dev
;
1422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1423 unsigned long flags
;
1425 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1428 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1429 if (ring
->irq_refcount
++ == 0) {
1430 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1431 I915_WRITE_IMR(ring
,
1432 ~(ring
->irq_enable_mask
|
1433 GT_PARITY_ERROR(dev
)));
1435 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1436 gen5_enable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1438 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1444 gen6_ring_put_irq(struct intel_engine_cs
*ring
)
1446 struct drm_device
*dev
= ring
->dev
;
1447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1448 unsigned long flags
;
1450 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1451 if (--ring
->irq_refcount
== 0) {
1452 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
)
1453 I915_WRITE_IMR(ring
, ~GT_PARITY_ERROR(dev
));
1455 I915_WRITE_IMR(ring
, ~0);
1456 gen5_disable_gt_irq(dev_priv
, ring
->irq_enable_mask
);
1458 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1462 hsw_vebox_get_irq(struct intel_engine_cs
*ring
)
1464 struct drm_device
*dev
= ring
->dev
;
1465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1466 unsigned long flags
;
1468 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1471 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1472 if (ring
->irq_refcount
++ == 0) {
1473 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1474 gen6_enable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1476 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1482 hsw_vebox_put_irq(struct intel_engine_cs
*ring
)
1484 struct drm_device
*dev
= ring
->dev
;
1485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1486 unsigned long flags
;
1488 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1489 if (--ring
->irq_refcount
== 0) {
1490 I915_WRITE_IMR(ring
, ~0);
1491 gen6_disable_pm_irq(dev_priv
, ring
->irq_enable_mask
);
1493 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1497 gen8_ring_get_irq(struct intel_engine_cs
*ring
)
1499 struct drm_device
*dev
= ring
->dev
;
1500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1501 unsigned long flags
;
1503 if (WARN_ON(!intel_irqs_enabled(dev_priv
)))
1506 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1507 if (ring
->irq_refcount
++ == 0) {
1508 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1509 I915_WRITE_IMR(ring
,
1510 ~(ring
->irq_enable_mask
|
1511 GT_RENDER_L3_PARITY_ERROR_INTERRUPT
));
1513 I915_WRITE_IMR(ring
, ~ring
->irq_enable_mask
);
1515 POSTING_READ(RING_IMR(ring
->mmio_base
));
1517 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1523 gen8_ring_put_irq(struct intel_engine_cs
*ring
)
1525 struct drm_device
*dev
= ring
->dev
;
1526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1527 unsigned long flags
;
1529 spin_lock_irqsave(&dev_priv
->irq_lock
, flags
);
1530 if (--ring
->irq_refcount
== 0) {
1531 if (HAS_L3_DPF(dev
) && ring
->id
== RCS
) {
1532 I915_WRITE_IMR(ring
,
1533 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT
);
1535 I915_WRITE_IMR(ring
, ~0);
1537 POSTING_READ(RING_IMR(ring
->mmio_base
));
1539 spin_unlock_irqrestore(&dev_priv
->irq_lock
, flags
);
1543 i965_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1544 u64 offset
, u32 length
,
1549 ret
= intel_ring_begin(ring
, 2);
1553 intel_ring_emit(ring
,
1554 MI_BATCH_BUFFER_START
|
1556 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
1557 intel_ring_emit(ring
, offset
);
1558 intel_ring_advance(ring
);
1563 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1564 #define I830_BATCH_LIMIT (256*1024)
1565 #define I830_TLB_ENTRIES (2)
1566 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1568 i830_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1569 u64 offset
, u32 len
,
1572 u32 cs_offset
= ring
->scratch
.gtt_offset
;
1575 ret
= intel_ring_begin(ring
, 6);
1579 /* Evict the invalid PTE TLBs */
1580 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1581 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1582 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1583 intel_ring_emit(ring
, cs_offset
);
1584 intel_ring_emit(ring
, 0xdeadbeef);
1585 intel_ring_emit(ring
, MI_NOOP
);
1586 intel_ring_advance(ring
);
1588 if ((flags
& I915_DISPATCH_PINNED
) == 0) {
1589 if (len
> I830_BATCH_LIMIT
)
1592 ret
= intel_ring_begin(ring
, 6 + 2);
1596 /* Blit the batch (which has now all relocs applied) to the
1597 * stable batch scratch bo area (so that the CS never
1598 * stumbles over its tlb invalidation bug) ...
1600 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1601 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1602 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1603 intel_ring_emit(ring
, cs_offset
);
1604 intel_ring_emit(ring
, 4096);
1605 intel_ring_emit(ring
, offset
);
1607 intel_ring_emit(ring
, MI_FLUSH
);
1608 intel_ring_emit(ring
, MI_NOOP
);
1609 intel_ring_advance(ring
);
1611 /* ... and execute it. */
1615 ret
= intel_ring_begin(ring
, 4);
1619 intel_ring_emit(ring
, MI_BATCH_BUFFER
);
1620 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1621 intel_ring_emit(ring
, offset
+ len
- 8);
1622 intel_ring_emit(ring
, MI_NOOP
);
1623 intel_ring_advance(ring
);
1629 i915_dispatch_execbuffer(struct intel_engine_cs
*ring
,
1630 u64 offset
, u32 len
,
1635 ret
= intel_ring_begin(ring
, 2);
1639 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1640 intel_ring_emit(ring
, offset
| (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE
));
1641 intel_ring_advance(ring
);
1646 static void cleanup_status_page(struct intel_engine_cs
*ring
)
1648 struct drm_i915_gem_object
*obj
;
1650 obj
= ring
->status_page
.obj
;
1654 kunmap(sg_page(obj
->pages
->sgl
));
1655 i915_gem_object_ggtt_unpin(obj
);
1656 drm_gem_object_unreference(&obj
->base
);
1657 ring
->status_page
.obj
= NULL
;
1660 static int init_status_page(struct intel_engine_cs
*ring
)
1662 struct drm_i915_gem_object
*obj
;
1664 if ((obj
= ring
->status_page
.obj
) == NULL
) {
1668 obj
= i915_gem_alloc_object(ring
->dev
, 4096);
1670 DRM_ERROR("Failed to allocate status page\n");
1674 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1679 if (!HAS_LLC(ring
->dev
))
1680 /* On g33, we cannot place HWS above 256MiB, so
1681 * restrict its pinning to the low mappable arena.
1682 * Though this restriction is not documented for
1683 * gen4, gen5, or byt, they also behave similarly
1684 * and hang if the HWS is placed at the top of the
1685 * GTT. To generalise, it appears that all !llc
1686 * platforms have issues with us placing the HWS
1687 * above the mappable region (even though we never
1690 flags
|= PIN_MAPPABLE
;
1691 ret
= i915_gem_obj_ggtt_pin(obj
, 4096, flags
);
1694 drm_gem_object_unreference(&obj
->base
);
1698 ring
->status_page
.obj
= obj
;
1701 ring
->status_page
.gfx_addr
= i915_gem_obj_ggtt_offset(obj
);
1702 ring
->status_page
.page_addr
= kmap(sg_page(obj
->pages
->sgl
));
1703 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1705 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1706 ring
->name
, ring
->status_page
.gfx_addr
);
1711 static int init_phys_status_page(struct intel_engine_cs
*ring
)
1713 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
1715 if (!dev_priv
->status_page_dmah
) {
1716 dev_priv
->status_page_dmah
=
1717 drm_pci_alloc(ring
->dev
, PAGE_SIZE
, PAGE_SIZE
);
1718 if (!dev_priv
->status_page_dmah
)
1722 ring
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1723 memset(ring
->status_page
.page_addr
, 0, PAGE_SIZE
);
1728 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1730 iounmap(ringbuf
->virtual_start
);
1731 ringbuf
->virtual_start
= NULL
;
1732 i915_gem_object_ggtt_unpin(ringbuf
->obj
);
1735 int intel_pin_and_map_ringbuffer_obj(struct drm_device
*dev
,
1736 struct intel_ringbuffer
*ringbuf
)
1738 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1739 struct drm_i915_gem_object
*obj
= ringbuf
->obj
;
1742 ret
= i915_gem_obj_ggtt_pin(obj
, PAGE_SIZE
, PIN_MAPPABLE
);
1746 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
1748 i915_gem_object_ggtt_unpin(obj
);
1752 ringbuf
->virtual_start
= ioremap_wc(dev_priv
->gtt
.mappable_base
+
1753 i915_gem_obj_ggtt_offset(obj
), ringbuf
->size
);
1754 if (ringbuf
->virtual_start
== NULL
) {
1755 i915_gem_object_ggtt_unpin(obj
);
1762 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer
*ringbuf
)
1764 drm_gem_object_unreference(&ringbuf
->obj
->base
);
1765 ringbuf
->obj
= NULL
;
1768 int intel_alloc_ringbuffer_obj(struct drm_device
*dev
,
1769 struct intel_ringbuffer
*ringbuf
)
1771 struct drm_i915_gem_object
*obj
;
1775 obj
= i915_gem_object_create_stolen(dev
, ringbuf
->size
);
1777 obj
= i915_gem_alloc_object(dev
, ringbuf
->size
);
1781 /* mark ring buffers as read-only from GPU side by default */
1789 static int intel_init_ring_buffer(struct drm_device
*dev
,
1790 struct intel_engine_cs
*ring
)
1792 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1795 if (ringbuf
== NULL
) {
1796 ringbuf
= kzalloc(sizeof(*ringbuf
), GFP_KERNEL
);
1799 ring
->buffer
= ringbuf
;
1803 INIT_LIST_HEAD(&ring
->active_list
);
1804 INIT_LIST_HEAD(&ring
->request_list
);
1805 INIT_LIST_HEAD(&ring
->execlist_queue
);
1806 ringbuf
->size
= 32 * PAGE_SIZE
;
1807 ringbuf
->ring
= ring
;
1808 memset(ring
->semaphore
.sync_seqno
, 0, sizeof(ring
->semaphore
.sync_seqno
));
1810 init_waitqueue_head(&ring
->irq_queue
);
1812 if (I915_NEED_GFX_HWS(dev
)) {
1813 ret
= init_status_page(ring
);
1817 BUG_ON(ring
->id
!= RCS
);
1818 ret
= init_phys_status_page(ring
);
1823 if (ringbuf
->obj
== NULL
) {
1824 ret
= intel_alloc_ringbuffer_obj(dev
, ringbuf
);
1826 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
1831 ret
= intel_pin_and_map_ringbuffer_obj(dev
, ringbuf
);
1833 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
1835 intel_destroy_ringbuffer_obj(ringbuf
);
1840 /* Workaround an erratum on the i830 which causes a hang if
1841 * the TAIL pointer points to within the last 2 cachelines
1844 ringbuf
->effective_size
= ringbuf
->size
;
1845 if (IS_I830(dev
) || IS_845G(dev
))
1846 ringbuf
->effective_size
-= 2 * CACHELINE_BYTES
;
1848 ret
= i915_cmd_parser_init_ring(ring
);
1852 ret
= ring
->init(ring
);
1860 ring
->buffer
= NULL
;
1864 void intel_cleanup_ring_buffer(struct intel_engine_cs
*ring
)
1866 struct drm_i915_private
*dev_priv
;
1867 struct intel_ringbuffer
*ringbuf
;
1869 if (!intel_ring_initialized(ring
))
1872 dev_priv
= to_i915(ring
->dev
);
1873 ringbuf
= ring
->buffer
;
1875 intel_stop_ring_buffer(ring
);
1876 WARN_ON(!IS_GEN2(ring
->dev
) && (I915_READ_MODE(ring
) & MODE_IDLE
) == 0);
1878 intel_unpin_ringbuffer_obj(ringbuf
);
1879 intel_destroy_ringbuffer_obj(ringbuf
);
1880 ring
->preallocated_lazy_request
= NULL
;
1881 ring
->outstanding_lazy_seqno
= 0;
1884 ring
->cleanup(ring
);
1886 cleanup_status_page(ring
);
1888 i915_cmd_parser_fini_ring(ring
);
1891 ring
->buffer
= NULL
;
1894 static int intel_ring_wait_request(struct intel_engine_cs
*ring
, int n
)
1896 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1897 struct drm_i915_gem_request
*request
;
1901 if (ringbuf
->last_retired_head
!= -1) {
1902 ringbuf
->head
= ringbuf
->last_retired_head
;
1903 ringbuf
->last_retired_head
= -1;
1905 ringbuf
->space
= intel_ring_space(ringbuf
);
1906 if (ringbuf
->space
>= n
)
1910 list_for_each_entry(request
, &ring
->request_list
, list
) {
1911 if (__intel_ring_space(request
->tail
, ringbuf
->tail
,
1912 ringbuf
->size
) >= n
) {
1913 seqno
= request
->seqno
;
1921 ret
= i915_wait_seqno(ring
, seqno
);
1925 i915_gem_retire_requests_ring(ring
);
1926 ringbuf
->head
= ringbuf
->last_retired_head
;
1927 ringbuf
->last_retired_head
= -1;
1929 ringbuf
->space
= intel_ring_space(ringbuf
);
1933 static int ring_wait_for_space(struct intel_engine_cs
*ring
, int n
)
1935 struct drm_device
*dev
= ring
->dev
;
1936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1937 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1941 ret
= intel_ring_wait_request(ring
, n
);
1945 /* force the tail write in case we have been skipping them */
1946 __intel_ring_advance(ring
);
1948 /* With GEM the hangcheck timer should kick us out of the loop,
1949 * leaving it early runs the risk of corrupting GEM state (due
1950 * to running on almost untested codepaths). But on resume
1951 * timers don't work yet, so prevent a complete hang in that
1952 * case by choosing an insanely large timeout. */
1953 end
= jiffies
+ 60 * HZ
;
1955 trace_i915_ring_wait_begin(ring
);
1957 ringbuf
->head
= I915_READ_HEAD(ring
);
1958 ringbuf
->space
= intel_ring_space(ringbuf
);
1959 if (ringbuf
->space
>= n
) {
1966 if (dev_priv
->mm
.interruptible
&& signal_pending(current
)) {
1971 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
1972 dev_priv
->mm
.interruptible
);
1976 if (time_after(jiffies
, end
)) {
1981 trace_i915_ring_wait_end(ring
);
1985 static int intel_wrap_ring_buffer(struct intel_engine_cs
*ring
)
1987 uint32_t __iomem
*virt
;
1988 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
1989 int rem
= ringbuf
->size
- ringbuf
->tail
;
1991 if (ringbuf
->space
< rem
) {
1992 int ret
= ring_wait_for_space(ring
, rem
);
1997 virt
= ringbuf
->virtual_start
+ ringbuf
->tail
;
2000 iowrite32(MI_NOOP
, virt
++);
2003 ringbuf
->space
= intel_ring_space(ringbuf
);
2008 int intel_ring_idle(struct intel_engine_cs
*ring
)
2013 /* We need to add any requests required to flush the objects and ring */
2014 if (ring
->outstanding_lazy_seqno
) {
2015 ret
= i915_add_request(ring
, NULL
);
2020 /* Wait upon the last request to be completed */
2021 if (list_empty(&ring
->request_list
))
2024 seqno
= list_entry(ring
->request_list
.prev
,
2025 struct drm_i915_gem_request
,
2028 return i915_wait_seqno(ring
, seqno
);
2032 intel_ring_alloc_seqno(struct intel_engine_cs
*ring
)
2034 if (ring
->outstanding_lazy_seqno
)
2037 if (ring
->preallocated_lazy_request
== NULL
) {
2038 struct drm_i915_gem_request
*request
;
2040 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2041 if (request
== NULL
)
2044 ring
->preallocated_lazy_request
= request
;
2047 return i915_gem_get_seqno(ring
->dev
, &ring
->outstanding_lazy_seqno
);
2050 static int __intel_ring_prepare(struct intel_engine_cs
*ring
,
2053 struct intel_ringbuffer
*ringbuf
= ring
->buffer
;
2056 if (unlikely(ringbuf
->tail
+ bytes
> ringbuf
->effective_size
)) {
2057 ret
= intel_wrap_ring_buffer(ring
);
2062 if (unlikely(ringbuf
->space
< bytes
)) {
2063 ret
= ring_wait_for_space(ring
, bytes
);
2071 int intel_ring_begin(struct intel_engine_cs
*ring
,
2074 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2077 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
,
2078 dev_priv
->mm
.interruptible
);
2082 ret
= __intel_ring_prepare(ring
, num_dwords
* sizeof(uint32_t));
2086 /* Preallocate the olr before touching the ring */
2087 ret
= intel_ring_alloc_seqno(ring
);
2091 ring
->buffer
->space
-= num_dwords
* sizeof(uint32_t);
2095 /* Align the ring tail to a cacheline boundary */
2096 int intel_ring_cacheline_align(struct intel_engine_cs
*ring
)
2098 int num_dwords
= (ring
->buffer
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2101 if (num_dwords
== 0)
2104 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2105 ret
= intel_ring_begin(ring
, num_dwords
);
2109 while (num_dwords
--)
2110 intel_ring_emit(ring
, MI_NOOP
);
2112 intel_ring_advance(ring
);
2117 void intel_ring_init_seqno(struct intel_engine_cs
*ring
, u32 seqno
)
2119 struct drm_device
*dev
= ring
->dev
;
2120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2122 BUG_ON(ring
->outstanding_lazy_seqno
);
2124 if (INTEL_INFO(dev
)->gen
== 6 || INTEL_INFO(dev
)->gen
== 7) {
2125 I915_WRITE(RING_SYNC_0(ring
->mmio_base
), 0);
2126 I915_WRITE(RING_SYNC_1(ring
->mmio_base
), 0);
2128 I915_WRITE(RING_SYNC_2(ring
->mmio_base
), 0);
2131 ring
->set_seqno(ring
, seqno
);
2132 ring
->hangcheck
.seqno
= seqno
;
2135 static void gen6_bsd_ring_write_tail(struct intel_engine_cs
*ring
,
2138 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2140 /* Every tail move must follow the sequence below */
2142 /* Disable notification that the ring is IDLE. The GT
2143 * will then assume that it is busy and bring it out of rc6.
2145 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2146 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2148 /* Clear the context id. Here be magic! */
2149 I915_WRITE64(GEN6_BSD_RNCID
, 0x0);
2151 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2152 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL
) &
2153 GEN6_BSD_SLEEP_INDICATOR
) == 0,
2155 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2157 /* Now that the ring is fully powered up, update the tail */
2158 I915_WRITE_TAIL(ring
, value
);
2159 POSTING_READ(RING_TAIL(ring
->mmio_base
));
2161 /* Let the ring send IDLE messages to the GT again,
2162 * and so let it sleep to conserve power when idle.
2164 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2165 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2168 static int gen6_bsd_ring_flush(struct intel_engine_cs
*ring
,
2169 u32 invalidate
, u32 flush
)
2174 ret
= intel_ring_begin(ring
, 4);
2179 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2182 * Bspec vol 1c.5 - video engine command streamer:
2183 * "If ENABLED, all TLBs will be invalidated once the flush
2184 * operation is complete. This bit is only valid when the
2185 * Post-Sync Operation field is a value of 1h or 3h."
2187 if (invalidate
& I915_GEM_GPU_DOMAINS
)
2188 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
|
2189 MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2190 intel_ring_emit(ring
, cmd
);
2191 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2192 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2193 intel_ring_emit(ring
, 0); /* upper addr */
2194 intel_ring_emit(ring
, 0); /* value */
2196 intel_ring_emit(ring
, 0);
2197 intel_ring_emit(ring
, MI_NOOP
);
2199 intel_ring_advance(ring
);
2204 gen8_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2205 u64 offset
, u32 len
,
2208 bool ppgtt
= USES_PPGTT(ring
->dev
) && !(flags
& I915_DISPATCH_SECURE
);
2211 ret
= intel_ring_begin(ring
, 4);
2215 /* FIXME(BDW): Address space and security selectors. */
2216 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8));
2217 intel_ring_emit(ring
, lower_32_bits(offset
));
2218 intel_ring_emit(ring
, upper_32_bits(offset
));
2219 intel_ring_emit(ring
, MI_NOOP
);
2220 intel_ring_advance(ring
);
2226 hsw_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2227 u64 offset
, u32 len
,
2232 ret
= intel_ring_begin(ring
, 2);
2236 intel_ring_emit(ring
,
2237 MI_BATCH_BUFFER_START
|
2238 (flags
& I915_DISPATCH_SECURE
?
2239 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
));
2240 /* bit0-7 is the length on GEN6+ */
2241 intel_ring_emit(ring
, offset
);
2242 intel_ring_advance(ring
);
2248 gen6_ring_dispatch_execbuffer(struct intel_engine_cs
*ring
,
2249 u64 offset
, u32 len
,
2254 ret
= intel_ring_begin(ring
, 2);
2258 intel_ring_emit(ring
,
2259 MI_BATCH_BUFFER_START
|
2260 (flags
& I915_DISPATCH_SECURE
? 0 : MI_BATCH_NON_SECURE_I965
));
2261 /* bit0-7 is the length on GEN6+ */
2262 intel_ring_emit(ring
, offset
);
2263 intel_ring_advance(ring
);
2268 /* Blitter support (SandyBridge+) */
2270 static int gen6_ring_flush(struct intel_engine_cs
*ring
,
2271 u32 invalidate
, u32 flush
)
2273 struct drm_device
*dev
= ring
->dev
;
2274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2278 ret
= intel_ring_begin(ring
, 4);
2283 if (INTEL_INFO(ring
->dev
)->gen
>= 8)
2286 * Bspec vol 1c.3 - blitter engine command streamer:
2287 * "If ENABLED, all TLBs will be invalidated once the flush
2288 * operation is complete. This bit is only valid when the
2289 * Post-Sync Operation field is a value of 1h or 3h."
2291 if (invalidate
& I915_GEM_DOMAIN_RENDER
)
2292 cmd
|= MI_INVALIDATE_TLB
| MI_FLUSH_DW_STORE_INDEX
|
2293 MI_FLUSH_DW_OP_STOREDW
;
2294 intel_ring_emit(ring
, cmd
);
2295 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2296 if (INTEL_INFO(ring
->dev
)->gen
>= 8) {
2297 intel_ring_emit(ring
, 0); /* upper addr */
2298 intel_ring_emit(ring
, 0); /* value */
2300 intel_ring_emit(ring
, 0);
2301 intel_ring_emit(ring
, MI_NOOP
);
2303 intel_ring_advance(ring
);
2305 if (!invalidate
&& flush
) {
2307 return gen7_ring_fbc_flush(ring
, FBC_REND_CACHE_CLEAN
);
2308 else if (IS_BROADWELL(dev
))
2309 dev_priv
->fbc
.need_sw_cache_clean
= true;
2315 int intel_init_render_ring_buffer(struct drm_device
*dev
)
2317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2318 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
2319 struct drm_i915_gem_object
*obj
;
2322 ring
->name
= "render ring";
2324 ring
->mmio_base
= RENDER_RING_BASE
;
2326 if (INTEL_INFO(dev
)->gen
>= 8) {
2327 if (i915_semaphore_is_enabled(dev
)) {
2328 obj
= i915_gem_alloc_object(dev
, 4096);
2330 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2331 i915
.semaphores
= 0;
2333 i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
2334 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_NONBLOCK
);
2336 drm_gem_object_unreference(&obj
->base
);
2337 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2338 i915
.semaphores
= 0;
2340 dev_priv
->semaphore_obj
= obj
;
2344 ring
->init_context
= intel_ring_workarounds_emit
;
2345 ring
->add_request
= gen6_add_request
;
2346 ring
->flush
= gen8_render_ring_flush
;
2347 ring
->irq_get
= gen8_ring_get_irq
;
2348 ring
->irq_put
= gen8_ring_put_irq
;
2349 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2350 ring
->get_seqno
= gen6_ring_get_seqno
;
2351 ring
->set_seqno
= ring_set_seqno
;
2352 if (i915_semaphore_is_enabled(dev
)) {
2353 WARN_ON(!dev_priv
->semaphore_obj
);
2354 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2355 ring
->semaphore
.signal
= gen8_rcs_signal
;
2356 GEN8_RING_SEMAPHORE_INIT
;
2358 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2359 ring
->add_request
= gen6_add_request
;
2360 ring
->flush
= gen7_render_ring_flush
;
2361 if (INTEL_INFO(dev
)->gen
== 6)
2362 ring
->flush
= gen6_render_ring_flush
;
2363 ring
->irq_get
= gen6_ring_get_irq
;
2364 ring
->irq_put
= gen6_ring_put_irq
;
2365 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
;
2366 ring
->get_seqno
= gen6_ring_get_seqno
;
2367 ring
->set_seqno
= ring_set_seqno
;
2368 if (i915_semaphore_is_enabled(dev
)) {
2369 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2370 ring
->semaphore
.signal
= gen6_signal
;
2372 * The current semaphore is only applied on pre-gen8
2373 * platform. And there is no VCS2 ring on the pre-gen8
2374 * platform. So the semaphore between RCS and VCS2 is
2375 * initialized as INVALID. Gen8 will initialize the
2376 * sema between VCS2 and RCS later.
2378 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2379 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_RV
;
2380 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_RB
;
2381 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_RVE
;
2382 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2383 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_NOSYNC
;
2384 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VRSYNC
;
2385 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BRSYNC
;
2386 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VERSYNC
;
2387 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2389 } else if (IS_GEN5(dev
)) {
2390 ring
->add_request
= pc_render_add_request
;
2391 ring
->flush
= gen4_render_ring_flush
;
2392 ring
->get_seqno
= pc_render_get_seqno
;
2393 ring
->set_seqno
= pc_render_set_seqno
;
2394 ring
->irq_get
= gen5_ring_get_irq
;
2395 ring
->irq_put
= gen5_ring_put_irq
;
2396 ring
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
|
2397 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT
;
2399 ring
->add_request
= i9xx_add_request
;
2400 if (INTEL_INFO(dev
)->gen
< 4)
2401 ring
->flush
= gen2_render_ring_flush
;
2403 ring
->flush
= gen4_render_ring_flush
;
2404 ring
->get_seqno
= ring_get_seqno
;
2405 ring
->set_seqno
= ring_set_seqno
;
2407 ring
->irq_get
= i8xx_ring_get_irq
;
2408 ring
->irq_put
= i8xx_ring_put_irq
;
2410 ring
->irq_get
= i9xx_ring_get_irq
;
2411 ring
->irq_put
= i9xx_ring_put_irq
;
2413 ring
->irq_enable_mask
= I915_USER_INTERRUPT
;
2415 ring
->write_tail
= ring_write_tail
;
2417 if (IS_HASWELL(dev
))
2418 ring
->dispatch_execbuffer
= hsw_ring_dispatch_execbuffer
;
2419 else if (IS_GEN8(dev
))
2420 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2421 else if (INTEL_INFO(dev
)->gen
>= 6)
2422 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2423 else if (INTEL_INFO(dev
)->gen
>= 4)
2424 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2425 else if (IS_I830(dev
) || IS_845G(dev
))
2426 ring
->dispatch_execbuffer
= i830_dispatch_execbuffer
;
2428 ring
->dispatch_execbuffer
= i915_dispatch_execbuffer
;
2429 ring
->init
= init_render_ring
;
2430 ring
->cleanup
= render_ring_cleanup
;
2432 /* Workaround batchbuffer to combat CS tlb bug. */
2433 if (HAS_BROKEN_CS_TLB(dev
)) {
2434 obj
= i915_gem_alloc_object(dev
, I830_WA_SIZE
);
2436 DRM_ERROR("Failed to allocate batch bo\n");
2440 ret
= i915_gem_obj_ggtt_pin(obj
, 0, 0);
2442 drm_gem_object_unreference(&obj
->base
);
2443 DRM_ERROR("Failed to ping batch bo\n");
2447 ring
->scratch
.obj
= obj
;
2448 ring
->scratch
.gtt_offset
= i915_gem_obj_ggtt_offset(obj
);
2451 return intel_init_ring_buffer(dev
, ring
);
2454 int intel_init_bsd_ring_buffer(struct drm_device
*dev
)
2456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2457 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS
];
2459 ring
->name
= "bsd ring";
2462 ring
->write_tail
= ring_write_tail
;
2463 if (INTEL_INFO(dev
)->gen
>= 6) {
2464 ring
->mmio_base
= GEN6_BSD_RING_BASE
;
2465 /* gen6 bsd needs a special wa for tail updates */
2467 ring
->write_tail
= gen6_bsd_ring_write_tail
;
2468 ring
->flush
= gen6_bsd_ring_flush
;
2469 ring
->add_request
= gen6_add_request
;
2470 ring
->get_seqno
= gen6_ring_get_seqno
;
2471 ring
->set_seqno
= ring_set_seqno
;
2472 if (INTEL_INFO(dev
)->gen
>= 8) {
2473 ring
->irq_enable_mask
=
2474 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS1_IRQ_SHIFT
;
2475 ring
->irq_get
= gen8_ring_get_irq
;
2476 ring
->irq_put
= gen8_ring_put_irq
;
2477 ring
->dispatch_execbuffer
=
2478 gen8_ring_dispatch_execbuffer
;
2479 if (i915_semaphore_is_enabled(dev
)) {
2480 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2481 ring
->semaphore
.signal
= gen8_xcs_signal
;
2482 GEN8_RING_SEMAPHORE_INIT
;
2485 ring
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2486 ring
->irq_get
= gen6_ring_get_irq
;
2487 ring
->irq_put
= gen6_ring_put_irq
;
2488 ring
->dispatch_execbuffer
=
2489 gen6_ring_dispatch_execbuffer
;
2490 if (i915_semaphore_is_enabled(dev
)) {
2491 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2492 ring
->semaphore
.signal
= gen6_signal
;
2493 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VR
;
2494 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2495 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VB
;
2496 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_VVE
;
2497 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2498 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVSYNC
;
2499 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_NOSYNC
;
2500 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVSYNC
;
2501 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEVSYNC
;
2502 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2506 ring
->mmio_base
= BSD_RING_BASE
;
2507 ring
->flush
= bsd_ring_flush
;
2508 ring
->add_request
= i9xx_add_request
;
2509 ring
->get_seqno
= ring_get_seqno
;
2510 ring
->set_seqno
= ring_set_seqno
;
2512 ring
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2513 ring
->irq_get
= gen5_ring_get_irq
;
2514 ring
->irq_put
= gen5_ring_put_irq
;
2516 ring
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2517 ring
->irq_get
= i9xx_ring_get_irq
;
2518 ring
->irq_put
= i9xx_ring_put_irq
;
2520 ring
->dispatch_execbuffer
= i965_dispatch_execbuffer
;
2522 ring
->init
= init_ring_common
;
2524 return intel_init_ring_buffer(dev
, ring
);
2528 * Initialize the second BSD ring for Broadwell GT3.
2529 * It is noted that this only exists on Broadwell GT3.
2531 int intel_init_bsd2_ring_buffer(struct drm_device
*dev
)
2533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2534 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VCS2
];
2536 if ((INTEL_INFO(dev
)->gen
!= 8)) {
2537 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2541 ring
->name
= "bsd2 ring";
2544 ring
->write_tail
= ring_write_tail
;
2545 ring
->mmio_base
= GEN8_BSD2_RING_BASE
;
2546 ring
->flush
= gen6_bsd_ring_flush
;
2547 ring
->add_request
= gen6_add_request
;
2548 ring
->get_seqno
= gen6_ring_get_seqno
;
2549 ring
->set_seqno
= ring_set_seqno
;
2550 ring
->irq_enable_mask
=
2551 GT_RENDER_USER_INTERRUPT
<< GEN8_VCS2_IRQ_SHIFT
;
2552 ring
->irq_get
= gen8_ring_get_irq
;
2553 ring
->irq_put
= gen8_ring_put_irq
;
2554 ring
->dispatch_execbuffer
=
2555 gen8_ring_dispatch_execbuffer
;
2556 if (i915_semaphore_is_enabled(dev
)) {
2557 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2558 ring
->semaphore
.signal
= gen8_xcs_signal
;
2559 GEN8_RING_SEMAPHORE_INIT
;
2561 ring
->init
= init_ring_common
;
2563 return intel_init_ring_buffer(dev
, ring
);
2566 int intel_init_blt_ring_buffer(struct drm_device
*dev
)
2568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2569 struct intel_engine_cs
*ring
= &dev_priv
->ring
[BCS
];
2571 ring
->name
= "blitter ring";
2574 ring
->mmio_base
= BLT_RING_BASE
;
2575 ring
->write_tail
= ring_write_tail
;
2576 ring
->flush
= gen6_ring_flush
;
2577 ring
->add_request
= gen6_add_request
;
2578 ring
->get_seqno
= gen6_ring_get_seqno
;
2579 ring
->set_seqno
= ring_set_seqno
;
2580 if (INTEL_INFO(dev
)->gen
>= 8) {
2581 ring
->irq_enable_mask
=
2582 GT_RENDER_USER_INTERRUPT
<< GEN8_BCS_IRQ_SHIFT
;
2583 ring
->irq_get
= gen8_ring_get_irq
;
2584 ring
->irq_put
= gen8_ring_put_irq
;
2585 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2586 if (i915_semaphore_is_enabled(dev
)) {
2587 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2588 ring
->semaphore
.signal
= gen8_xcs_signal
;
2589 GEN8_RING_SEMAPHORE_INIT
;
2592 ring
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2593 ring
->irq_get
= gen6_ring_get_irq
;
2594 ring
->irq_put
= gen6_ring_put_irq
;
2595 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2596 if (i915_semaphore_is_enabled(dev
)) {
2597 ring
->semaphore
.signal
= gen6_signal
;
2598 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2600 * The current semaphore is only applied on pre-gen8
2601 * platform. And there is no VCS2 ring on the pre-gen8
2602 * platform. So the semaphore between BCS and VCS2 is
2603 * initialized as INVALID. Gen8 will initialize the
2604 * sema between BCS and VCS2 later.
2606 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_BR
;
2607 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_BV
;
2608 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_INVALID
;
2609 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_BVE
;
2610 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2611 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RBSYNC
;
2612 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VBSYNC
;
2613 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_NOSYNC
;
2614 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_VEBSYNC
;
2615 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2618 ring
->init
= init_ring_common
;
2620 return intel_init_ring_buffer(dev
, ring
);
2623 int intel_init_vebox_ring_buffer(struct drm_device
*dev
)
2625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2626 struct intel_engine_cs
*ring
= &dev_priv
->ring
[VECS
];
2628 ring
->name
= "video enhancement ring";
2631 ring
->mmio_base
= VEBOX_RING_BASE
;
2632 ring
->write_tail
= ring_write_tail
;
2633 ring
->flush
= gen6_ring_flush
;
2634 ring
->add_request
= gen6_add_request
;
2635 ring
->get_seqno
= gen6_ring_get_seqno
;
2636 ring
->set_seqno
= ring_set_seqno
;
2638 if (INTEL_INFO(dev
)->gen
>= 8) {
2639 ring
->irq_enable_mask
=
2640 GT_RENDER_USER_INTERRUPT
<< GEN8_VECS_IRQ_SHIFT
;
2641 ring
->irq_get
= gen8_ring_get_irq
;
2642 ring
->irq_put
= gen8_ring_put_irq
;
2643 ring
->dispatch_execbuffer
= gen8_ring_dispatch_execbuffer
;
2644 if (i915_semaphore_is_enabled(dev
)) {
2645 ring
->semaphore
.sync_to
= gen8_ring_sync
;
2646 ring
->semaphore
.signal
= gen8_xcs_signal
;
2647 GEN8_RING_SEMAPHORE_INIT
;
2650 ring
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2651 ring
->irq_get
= hsw_vebox_get_irq
;
2652 ring
->irq_put
= hsw_vebox_put_irq
;
2653 ring
->dispatch_execbuffer
= gen6_ring_dispatch_execbuffer
;
2654 if (i915_semaphore_is_enabled(dev
)) {
2655 ring
->semaphore
.sync_to
= gen6_ring_sync
;
2656 ring
->semaphore
.signal
= gen6_signal
;
2657 ring
->semaphore
.mbox
.wait
[RCS
] = MI_SEMAPHORE_SYNC_VER
;
2658 ring
->semaphore
.mbox
.wait
[VCS
] = MI_SEMAPHORE_SYNC_VEV
;
2659 ring
->semaphore
.mbox
.wait
[BCS
] = MI_SEMAPHORE_SYNC_VEB
;
2660 ring
->semaphore
.mbox
.wait
[VECS
] = MI_SEMAPHORE_SYNC_INVALID
;
2661 ring
->semaphore
.mbox
.wait
[VCS2
] = MI_SEMAPHORE_SYNC_INVALID
;
2662 ring
->semaphore
.mbox
.signal
[RCS
] = GEN6_RVESYNC
;
2663 ring
->semaphore
.mbox
.signal
[VCS
] = GEN6_VVESYNC
;
2664 ring
->semaphore
.mbox
.signal
[BCS
] = GEN6_BVESYNC
;
2665 ring
->semaphore
.mbox
.signal
[VECS
] = GEN6_NOSYNC
;
2666 ring
->semaphore
.mbox
.signal
[VCS2
] = GEN6_NOSYNC
;
2669 ring
->init
= init_ring_common
;
2671 return intel_init_ring_buffer(dev
, ring
);
2675 intel_ring_flush_all_caches(struct intel_engine_cs
*ring
)
2679 if (!ring
->gpu_caches_dirty
)
2682 ret
= ring
->flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2686 trace_i915_gem_ring_flush(ring
, 0, I915_GEM_GPU_DOMAINS
);
2688 ring
->gpu_caches_dirty
= false;
2693 intel_ring_invalidate_all_caches(struct intel_engine_cs
*ring
)
2695 uint32_t flush_domains
;
2699 if (ring
->gpu_caches_dirty
)
2700 flush_domains
= I915_GEM_GPU_DOMAINS
;
2702 ret
= ring
->flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2706 trace_i915_gem_ring_flush(ring
, I915_GEM_GPU_DOMAINS
, flush_domains
);
2708 ring
->gpu_caches_dirty
= false;
2713 intel_stop_ring_buffer(struct intel_engine_cs
*ring
)
2717 if (!intel_ring_initialized(ring
))
2720 ret
= intel_ring_idle(ring
);
2721 if (ret
&& !i915_reset_in_progress(&to_i915(ring
->dev
)->gpu_error
))
2722 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",