2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include <linux/log2.h>
33 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 /* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
40 #define LEGACY_REQUEST_SIZE 200
42 int __intel_ring_space(int head
, int tail
, int size
)
44 int space
= head
- tail
;
47 return space
- I915_RING_FREE_SPACE
;
50 void intel_ring_update_space(struct intel_ring
*ring
)
52 if (ring
->last_retired_head
!= -1) {
53 ring
->head
= ring
->last_retired_head
;
54 ring
->last_retired_head
= -1;
57 ring
->space
= __intel_ring_space(ring
->head
& HEAD_ADDR
,
58 ring
->tail
, ring
->size
);
62 gen2_render_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
64 struct intel_ring
*ring
= req
->ring
;
70 if (mode
& EMIT_INVALIDATE
)
73 ret
= intel_ring_begin(req
, 2);
77 intel_ring_emit(ring
, cmd
);
78 intel_ring_emit(ring
, MI_NOOP
);
79 intel_ring_advance(ring
);
85 gen4_render_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
87 struct intel_ring
*ring
= req
->ring
;
94 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
95 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
96 * also flushed at 2d versus 3d pipeline switches.
100 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
101 * MI_READ_FLUSH is set, and is always flushed on 965.
103 * I915_GEM_DOMAIN_COMMAND may not exist?
105 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
106 * invalidated when MI_EXE_FLUSH is set.
108 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
109 * invalidated with every MI_FLUSH.
113 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
114 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
115 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
116 * are flushed at any MI_FLUSH.
120 if (mode
& EMIT_INVALIDATE
) {
122 if (IS_G4X(req
->i915
) || IS_GEN5(req
->i915
))
123 cmd
|= MI_INVALIDATE_ISP
;
126 ret
= intel_ring_begin(req
, 2);
130 intel_ring_emit(ring
, cmd
);
131 intel_ring_emit(ring
, MI_NOOP
);
132 intel_ring_advance(ring
);
138 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
139 * implementing two workarounds on gen6. From section 1.4.7.1
140 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
142 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
143 * produced by non-pipelined state commands), software needs to first
144 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
147 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
148 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
150 * And the workaround for these two requires this workaround first:
152 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
153 * BEFORE the pipe-control with a post-sync op and no write-cache
156 * And this last workaround is tricky because of the requirements on
157 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
160 * "1 of the following must also be set:
161 * - Render Target Cache Flush Enable ([12] of DW1)
162 * - Depth Cache Flush Enable ([0] of DW1)
163 * - Stall at Pixel Scoreboard ([1] of DW1)
164 * - Depth Stall ([13] of DW1)
165 * - Post-Sync Operation ([13] of DW1)
166 * - Notify Enable ([8] of DW1)"
168 * The cache flushes require the workaround flush that triggered this
169 * one, so we can't use it. Depth stall would trigger the same.
170 * Post-sync nonzero is what triggered this second workaround, so we
171 * can't use that one either. Notify enable is IRQs, which aren't
172 * really our business. That leaves only stall at scoreboard.
175 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request
*req
)
177 struct intel_ring
*ring
= req
->ring
;
179 i915_ggtt_offset(req
->engine
->scratch
) + 2 * CACHELINE_BYTES
;
182 ret
= intel_ring_begin(req
, 6);
186 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring
, PIPE_CONTROL_CS_STALL
|
188 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
189 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
190 intel_ring_emit(ring
, 0); /* low dword */
191 intel_ring_emit(ring
, 0); /* high dword */
192 intel_ring_emit(ring
, MI_NOOP
);
193 intel_ring_advance(ring
);
195 ret
= intel_ring_begin(req
, 6);
199 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring
, PIPE_CONTROL_QW_WRITE
);
201 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
202 intel_ring_emit(ring
, 0);
203 intel_ring_emit(ring
, 0);
204 intel_ring_emit(ring
, MI_NOOP
);
205 intel_ring_advance(ring
);
211 gen6_render_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
213 struct intel_ring
*ring
= req
->ring
;
215 i915_ggtt_offset(req
->engine
->scratch
) + 2 * CACHELINE_BYTES
;
219 /* Force SNB workarounds for PIPE_CONTROL flushes */
220 ret
= intel_emit_post_sync_nonzero_flush(req
);
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
228 if (mode
& EMIT_FLUSH
) {
229 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
230 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
232 * Ensure that any following seqno writes only happen
233 * when the render cache is indeed flushed.
235 flags
|= PIPE_CONTROL_CS_STALL
;
237 if (mode
& EMIT_INVALIDATE
) {
238 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
239 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
240 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
241 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
242 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
243 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
245 * TLB invalidate requires a post-sync write.
247 flags
|= PIPE_CONTROL_QW_WRITE
| PIPE_CONTROL_CS_STALL
;
250 ret
= intel_ring_begin(req
, 4);
254 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
255 intel_ring_emit(ring
, flags
);
256 intel_ring_emit(ring
, scratch_addr
| PIPE_CONTROL_GLOBAL_GTT
);
257 intel_ring_emit(ring
, 0);
258 intel_ring_advance(ring
);
264 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request
*req
)
266 struct intel_ring
*ring
= req
->ring
;
269 ret
= intel_ring_begin(req
, 4);
273 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring
,
275 PIPE_CONTROL_CS_STALL
|
276 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
277 intel_ring_emit(ring
, 0);
278 intel_ring_emit(ring
, 0);
279 intel_ring_advance(ring
);
285 gen7_render_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
287 struct intel_ring
*ring
= req
->ring
;
289 i915_ggtt_offset(req
->engine
->scratch
) + 2 * CACHELINE_BYTES
;
294 * Ensure that any following seqno writes only happen when the render
295 * cache is indeed flushed.
297 * Workaround: 4th PIPE_CONTROL command (except the ones with only
298 * read-cache invalidate bits set) must have the CS_STALL bit set. We
299 * don't try to be clever and just set it unconditionally.
301 flags
|= PIPE_CONTROL_CS_STALL
;
303 /* Just flush everything. Experiments have shown that reducing the
304 * number of bits based on the write domains has little performance
307 if (mode
& EMIT_FLUSH
) {
308 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
309 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
310 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
311 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
313 if (mode
& EMIT_INVALIDATE
) {
314 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
315 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
316 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
317 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
318 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
319 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
320 flags
|= PIPE_CONTROL_MEDIA_STATE_CLEAR
;
322 * TLB invalidate requires a post-sync write.
324 flags
|= PIPE_CONTROL_QW_WRITE
;
325 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
327 flags
|= PIPE_CONTROL_STALL_AT_SCOREBOARD
;
329 /* Workaround: we must issue a pipe_control with CS-stall bit
330 * set before a pipe_control command that has the state cache
331 * invalidate bit set. */
332 gen7_render_ring_cs_stall_wa(req
);
335 ret
= intel_ring_begin(req
, 4);
339 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(4));
340 intel_ring_emit(ring
, flags
);
341 intel_ring_emit(ring
, scratch_addr
);
342 intel_ring_emit(ring
, 0);
343 intel_ring_advance(ring
);
349 gen8_emit_pipe_control(struct drm_i915_gem_request
*req
,
350 u32 flags
, u32 scratch_addr
)
352 struct intel_ring
*ring
= req
->ring
;
355 ret
= intel_ring_begin(req
, 6);
359 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
360 intel_ring_emit(ring
, flags
);
361 intel_ring_emit(ring
, scratch_addr
);
362 intel_ring_emit(ring
, 0);
363 intel_ring_emit(ring
, 0);
364 intel_ring_emit(ring
, 0);
365 intel_ring_advance(ring
);
371 gen8_render_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
374 i915_ggtt_offset(req
->engine
->scratch
) + 2 * CACHELINE_BYTES
;
378 flags
|= PIPE_CONTROL_CS_STALL
;
380 if (mode
& EMIT_FLUSH
) {
381 flags
|= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH
;
382 flags
|= PIPE_CONTROL_DEPTH_CACHE_FLUSH
;
383 flags
|= PIPE_CONTROL_DC_FLUSH_ENABLE
;
384 flags
|= PIPE_CONTROL_FLUSH_ENABLE
;
386 if (mode
& EMIT_INVALIDATE
) {
387 flags
|= PIPE_CONTROL_TLB_INVALIDATE
;
388 flags
|= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE
;
389 flags
|= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
;
390 flags
|= PIPE_CONTROL_VF_CACHE_INVALIDATE
;
391 flags
|= PIPE_CONTROL_CONST_CACHE_INVALIDATE
;
392 flags
|= PIPE_CONTROL_STATE_CACHE_INVALIDATE
;
393 flags
|= PIPE_CONTROL_QW_WRITE
;
394 flags
|= PIPE_CONTROL_GLOBAL_GTT_IVB
;
396 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
397 ret
= gen8_emit_pipe_control(req
,
398 PIPE_CONTROL_CS_STALL
|
399 PIPE_CONTROL_STALL_AT_SCOREBOARD
,
405 return gen8_emit_pipe_control(req
, flags
, scratch_addr
);
408 static void ring_setup_phys_status_page(struct intel_engine_cs
*engine
)
410 struct drm_i915_private
*dev_priv
= engine
->i915
;
413 addr
= dev_priv
->status_page_dmah
->busaddr
;
414 if (INTEL_GEN(dev_priv
) >= 4)
415 addr
|= (dev_priv
->status_page_dmah
->busaddr
>> 28) & 0xf0;
416 I915_WRITE(HWS_PGA
, addr
);
419 static void intel_ring_setup_status_page(struct intel_engine_cs
*engine
)
421 struct drm_i915_private
*dev_priv
= engine
->i915
;
424 /* The ring status page addresses are no longer next to the rest of
425 * the ring registers as of gen7.
427 if (IS_GEN7(dev_priv
)) {
428 switch (engine
->id
) {
430 mmio
= RENDER_HWS_PGA_GEN7
;
433 mmio
= BLT_HWS_PGA_GEN7
;
436 * VCS2 actually doesn't exist on Gen7. Only shut up
437 * gcc switch check warning
441 mmio
= BSD_HWS_PGA_GEN7
;
444 mmio
= VEBOX_HWS_PGA_GEN7
;
447 } else if (IS_GEN6(dev_priv
)) {
448 mmio
= RING_HWS_PGA_GEN6(engine
->mmio_base
);
450 /* XXX: gen8 returns to sanity */
451 mmio
= RING_HWS_PGA(engine
->mmio_base
);
454 I915_WRITE(mmio
, engine
->status_page
.ggtt_offset
);
458 * Flush the TLB for this page
460 * FIXME: These two bits have disappeared on gen8, so a question
461 * arises: do we still need this and if so how should we go about
462 * invalidating the TLB?
464 if (IS_GEN(dev_priv
, 6, 7)) {
465 i915_reg_t reg
= RING_INSTPM(engine
->mmio_base
);
467 /* ring should be idle before issuing a sync flush*/
468 WARN_ON((I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
471 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE
|
473 if (intel_wait_for_register(dev_priv
,
474 reg
, INSTPM_SYNC_FLUSH
, 0,
476 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
481 static bool stop_ring(struct intel_engine_cs
*engine
)
483 struct drm_i915_private
*dev_priv
= engine
->i915
;
485 if (INTEL_GEN(dev_priv
) > 2) {
486 I915_WRITE_MODE(engine
, _MASKED_BIT_ENABLE(STOP_RING
));
487 if (intel_wait_for_register(dev_priv
,
488 RING_MI_MODE(engine
->mmio_base
),
492 DRM_ERROR("%s : timed out trying to stop ring\n",
494 /* Sometimes we observe that the idle flag is not
495 * set even though the ring is empty. So double
496 * check before giving up.
498 if (I915_READ_HEAD(engine
) != I915_READ_TAIL(engine
))
503 I915_WRITE_CTL(engine
, 0);
504 I915_WRITE_HEAD(engine
, 0);
505 I915_WRITE_TAIL(engine
, 0);
507 if (INTEL_GEN(dev_priv
) > 2) {
508 (void)I915_READ_CTL(engine
);
509 I915_WRITE_MODE(engine
, _MASKED_BIT_DISABLE(STOP_RING
));
512 return (I915_READ_HEAD(engine
) & HEAD_ADDR
) == 0;
515 static int init_ring_common(struct intel_engine_cs
*engine
)
517 struct drm_i915_private
*dev_priv
= engine
->i915
;
518 struct intel_ring
*ring
= engine
->buffer
;
521 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
523 if (!stop_ring(engine
)) {
524 /* G45 ring initialization often fails to reset head to zero */
525 DRM_DEBUG_KMS("%s head not reset to zero "
526 "ctl %08x head %08x tail %08x start %08x\n",
528 I915_READ_CTL(engine
),
529 I915_READ_HEAD(engine
),
530 I915_READ_TAIL(engine
),
531 I915_READ_START(engine
));
533 if (!stop_ring(engine
)) {
534 DRM_ERROR("failed to set %s head to zero "
535 "ctl %08x head %08x tail %08x start %08x\n",
537 I915_READ_CTL(engine
),
538 I915_READ_HEAD(engine
),
539 I915_READ_TAIL(engine
),
540 I915_READ_START(engine
));
546 if (HWS_NEEDS_PHYSICAL(dev_priv
))
547 ring_setup_phys_status_page(engine
);
549 intel_ring_setup_status_page(engine
);
551 intel_engine_reset_breadcrumbs(engine
);
553 /* Enforce ordering by reading HEAD register back */
554 I915_READ_HEAD(engine
);
556 /* Initialize the ring. This must happen _after_ we've cleared the ring
557 * registers with the above sequence (the readback of the HEAD registers
558 * also enforces ordering), otherwise the hw might lose the new ring
559 * register values. */
560 I915_WRITE_START(engine
, i915_ggtt_offset(ring
->vma
));
562 /* WaClearRingBufHeadRegAtInit:ctg,elk */
563 if (I915_READ_HEAD(engine
))
564 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
565 engine
->name
, I915_READ_HEAD(engine
));
567 intel_ring_update_space(ring
);
568 I915_WRITE_HEAD(engine
, ring
->head
);
569 I915_WRITE_TAIL(engine
, ring
->tail
);
570 (void)I915_READ_TAIL(engine
);
572 I915_WRITE_CTL(engine
, RING_CTL_SIZE(ring
->size
) | RING_VALID
);
574 /* If the head is still not zero, the ring is dead */
575 if (intel_wait_for_register_fw(dev_priv
, RING_CTL(engine
->mmio_base
),
576 RING_VALID
, RING_VALID
,
578 DRM_ERROR("%s initialization failed "
579 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
581 I915_READ_CTL(engine
),
582 I915_READ_CTL(engine
) & RING_VALID
,
583 I915_READ_HEAD(engine
), ring
->head
,
584 I915_READ_TAIL(engine
), ring
->tail
,
585 I915_READ_START(engine
),
586 i915_ggtt_offset(ring
->vma
));
591 intel_engine_init_hangcheck(engine
);
594 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
599 static void reset_ring_common(struct intel_engine_cs
*engine
,
600 struct drm_i915_gem_request
*request
)
602 struct intel_ring
*ring
= request
->ring
;
604 ring
->head
= request
->postfix
;
605 ring
->last_retired_head
= -1;
608 static int intel_ring_workarounds_emit(struct drm_i915_gem_request
*req
)
610 struct intel_ring
*ring
= req
->ring
;
611 struct i915_workarounds
*w
= &req
->i915
->workarounds
;
617 ret
= req
->engine
->emit_flush(req
, EMIT_BARRIER
);
621 ret
= intel_ring_begin(req
, (w
->count
* 2 + 2));
625 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(w
->count
));
626 for (i
= 0; i
< w
->count
; i
++) {
627 intel_ring_emit_reg(ring
, w
->reg
[i
].addr
);
628 intel_ring_emit(ring
, w
->reg
[i
].value
);
630 intel_ring_emit(ring
, MI_NOOP
);
632 intel_ring_advance(ring
);
634 ret
= req
->engine
->emit_flush(req
, EMIT_BARRIER
);
638 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w
->count
);
643 static int intel_rcs_ctx_init(struct drm_i915_gem_request
*req
)
647 ret
= intel_ring_workarounds_emit(req
);
651 ret
= i915_gem_render_state_init(req
);
658 static int wa_add(struct drm_i915_private
*dev_priv
,
660 const u32 mask
, const u32 val
)
662 const u32 idx
= dev_priv
->workarounds
.count
;
664 if (WARN_ON(idx
>= I915_MAX_WA_REGS
))
667 dev_priv
->workarounds
.reg
[idx
].addr
= addr
;
668 dev_priv
->workarounds
.reg
[idx
].value
= val
;
669 dev_priv
->workarounds
.reg
[idx
].mask
= mask
;
671 dev_priv
->workarounds
.count
++;
676 #define WA_REG(addr, mask, val) do { \
677 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
682 #define WA_SET_BIT_MASKED(addr, mask) \
683 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
685 #define WA_CLR_BIT_MASKED(addr, mask) \
686 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
688 #define WA_SET_FIELD_MASKED(addr, mask, value) \
689 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
691 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
692 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
694 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
696 static int wa_ring_whitelist_reg(struct intel_engine_cs
*engine
,
699 struct drm_i915_private
*dev_priv
= engine
->i915
;
700 struct i915_workarounds
*wa
= &dev_priv
->workarounds
;
701 const uint32_t index
= wa
->hw_whitelist_count
[engine
->id
];
703 if (WARN_ON(index
>= RING_MAX_NONPRIV_SLOTS
))
706 WA_WRITE(RING_FORCE_TO_NONPRIV(engine
->mmio_base
, index
),
707 i915_mmio_reg_offset(reg
));
708 wa
->hw_whitelist_count
[engine
->id
]++;
713 static int gen8_init_workarounds(struct intel_engine_cs
*engine
)
715 struct drm_i915_private
*dev_priv
= engine
->i915
;
717 WA_SET_BIT_MASKED(INSTPM
, INSTPM_FORCE_ORDERING
);
719 /* WaDisableAsyncFlipPerfMode:bdw,chv */
720 WA_SET_BIT_MASKED(MI_MODE
, ASYNC_FLIP_PERF_DISABLE
);
722 /* WaDisablePartialInstShootdown:bdw,chv */
723 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
724 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
726 /* Use Force Non-Coherent whenever executing a 3D context. This is a
727 * workaround for for a possible hang in the unlikely event a TLB
728 * invalidation occurs during a PSD flush.
730 /* WaForceEnableNonCoherent:bdw,chv */
731 /* WaHdcDisableFetchWhenMasked:bdw,chv */
732 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
733 HDC_DONOT_FETCH_MEM_WHEN_MASKED
|
734 HDC_FORCE_NON_COHERENT
);
736 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
737 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
738 * polygons in the same 8x4 pixel/sample area to be processed without
739 * stalling waiting for the earlier ones to write to Hierarchical Z
742 * This optimization is off by default for BDW and CHV; turn it on.
744 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7
, HIZ_RAW_STALL_OPT_DISABLE
);
746 /* Wa4x4STCOptimizationDisable:bdw,chv */
747 WA_SET_BIT_MASKED(CACHE_MODE_1
, GEN8_4x4_STC_OPTIMIZATION_DISABLE
);
750 * BSpec recommends 8x4 when MSAA is used,
751 * however in practice 16x4 seems fastest.
753 * Note that PS/WM thread counts depend on the WIZ hashing
754 * disable bit, which we don't touch here, but it's good
755 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
757 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
758 GEN6_WIZ_HASHING_MASK
,
759 GEN6_WIZ_HASHING_16x4
);
764 static int bdw_init_workarounds(struct intel_engine_cs
*engine
)
766 struct drm_i915_private
*dev_priv
= engine
->i915
;
769 ret
= gen8_init_workarounds(engine
);
773 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
774 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
776 /* WaDisableDopClockGating:bdw */
777 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2
,
778 DOP_CLOCK_GATING_DISABLE
);
780 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
781 GEN8_SAMPLER_POWER_BYPASS_DIS
);
783 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
784 /* WaForceContextSaveRestoreNonCoherent:bdw */
785 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
786 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
787 (IS_BDW_GT3(dev_priv
) ? HDC_FENCE_DEST_SLM_DISABLE
: 0));
792 static int chv_init_workarounds(struct intel_engine_cs
*engine
)
794 struct drm_i915_private
*dev_priv
= engine
->i915
;
797 ret
= gen8_init_workarounds(engine
);
801 /* WaDisableThreadStallDopClockGating:chv */
802 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
, STALL_DOP_GATING_DISABLE
);
804 /* Improve HiZ throughput on CHV. */
805 WA_SET_BIT_MASKED(HIZ_CHICKEN
, CHV_HZ_8X8_MODE_IN_1X
);
810 static int gen9_init_workarounds(struct intel_engine_cs
*engine
)
812 struct drm_i915_private
*dev_priv
= engine
->i915
;
815 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
816 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS
, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE
));
818 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
819 I915_WRITE(BDW_SCRATCH1
, I915_READ(BDW_SCRATCH1
) |
820 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE
);
822 /* WaDisableKillLogic:bxt,skl,kbl */
823 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
826 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
827 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
828 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
829 FLOW_CONTROL_ENABLE
|
830 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
);
832 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
833 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
834 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC
);
836 /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
837 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
838 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
839 GEN9_DG_MIRROR_FIX_ENABLE
);
841 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
842 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
843 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1
,
844 GEN9_RHWO_OPTIMIZATION_DISABLE
);
846 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
847 * but we do that in per ctx batchbuffer as there is an issue
848 * with this register not getting restored on ctx restore
852 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
853 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
854 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7
,
855 GEN9_ENABLE_YV12_BUGFIX
|
856 GEN9_ENABLE_GPGPU_PREEMPTION
);
858 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
859 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
860 WA_SET_BIT_MASKED(CACHE_MODE_1
, (GEN8_4x4_STC_OPTIMIZATION_DISABLE
|
861 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE
));
863 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
864 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5
,
865 GEN9_CCS_TLB_PREFETCH_ENABLE
);
867 /* WaDisableMaskBasedCammingInRCC:bxt */
868 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
869 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0
,
870 PIXEL_MASK_CAMMING_DISABLE
);
872 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
873 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
874 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT
|
875 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE
);
877 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
878 * both tied to WaForceContextSaveRestoreNonCoherent
879 * in some hsds for skl. We keep the tie for all gen9. The
880 * documentation is a bit hazy and so we want to get common behaviour,
881 * even though there is no clear evidence we would need both on kbl/bxt.
882 * This area has been source of system hangs so we play it safe
883 * and mimic the skl regardless of what bspec says.
885 * Use Force Non-Coherent whenever executing a 3D context. This
886 * is a workaround for a possible hang in the unlikely event
887 * a TLB invalidation occurs during a PSD flush.
890 /* WaForceEnableNonCoherent:skl,bxt,kbl */
891 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
892 HDC_FORCE_NON_COHERENT
);
894 /* WaDisableHDCInvalidation:skl,bxt,kbl */
895 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) |
896 BDW_DISABLE_HDC_INVALIDATION
);
898 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
899 if (IS_SKYLAKE(dev_priv
) ||
900 IS_KABYLAKE(dev_priv
) ||
901 IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
))
902 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3
,
903 GEN8_SAMPLER_POWER_BYPASS_DIS
);
905 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
906 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2
, GEN8_ST_PO_DISABLE
);
908 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
909 I915_WRITE(GEN8_L3SQCREG4
, (I915_READ(GEN8_L3SQCREG4
) |
910 GEN8_LQSC_FLUSH_COHERENT_LINES
));
912 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
913 ret
= wa_ring_whitelist_reg(engine
, GEN9_CTX_PREEMPT_REG
);
917 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
918 ret
= wa_ring_whitelist_reg(engine
, GEN8_CS_CHICKEN1
);
922 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
923 ret
= wa_ring_whitelist_reg(engine
, GEN8_HDC_CHICKEN1
);
930 static int skl_tune_iz_hashing(struct intel_engine_cs
*engine
)
932 struct drm_i915_private
*dev_priv
= engine
->i915
;
933 u8 vals
[3] = { 0, 0, 0 };
936 for (i
= 0; i
< 3; i
++) {
940 * Only consider slices where one, and only one, subslice has 7
943 if (!is_power_of_2(INTEL_INFO(dev_priv
)->sseu
.subslice_7eu
[i
]))
947 * subslice_7eu[i] != 0 (because of the check above) and
948 * ss_max == 4 (maximum number of subslices possible per slice)
952 ss
= ffs(INTEL_INFO(dev_priv
)->sseu
.subslice_7eu
[i
]) - 1;
956 if (vals
[0] == 0 && vals
[1] == 0 && vals
[2] == 0)
959 /* Tune IZ hashing. See intel_device_info_runtime_init() */
960 WA_SET_FIELD_MASKED(GEN7_GT_MODE
,
961 GEN9_IZ_HASHING_MASK(2) |
962 GEN9_IZ_HASHING_MASK(1) |
963 GEN9_IZ_HASHING_MASK(0),
964 GEN9_IZ_HASHING(2, vals
[2]) |
965 GEN9_IZ_HASHING(1, vals
[1]) |
966 GEN9_IZ_HASHING(0, vals
[0]));
971 static int skl_init_workarounds(struct intel_engine_cs
*engine
)
973 struct drm_i915_private
*dev_priv
= engine
->i915
;
976 ret
= gen9_init_workarounds(engine
);
981 * Actual WA is to disable percontext preemption granularity control
982 * until D0 which is the default case so this is equivalent to
983 * !WaDisablePerCtxtPreemptionGranularityControl:skl
985 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1
,
986 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL
));
988 /* WaEnableGapsTsvCreditFix:skl */
989 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
990 GEN9_GAPS_TSV_CREDIT_DISABLE
));
992 /* WaDisableGafsUnitClkGating:skl */
993 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
995 /* WaInPlaceDecompressionHang:skl */
996 if (IS_SKL_REVID(dev_priv
, SKL_REVID_H0
, REVID_FOREVER
))
997 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
998 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1000 /* WaDisableLSQCROPERFforOCL:skl */
1001 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1005 return skl_tune_iz_hashing(engine
);
1008 static int bxt_init_workarounds(struct intel_engine_cs
*engine
)
1010 struct drm_i915_private
*dev_priv
= engine
->i915
;
1013 ret
= gen9_init_workarounds(engine
);
1017 /* WaStoreMultiplePTEenable:bxt */
1018 /* This is a requirement according to Hardware specification */
1019 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
))
1020 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_TLBPF
);
1022 /* WaSetClckGatingDisableMedia:bxt */
1023 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1024 I915_WRITE(GEN7_MISCCPCTL
, (I915_READ(GEN7_MISCCPCTL
) &
1025 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE
));
1028 /* WaDisableThreadStallDopClockGating:bxt */
1029 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN
,
1030 STALL_DOP_GATING_DISABLE
);
1032 /* WaDisablePooledEuLoadBalancingFix:bxt */
1033 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
)) {
1034 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2
,
1035 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE
);
1038 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1039 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_B0
)) {
1041 GEN7_HALF_SLICE_CHICKEN1
,
1042 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1045 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1046 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1047 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1048 /* WaDisableLSQCROPERFforOCL:bxt */
1049 if (IS_BXT_REVID(dev_priv
, 0, BXT_REVID_A1
)) {
1050 ret
= wa_ring_whitelist_reg(engine
, GEN9_CS_DEBUG_MODE1
);
1054 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1059 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1060 if (IS_BXT_REVID(dev_priv
, BXT_REVID_B0
, REVID_FOREVER
))
1061 I915_WRITE(GEN8_L3SQCREG1
, L3_GENERAL_PRIO_CREDITS(62) |
1062 L3_HIGH_PRIO_CREDITS(2));
1064 /* WaToEnableHwFixForPushConstHWBug:bxt */
1065 if (IS_BXT_REVID(dev_priv
, BXT_REVID_C0
, REVID_FOREVER
))
1066 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1067 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1069 /* WaInPlaceDecompressionHang:bxt */
1070 if (IS_BXT_REVID(dev_priv
, BXT_REVID_C0
, REVID_FOREVER
))
1071 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1072 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1077 static int kbl_init_workarounds(struct intel_engine_cs
*engine
)
1079 struct drm_i915_private
*dev_priv
= engine
->i915
;
1082 ret
= gen9_init_workarounds(engine
);
1086 /* WaEnableGapsTsvCreditFix:kbl */
1087 I915_WRITE(GEN8_GARBCNTL
, (I915_READ(GEN8_GARBCNTL
) |
1088 GEN9_GAPS_TSV_CREDIT_DISABLE
));
1090 /* WaDisableDynamicCreditSharing:kbl */
1091 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_B0
))
1092 WA_SET_BIT(GAMT_CHKN_BIT_REG
,
1093 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING
);
1095 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1096 if (IS_KBL_REVID(dev_priv
, KBL_REVID_A0
, KBL_REVID_A0
))
1097 WA_SET_BIT_MASKED(HDC_CHICKEN0
,
1098 HDC_FENCE_DEST_SLM_DISABLE
);
1100 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1101 * involving this register should also be added to WA batch as required.
1103 if (IS_KBL_REVID(dev_priv
, 0, KBL_REVID_E0
))
1104 /* WaDisableLSQCROPERFforOCL:kbl */
1105 I915_WRITE(GEN8_L3SQCREG4
, I915_READ(GEN8_L3SQCREG4
) |
1106 GEN8_LQSC_RO_PERF_DIS
);
1108 /* WaToEnableHwFixForPushConstHWBug:kbl */
1109 if (IS_KBL_REVID(dev_priv
, KBL_REVID_C0
, REVID_FOREVER
))
1110 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2
,
1111 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION
);
1113 /* WaDisableGafsUnitClkGating:kbl */
1114 WA_SET_BIT(GEN7_UCGCTL4
, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE
);
1116 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1118 GEN7_HALF_SLICE_CHICKEN1
,
1119 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE
);
1121 /* WaInPlaceDecompressionHang:kbl */
1122 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA
,
1123 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS
);
1125 /* WaDisableLSQCROPERFforOCL:kbl */
1126 ret
= wa_ring_whitelist_reg(engine
, GEN8_L3SQCREG4
);
1133 int init_workarounds_ring(struct intel_engine_cs
*engine
)
1135 struct drm_i915_private
*dev_priv
= engine
->i915
;
1137 WARN_ON(engine
->id
!= RCS
);
1139 dev_priv
->workarounds
.count
= 0;
1140 dev_priv
->workarounds
.hw_whitelist_count
[RCS
] = 0;
1142 if (IS_BROADWELL(dev_priv
))
1143 return bdw_init_workarounds(engine
);
1145 if (IS_CHERRYVIEW(dev_priv
))
1146 return chv_init_workarounds(engine
);
1148 if (IS_SKYLAKE(dev_priv
))
1149 return skl_init_workarounds(engine
);
1151 if (IS_BROXTON(dev_priv
))
1152 return bxt_init_workarounds(engine
);
1154 if (IS_KABYLAKE(dev_priv
))
1155 return kbl_init_workarounds(engine
);
1160 static int init_render_ring(struct intel_engine_cs
*engine
)
1162 struct drm_i915_private
*dev_priv
= engine
->i915
;
1163 int ret
= init_ring_common(engine
);
1167 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1168 if (IS_GEN(dev_priv
, 4, 6))
1169 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH
));
1171 /* We need to disable the AsyncFlip performance optimisations in order
1172 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1173 * programmed to '1' on all products.
1175 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1177 if (IS_GEN(dev_priv
, 6, 7))
1178 I915_WRITE(MI_MODE
, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE
));
1180 /* Required for the hardware to program scanline values for waiting */
1181 /* WaEnableFlushTlbInvalidationMode:snb */
1182 if (IS_GEN6(dev_priv
))
1183 I915_WRITE(GFX_MODE
,
1184 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
));
1186 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1187 if (IS_GEN7(dev_priv
))
1188 I915_WRITE(GFX_MODE_GEN7
,
1189 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT
) |
1190 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE
));
1192 if (IS_GEN6(dev_priv
)) {
1193 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1194 * "If this bit is set, STCunit will have LRA as replacement
1195 * policy. [...] This bit must be reset. LRA replacement
1196 * policy is not supported."
1198 I915_WRITE(CACHE_MODE_0
,
1199 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
1202 if (IS_GEN(dev_priv
, 6, 7))
1203 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING
));
1205 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1206 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1208 return init_workarounds_ring(engine
);
1211 static void render_ring_cleanup(struct intel_engine_cs
*engine
)
1213 struct drm_i915_private
*dev_priv
= engine
->i915
;
1215 i915_vma_unpin_and_release(&dev_priv
->semaphore
);
1218 static int gen8_rcs_signal(struct drm_i915_gem_request
*req
)
1220 struct intel_ring
*ring
= req
->ring
;
1221 struct drm_i915_private
*dev_priv
= req
->i915
;
1222 struct intel_engine_cs
*waiter
;
1223 enum intel_engine_id id
;
1226 num_rings
= INTEL_INFO(dev_priv
)->num_rings
;
1227 ret
= intel_ring_begin(req
, (num_rings
-1) * 8);
1231 for_each_engine(waiter
, dev_priv
, id
) {
1232 u64 gtt_offset
= req
->engine
->semaphore
.signal_ggtt
[id
];
1233 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1236 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1237 intel_ring_emit(ring
,
1238 PIPE_CONTROL_GLOBAL_GTT_IVB
|
1239 PIPE_CONTROL_QW_WRITE
|
1240 PIPE_CONTROL_CS_STALL
);
1241 intel_ring_emit(ring
, lower_32_bits(gtt_offset
));
1242 intel_ring_emit(ring
, upper_32_bits(gtt_offset
));
1243 intel_ring_emit(ring
, req
->fence
.seqno
);
1244 intel_ring_emit(ring
, 0);
1245 intel_ring_emit(ring
,
1246 MI_SEMAPHORE_SIGNAL
|
1247 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1248 intel_ring_emit(ring
, 0);
1250 intel_ring_advance(ring
);
1255 static int gen8_xcs_signal(struct drm_i915_gem_request
*req
)
1257 struct intel_ring
*ring
= req
->ring
;
1258 struct drm_i915_private
*dev_priv
= req
->i915
;
1259 struct intel_engine_cs
*waiter
;
1260 enum intel_engine_id id
;
1263 num_rings
= INTEL_INFO(dev_priv
)->num_rings
;
1264 ret
= intel_ring_begin(req
, (num_rings
-1) * 6);
1268 for_each_engine(waiter
, dev_priv
, id
) {
1269 u64 gtt_offset
= req
->engine
->semaphore
.signal_ggtt
[id
];
1270 if (gtt_offset
== MI_SEMAPHORE_SYNC_INVALID
)
1273 intel_ring_emit(ring
,
1274 (MI_FLUSH_DW
+ 1) | MI_FLUSH_DW_OP_STOREDW
);
1275 intel_ring_emit(ring
,
1276 lower_32_bits(gtt_offset
) |
1277 MI_FLUSH_DW_USE_GTT
);
1278 intel_ring_emit(ring
, upper_32_bits(gtt_offset
));
1279 intel_ring_emit(ring
, req
->fence
.seqno
);
1280 intel_ring_emit(ring
,
1281 MI_SEMAPHORE_SIGNAL
|
1282 MI_SEMAPHORE_TARGET(waiter
->hw_id
));
1283 intel_ring_emit(ring
, 0);
1285 intel_ring_advance(ring
);
1290 static int gen6_signal(struct drm_i915_gem_request
*req
)
1292 struct intel_ring
*ring
= req
->ring
;
1293 struct drm_i915_private
*dev_priv
= req
->i915
;
1294 struct intel_engine_cs
*engine
;
1295 enum intel_engine_id id
;
1298 num_rings
= INTEL_INFO(dev_priv
)->num_rings
;
1299 ret
= intel_ring_begin(req
, round_up((num_rings
-1) * 3, 2));
1303 for_each_engine(engine
, dev_priv
, id
) {
1304 i915_reg_t mbox_reg
;
1306 if (!(BIT(engine
->hw_id
) & GEN6_SEMAPHORES_MASK
))
1309 mbox_reg
= req
->engine
->semaphore
.mbox
.signal
[engine
->hw_id
];
1310 if (i915_mmio_reg_valid(mbox_reg
)) {
1311 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
1312 intel_ring_emit_reg(ring
, mbox_reg
);
1313 intel_ring_emit(ring
, req
->fence
.seqno
);
1317 /* If num_dwords was rounded, make sure the tail pointer is correct */
1318 if (num_rings
% 2 == 0)
1319 intel_ring_emit(ring
, MI_NOOP
);
1320 intel_ring_advance(ring
);
1325 static void i9xx_submit_request(struct drm_i915_gem_request
*request
)
1327 struct drm_i915_private
*dev_priv
= request
->i915
;
1329 I915_WRITE_TAIL(request
->engine
,
1330 intel_ring_offset(request
->ring
, request
->tail
));
1333 static int i9xx_emit_request(struct drm_i915_gem_request
*req
)
1335 struct intel_ring
*ring
= req
->ring
;
1338 ret
= intel_ring_begin(req
, 4);
1342 intel_ring_emit(ring
, MI_STORE_DWORD_INDEX
);
1343 intel_ring_emit(ring
, I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1344 intel_ring_emit(ring
, req
->fence
.seqno
);
1345 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1346 intel_ring_advance(ring
);
1348 req
->tail
= ring
->tail
;
1354 * gen6_sema_emit_request - Update the semaphore mailbox registers
1356 * @request - request to write to the ring
1358 * Update the mailbox registers in the *other* rings with the current seqno.
1359 * This acts like a signal in the canonical semaphore.
1361 static int gen6_sema_emit_request(struct drm_i915_gem_request
*req
)
1365 ret
= req
->engine
->semaphore
.signal(req
);
1369 return i9xx_emit_request(req
);
1372 static int gen8_render_emit_request(struct drm_i915_gem_request
*req
)
1374 struct intel_engine_cs
*engine
= req
->engine
;
1375 struct intel_ring
*ring
= req
->ring
;
1378 if (engine
->semaphore
.signal
) {
1379 ret
= engine
->semaphore
.signal(req
);
1384 ret
= intel_ring_begin(req
, 8);
1388 intel_ring_emit(ring
, GFX_OP_PIPE_CONTROL(6));
1389 intel_ring_emit(ring
, (PIPE_CONTROL_GLOBAL_GTT_IVB
|
1390 PIPE_CONTROL_CS_STALL
|
1391 PIPE_CONTROL_QW_WRITE
));
1392 intel_ring_emit(ring
, intel_hws_seqno_address(engine
));
1393 intel_ring_emit(ring
, 0);
1394 intel_ring_emit(ring
, i915_gem_request_get_seqno(req
));
1395 /* We're thrashing one dword of HWS. */
1396 intel_ring_emit(ring
, 0);
1397 intel_ring_emit(ring
, MI_USER_INTERRUPT
);
1398 intel_ring_emit(ring
, MI_NOOP
);
1399 intel_ring_advance(ring
);
1401 req
->tail
= ring
->tail
;
1407 * intel_ring_sync - sync the waiter to the signaller on seqno
1409 * @waiter - ring that is waiting
1410 * @signaller - ring which has, or will signal
1411 * @seqno - seqno which the waiter will block on
1415 gen8_ring_sync_to(struct drm_i915_gem_request
*req
,
1416 struct drm_i915_gem_request
*signal
)
1418 struct intel_ring
*ring
= req
->ring
;
1419 struct drm_i915_private
*dev_priv
= req
->i915
;
1420 u64 offset
= GEN8_WAIT_OFFSET(req
->engine
, signal
->engine
->id
);
1421 struct i915_hw_ppgtt
*ppgtt
;
1424 ret
= intel_ring_begin(req
, 4);
1428 intel_ring_emit(ring
,
1430 MI_SEMAPHORE_GLOBAL_GTT
|
1431 MI_SEMAPHORE_SAD_GTE_SDD
);
1432 intel_ring_emit(ring
, signal
->fence
.seqno
);
1433 intel_ring_emit(ring
, lower_32_bits(offset
));
1434 intel_ring_emit(ring
, upper_32_bits(offset
));
1435 intel_ring_advance(ring
);
1437 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1438 * pagetables and we must reload them before executing the batch.
1439 * We do this on the i915_switch_context() following the wait and
1440 * before the dispatch.
1442 ppgtt
= req
->ctx
->ppgtt
;
1443 if (ppgtt
&& req
->engine
->id
!= RCS
)
1444 ppgtt
->pd_dirty_rings
|= intel_engine_flag(req
->engine
);
1449 gen6_ring_sync_to(struct drm_i915_gem_request
*req
,
1450 struct drm_i915_gem_request
*signal
)
1452 struct intel_ring
*ring
= req
->ring
;
1453 u32 dw1
= MI_SEMAPHORE_MBOX
|
1454 MI_SEMAPHORE_COMPARE
|
1455 MI_SEMAPHORE_REGISTER
;
1456 u32 wait_mbox
= signal
->engine
->semaphore
.mbox
.wait
[req
->engine
->hw_id
];
1459 WARN_ON(wait_mbox
== MI_SEMAPHORE_SYNC_INVALID
);
1461 ret
= intel_ring_begin(req
, 4);
1465 intel_ring_emit(ring
, dw1
| wait_mbox
);
1466 /* Throughout all of the GEM code, seqno passed implies our current
1467 * seqno is >= the last seqno executed. However for hardware the
1468 * comparison is strictly greater than.
1470 intel_ring_emit(ring
, signal
->fence
.seqno
- 1);
1471 intel_ring_emit(ring
, 0);
1472 intel_ring_emit(ring
, MI_NOOP
);
1473 intel_ring_advance(ring
);
1479 gen5_seqno_barrier(struct intel_engine_cs
*engine
)
1481 /* MI_STORE are internally buffered by the GPU and not flushed
1482 * either by MI_FLUSH or SyncFlush or any other combination of
1485 * "Only the submission of the store operation is guaranteed.
1486 * The write result will be complete (coherent) some time later
1487 * (this is practically a finite period but there is no guaranteed
1490 * Empirically, we observe that we need a delay of at least 75us to
1491 * be sure that the seqno write is visible by the CPU.
1493 usleep_range(125, 250);
1497 gen6_seqno_barrier(struct intel_engine_cs
*engine
)
1499 struct drm_i915_private
*dev_priv
= engine
->i915
;
1501 /* Workaround to force correct ordering between irq and seqno writes on
1502 * ivb (and maybe also on snb) by reading from a CS register (like
1503 * ACTHD) before reading the status page.
1505 * Note that this effectively stalls the read by the time it takes to
1506 * do a memory transaction, which more or less ensures that the write
1507 * from the GPU has sufficient time to invalidate the CPU cacheline.
1508 * Alternatively we could delay the interrupt from the CS ring to give
1509 * the write time to land, but that would incur a delay after every
1510 * batch i.e. much more frequent than a delay when waiting for the
1511 * interrupt (with the same net latency).
1513 * Also note that to prevent whole machine hangs on gen7, we have to
1514 * take the spinlock to guard against concurrent cacheline access.
1516 spin_lock_irq(&dev_priv
->uncore
.lock
);
1517 POSTING_READ_FW(RING_ACTHD(engine
->mmio_base
));
1518 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1522 gen5_irq_enable(struct intel_engine_cs
*engine
)
1524 gen5_enable_gt_irq(engine
->i915
, engine
->irq_enable_mask
);
1528 gen5_irq_disable(struct intel_engine_cs
*engine
)
1530 gen5_disable_gt_irq(engine
->i915
, engine
->irq_enable_mask
);
1534 i9xx_irq_enable(struct intel_engine_cs
*engine
)
1536 struct drm_i915_private
*dev_priv
= engine
->i915
;
1538 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1539 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1540 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1544 i9xx_irq_disable(struct intel_engine_cs
*engine
)
1546 struct drm_i915_private
*dev_priv
= engine
->i915
;
1548 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1549 I915_WRITE(IMR
, dev_priv
->irq_mask
);
1553 i8xx_irq_enable(struct intel_engine_cs
*engine
)
1555 struct drm_i915_private
*dev_priv
= engine
->i915
;
1557 dev_priv
->irq_mask
&= ~engine
->irq_enable_mask
;
1558 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1559 POSTING_READ16(RING_IMR(engine
->mmio_base
));
1563 i8xx_irq_disable(struct intel_engine_cs
*engine
)
1565 struct drm_i915_private
*dev_priv
= engine
->i915
;
1567 dev_priv
->irq_mask
|= engine
->irq_enable_mask
;
1568 I915_WRITE16(IMR
, dev_priv
->irq_mask
);
1572 bsd_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
1574 struct intel_ring
*ring
= req
->ring
;
1577 ret
= intel_ring_begin(req
, 2);
1581 intel_ring_emit(ring
, MI_FLUSH
);
1582 intel_ring_emit(ring
, MI_NOOP
);
1583 intel_ring_advance(ring
);
1588 gen6_irq_enable(struct intel_engine_cs
*engine
)
1590 struct drm_i915_private
*dev_priv
= engine
->i915
;
1592 I915_WRITE_IMR(engine
,
1593 ~(engine
->irq_enable_mask
|
1594 engine
->irq_keep_mask
));
1595 gen5_enable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1599 gen6_irq_disable(struct intel_engine_cs
*engine
)
1601 struct drm_i915_private
*dev_priv
= engine
->i915
;
1603 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1604 gen5_disable_gt_irq(dev_priv
, engine
->irq_enable_mask
);
1608 hsw_vebox_irq_enable(struct intel_engine_cs
*engine
)
1610 struct drm_i915_private
*dev_priv
= engine
->i915
;
1612 I915_WRITE_IMR(engine
, ~engine
->irq_enable_mask
);
1613 gen6_enable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1617 hsw_vebox_irq_disable(struct intel_engine_cs
*engine
)
1619 struct drm_i915_private
*dev_priv
= engine
->i915
;
1621 I915_WRITE_IMR(engine
, ~0);
1622 gen6_disable_pm_irq(dev_priv
, engine
->irq_enable_mask
);
1626 gen8_irq_enable(struct intel_engine_cs
*engine
)
1628 struct drm_i915_private
*dev_priv
= engine
->i915
;
1630 I915_WRITE_IMR(engine
,
1631 ~(engine
->irq_enable_mask
|
1632 engine
->irq_keep_mask
));
1633 POSTING_READ_FW(RING_IMR(engine
->mmio_base
));
1637 gen8_irq_disable(struct intel_engine_cs
*engine
)
1639 struct drm_i915_private
*dev_priv
= engine
->i915
;
1641 I915_WRITE_IMR(engine
, ~engine
->irq_keep_mask
);
1645 i965_emit_bb_start(struct drm_i915_gem_request
*req
,
1646 u64 offset
, u32 length
,
1647 unsigned int dispatch_flags
)
1649 struct intel_ring
*ring
= req
->ring
;
1652 ret
= intel_ring_begin(req
, 2);
1656 intel_ring_emit(ring
,
1657 MI_BATCH_BUFFER_START
|
1659 (dispatch_flags
& I915_DISPATCH_SECURE
?
1660 0 : MI_BATCH_NON_SECURE_I965
));
1661 intel_ring_emit(ring
, offset
);
1662 intel_ring_advance(ring
);
1667 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1668 #define I830_BATCH_LIMIT (256*1024)
1669 #define I830_TLB_ENTRIES (2)
1670 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1672 i830_emit_bb_start(struct drm_i915_gem_request
*req
,
1673 u64 offset
, u32 len
,
1674 unsigned int dispatch_flags
)
1676 struct intel_ring
*ring
= req
->ring
;
1677 u32 cs_offset
= i915_ggtt_offset(req
->engine
->scratch
);
1680 ret
= intel_ring_begin(req
, 6);
1684 /* Evict the invalid PTE TLBs */
1685 intel_ring_emit(ring
, COLOR_BLT_CMD
| BLT_WRITE_RGBA
);
1686 intel_ring_emit(ring
, BLT_DEPTH_32
| BLT_ROP_COLOR_COPY
| 4096);
1687 intel_ring_emit(ring
, I830_TLB_ENTRIES
<< 16 | 4); /* load each page */
1688 intel_ring_emit(ring
, cs_offset
);
1689 intel_ring_emit(ring
, 0xdeadbeef);
1690 intel_ring_emit(ring
, MI_NOOP
);
1691 intel_ring_advance(ring
);
1693 if ((dispatch_flags
& I915_DISPATCH_PINNED
) == 0) {
1694 if (len
> I830_BATCH_LIMIT
)
1697 ret
= intel_ring_begin(req
, 6 + 2);
1701 /* Blit the batch (which has now all relocs applied) to the
1702 * stable batch scratch bo area (so that the CS never
1703 * stumbles over its tlb invalidation bug) ...
1705 intel_ring_emit(ring
, SRC_COPY_BLT_CMD
| BLT_WRITE_RGBA
);
1706 intel_ring_emit(ring
,
1707 BLT_DEPTH_32
| BLT_ROP_SRC_COPY
| 4096);
1708 intel_ring_emit(ring
, DIV_ROUND_UP(len
, 4096) << 16 | 4096);
1709 intel_ring_emit(ring
, cs_offset
);
1710 intel_ring_emit(ring
, 4096);
1711 intel_ring_emit(ring
, offset
);
1713 intel_ring_emit(ring
, MI_FLUSH
);
1714 intel_ring_emit(ring
, MI_NOOP
);
1715 intel_ring_advance(ring
);
1717 /* ... and execute it. */
1721 ret
= intel_ring_begin(req
, 2);
1725 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1726 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1727 0 : MI_BATCH_NON_SECURE
));
1728 intel_ring_advance(ring
);
1734 i915_emit_bb_start(struct drm_i915_gem_request
*req
,
1735 u64 offset
, u32 len
,
1736 unsigned int dispatch_flags
)
1738 struct intel_ring
*ring
= req
->ring
;
1741 ret
= intel_ring_begin(req
, 2);
1745 intel_ring_emit(ring
, MI_BATCH_BUFFER_START
| MI_BATCH_GTT
);
1746 intel_ring_emit(ring
, offset
| (dispatch_flags
& I915_DISPATCH_SECURE
?
1747 0 : MI_BATCH_NON_SECURE
));
1748 intel_ring_advance(ring
);
1753 static void cleanup_phys_status_page(struct intel_engine_cs
*engine
)
1755 struct drm_i915_private
*dev_priv
= engine
->i915
;
1757 if (!dev_priv
->status_page_dmah
)
1760 drm_pci_free(&dev_priv
->drm
, dev_priv
->status_page_dmah
);
1761 engine
->status_page
.page_addr
= NULL
;
1764 static void cleanup_status_page(struct intel_engine_cs
*engine
)
1766 struct i915_vma
*vma
;
1768 vma
= fetch_and_zero(&engine
->status_page
.vma
);
1772 i915_vma_unpin(vma
);
1773 i915_gem_object_unpin_map(vma
->obj
);
1777 static int init_status_page(struct intel_engine_cs
*engine
)
1779 struct drm_i915_gem_object
*obj
;
1780 struct i915_vma
*vma
;
1784 obj
= i915_gem_object_create(&engine
->i915
->drm
, 4096);
1786 DRM_ERROR("Failed to allocate status page\n");
1787 return PTR_ERR(obj
);
1790 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_LLC
);
1794 vma
= i915_vma_create(obj
, &engine
->i915
->ggtt
.base
, NULL
);
1801 if (!HAS_LLC(engine
->i915
))
1802 /* On g33, we cannot place HWS above 256MiB, so
1803 * restrict its pinning to the low mappable arena.
1804 * Though this restriction is not documented for
1805 * gen4, gen5, or byt, they also behave similarly
1806 * and hang if the HWS is placed at the top of the
1807 * GTT. To generalise, it appears that all !llc
1808 * platforms have issues with us placing the HWS
1809 * above the mappable region (even though we never
1812 flags
|= PIN_MAPPABLE
;
1813 ret
= i915_vma_pin(vma
, 0, 4096, flags
);
1817 engine
->status_page
.vma
= vma
;
1818 engine
->status_page
.ggtt_offset
= i915_ggtt_offset(vma
);
1819 engine
->status_page
.page_addr
=
1820 i915_gem_object_pin_map(obj
, I915_MAP_WB
);
1822 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1823 engine
->name
, i915_ggtt_offset(vma
));
1827 i915_gem_object_put(obj
);
1831 static int init_phys_status_page(struct intel_engine_cs
*engine
)
1833 struct drm_i915_private
*dev_priv
= engine
->i915
;
1835 dev_priv
->status_page_dmah
=
1836 drm_pci_alloc(&dev_priv
->drm
, PAGE_SIZE
, PAGE_SIZE
);
1837 if (!dev_priv
->status_page_dmah
)
1840 engine
->status_page
.page_addr
= dev_priv
->status_page_dmah
->vaddr
;
1841 memset(engine
->status_page
.page_addr
, 0, PAGE_SIZE
);
1846 int intel_ring_pin(struct intel_ring
*ring
)
1848 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1849 unsigned int flags
= PIN_GLOBAL
| PIN_OFFSET_BIAS
| 4096;
1850 enum i915_map_type map
;
1851 struct i915_vma
*vma
= ring
->vma
;
1855 GEM_BUG_ON(ring
->vaddr
);
1857 map
= HAS_LLC(ring
->engine
->i915
) ? I915_MAP_WB
: I915_MAP_WC
;
1859 if (vma
->obj
->stolen
)
1860 flags
|= PIN_MAPPABLE
;
1862 if (!(vma
->flags
& I915_VMA_GLOBAL_BIND
)) {
1863 if (flags
& PIN_MAPPABLE
|| map
== I915_MAP_WC
)
1864 ret
= i915_gem_object_set_to_gtt_domain(vma
->obj
, true);
1866 ret
= i915_gem_object_set_to_cpu_domain(vma
->obj
, true);
1871 ret
= i915_vma_pin(vma
, 0, PAGE_SIZE
, flags
);
1875 if (i915_vma_is_map_and_fenceable(vma
))
1876 addr
= (void __force
*)i915_vma_pin_iomap(vma
);
1878 addr
= i915_gem_object_pin_map(vma
->obj
, map
);
1886 i915_vma_unpin(vma
);
1887 return PTR_ERR(addr
);
1890 void intel_ring_unpin(struct intel_ring
*ring
)
1892 GEM_BUG_ON(!ring
->vma
);
1893 GEM_BUG_ON(!ring
->vaddr
);
1895 if (i915_vma_is_map_and_fenceable(ring
->vma
))
1896 i915_vma_unpin_iomap(ring
->vma
);
1898 i915_gem_object_unpin_map(ring
->vma
->obj
);
1901 i915_vma_unpin(ring
->vma
);
1904 static struct i915_vma
*
1905 intel_ring_create_vma(struct drm_i915_private
*dev_priv
, int size
)
1907 struct drm_i915_gem_object
*obj
;
1908 struct i915_vma
*vma
;
1910 obj
= i915_gem_object_create_stolen(&dev_priv
->drm
, size
);
1912 obj
= i915_gem_object_create(&dev_priv
->drm
, size
);
1914 return ERR_CAST(obj
);
1916 /* mark ring buffers as read-only from GPU side by default */
1919 vma
= i915_vma_create(obj
, &dev_priv
->ggtt
.base
, NULL
);
1926 i915_gem_object_put(obj
);
1931 intel_engine_create_ring(struct intel_engine_cs
*engine
, int size
)
1933 struct intel_ring
*ring
;
1934 struct i915_vma
*vma
;
1936 GEM_BUG_ON(!is_power_of_2(size
));
1937 GEM_BUG_ON(RING_CTL_SIZE(size
) & ~RING_NR_PAGES
);
1939 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
1941 return ERR_PTR(-ENOMEM
);
1943 ring
->engine
= engine
;
1945 INIT_LIST_HEAD(&ring
->request_list
);
1948 /* Workaround an erratum on the i830 which causes a hang if
1949 * the TAIL pointer points to within the last 2 cachelines
1952 ring
->effective_size
= size
;
1953 if (IS_I830(engine
->i915
) || IS_845G(engine
->i915
))
1954 ring
->effective_size
-= 2 * CACHELINE_BYTES
;
1956 ring
->last_retired_head
= -1;
1957 intel_ring_update_space(ring
);
1959 vma
= intel_ring_create_vma(engine
->i915
, size
);
1962 return ERR_CAST(vma
);
1970 intel_ring_free(struct intel_ring
*ring
)
1972 i915_vma_put(ring
->vma
);
1976 static int intel_ring_context_pin(struct i915_gem_context
*ctx
,
1977 struct intel_engine_cs
*engine
)
1979 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
1982 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
1984 if (ce
->pin_count
++)
1988 ret
= i915_gem_object_set_to_gtt_domain(ce
->state
->obj
, false);
1992 ret
= i915_vma_pin(ce
->state
, 0, ctx
->ggtt_alignment
,
1993 PIN_GLOBAL
| PIN_HIGH
);
1998 /* The kernel context is only used as a placeholder for flushing the
1999 * active context. It is never used for submitting user rendering and
2000 * as such never requires the golden render context, and so we can skip
2001 * emitting it when we switch to the kernel context. This is required
2002 * as during eviction we cannot allocate and pin the renderstate in
2003 * order to initialise the context.
2005 if (ctx
== ctx
->i915
->kernel_context
)
2006 ce
->initialised
= true;
2008 i915_gem_context_get(ctx
);
2016 static void intel_ring_context_unpin(struct i915_gem_context
*ctx
,
2017 struct intel_engine_cs
*engine
)
2019 struct intel_context
*ce
= &ctx
->engine
[engine
->id
];
2021 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
2023 if (--ce
->pin_count
)
2027 i915_vma_unpin(ce
->state
);
2029 i915_gem_context_put(ctx
);
2032 static int intel_init_ring_buffer(struct intel_engine_cs
*engine
)
2034 struct drm_i915_private
*dev_priv
= engine
->i915
;
2035 struct intel_ring
*ring
;
2038 WARN_ON(engine
->buffer
);
2040 intel_engine_setup_common(engine
);
2042 memset(engine
->semaphore
.sync_seqno
, 0,
2043 sizeof(engine
->semaphore
.sync_seqno
));
2045 ret
= intel_engine_init_common(engine
);
2049 /* We may need to do things with the shrinker which
2050 * require us to immediately switch back to the default
2051 * context. This can cause a problem as pinning the
2052 * default context also requires GTT space which may not
2053 * be available. To avoid this we always pin the default
2056 ret
= intel_ring_context_pin(dev_priv
->kernel_context
, engine
);
2060 ring
= intel_engine_create_ring(engine
, 32 * PAGE_SIZE
);
2062 ret
= PTR_ERR(ring
);
2066 if (HWS_NEEDS_PHYSICAL(dev_priv
)) {
2067 WARN_ON(engine
->id
!= RCS
);
2068 ret
= init_phys_status_page(engine
);
2072 ret
= init_status_page(engine
);
2077 ret
= intel_ring_pin(ring
);
2079 intel_ring_free(ring
);
2082 engine
->buffer
= ring
;
2087 intel_engine_cleanup(engine
);
2091 void intel_engine_cleanup(struct intel_engine_cs
*engine
)
2093 struct drm_i915_private
*dev_priv
;
2095 dev_priv
= engine
->i915
;
2097 if (engine
->buffer
) {
2098 WARN_ON(INTEL_GEN(dev_priv
) > 2 &&
2099 (I915_READ_MODE(engine
) & MODE_IDLE
) == 0);
2101 intel_ring_unpin(engine
->buffer
);
2102 intel_ring_free(engine
->buffer
);
2103 engine
->buffer
= NULL
;
2106 if (engine
->cleanup
)
2107 engine
->cleanup(engine
);
2109 if (HWS_NEEDS_PHYSICAL(dev_priv
)) {
2110 WARN_ON(engine
->id
!= RCS
);
2111 cleanup_phys_status_page(engine
);
2113 cleanup_status_page(engine
);
2116 intel_engine_cleanup_common(engine
);
2118 intel_ring_context_unpin(dev_priv
->kernel_context
, engine
);
2120 engine
->i915
= NULL
;
2121 dev_priv
->engine
[engine
->id
] = NULL
;
2125 void intel_legacy_submission_resume(struct drm_i915_private
*dev_priv
)
2127 struct intel_engine_cs
*engine
;
2128 enum intel_engine_id id
;
2130 for_each_engine(engine
, dev_priv
, id
) {
2131 engine
->buffer
->head
= engine
->buffer
->tail
;
2132 engine
->buffer
->last_retired_head
= -1;
2136 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
)
2140 /* Flush enough space to reduce the likelihood of waiting after
2141 * we start building the request - in which case we will just
2142 * have to repeat work.
2144 request
->reserved_space
+= LEGACY_REQUEST_SIZE
;
2146 request
->ring
= request
->engine
->buffer
;
2148 ret
= intel_ring_begin(request
, 0);
2152 request
->reserved_space
-= LEGACY_REQUEST_SIZE
;
2156 static int wait_for_space(struct drm_i915_gem_request
*req
, int bytes
)
2158 struct intel_ring
*ring
= req
->ring
;
2159 struct drm_i915_gem_request
*target
;
2162 intel_ring_update_space(ring
);
2163 if (ring
->space
>= bytes
)
2167 * Space is reserved in the ringbuffer for finalising the request,
2168 * as that cannot be allowed to fail. During request finalisation,
2169 * reserved_space is set to 0 to stop the overallocation and the
2170 * assumption is that then we never need to wait (which has the
2171 * risk of failing with EINTR).
2173 * See also i915_gem_request_alloc() and i915_add_request().
2175 GEM_BUG_ON(!req
->reserved_space
);
2177 list_for_each_entry(target
, &ring
->request_list
, ring_link
) {
2180 /* Would completion of this request free enough space? */
2181 space
= __intel_ring_space(target
->postfix
, ring
->tail
,
2187 if (WARN_ON(&target
->ring_link
== &ring
->request_list
))
2190 ret
= i915_wait_request(target
,
2191 I915_WAIT_INTERRUPTIBLE
| I915_WAIT_LOCKED
,
2192 NULL
, NO_WAITBOOST
);
2196 i915_gem_request_retire_upto(target
);
2198 intel_ring_update_space(ring
);
2199 GEM_BUG_ON(ring
->space
< bytes
);
2203 int intel_ring_begin(struct drm_i915_gem_request
*req
, int num_dwords
)
2205 struct intel_ring
*ring
= req
->ring
;
2206 int remain_actual
= ring
->size
- ring
->tail
;
2207 int remain_usable
= ring
->effective_size
- ring
->tail
;
2208 int bytes
= num_dwords
* sizeof(u32
);
2209 int total_bytes
, wait_bytes
;
2210 bool need_wrap
= false;
2212 total_bytes
= bytes
+ req
->reserved_space
;
2214 if (unlikely(bytes
> remain_usable
)) {
2216 * Not enough space for the basic request. So need to flush
2217 * out the remainder and then wait for base + reserved.
2219 wait_bytes
= remain_actual
+ total_bytes
;
2221 } else if (unlikely(total_bytes
> remain_usable
)) {
2223 * The base request will fit but the reserved space
2224 * falls off the end. So we don't need an immediate wrap
2225 * and only need to effectively wait for the reserved
2226 * size space from the start of ringbuffer.
2228 wait_bytes
= remain_actual
+ req
->reserved_space
;
2230 /* No wrapping required, just waiting. */
2231 wait_bytes
= total_bytes
;
2234 if (wait_bytes
> ring
->space
) {
2235 int ret
= wait_for_space(req
, wait_bytes
);
2240 if (unlikely(need_wrap
)) {
2241 GEM_BUG_ON(remain_actual
> ring
->space
);
2242 GEM_BUG_ON(ring
->tail
+ remain_actual
> ring
->size
);
2244 /* Fill the tail with MI_NOOP */
2245 memset(ring
->vaddr
+ ring
->tail
, 0, remain_actual
);
2247 ring
->space
-= remain_actual
;
2250 ring
->space
-= bytes
;
2251 GEM_BUG_ON(ring
->space
< 0);
2255 /* Align the ring tail to a cacheline boundary */
2256 int intel_ring_cacheline_align(struct drm_i915_gem_request
*req
)
2258 struct intel_ring
*ring
= req
->ring
;
2260 (ring
->tail
& (CACHELINE_BYTES
- 1)) / sizeof(uint32_t);
2263 if (num_dwords
== 0)
2266 num_dwords
= CACHELINE_BYTES
/ sizeof(uint32_t) - num_dwords
;
2267 ret
= intel_ring_begin(req
, num_dwords
);
2271 while (num_dwords
--)
2272 intel_ring_emit(ring
, MI_NOOP
);
2274 intel_ring_advance(ring
);
2279 static void gen6_bsd_submit_request(struct drm_i915_gem_request
*request
)
2281 struct drm_i915_private
*dev_priv
= request
->i915
;
2283 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
2285 /* Every tail move must follow the sequence below */
2287 /* Disable notification that the ring is IDLE. The GT
2288 * will then assume that it is busy and bring it out of rc6.
2290 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2291 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2293 /* Clear the context id. Here be magic! */
2294 I915_WRITE64_FW(GEN6_BSD_RNCID
, 0x0);
2296 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2297 if (intel_wait_for_register_fw(dev_priv
,
2298 GEN6_BSD_SLEEP_PSMI_CONTROL
,
2299 GEN6_BSD_SLEEP_INDICATOR
,
2302 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2304 /* Now that the ring is fully powered up, update the tail */
2305 i9xx_submit_request(request
);
2307 /* Let the ring send IDLE messages to the GT again,
2308 * and so let it sleep to conserve power when idle.
2310 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL
,
2311 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE
));
2313 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
2316 static int gen6_bsd_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
2318 struct intel_ring
*ring
= req
->ring
;
2322 ret
= intel_ring_begin(req
, 4);
2327 if (INTEL_GEN(req
->i915
) >= 8)
2330 /* We always require a command barrier so that subsequent
2331 * commands, such as breadcrumb interrupts, are strictly ordered
2332 * wrt the contents of the write cache being flushed to memory
2333 * (and thus being coherent from the CPU).
2335 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2338 * Bspec vol 1c.5 - video engine command streamer:
2339 * "If ENABLED, all TLBs will be invalidated once the flush
2340 * operation is complete. This bit is only valid when the
2341 * Post-Sync Operation field is a value of 1h or 3h."
2343 if (mode
& EMIT_INVALIDATE
)
2344 cmd
|= MI_INVALIDATE_TLB
| MI_INVALIDATE_BSD
;
2346 intel_ring_emit(ring
, cmd
);
2347 intel_ring_emit(ring
, I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2348 if (INTEL_GEN(req
->i915
) >= 8) {
2349 intel_ring_emit(ring
, 0); /* upper addr */
2350 intel_ring_emit(ring
, 0); /* value */
2352 intel_ring_emit(ring
, 0);
2353 intel_ring_emit(ring
, MI_NOOP
);
2355 intel_ring_advance(ring
);
2360 gen8_emit_bb_start(struct drm_i915_gem_request
*req
,
2361 u64 offset
, u32 len
,
2362 unsigned int dispatch_flags
)
2364 struct intel_ring
*ring
= req
->ring
;
2365 bool ppgtt
= USES_PPGTT(req
->i915
) &&
2366 !(dispatch_flags
& I915_DISPATCH_SECURE
);
2369 ret
= intel_ring_begin(req
, 4);
2373 /* FIXME(BDW): Address space and security selectors. */
2374 intel_ring_emit(ring
, MI_BATCH_BUFFER_START_GEN8
| (ppgtt
<<8) |
2375 (dispatch_flags
& I915_DISPATCH_RS
?
2376 MI_BATCH_RESOURCE_STREAMER
: 0));
2377 intel_ring_emit(ring
, lower_32_bits(offset
));
2378 intel_ring_emit(ring
, upper_32_bits(offset
));
2379 intel_ring_emit(ring
, MI_NOOP
);
2380 intel_ring_advance(ring
);
2386 hsw_emit_bb_start(struct drm_i915_gem_request
*req
,
2387 u64 offset
, u32 len
,
2388 unsigned int dispatch_flags
)
2390 struct intel_ring
*ring
= req
->ring
;
2393 ret
= intel_ring_begin(req
, 2);
2397 intel_ring_emit(ring
,
2398 MI_BATCH_BUFFER_START
|
2399 (dispatch_flags
& I915_DISPATCH_SECURE
?
2400 0 : MI_BATCH_PPGTT_HSW
| MI_BATCH_NON_SECURE_HSW
) |
2401 (dispatch_flags
& I915_DISPATCH_RS
?
2402 MI_BATCH_RESOURCE_STREAMER
: 0));
2403 /* bit0-7 is the length on GEN6+ */
2404 intel_ring_emit(ring
, offset
);
2405 intel_ring_advance(ring
);
2411 gen6_emit_bb_start(struct drm_i915_gem_request
*req
,
2412 u64 offset
, u32 len
,
2413 unsigned int dispatch_flags
)
2415 struct intel_ring
*ring
= req
->ring
;
2418 ret
= intel_ring_begin(req
, 2);
2422 intel_ring_emit(ring
,
2423 MI_BATCH_BUFFER_START
|
2424 (dispatch_flags
& I915_DISPATCH_SECURE
?
2425 0 : MI_BATCH_NON_SECURE_I965
));
2426 /* bit0-7 is the length on GEN6+ */
2427 intel_ring_emit(ring
, offset
);
2428 intel_ring_advance(ring
);
2433 /* Blitter support (SandyBridge+) */
2435 static int gen6_ring_flush(struct drm_i915_gem_request
*req
, u32 mode
)
2437 struct intel_ring
*ring
= req
->ring
;
2441 ret
= intel_ring_begin(req
, 4);
2446 if (INTEL_GEN(req
->i915
) >= 8)
2449 /* We always require a command barrier so that subsequent
2450 * commands, such as breadcrumb interrupts, are strictly ordered
2451 * wrt the contents of the write cache being flushed to memory
2452 * (and thus being coherent from the CPU).
2454 cmd
|= MI_FLUSH_DW_STORE_INDEX
| MI_FLUSH_DW_OP_STOREDW
;
2457 * Bspec vol 1c.3 - blitter engine command streamer:
2458 * "If ENABLED, all TLBs will be invalidated once the flush
2459 * operation is complete. This bit is only valid when the
2460 * Post-Sync Operation field is a value of 1h or 3h."
2462 if (mode
& EMIT_INVALIDATE
)
2463 cmd
|= MI_INVALIDATE_TLB
;
2464 intel_ring_emit(ring
, cmd
);
2465 intel_ring_emit(ring
,
2466 I915_GEM_HWS_SCRATCH_ADDR
| MI_FLUSH_DW_USE_GTT
);
2467 if (INTEL_GEN(req
->i915
) >= 8) {
2468 intel_ring_emit(ring
, 0); /* upper addr */
2469 intel_ring_emit(ring
, 0); /* value */
2471 intel_ring_emit(ring
, 0);
2472 intel_ring_emit(ring
, MI_NOOP
);
2474 intel_ring_advance(ring
);
2479 static void intel_ring_init_semaphores(struct drm_i915_private
*dev_priv
,
2480 struct intel_engine_cs
*engine
)
2482 struct drm_i915_gem_object
*obj
;
2485 if (!i915
.semaphores
)
2488 if (INTEL_GEN(dev_priv
) >= 8 && !dev_priv
->semaphore
) {
2489 struct i915_vma
*vma
;
2491 obj
= i915_gem_object_create(&dev_priv
->drm
, 4096);
2495 vma
= i915_vma_create(obj
, &dev_priv
->ggtt
.base
, NULL
);
2499 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
2503 ret
= i915_vma_pin(vma
, 0, 0, PIN_GLOBAL
| PIN_HIGH
);
2507 dev_priv
->semaphore
= vma
;
2510 if (INTEL_GEN(dev_priv
) >= 8) {
2511 u32 offset
= i915_ggtt_offset(dev_priv
->semaphore
);
2513 engine
->semaphore
.sync_to
= gen8_ring_sync_to
;
2514 engine
->semaphore
.signal
= gen8_xcs_signal
;
2516 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
2519 if (i
!= engine
->id
)
2520 ring_offset
= offset
+ GEN8_SEMAPHORE_OFFSET(engine
->id
, i
);
2522 ring_offset
= MI_SEMAPHORE_SYNC_INVALID
;
2524 engine
->semaphore
.signal_ggtt
[i
] = ring_offset
;
2526 } else if (INTEL_GEN(dev_priv
) >= 6) {
2527 engine
->semaphore
.sync_to
= gen6_ring_sync_to
;
2528 engine
->semaphore
.signal
= gen6_signal
;
2531 * The current semaphore is only applied on pre-gen8
2532 * platform. And there is no VCS2 ring on the pre-gen8
2533 * platform. So the semaphore between RCS and VCS2 is
2534 * initialized as INVALID. Gen8 will initialize the
2535 * sema between VCS2 and RCS later.
2537 for (i
= 0; i
< GEN6_NUM_SEMAPHORES
; i
++) {
2538 static const struct {
2540 i915_reg_t mbox_reg
;
2541 } sem_data
[GEN6_NUM_SEMAPHORES
][GEN6_NUM_SEMAPHORES
] = {
2543 [VCS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RV
, .mbox_reg
= GEN6_VRSYNC
},
2544 [BCS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RB
, .mbox_reg
= GEN6_BRSYNC
},
2545 [VECS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_RVE
, .mbox_reg
= GEN6_VERSYNC
},
2548 [RCS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VR
, .mbox_reg
= GEN6_RVSYNC
},
2549 [BCS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VB
, .mbox_reg
= GEN6_BVSYNC
},
2550 [VECS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VVE
, .mbox_reg
= GEN6_VEVSYNC
},
2553 [RCS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BR
, .mbox_reg
= GEN6_RBSYNC
},
2554 [VCS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BV
, .mbox_reg
= GEN6_VBSYNC
},
2555 [VECS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_BVE
, .mbox_reg
= GEN6_VEBSYNC
},
2558 [RCS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VER
, .mbox_reg
= GEN6_RVESYNC
},
2559 [VCS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VEV
, .mbox_reg
= GEN6_VVESYNC
},
2560 [BCS_HW
] = { .wait_mbox
= MI_SEMAPHORE_SYNC_VEB
, .mbox_reg
= GEN6_BVESYNC
},
2564 i915_reg_t mbox_reg
;
2566 if (i
== engine
->hw_id
) {
2567 wait_mbox
= MI_SEMAPHORE_SYNC_INVALID
;
2568 mbox_reg
= GEN6_NOSYNC
;
2570 wait_mbox
= sem_data
[engine
->hw_id
][i
].wait_mbox
;
2571 mbox_reg
= sem_data
[engine
->hw_id
][i
].mbox_reg
;
2574 engine
->semaphore
.mbox
.wait
[i
] = wait_mbox
;
2575 engine
->semaphore
.mbox
.signal
[i
] = mbox_reg
;
2582 i915_gem_object_put(obj
);
2584 DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n");
2585 i915
.semaphores
= 0;
2588 static void intel_ring_init_irq(struct drm_i915_private
*dev_priv
,
2589 struct intel_engine_cs
*engine
)
2591 engine
->irq_enable_mask
= GT_RENDER_USER_INTERRUPT
<< engine
->irq_shift
;
2593 if (INTEL_GEN(dev_priv
) >= 8) {
2594 engine
->irq_enable
= gen8_irq_enable
;
2595 engine
->irq_disable
= gen8_irq_disable
;
2596 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2597 } else if (INTEL_GEN(dev_priv
) >= 6) {
2598 engine
->irq_enable
= gen6_irq_enable
;
2599 engine
->irq_disable
= gen6_irq_disable
;
2600 engine
->irq_seqno_barrier
= gen6_seqno_barrier
;
2601 } else if (INTEL_GEN(dev_priv
) >= 5) {
2602 engine
->irq_enable
= gen5_irq_enable
;
2603 engine
->irq_disable
= gen5_irq_disable
;
2604 engine
->irq_seqno_barrier
= gen5_seqno_barrier
;
2605 } else if (INTEL_GEN(dev_priv
) >= 3) {
2606 engine
->irq_enable
= i9xx_irq_enable
;
2607 engine
->irq_disable
= i9xx_irq_disable
;
2609 engine
->irq_enable
= i8xx_irq_enable
;
2610 engine
->irq_disable
= i8xx_irq_disable
;
2614 static void intel_ring_default_vfuncs(struct drm_i915_private
*dev_priv
,
2615 struct intel_engine_cs
*engine
)
2617 intel_ring_init_irq(dev_priv
, engine
);
2618 intel_ring_init_semaphores(dev_priv
, engine
);
2620 engine
->init_hw
= init_ring_common
;
2621 engine
->reset_hw
= reset_ring_common
;
2623 engine
->emit_request
= i9xx_emit_request
;
2624 if (i915
.semaphores
)
2625 engine
->emit_request
= gen6_sema_emit_request
;
2626 engine
->submit_request
= i9xx_submit_request
;
2628 if (INTEL_GEN(dev_priv
) >= 8)
2629 engine
->emit_bb_start
= gen8_emit_bb_start
;
2630 else if (INTEL_GEN(dev_priv
) >= 6)
2631 engine
->emit_bb_start
= gen6_emit_bb_start
;
2632 else if (INTEL_GEN(dev_priv
) >= 4)
2633 engine
->emit_bb_start
= i965_emit_bb_start
;
2634 else if (IS_I830(dev_priv
) || IS_845G(dev_priv
))
2635 engine
->emit_bb_start
= i830_emit_bb_start
;
2637 engine
->emit_bb_start
= i915_emit_bb_start
;
2640 int intel_init_render_ring_buffer(struct intel_engine_cs
*engine
)
2642 struct drm_i915_private
*dev_priv
= engine
->i915
;
2645 intel_ring_default_vfuncs(dev_priv
, engine
);
2647 if (HAS_L3_DPF(dev_priv
))
2648 engine
->irq_keep_mask
= GT_RENDER_L3_PARITY_ERROR_INTERRUPT
;
2650 if (INTEL_GEN(dev_priv
) >= 8) {
2651 engine
->init_context
= intel_rcs_ctx_init
;
2652 engine
->emit_request
= gen8_render_emit_request
;
2653 engine
->emit_flush
= gen8_render_ring_flush
;
2654 if (i915
.semaphores
)
2655 engine
->semaphore
.signal
= gen8_rcs_signal
;
2656 } else if (INTEL_GEN(dev_priv
) >= 6) {
2657 engine
->init_context
= intel_rcs_ctx_init
;
2658 engine
->emit_flush
= gen7_render_ring_flush
;
2659 if (IS_GEN6(dev_priv
))
2660 engine
->emit_flush
= gen6_render_ring_flush
;
2661 } else if (IS_GEN5(dev_priv
)) {
2662 engine
->emit_flush
= gen4_render_ring_flush
;
2664 if (INTEL_GEN(dev_priv
) < 4)
2665 engine
->emit_flush
= gen2_render_ring_flush
;
2667 engine
->emit_flush
= gen4_render_ring_flush
;
2668 engine
->irq_enable_mask
= I915_USER_INTERRUPT
;
2671 if (IS_HASWELL(dev_priv
))
2672 engine
->emit_bb_start
= hsw_emit_bb_start
;
2674 engine
->init_hw
= init_render_ring
;
2675 engine
->cleanup
= render_ring_cleanup
;
2677 ret
= intel_init_ring_buffer(engine
);
2681 if (INTEL_GEN(dev_priv
) >= 6) {
2682 ret
= intel_engine_create_scratch(engine
, 4096);
2685 } else if (HAS_BROKEN_CS_TLB(dev_priv
)) {
2686 ret
= intel_engine_create_scratch(engine
, I830_WA_SIZE
);
2694 int intel_init_bsd_ring_buffer(struct intel_engine_cs
*engine
)
2696 struct drm_i915_private
*dev_priv
= engine
->i915
;
2698 intel_ring_default_vfuncs(dev_priv
, engine
);
2700 if (INTEL_GEN(dev_priv
) >= 6) {
2701 /* gen6 bsd needs a special wa for tail updates */
2702 if (IS_GEN6(dev_priv
))
2703 engine
->submit_request
= gen6_bsd_submit_request
;
2704 engine
->emit_flush
= gen6_bsd_ring_flush
;
2705 if (INTEL_GEN(dev_priv
) < 8)
2706 engine
->irq_enable_mask
= GT_BSD_USER_INTERRUPT
;
2708 engine
->mmio_base
= BSD_RING_BASE
;
2709 engine
->emit_flush
= bsd_ring_flush
;
2710 if (IS_GEN5(dev_priv
))
2711 engine
->irq_enable_mask
= ILK_BSD_USER_INTERRUPT
;
2713 engine
->irq_enable_mask
= I915_BSD_USER_INTERRUPT
;
2716 return intel_init_ring_buffer(engine
);
2720 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2722 int intel_init_bsd2_ring_buffer(struct intel_engine_cs
*engine
)
2724 struct drm_i915_private
*dev_priv
= engine
->i915
;
2726 intel_ring_default_vfuncs(dev_priv
, engine
);
2728 engine
->emit_flush
= gen6_bsd_ring_flush
;
2730 return intel_init_ring_buffer(engine
);
2733 int intel_init_blt_ring_buffer(struct intel_engine_cs
*engine
)
2735 struct drm_i915_private
*dev_priv
= engine
->i915
;
2737 intel_ring_default_vfuncs(dev_priv
, engine
);
2739 engine
->emit_flush
= gen6_ring_flush
;
2740 if (INTEL_GEN(dev_priv
) < 8)
2741 engine
->irq_enable_mask
= GT_BLT_USER_INTERRUPT
;
2743 return intel_init_ring_buffer(engine
);
2746 int intel_init_vebox_ring_buffer(struct intel_engine_cs
*engine
)
2748 struct drm_i915_private
*dev_priv
= engine
->i915
;
2750 intel_ring_default_vfuncs(dev_priv
, engine
);
2752 engine
->emit_flush
= gen6_ring_flush
;
2754 if (INTEL_GEN(dev_priv
) < 8) {
2755 engine
->irq_enable_mask
= PM_VEBOX_USER_INTERRUPT
;
2756 engine
->irq_enable
= hsw_vebox_irq_enable
;
2757 engine
->irq_disable
= hsw_vebox_irq_disable
;
2760 return intel_init_ring_buffer(engine
);