1 #ifndef _INTEL_RINGBUFFER_H_
2 #define _INTEL_RINGBUFFER_H_
4 #include <linux/hashtable.h>
5 #include "i915_gem_batch_pool.h"
6 #include "i915_gem_request.h"
7 #include "i915_gem_timeline.h"
9 #define I915_CMD_HASH_ORDER 9
11 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
12 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
13 * to give some inclination as to some of the magic values used in the various
16 #define CACHELINE_BYTES 64
17 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
20 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
21 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
22 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
24 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
25 * cacheline, the Head Pointer must not be greater than the Tail
28 #define I915_RING_FREE_SPACE 64
30 struct intel_hw_status_page
{
36 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
37 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
39 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
40 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
42 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
43 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
45 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
46 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
48 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
49 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
51 #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
52 #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
54 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
55 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
57 #define gen8_semaphore_seqno_size sizeof(uint64_t)
58 #define GEN8_SEMAPHORE_OFFSET(__from, __to) \
59 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
60 #define GEN8_SIGNAL_OFFSET(__ring, to) \
61 (dev_priv->semaphore->node.start + \
62 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to)))
63 #define GEN8_WAIT_OFFSET(__ring, from) \
64 (dev_priv->semaphore->node.start + \
65 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id))
67 enum intel_engine_hangcheck_action
{
75 #define HANGCHECK_SCORE_RING_HUNG 31
77 #define I915_MAX_SLICES 3
78 #define I915_MAX_SUBSLICES 3
80 #define instdone_slice_mask(dev_priv__) \
81 (INTEL_GEN(dev_priv__) == 7 ? \
82 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask)
84 #define instdone_subslice_mask(dev_priv__) \
85 (INTEL_GEN(dev_priv__) == 7 ? \
86 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask)
88 #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
89 for ((slice__) = 0, (subslice__) = 0; \
90 (slice__) < I915_MAX_SLICES; \
91 (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
92 (slice__) += ((subslice__) == 0)) \
93 for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
94 (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
96 struct intel_instdone
{
98 /* The following exist only in the RCS engine */
100 u32 sampler
[I915_MAX_SLICES
][I915_MAX_SUBSLICES
];
101 u32 row
[I915_MAX_SLICES
][I915_MAX_SUBSLICES
];
104 struct intel_engine_hangcheck
{
108 enum intel_engine_hangcheck_action action
;
110 struct intel_instdone instdone
;
114 struct i915_vma
*vma
;
117 struct intel_engine_cs
*engine
;
119 struct list_head request_list
;
127 /** We track the position of the requests in the ring buffer, and
128 * when each is retired we increment last_retired_head as the GPU
129 * must have finished processing the request and so we know we
130 * can advance the ringbuffer up to that position.
132 * last_retired_head is set to -1 after the value is consumed so
133 * we can detect new retirements.
135 u32 last_retired_head
;
138 struct i915_gem_context
;
139 struct drm_i915_reg_table
;
142 * we use a single page to load ctx workarounds so all of these
143 * values are referred in terms of dwords
145 * struct i915_wa_ctx_bb:
146 * offset: specifies batch starting position, also helpful in case
147 * if we want to have multiple batches at different offsets based on
148 * some criteria. It is not a requirement at the moment but provides
149 * an option for future use.
150 * size: size of the batch in DWORDS
152 struct i915_ctx_workarounds
{
153 struct i915_wa_ctx_bb
{
156 } indirect_ctx
, per_ctx
;
157 struct i915_vma
*vma
;
160 struct drm_i915_gem_request
;
161 struct intel_render_state
;
163 struct intel_engine_cs
{
164 struct drm_i915_private
*i915
;
166 enum intel_engine_id
{
170 VCS2
, /* Keep instances of the same type engine together. */
173 #define _VCS(n) (VCS + (n))
174 unsigned int exec_id
;
175 enum intel_engine_hw_id
{
182 enum intel_engine_hw_id guc_id
; /* XXX same as hw_id? */
184 unsigned int irq_shift
;
185 struct intel_ring
*buffer
;
186 struct intel_timeline
*timeline
;
188 struct intel_render_state
*render_state
;
190 /* Rather than have every client wait upon all user interrupts,
191 * with the herd waking after every interrupt and each doing the
192 * heavyweight seqno dance, we delegate the task (of being the
193 * bottom-half of the user interrupt) to the first client. After
194 * every interrupt, we wake up one client, who does the heavyweight
195 * coherent seqno read and either goes back to sleep (if incomplete),
196 * or wakes up all the completed clients in parallel, before then
197 * transferring the bottom-half status to the next client in the queue.
199 * Compared to walking the entire list of waiters in a single dedicated
200 * bottom-half, we reduce the latency of the first waiter by avoiding
201 * a context switch, but incur additional coherent seqno reads when
202 * following the chain of request breadcrumbs. Since it is most likely
203 * that we have a single client waiting on each seqno, then reducing
204 * the overhead of waking that client is much preferred.
206 struct intel_breadcrumbs
{
207 struct task_struct __rcu
*irq_seqno_bh
; /* bh for interrupts */
210 spinlock_t lock
; /* protects the lists of requests; irqsafe */
211 struct rb_root waiters
; /* sorted by retirement, priority */
212 struct rb_root signals
; /* sorted by retirement */
213 struct intel_wait
*first_wait
; /* oldest waiter by retirement */
214 struct task_struct
*signaler
; /* used for fence signalling */
215 struct drm_i915_gem_request
*first_signal
;
216 struct timer_list fake_irq
; /* used after a missed interrupt */
217 struct timer_list hangcheck
; /* detect missed interrupts */
219 unsigned long timeout
;
221 bool irq_enabled
: 1;
222 bool rpm_wakelock
: 1;
226 * A pool of objects to use as shadow copies of client batch buffers
227 * when the command parser is enabled. Prevents the client from
228 * modifying the batch contents after software parsing.
230 struct i915_gem_batch_pool batch_pool
;
232 struct intel_hw_status_page status_page
;
233 struct i915_ctx_workarounds wa_ctx
;
234 struct i915_vma
*scratch
;
236 u32 irq_keep_mask
; /* always keep these interrupts */
237 u32 irq_enable_mask
; /* bitmask to enable ring interrupt */
238 void (*irq_enable
)(struct intel_engine_cs
*engine
);
239 void (*irq_disable
)(struct intel_engine_cs
*engine
);
241 int (*init_hw
)(struct intel_engine_cs
*engine
);
242 void (*reset_hw
)(struct intel_engine_cs
*engine
,
243 struct drm_i915_gem_request
*req
);
245 int (*init_context
)(struct drm_i915_gem_request
*req
);
247 int (*emit_flush
)(struct drm_i915_gem_request
*request
,
249 #define EMIT_INVALIDATE BIT(0)
250 #define EMIT_FLUSH BIT(1)
251 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)
252 int (*emit_bb_start
)(struct drm_i915_gem_request
*req
,
253 u64 offset
, u32 length
,
254 unsigned int dispatch_flags
);
255 #define I915_DISPATCH_SECURE BIT(0)
256 #define I915_DISPATCH_PINNED BIT(1)
257 #define I915_DISPATCH_RS BIT(2)
258 void (*emit_breadcrumb
)(struct drm_i915_gem_request
*req
,
260 int emit_breadcrumb_sz
;
262 /* Pass the request to the hardware queue (e.g. directly into
263 * the legacy ringbuffer or to the end of an execlist).
265 * This is called from an atomic context with irqs disabled; must
268 void (*submit_request
)(struct drm_i915_gem_request
*req
);
270 /* Some chipsets are not quite as coherent as advertised and need
271 * an expensive kick to force a true read of the up-to-date seqno.
272 * However, the up-to-date seqno is not always required and the last
273 * seen value is good enough. Note that the seqno will always be
274 * monotonic, even if not coherent.
276 void (*irq_seqno_barrier
)(struct intel_engine_cs
*engine
);
277 void (*cleanup
)(struct intel_engine_cs
*engine
);
279 /* GEN8 signal/wait table - never trust comments!
280 * signal to signal to signal to signal to signal to
281 * RCS VCS BCS VECS VCS2
282 * --------------------------------------------------------------------
283 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
284 * |-------------------------------------------------------------------
285 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
286 * |-------------------------------------------------------------------
287 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
288 * |-------------------------------------------------------------------
289 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
290 * |-------------------------------------------------------------------
291 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
292 * |-------------------------------------------------------------------
295 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
296 * ie. transpose of g(x, y)
298 * sync from sync from sync from sync from sync from
299 * RCS VCS BCS VECS VCS2
300 * --------------------------------------------------------------------
301 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
302 * |-------------------------------------------------------------------
303 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
304 * |-------------------------------------------------------------------
305 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
306 * |-------------------------------------------------------------------
307 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
308 * |-------------------------------------------------------------------
309 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
310 * |-------------------------------------------------------------------
313 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
314 * ie. transpose of f(x, y)
318 #define GEN6_SEMAPHORE_LAST VECS_HW
319 #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1)
320 #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0)
322 /* our mbox written by others */
323 u32 wait
[GEN6_NUM_SEMAPHORES
];
324 /* mboxes this ring signals to */
325 i915_reg_t signal
[GEN6_NUM_SEMAPHORES
];
327 u64 signal_ggtt
[I915_NUM_ENGINES
];
331 int (*sync_to
)(struct drm_i915_gem_request
*req
,
332 struct drm_i915_gem_request
*signal
);
333 u32
*(*signal
)(struct drm_i915_gem_request
*req
, u32
*out
);
337 struct tasklet_struct irq_tasklet
;
338 spinlock_t execlist_lock
; /* used inside tasklet, use spin_lock_bh */
339 struct execlist_port
{
340 struct drm_i915_gem_request
*request
;
343 struct list_head execlist_queue
;
344 unsigned int fw_domains
;
345 bool disable_lite_restore_wa
;
347 u32 ctx_desc_template
;
349 struct i915_gem_context
*last_context
;
351 struct intel_engine_hangcheck hangcheck
;
353 bool needs_cmd_parser
;
356 * Table of commands the command parser needs to know about
359 DECLARE_HASHTABLE(cmd_hash
, I915_CMD_HASH_ORDER
);
362 * Table of registers allowed in commands that read/write registers.
364 const struct drm_i915_reg_table
*reg_tables
;
368 * Returns the bitmask for the length field of the specified command.
369 * Return 0 for an unrecognized/invalid command.
371 * If the command parser finds an entry for a command in the engine's
372 * cmd_tables, it gets the command's length based on the table entry.
373 * If not, it calls this function to determine the per-engine length
374 * field encoding for the command (i.e. different opcode ranges use
375 * certain bits to encode the command length in the header).
377 u32 (*get_cmd_length_mask
)(u32 cmd_header
);
380 static inline unsigned
381 intel_engine_flag(const struct intel_engine_cs
*engine
)
383 return 1 << engine
->id
;
387 intel_flush_status_page(struct intel_engine_cs
*engine
, int reg
)
390 clflush(&engine
->status_page
.page_addr
[reg
]);
395 intel_read_status_page(struct intel_engine_cs
*engine
, int reg
)
397 /* Ensure that the compiler doesn't optimize away the load. */
398 return READ_ONCE(engine
->status_page
.page_addr
[reg
]);
402 intel_write_status_page(struct intel_engine_cs
*engine
,
405 engine
->status_page
.page_addr
[reg
] = value
;
409 * Reads a dword out of the status page, which is written to from the command
410 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
413 * The following dwords have a reserved meaning:
414 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
415 * 0x04: ring 0 head pointer
416 * 0x05: ring 1 head pointer (915-class)
417 * 0x06: ring 2 head pointer (915-class)
418 * 0x10-0x1b: Context status DWords (GM45)
419 * 0x1f: Last written status offset. (GM45)
420 * 0x20-0x2f: Reserved (Gen6+)
422 * The area from dword 0x30 to 0x3ff is available for driver usage.
424 #define I915_GEM_HWS_INDEX 0x30
425 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
426 #define I915_GEM_HWS_SCRATCH_INDEX 0x40
427 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
430 intel_engine_create_ring(struct intel_engine_cs
*engine
, int size
);
431 int intel_ring_pin(struct intel_ring
*ring
);
432 void intel_ring_unpin(struct intel_ring
*ring
);
433 void intel_ring_free(struct intel_ring
*ring
);
435 void intel_engine_stop(struct intel_engine_cs
*engine
);
436 void intel_engine_cleanup(struct intel_engine_cs
*engine
);
438 void intel_legacy_submission_resume(struct drm_i915_private
*dev_priv
);
440 int intel_ring_alloc_request_extras(struct drm_i915_gem_request
*request
);
442 int __must_check
intel_ring_begin(struct drm_i915_gem_request
*req
, int n
);
443 int __must_check
intel_ring_cacheline_align(struct drm_i915_gem_request
*req
);
445 static inline void intel_ring_emit(struct intel_ring
*ring
, u32 data
)
447 *(uint32_t *)(ring
->vaddr
+ ring
->tail
) = data
;
451 static inline void intel_ring_emit_reg(struct intel_ring
*ring
, i915_reg_t reg
)
453 intel_ring_emit(ring
, i915_mmio_reg_offset(reg
));
456 static inline void intel_ring_advance(struct intel_ring
*ring
)
460 * This serves as a placeholder in the code so that the reader
461 * can compare against the preceding intel_ring_begin() and
462 * check that the number of dwords emitted matches the space
463 * reserved for the command packet (i.e. the value passed to
464 * intel_ring_begin()).
468 static inline u32
intel_ring_offset(struct intel_ring
*ring
, void *addr
)
470 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */
471 u32 offset
= addr
- ring
->vaddr
;
472 return offset
& (ring
->size
- 1);
475 int __intel_ring_space(int head
, int tail
, int size
);
476 void intel_ring_update_space(struct intel_ring
*ring
);
478 void intel_engine_init_global_seqno(struct intel_engine_cs
*engine
, u32 seqno
);
480 void intel_engine_setup_common(struct intel_engine_cs
*engine
);
481 int intel_engine_init_common(struct intel_engine_cs
*engine
);
482 int intel_engine_create_scratch(struct intel_engine_cs
*engine
, int size
);
483 void intel_engine_cleanup_common(struct intel_engine_cs
*engine
);
485 int intel_init_render_ring_buffer(struct intel_engine_cs
*engine
);
486 int intel_init_bsd_ring_buffer(struct intel_engine_cs
*engine
);
487 int intel_init_bsd2_ring_buffer(struct intel_engine_cs
*engine
);
488 int intel_init_blt_ring_buffer(struct intel_engine_cs
*engine
);
489 int intel_init_vebox_ring_buffer(struct intel_engine_cs
*engine
);
491 u64
intel_engine_get_active_head(struct intel_engine_cs
*engine
);
492 u64
intel_engine_get_last_batch_head(struct intel_engine_cs
*engine
);
494 static inline u32
intel_engine_get_seqno(struct intel_engine_cs
*engine
)
496 return intel_read_status_page(engine
, I915_GEM_HWS_INDEX
);
499 static inline u32
intel_engine_last_submit(struct intel_engine_cs
*engine
)
501 /* We are only peeking at the tail of the submit queue (and not the
502 * queue itself) in order to gain a hint as to the current active
503 * state of the engine. Callers are not expected to be taking
504 * engine->timeline->lock, nor are they expected to be concerned
505 * wtih serialising this hint with anything, so document it as
506 * a hint and nothing more.
508 return READ_ONCE(engine
->timeline
->last_submitted_seqno
);
511 int init_workarounds_ring(struct intel_engine_cs
*engine
);
513 void intel_engine_get_instdone(struct intel_engine_cs
*engine
,
514 struct intel_instdone
*instdone
);
517 * Arbitrary size for largest possible 'add request' sequence. The code paths
518 * are complex and variable. Empirical measurement shows that the worst case
519 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However,
520 * we need to allocate double the largest single packet within that emission
521 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW).
523 #define MIN_SPACE_FOR_ADD_REQUEST 336
525 static inline u32
intel_hws_seqno_address(struct intel_engine_cs
*engine
)
527 return engine
->status_page
.ggtt_offset
+ I915_GEM_HWS_INDEX_ADDR
;
530 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */
531 int intel_engine_init_breadcrumbs(struct intel_engine_cs
*engine
);
533 static inline void intel_wait_init(struct intel_wait
*wait
, u32 seqno
)
539 static inline bool intel_wait_complete(const struct intel_wait
*wait
)
541 return RB_EMPTY_NODE(&wait
->node
);
544 bool intel_engine_add_wait(struct intel_engine_cs
*engine
,
545 struct intel_wait
*wait
);
546 void intel_engine_remove_wait(struct intel_engine_cs
*engine
,
547 struct intel_wait
*wait
);
548 void intel_engine_enable_signaling(struct drm_i915_gem_request
*request
);
550 static inline bool intel_engine_has_waiter(const struct intel_engine_cs
*engine
)
552 return rcu_access_pointer(engine
->breadcrumbs
.irq_seqno_bh
);
555 static inline bool intel_engine_wakeup(const struct intel_engine_cs
*engine
)
559 /* Note that for this not to dangerously chase a dangling pointer,
560 * we must hold the rcu_read_lock here.
562 * Also note that tsk is likely to be in !TASK_RUNNING state so an
563 * early test for tsk->state != TASK_RUNNING before wake_up_process()
564 * is unlikely to be beneficial.
566 if (intel_engine_has_waiter(engine
)) {
567 struct task_struct
*tsk
;
570 tsk
= rcu_dereference(engine
->breadcrumbs
.irq_seqno_bh
);
572 wakeup
= wake_up_process(tsk
);
579 void intel_engine_reset_breadcrumbs(struct intel_engine_cs
*engine
);
580 void intel_engine_fini_breadcrumbs(struct intel_engine_cs
*engine
);
581 unsigned int intel_breadcrumbs_busy(struct drm_i915_private
*i915
);
583 #endif /* _INTEL_RINGBUFFER_H_ */