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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/export.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_sdvo_regs.h"
40
41 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
44 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
45
46 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
47 SDVO_TV_MASK)
48
49 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
50 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
51 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
52 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
53 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
54
55
56 static const char * const tv_format_names[] = {
57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64 };
65
66 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
67
68 struct intel_sdvo {
69 struct intel_encoder base;
70
71 struct i2c_adapter *i2c;
72 u8 slave_addr;
73
74 struct i2c_adapter ddc;
75
76 /* Register for the SDVO device: SDVOB or SDVOC */
77 uint32_t sdvo_reg;
78
79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
81
82 /*
83 * Capabilities of the SDVO device returned by
84 * intel_sdvo_get_capabilities()
85 */
86 struct intel_sdvo_caps caps;
87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
89 int pixel_clock_min, pixel_clock_max;
90
91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
97 /*
98 * Hotplug activation bits for this device
99 */
100 uint16_t hotplug_active;
101
102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107 bool color_range_auto;
108
109 /**
110 * HDMI user specified aspect ratio
111 */
112 enum hdmi_picture_aspect aspect_ratio;
113
114 /**
115 * This is set if we're going to treat the device as TV-out.
116 *
117 * While we have these nice friendly flags for output types that ought
118 * to decide this for us, the S-Video output on our HDMI+S-Video card
119 * shows up as RGB1 (VGA).
120 */
121 bool is_tv;
122
123 /* On different gens SDVOB is at different places. */
124 bool is_sdvob;
125
126 /* This is for current tv format name */
127 int tv_format_index;
128
129 /**
130 * This is set if we treat the device as HDMI, instead of DVI.
131 */
132 bool is_hdmi;
133 bool has_hdmi_monitor;
134 bool has_hdmi_audio;
135 bool rgb_quant_range_selectable;
136
137 /**
138 * This is set if we detect output of sdvo device as LVDS and
139 * have a valid fixed mode to use with the panel.
140 */
141 bool is_lvds;
142
143 /**
144 * This is sdvo fixed pannel mode pointer
145 */
146 struct drm_display_mode *sdvo_lvds_fixed_mode;
147
148 /* DDC bus used by this SDVO encoder */
149 uint8_t ddc_bus;
150
151 /*
152 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
153 */
154 uint8_t dtd_sdvo_flags;
155 };
156
157 struct intel_sdvo_connector {
158 struct intel_connector base;
159
160 /* Mark the type of connector */
161 uint16_t output_flag;
162
163 enum hdmi_force_audio force_audio;
164
165 /* This contains all current supported TV format */
166 u8 tv_format_supported[TV_FORMAT_NUM];
167 int format_supported_num;
168 struct drm_property *tv_format;
169
170 /* add the property for the SDVO-TV */
171 struct drm_property *left;
172 struct drm_property *right;
173 struct drm_property *top;
174 struct drm_property *bottom;
175 struct drm_property *hpos;
176 struct drm_property *vpos;
177 struct drm_property *contrast;
178 struct drm_property *saturation;
179 struct drm_property *hue;
180 struct drm_property *sharpness;
181 struct drm_property *flicker_filter;
182 struct drm_property *flicker_filter_adaptive;
183 struct drm_property *flicker_filter_2d;
184 struct drm_property *tv_chroma_filter;
185 struct drm_property *tv_luma_filter;
186 struct drm_property *dot_crawl;
187
188 /* add the property for the SDVO-TV/LVDS */
189 struct drm_property *brightness;
190
191 /* Add variable to record current setting for the above property */
192 u32 left_margin, right_margin, top_margin, bottom_margin;
193
194 /* this is to get the range of margin.*/
195 u32 max_hscan, max_vscan;
196 u32 max_hpos, cur_hpos;
197 u32 max_vpos, cur_vpos;
198 u32 cur_brightness, max_brightness;
199 u32 cur_contrast, max_contrast;
200 u32 cur_saturation, max_saturation;
201 u32 cur_hue, max_hue;
202 u32 cur_sharpness, max_sharpness;
203 u32 cur_flicker_filter, max_flicker_filter;
204 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
205 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
206 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
207 u32 cur_tv_luma_filter, max_tv_luma_filter;
208 u32 cur_dot_crawl, max_dot_crawl;
209 };
210
211 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
212 {
213 return container_of(encoder, struct intel_sdvo, base);
214 }
215
216 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
217 {
218 return to_sdvo(intel_attached_encoder(connector));
219 }
220
221 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
222 {
223 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
224 }
225
226 static bool
227 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
228 static bool
229 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
230 struct intel_sdvo_connector *intel_sdvo_connector,
231 int type);
232 static bool
233 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
234 struct intel_sdvo_connector *intel_sdvo_connector);
235
236 /**
237 * Writes the SDVOB or SDVOC with the given value, but always writes both
238 * SDVOB and SDVOC to work around apparent hardware issues (according to
239 * comments in the BIOS).
240 */
241 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
242 {
243 struct drm_device *dev = intel_sdvo->base.base.dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 u32 bval = val, cval = val;
246 int i;
247
248 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
249 I915_WRITE(intel_sdvo->sdvo_reg, val);
250 POSTING_READ(intel_sdvo->sdvo_reg);
251 /*
252 * HW workaround, need to write this twice for issue
253 * that may result in first write getting masked.
254 */
255 if (HAS_PCH_IBX(dev)) {
256 I915_WRITE(intel_sdvo->sdvo_reg, val);
257 POSTING_READ(intel_sdvo->sdvo_reg);
258 }
259 return;
260 }
261
262 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
263 cval = I915_READ(GEN3_SDVOC);
264 else
265 bval = I915_READ(GEN3_SDVOB);
266
267 /*
268 * Write the registers twice for luck. Sometimes,
269 * writing them only once doesn't appear to 'stick'.
270 * The BIOS does this too. Yay, magic
271 */
272 for (i = 0; i < 2; i++)
273 {
274 I915_WRITE(GEN3_SDVOB, bval);
275 POSTING_READ(GEN3_SDVOB);
276 I915_WRITE(GEN3_SDVOC, cval);
277 POSTING_READ(GEN3_SDVOC);
278 }
279 }
280
281 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
282 {
283 struct i2c_msg msgs[] = {
284 {
285 .addr = intel_sdvo->slave_addr,
286 .flags = 0,
287 .len = 1,
288 .buf = &addr,
289 },
290 {
291 .addr = intel_sdvo->slave_addr,
292 .flags = I2C_M_RD,
293 .len = 1,
294 .buf = ch,
295 }
296 };
297 int ret;
298
299 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
300 return true;
301
302 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
303 return false;
304 }
305
306 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
307 /** Mapping of command numbers to names, for debug output */
308 static const struct _sdvo_cmd_name {
309 u8 cmd;
310 const char *name;
311 } sdvo_cmd_names[] = {
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
355
356 /* Add the op code for SDVO enhancements */
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
401
402 /* HDMI op code */
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
412 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
413 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
414 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
415 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
416 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
417 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
418 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
419 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
420 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
421 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
422 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
423 };
424
425 #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
426
427 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
428 const void *args, int args_len)
429 {
430 int i, pos = 0;
431 #define BUF_LEN 256
432 char buffer[BUF_LEN];
433
434 #define BUF_PRINT(args...) \
435 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
436
437
438 for (i = 0; i < args_len; i++) {
439 BUF_PRINT("%02X ", ((u8 *)args)[i]);
440 }
441 for (; i < 8; i++) {
442 BUF_PRINT(" ");
443 }
444 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
445 if (cmd == sdvo_cmd_names[i].cmd) {
446 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
447 break;
448 }
449 }
450 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
451 BUF_PRINT("(%02X)", cmd);
452 }
453 BUG_ON(pos >= BUF_LEN - 1);
454 #undef BUF_PRINT
455 #undef BUF_LEN
456
457 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
458 }
459
460 static const char * const cmd_status_names[] = {
461 "Power on",
462 "Success",
463 "Not supported",
464 "Invalid arg",
465 "Pending",
466 "Target not specified",
467 "Scaling not supported"
468 };
469
470 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
471 const void *args, int args_len)
472 {
473 u8 *buf, status;
474 struct i2c_msg *msgs;
475 int i, ret = true;
476
477 /* Would be simpler to allocate both in one go ? */
478 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
479 if (!buf)
480 return false;
481
482 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
483 if (!msgs) {
484 kfree(buf);
485 return false;
486 }
487
488 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
489
490 for (i = 0; i < args_len; i++) {
491 msgs[i].addr = intel_sdvo->slave_addr;
492 msgs[i].flags = 0;
493 msgs[i].len = 2;
494 msgs[i].buf = buf + 2 *i;
495 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
496 buf[2*i + 1] = ((u8*)args)[i];
497 }
498 msgs[i].addr = intel_sdvo->slave_addr;
499 msgs[i].flags = 0;
500 msgs[i].len = 2;
501 msgs[i].buf = buf + 2*i;
502 buf[2*i + 0] = SDVO_I2C_OPCODE;
503 buf[2*i + 1] = cmd;
504
505 /* the following two are to read the response */
506 status = SDVO_I2C_CMD_STATUS;
507 msgs[i+1].addr = intel_sdvo->slave_addr;
508 msgs[i+1].flags = 0;
509 msgs[i+1].len = 1;
510 msgs[i+1].buf = &status;
511
512 msgs[i+2].addr = intel_sdvo->slave_addr;
513 msgs[i+2].flags = I2C_M_RD;
514 msgs[i+2].len = 1;
515 msgs[i+2].buf = &status;
516
517 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
518 if (ret < 0) {
519 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
520 ret = false;
521 goto out;
522 }
523 if (ret != i+3) {
524 /* failure in I2C transfer */
525 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
526 ret = false;
527 }
528
529 out:
530 kfree(msgs);
531 kfree(buf);
532 return ret;
533 }
534
535 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
536 void *response, int response_len)
537 {
538 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
539 u8 status;
540 int i, pos = 0;
541 #define BUF_LEN 256
542 char buffer[BUF_LEN];
543
544
545 /*
546 * The documentation states that all commands will be
547 * processed within 15µs, and that we need only poll
548 * the status byte a maximum of 3 times in order for the
549 * command to be complete.
550 *
551 * Check 5 times in case the hardware failed to read the docs.
552 *
553 * Also beware that the first response by many devices is to
554 * reply PENDING and stall for time. TVs are notorious for
555 * requiring longer than specified to complete their replies.
556 * Originally (in the DDX long ago), the delay was only ever 15ms
557 * with an additional delay of 30ms applied for TVs added later after
558 * many experiments. To accommodate both sets of delays, we do a
559 * sequence of slow checks if the device is falling behind and fails
560 * to reply within 5*15µs.
561 */
562 if (!intel_sdvo_read_byte(intel_sdvo,
563 SDVO_I2C_CMD_STATUS,
564 &status))
565 goto log_fail;
566
567 while ((status == SDVO_CMD_STATUS_PENDING ||
568 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
569 if (retry < 10)
570 msleep(15);
571 else
572 udelay(15);
573
574 if (!intel_sdvo_read_byte(intel_sdvo,
575 SDVO_I2C_CMD_STATUS,
576 &status))
577 goto log_fail;
578 }
579
580 #define BUF_PRINT(args...) \
581 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
582
583 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
584 BUF_PRINT("(%s)", cmd_status_names[status]);
585 else
586 BUF_PRINT("(??? %d)", status);
587
588 if (status != SDVO_CMD_STATUS_SUCCESS)
589 goto log_fail;
590
591 /* Read the command response */
592 for (i = 0; i < response_len; i++) {
593 if (!intel_sdvo_read_byte(intel_sdvo,
594 SDVO_I2C_RETURN_0 + i,
595 &((u8 *)response)[i]))
596 goto log_fail;
597 BUF_PRINT(" %02X", ((u8 *)response)[i]);
598 }
599 BUG_ON(pos >= BUF_LEN - 1);
600 #undef BUF_PRINT
601 #undef BUF_LEN
602
603 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
604 return true;
605
606 log_fail:
607 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
608 return false;
609 }
610
611 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
612 {
613 if (adjusted_mode->crtc_clock >= 100000)
614 return 1;
615 else if (adjusted_mode->crtc_clock >= 50000)
616 return 2;
617 else
618 return 4;
619 }
620
621 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
622 u8 ddc_bus)
623 {
624 /* This must be the immediately preceding write before the i2c xfer */
625 return intel_sdvo_write_cmd(intel_sdvo,
626 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
627 &ddc_bus, 1);
628 }
629
630 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
631 {
632 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
633 return false;
634
635 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
636 }
637
638 static bool
639 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
640 {
641 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
642 return false;
643
644 return intel_sdvo_read_response(intel_sdvo, value, len);
645 }
646
647 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
648 {
649 struct intel_sdvo_set_target_input_args targets = {0};
650 return intel_sdvo_set_value(intel_sdvo,
651 SDVO_CMD_SET_TARGET_INPUT,
652 &targets, sizeof(targets));
653 }
654
655 /**
656 * Return whether each input is trained.
657 *
658 * This function is making an assumption about the layout of the response,
659 * which should be checked against the docs.
660 */
661 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
662 {
663 struct intel_sdvo_get_trained_inputs_response response;
664
665 BUILD_BUG_ON(sizeof(response) != 1);
666 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
667 &response, sizeof(response)))
668 return false;
669
670 *input_1 = response.input0_trained;
671 *input_2 = response.input1_trained;
672 return true;
673 }
674
675 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
676 u16 outputs)
677 {
678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ACTIVE_OUTPUTS,
680 &outputs, sizeof(outputs));
681 }
682
683 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
684 u16 *outputs)
685 {
686 return intel_sdvo_get_value(intel_sdvo,
687 SDVO_CMD_GET_ACTIVE_OUTPUTS,
688 outputs, sizeof(*outputs));
689 }
690
691 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
692 int mode)
693 {
694 u8 state = SDVO_ENCODER_STATE_ON;
695
696 switch (mode) {
697 case DRM_MODE_DPMS_ON:
698 state = SDVO_ENCODER_STATE_ON;
699 break;
700 case DRM_MODE_DPMS_STANDBY:
701 state = SDVO_ENCODER_STATE_STANDBY;
702 break;
703 case DRM_MODE_DPMS_SUSPEND:
704 state = SDVO_ENCODER_STATE_SUSPEND;
705 break;
706 case DRM_MODE_DPMS_OFF:
707 state = SDVO_ENCODER_STATE_OFF;
708 break;
709 }
710
711 return intel_sdvo_set_value(intel_sdvo,
712 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
713 }
714
715 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
716 int *clock_min,
717 int *clock_max)
718 {
719 struct intel_sdvo_pixel_clock_range clocks;
720
721 BUILD_BUG_ON(sizeof(clocks) != 4);
722 if (!intel_sdvo_get_value(intel_sdvo,
723 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
724 &clocks, sizeof(clocks)))
725 return false;
726
727 /* Convert the values from units of 10 kHz to kHz. */
728 *clock_min = clocks.min * 10;
729 *clock_max = clocks.max * 10;
730 return true;
731 }
732
733 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
734 u16 outputs)
735 {
736 return intel_sdvo_set_value(intel_sdvo,
737 SDVO_CMD_SET_TARGET_OUTPUT,
738 &outputs, sizeof(outputs));
739 }
740
741 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
742 struct intel_sdvo_dtd *dtd)
743 {
744 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
745 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
746 }
747
748 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
749 struct intel_sdvo_dtd *dtd)
750 {
751 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
752 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
753 }
754
755 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
756 struct intel_sdvo_dtd *dtd)
757 {
758 return intel_sdvo_set_timing(intel_sdvo,
759 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
760 }
761
762 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
763 struct intel_sdvo_dtd *dtd)
764 {
765 return intel_sdvo_set_timing(intel_sdvo,
766 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
767 }
768
769 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
770 struct intel_sdvo_dtd *dtd)
771 {
772 return intel_sdvo_get_timing(intel_sdvo,
773 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
774 }
775
776 static bool
777 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
778 uint16_t clock,
779 uint16_t width,
780 uint16_t height)
781 {
782 struct intel_sdvo_preferred_input_timing_args args;
783
784 memset(&args, 0, sizeof(args));
785 args.clock = clock;
786 args.width = width;
787 args.height = height;
788 args.interlace = 0;
789
790 if (intel_sdvo->is_lvds &&
791 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
792 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
793 args.scaled = 1;
794
795 return intel_sdvo_set_value(intel_sdvo,
796 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
797 &args, sizeof(args));
798 }
799
800 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
801 struct intel_sdvo_dtd *dtd)
802 {
803 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
804 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
805 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
806 &dtd->part1, sizeof(dtd->part1)) &&
807 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
808 &dtd->part2, sizeof(dtd->part2));
809 }
810
811 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
812 {
813 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
814 }
815
816 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
817 const struct drm_display_mode *mode)
818 {
819 uint16_t width, height;
820 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
821 uint16_t h_sync_offset, v_sync_offset;
822 int mode_clock;
823
824 memset(dtd, 0, sizeof(*dtd));
825
826 width = mode->hdisplay;
827 height = mode->vdisplay;
828
829 /* do some mode translations */
830 h_blank_len = mode->htotal - mode->hdisplay;
831 h_sync_len = mode->hsync_end - mode->hsync_start;
832
833 v_blank_len = mode->vtotal - mode->vdisplay;
834 v_sync_len = mode->vsync_end - mode->vsync_start;
835
836 h_sync_offset = mode->hsync_start - mode->hdisplay;
837 v_sync_offset = mode->vsync_start - mode->vdisplay;
838
839 mode_clock = mode->clock;
840 mode_clock /= 10;
841 dtd->part1.clock = mode_clock;
842
843 dtd->part1.h_active = width & 0xff;
844 dtd->part1.h_blank = h_blank_len & 0xff;
845 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
846 ((h_blank_len >> 8) & 0xf);
847 dtd->part1.v_active = height & 0xff;
848 dtd->part1.v_blank = v_blank_len & 0xff;
849 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
850 ((v_blank_len >> 8) & 0xf);
851
852 dtd->part2.h_sync_off = h_sync_offset & 0xff;
853 dtd->part2.h_sync_width = h_sync_len & 0xff;
854 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
855 (v_sync_len & 0xf);
856 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
857 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
858 ((v_sync_len & 0x30) >> 4);
859
860 dtd->part2.dtd_flags = 0x18;
861 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
862 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
863 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
864 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
865 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
866 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
867
868 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
869 }
870
871 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
872 const struct intel_sdvo_dtd *dtd)
873 {
874 struct drm_display_mode mode = {};
875
876 mode.hdisplay = dtd->part1.h_active;
877 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
878 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
879 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
880 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
881 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
882 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
883 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
884
885 mode.vdisplay = dtd->part1.v_active;
886 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
887 mode.vsync_start = mode.vdisplay;
888 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
889 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
890 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
891 mode.vsync_end = mode.vsync_start +
892 (dtd->part2.v_sync_off_width & 0xf);
893 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
894 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
895 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
896
897 mode.clock = dtd->part1.clock * 10;
898
899 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
900 mode.flags |= DRM_MODE_FLAG_INTERLACE;
901 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
902 mode.flags |= DRM_MODE_FLAG_PHSYNC;
903 else
904 mode.flags |= DRM_MODE_FLAG_NHSYNC;
905 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
906 mode.flags |= DRM_MODE_FLAG_PVSYNC;
907 else
908 mode.flags |= DRM_MODE_FLAG_NVSYNC;
909
910 drm_mode_set_crtcinfo(&mode, 0);
911
912 drm_mode_copy(pmode, &mode);
913 }
914
915 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
916 {
917 struct intel_sdvo_encode encode;
918
919 BUILD_BUG_ON(sizeof(encode) != 2);
920 return intel_sdvo_get_value(intel_sdvo,
921 SDVO_CMD_GET_SUPP_ENCODE,
922 &encode, sizeof(encode));
923 }
924
925 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
926 uint8_t mode)
927 {
928 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
929 }
930
931 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
932 uint8_t mode)
933 {
934 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
935 }
936
937 #if 0
938 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
939 {
940 int i, j;
941 uint8_t set_buf_index[2];
942 uint8_t av_split;
943 uint8_t buf_size;
944 uint8_t buf[48];
945 uint8_t *pos;
946
947 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
948
949 for (i = 0; i <= av_split; i++) {
950 set_buf_index[0] = i; set_buf_index[1] = 0;
951 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
952 set_buf_index, 2);
953 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
954 intel_sdvo_read_response(encoder, &buf_size, 1);
955
956 pos = buf;
957 for (j = 0; j <= buf_size; j += 8) {
958 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
959 NULL, 0);
960 intel_sdvo_read_response(encoder, pos, 8);
961 pos += 8;
962 }
963 }
964 }
965 #endif
966
967 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
968 unsigned if_index, uint8_t tx_rate,
969 const uint8_t *data, unsigned length)
970 {
971 uint8_t set_buf_index[2] = { if_index, 0 };
972 uint8_t hbuf_size, tmp[8];
973 int i;
974
975 if (!intel_sdvo_set_value(intel_sdvo,
976 SDVO_CMD_SET_HBUF_INDEX,
977 set_buf_index, 2))
978 return false;
979
980 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
981 &hbuf_size, 1))
982 return false;
983
984 /* Buffer size is 0 based, hooray! */
985 hbuf_size++;
986
987 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
988 if_index, length, hbuf_size);
989
990 for (i = 0; i < hbuf_size; i += 8) {
991 memset(tmp, 0, 8);
992 if (i < length)
993 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
994
995 if (!intel_sdvo_set_value(intel_sdvo,
996 SDVO_CMD_SET_HBUF_DATA,
997 tmp, 8))
998 return false;
999 }
1000
1001 return intel_sdvo_set_value(intel_sdvo,
1002 SDVO_CMD_SET_HBUF_TXRATE,
1003 &tx_rate, 1);
1004 }
1005
1006 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1007 const struct drm_display_mode *adjusted_mode)
1008 {
1009 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1010 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1012 union hdmi_infoframe frame;
1013 int ret;
1014 ssize_t len;
1015
1016 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
1017 adjusted_mode);
1018 if (ret < 0) {
1019 DRM_ERROR("couldn't fill AVI infoframe\n");
1020 return false;
1021 }
1022
1023 if (intel_sdvo->rgb_quant_range_selectable) {
1024 if (intel_crtc->config->limited_color_range)
1025 frame.avi.quantization_range =
1026 HDMI_QUANTIZATION_RANGE_LIMITED;
1027 else
1028 frame.avi.quantization_range =
1029 HDMI_QUANTIZATION_RANGE_FULL;
1030 }
1031
1032 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1033 if (len < 0)
1034 return false;
1035
1036 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1037 SDVO_HBUF_TX_VSYNC,
1038 sdvo_data, sizeof(sdvo_data));
1039 }
1040
1041 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
1042 {
1043 struct intel_sdvo_tv_format format;
1044 uint32_t format_map;
1045
1046 format_map = 1 << intel_sdvo->tv_format_index;
1047 memset(&format, 0, sizeof(format));
1048 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1049
1050 BUILD_BUG_ON(sizeof(format) != 6);
1051 return intel_sdvo_set_value(intel_sdvo,
1052 SDVO_CMD_SET_TV_FORMAT,
1053 &format, sizeof(format));
1054 }
1055
1056 static bool
1057 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1058 const struct drm_display_mode *mode)
1059 {
1060 struct intel_sdvo_dtd output_dtd;
1061
1062 if (!intel_sdvo_set_target_output(intel_sdvo,
1063 intel_sdvo->attached_output))
1064 return false;
1065
1066 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1067 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1068 return false;
1069
1070 return true;
1071 }
1072
1073 /* Asks the sdvo controller for the preferred input mode given the output mode.
1074 * Unfortunately we have to set up the full output mode to do that. */
1075 static bool
1076 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1077 const struct drm_display_mode *mode,
1078 struct drm_display_mode *adjusted_mode)
1079 {
1080 struct intel_sdvo_dtd input_dtd;
1081
1082 /* Reset the input timing to the screen. Assume always input 0. */
1083 if (!intel_sdvo_set_target_input(intel_sdvo))
1084 return false;
1085
1086 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1087 mode->clock / 10,
1088 mode->hdisplay,
1089 mode->vdisplay))
1090 return false;
1091
1092 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1093 &input_dtd))
1094 return false;
1095
1096 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1097 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1098
1099 return true;
1100 }
1101
1102 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1103 {
1104 unsigned dotclock = pipe_config->port_clock;
1105 struct dpll *clock = &pipe_config->dpll;
1106
1107 /* SDVO TV has fixed PLL values depend on its clock range,
1108 this mirrors vbios setting. */
1109 if (dotclock >= 100000 && dotclock < 140500) {
1110 clock->p1 = 2;
1111 clock->p2 = 10;
1112 clock->n = 3;
1113 clock->m1 = 16;
1114 clock->m2 = 8;
1115 } else if (dotclock >= 140500 && dotclock <= 200000) {
1116 clock->p1 = 1;
1117 clock->p2 = 10;
1118 clock->n = 6;
1119 clock->m1 = 12;
1120 clock->m2 = 8;
1121 } else {
1122 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1123 }
1124
1125 pipe_config->clock_set = true;
1126 }
1127
1128 static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1129 struct intel_crtc_state *pipe_config)
1130 {
1131 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1132 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1133 struct drm_display_mode *mode = &pipe_config->base.mode;
1134
1135 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1136 pipe_config->pipe_bpp = 8*3;
1137
1138 if (HAS_PCH_SPLIT(encoder->base.dev))
1139 pipe_config->has_pch_encoder = true;
1140
1141 /* We need to construct preferred input timings based on our
1142 * output timings. To do that, we have to set the output
1143 * timings, even though this isn't really the right place in
1144 * the sequence to do it. Oh well.
1145 */
1146 if (intel_sdvo->is_tv) {
1147 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1148 return false;
1149
1150 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1151 mode,
1152 adjusted_mode);
1153 pipe_config->sdvo_tv_clock = true;
1154 } else if (intel_sdvo->is_lvds) {
1155 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1156 intel_sdvo->sdvo_lvds_fixed_mode))
1157 return false;
1158
1159 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1160 mode,
1161 adjusted_mode);
1162 }
1163
1164 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1165 * SDVO device will factor out the multiplier during mode_set.
1166 */
1167 pipe_config->pixel_multiplier =
1168 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1169
1170 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1171
1172 if (intel_sdvo->color_range_auto) {
1173 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1174 /* FIXME: This bit is only valid when using TMDS encoding and 8
1175 * bit per color mode. */
1176 if (pipe_config->has_hdmi_sink &&
1177 drm_match_cea_mode(adjusted_mode) > 1)
1178 pipe_config->limited_color_range = true;
1179 } else {
1180 if (pipe_config->has_hdmi_sink &&
1181 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235)
1182 pipe_config->limited_color_range = true;
1183 }
1184
1185 /* Clock computation needs to happen after pixel multiplier. */
1186 if (intel_sdvo->is_tv)
1187 i9xx_adjust_sdvo_tv_clock(pipe_config);
1188
1189 /* Set user selected PAR to incoming mode's member */
1190 if (intel_sdvo->is_hdmi)
1191 adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio;
1192
1193 return true;
1194 }
1195
1196 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
1197 {
1198 struct drm_device *dev = intel_encoder->base.dev;
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1200 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
1201 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1202 struct drm_display_mode *mode = &crtc->config->base.mode;
1203 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1204 u32 sdvox;
1205 struct intel_sdvo_in_out_map in_out;
1206 struct intel_sdvo_dtd input_dtd, output_dtd;
1207 int rate;
1208
1209 if (!mode)
1210 return;
1211
1212 /* First, set the input mapping for the first input to our controlled
1213 * output. This is only correct if we're a single-input device, in
1214 * which case the first input is the output from the appropriate SDVO
1215 * channel on the motherboard. In a two-input device, the first input
1216 * will be SDVOB and the second SDVOC.
1217 */
1218 in_out.in0 = intel_sdvo->attached_output;
1219 in_out.in1 = 0;
1220
1221 intel_sdvo_set_value(intel_sdvo,
1222 SDVO_CMD_SET_IN_OUT_MAP,
1223 &in_out, sizeof(in_out));
1224
1225 /* Set the output timings to the screen */
1226 if (!intel_sdvo_set_target_output(intel_sdvo,
1227 intel_sdvo->attached_output))
1228 return;
1229
1230 /* lvds has a special fixed output timing. */
1231 if (intel_sdvo->is_lvds)
1232 intel_sdvo_get_dtd_from_mode(&output_dtd,
1233 intel_sdvo->sdvo_lvds_fixed_mode);
1234 else
1235 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1236 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1237 DRM_INFO("Setting output timings on %s failed\n",
1238 SDVO_NAME(intel_sdvo));
1239
1240 /* Set the input timing to the screen. Assume always input 0. */
1241 if (!intel_sdvo_set_target_input(intel_sdvo))
1242 return;
1243
1244 if (crtc->config->has_hdmi_sink) {
1245 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1246 intel_sdvo_set_colorimetry(intel_sdvo,
1247 SDVO_COLORIMETRY_RGB256);
1248 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
1249 } else
1250 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1251
1252 if (intel_sdvo->is_tv &&
1253 !intel_sdvo_set_tv_format(intel_sdvo))
1254 return;
1255
1256 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1257
1258 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1259 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1260 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1261 DRM_INFO("Setting input timings on %s failed\n",
1262 SDVO_NAME(intel_sdvo));
1263
1264 switch (crtc->config->pixel_multiplier) {
1265 default:
1266 WARN(1, "unknown pixel multiplier specified\n");
1267 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1268 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1269 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1270 }
1271 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1272 return;
1273
1274 /* Set the SDVO control regs. */
1275 if (INTEL_INFO(dev)->gen >= 4) {
1276 /* The real mode polarity is set by the SDVO commands, using
1277 * struct intel_sdvo_dtd. */
1278 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1279 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
1280 sdvox |= HDMI_COLOR_RANGE_16_235;
1281 if (INTEL_INFO(dev)->gen < 5)
1282 sdvox |= SDVO_BORDER_ENABLE;
1283 } else {
1284 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1285 switch (intel_sdvo->sdvo_reg) {
1286 case GEN3_SDVOB:
1287 sdvox &= SDVOB_PRESERVE_MASK;
1288 break;
1289 case GEN3_SDVOC:
1290 sdvox &= SDVOC_PRESERVE_MASK;
1291 break;
1292 }
1293 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1294 }
1295
1296 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1297 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1298 else
1299 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1300
1301 if (intel_sdvo->has_hdmi_audio)
1302 sdvox |= SDVO_AUDIO_ENABLE;
1303
1304 if (INTEL_INFO(dev)->gen >= 4) {
1305 /* done in crtc_mode_set as the dpll_md reg must be written early */
1306 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1307 /* done in crtc_mode_set as it lives inside the dpll register */
1308 } else {
1309 sdvox |= (crtc->config->pixel_multiplier - 1)
1310 << SDVO_PORT_MULTIPLY_SHIFT;
1311 }
1312
1313 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1314 INTEL_INFO(dev)->gen < 5)
1315 sdvox |= SDVO_STALL_SELECT;
1316 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1317 }
1318
1319 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1320 {
1321 struct intel_sdvo_connector *intel_sdvo_connector =
1322 to_intel_sdvo_connector(&connector->base);
1323 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1324 u16 active_outputs = 0;
1325
1326 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1327
1328 if (active_outputs & intel_sdvo_connector->output_flag)
1329 return true;
1330 else
1331 return false;
1332 }
1333
1334 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1335 enum pipe *pipe)
1336 {
1337 struct drm_device *dev = encoder->base.dev;
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1340 u16 active_outputs = 0;
1341 u32 tmp;
1342
1343 tmp = I915_READ(intel_sdvo->sdvo_reg);
1344 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1345
1346 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
1347 return false;
1348
1349 if (HAS_PCH_CPT(dev))
1350 *pipe = PORT_TO_PIPE_CPT(tmp);
1351 else
1352 *pipe = PORT_TO_PIPE(tmp);
1353
1354 return true;
1355 }
1356
1357 static void intel_sdvo_get_config(struct intel_encoder *encoder,
1358 struct intel_crtc_state *pipe_config)
1359 {
1360 struct drm_device *dev = encoder->base.dev;
1361 struct drm_i915_private *dev_priv = dev->dev_private;
1362 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1363 struct intel_sdvo_dtd dtd;
1364 int encoder_pixel_multiplier = 0;
1365 int dotclock;
1366 u32 flags = 0, sdvox;
1367 u8 val;
1368 bool ret;
1369
1370 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1371
1372 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1373 if (!ret) {
1374 /* Some sdvo encoders are not spec compliant and don't
1375 * implement the mandatory get_timings function. */
1376 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1377 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1378 } else {
1379 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1380 flags |= DRM_MODE_FLAG_PHSYNC;
1381 else
1382 flags |= DRM_MODE_FLAG_NHSYNC;
1383
1384 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1385 flags |= DRM_MODE_FLAG_PVSYNC;
1386 else
1387 flags |= DRM_MODE_FLAG_NVSYNC;
1388 }
1389
1390 pipe_config->base.adjusted_mode.flags |= flags;
1391
1392 /*
1393 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1394 * the sdvo port register, on all other platforms it is part of the dpll
1395 * state. Since the general pipe state readout happens before the
1396 * encoder->get_config we so already have a valid pixel multplier on all
1397 * other platfroms.
1398 */
1399 if (IS_I915G(dev) || IS_I915GM(dev)) {
1400 pipe_config->pixel_multiplier =
1401 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1402 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1403 }
1404
1405 dotclock = pipe_config->port_clock;
1406 if (pipe_config->pixel_multiplier)
1407 dotclock /= pipe_config->pixel_multiplier;
1408
1409 if (HAS_PCH_SPLIT(dev))
1410 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1411
1412 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1413
1414 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1415 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1416 &val, 1)) {
1417 switch (val) {
1418 case SDVO_CLOCK_RATE_MULT_1X:
1419 encoder_pixel_multiplier = 1;
1420 break;
1421 case SDVO_CLOCK_RATE_MULT_2X:
1422 encoder_pixel_multiplier = 2;
1423 break;
1424 case SDVO_CLOCK_RATE_MULT_4X:
1425 encoder_pixel_multiplier = 4;
1426 break;
1427 }
1428 }
1429
1430 if (sdvox & HDMI_COLOR_RANGE_16_235)
1431 pipe_config->limited_color_range = true;
1432
1433 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1434 &val, 1)) {
1435 if (val == SDVO_ENCODE_HDMI)
1436 pipe_config->has_hdmi_sink = true;
1437 }
1438
1439 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1440 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1441 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1442 }
1443
1444 static void intel_disable_sdvo(struct intel_encoder *encoder)
1445 {
1446 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1447 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1448 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1449 u32 temp;
1450
1451 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1452 if (0)
1453 intel_sdvo_set_encoder_power_state(intel_sdvo,
1454 DRM_MODE_DPMS_OFF);
1455
1456 temp = I915_READ(intel_sdvo->sdvo_reg);
1457
1458 temp &= ~SDVO_ENABLE;
1459 intel_sdvo_write_sdvox(intel_sdvo, temp);
1460
1461 /*
1462 * HW workaround for IBX, we need to move the port
1463 * to transcoder A after disabling it to allow the
1464 * matching DP port to be enabled on transcoder A.
1465 */
1466 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1467 /*
1468 * We get CPU/PCH FIFO underruns on the other pipe when
1469 * doing the workaround. Sweep them under the rug.
1470 */
1471 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1472 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1473
1474 temp &= ~SDVO_PIPE_B_SELECT;
1475 temp |= SDVO_ENABLE;
1476 intel_sdvo_write_sdvox(intel_sdvo, temp);
1477
1478 temp &= ~SDVO_ENABLE;
1479 intel_sdvo_write_sdvox(intel_sdvo, temp);
1480
1481 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
1482 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1483 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1484 }
1485 }
1486
1487 static void pch_disable_sdvo(struct intel_encoder *encoder)
1488 {
1489 }
1490
1491 static void pch_post_disable_sdvo(struct intel_encoder *encoder)
1492 {
1493 intel_disable_sdvo(encoder);
1494 }
1495
1496 static void intel_enable_sdvo(struct intel_encoder *encoder)
1497 {
1498 struct drm_device *dev = encoder->base.dev;
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1501 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1502 u32 temp;
1503 bool input1, input2;
1504 int i;
1505 bool success;
1506
1507 temp = I915_READ(intel_sdvo->sdvo_reg);
1508 temp |= SDVO_ENABLE;
1509 intel_sdvo_write_sdvox(intel_sdvo, temp);
1510
1511 for (i = 0; i < 2; i++)
1512 intel_wait_for_vblank(dev, intel_crtc->pipe);
1513
1514 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1515 /* Warn if the device reported failure to sync.
1516 * A lot of SDVO devices fail to notify of sync, but it's
1517 * a given it the status is a success, we succeeded.
1518 */
1519 if (success && !input1) {
1520 DRM_DEBUG_KMS("First %s output reported failure to "
1521 "sync\n", SDVO_NAME(intel_sdvo));
1522 }
1523
1524 if (0)
1525 intel_sdvo_set_encoder_power_state(intel_sdvo,
1526 DRM_MODE_DPMS_ON);
1527 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1528 }
1529
1530 static enum drm_mode_status
1531 intel_sdvo_mode_valid(struct drm_connector *connector,
1532 struct drm_display_mode *mode)
1533 {
1534 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1535
1536 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1537 return MODE_NO_DBLESCAN;
1538
1539 if (intel_sdvo->pixel_clock_min > mode->clock)
1540 return MODE_CLOCK_LOW;
1541
1542 if (intel_sdvo->pixel_clock_max < mode->clock)
1543 return MODE_CLOCK_HIGH;
1544
1545 if (intel_sdvo->is_lvds) {
1546 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1547 return MODE_PANEL;
1548
1549 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1550 return MODE_PANEL;
1551 }
1552
1553 return MODE_OK;
1554 }
1555
1556 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1557 {
1558 BUILD_BUG_ON(sizeof(*caps) != 8);
1559 if (!intel_sdvo_get_value(intel_sdvo,
1560 SDVO_CMD_GET_DEVICE_CAPS,
1561 caps, sizeof(*caps)))
1562 return false;
1563
1564 DRM_DEBUG_KMS("SDVO capabilities:\n"
1565 " vendor_id: %d\n"
1566 " device_id: %d\n"
1567 " device_rev_id: %d\n"
1568 " sdvo_version_major: %d\n"
1569 " sdvo_version_minor: %d\n"
1570 " sdvo_inputs_mask: %d\n"
1571 " smooth_scaling: %d\n"
1572 " sharp_scaling: %d\n"
1573 " up_scaling: %d\n"
1574 " down_scaling: %d\n"
1575 " stall_support: %d\n"
1576 " output_flags: %d\n",
1577 caps->vendor_id,
1578 caps->device_id,
1579 caps->device_rev_id,
1580 caps->sdvo_version_major,
1581 caps->sdvo_version_minor,
1582 caps->sdvo_inputs_mask,
1583 caps->smooth_scaling,
1584 caps->sharp_scaling,
1585 caps->up_scaling,
1586 caps->down_scaling,
1587 caps->stall_support,
1588 caps->output_flags);
1589
1590 return true;
1591 }
1592
1593 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1594 {
1595 struct drm_device *dev = intel_sdvo->base.base.dev;
1596 uint16_t hotplug;
1597
1598 if (!I915_HAS_HOTPLUG(dev))
1599 return 0;
1600
1601 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1602 * on the line. */
1603 if (IS_I945G(dev) || IS_I945GM(dev))
1604 return 0;
1605
1606 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1607 &hotplug, sizeof(hotplug)))
1608 return 0;
1609
1610 return hotplug;
1611 }
1612
1613 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1614 {
1615 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1616
1617 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1618 &intel_sdvo->hotplug_active, 2);
1619 }
1620
1621 static bool
1622 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1623 {
1624 /* Is there more than one type of output? */
1625 return hweight16(intel_sdvo->caps.output_flags) > 1;
1626 }
1627
1628 static struct edid *
1629 intel_sdvo_get_edid(struct drm_connector *connector)
1630 {
1631 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1632 return drm_get_edid(connector, &sdvo->ddc);
1633 }
1634
1635 /* Mac mini hack -- use the same DDC as the analog connector */
1636 static struct edid *
1637 intel_sdvo_get_analog_edid(struct drm_connector *connector)
1638 {
1639 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1640
1641 return drm_get_edid(connector,
1642 intel_gmbus_get_adapter(dev_priv,
1643 dev_priv->vbt.crt_ddc_pin));
1644 }
1645
1646 static enum drm_connector_status
1647 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
1648 {
1649 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1650 enum drm_connector_status status;
1651 struct edid *edid;
1652
1653 edid = intel_sdvo_get_edid(connector);
1654
1655 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1656 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
1657
1658 /*
1659 * Don't use the 1 as the argument of DDC bus switch to get
1660 * the EDID. It is used for SDVO SPD ROM.
1661 */
1662 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1663 intel_sdvo->ddc_bus = ddc;
1664 edid = intel_sdvo_get_edid(connector);
1665 if (edid)
1666 break;
1667 }
1668 /*
1669 * If we found the EDID on the other bus,
1670 * assume that is the correct DDC bus.
1671 */
1672 if (edid == NULL)
1673 intel_sdvo->ddc_bus = saved_ddc;
1674 }
1675
1676 /*
1677 * When there is no edid and no monitor is connected with VGA
1678 * port, try to use the CRT ddc to read the EDID for DVI-connector.
1679 */
1680 if (edid == NULL)
1681 edid = intel_sdvo_get_analog_edid(connector);
1682
1683 status = connector_status_unknown;
1684 if (edid != NULL) {
1685 /* DDC bus is shared, match EDID to connector type */
1686 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1687 status = connector_status_connected;
1688 if (intel_sdvo->is_hdmi) {
1689 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1690 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1691 intel_sdvo->rgb_quant_range_selectable =
1692 drm_rgb_quant_range_selectable(edid);
1693 }
1694 } else
1695 status = connector_status_disconnected;
1696 kfree(edid);
1697 }
1698
1699 if (status == connector_status_connected) {
1700 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1701 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1702 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
1703 }
1704
1705 return status;
1706 }
1707
1708 static bool
1709 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1710 struct edid *edid)
1711 {
1712 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1713 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1714
1715 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1716 connector_is_digital, monitor_is_digital);
1717 return connector_is_digital == monitor_is_digital;
1718 }
1719
1720 static enum drm_connector_status
1721 intel_sdvo_detect(struct drm_connector *connector, bool force)
1722 {
1723 uint16_t response;
1724 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1725 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1726 enum drm_connector_status ret;
1727
1728 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1729 connector->base.id, connector->name);
1730
1731 if (!intel_sdvo_get_value(intel_sdvo,
1732 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1733 &response, 2))
1734 return connector_status_unknown;
1735
1736 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1737 response & 0xff, response >> 8,
1738 intel_sdvo_connector->output_flag);
1739
1740 if (response == 0)
1741 return connector_status_disconnected;
1742
1743 intel_sdvo->attached_output = response;
1744
1745 intel_sdvo->has_hdmi_monitor = false;
1746 intel_sdvo->has_hdmi_audio = false;
1747 intel_sdvo->rgb_quant_range_selectable = false;
1748
1749 if ((intel_sdvo_connector->output_flag & response) == 0)
1750 ret = connector_status_disconnected;
1751 else if (IS_TMDS(intel_sdvo_connector))
1752 ret = intel_sdvo_tmds_sink_detect(connector);
1753 else {
1754 struct edid *edid;
1755
1756 /* if we have an edid check it matches the connection */
1757 edid = intel_sdvo_get_edid(connector);
1758 if (edid == NULL)
1759 edid = intel_sdvo_get_analog_edid(connector);
1760 if (edid != NULL) {
1761 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1762 edid))
1763 ret = connector_status_connected;
1764 else
1765 ret = connector_status_disconnected;
1766
1767 kfree(edid);
1768 } else
1769 ret = connector_status_connected;
1770 }
1771
1772 /* May update encoder flag for like clock for SDVO TV, etc.*/
1773 if (ret == connector_status_connected) {
1774 intel_sdvo->is_tv = false;
1775 intel_sdvo->is_lvds = false;
1776
1777 if (response & SDVO_TV_MASK)
1778 intel_sdvo->is_tv = true;
1779 if (response & SDVO_LVDS_MASK)
1780 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1781 }
1782
1783 return ret;
1784 }
1785
1786 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1787 {
1788 struct edid *edid;
1789
1790 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1791 connector->base.id, connector->name);
1792
1793 /* set the bus switch and get the modes */
1794 edid = intel_sdvo_get_edid(connector);
1795
1796 /*
1797 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1798 * link between analog and digital outputs. So, if the regular SDVO
1799 * DDC fails, check to see if the analog output is disconnected, in
1800 * which case we'll look there for the digital DDC data.
1801 */
1802 if (edid == NULL)
1803 edid = intel_sdvo_get_analog_edid(connector);
1804
1805 if (edid != NULL) {
1806 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1807 edid)) {
1808 drm_mode_connector_update_edid_property(connector, edid);
1809 drm_add_edid_modes(connector, edid);
1810 }
1811
1812 kfree(edid);
1813 }
1814 }
1815
1816 /*
1817 * Set of SDVO TV modes.
1818 * Note! This is in reply order (see loop in get_tv_modes).
1819 * XXX: all 60Hz refresh?
1820 */
1821 static const struct drm_display_mode sdvo_tv_modes[] = {
1822 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1823 416, 0, 200, 201, 232, 233, 0,
1824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1825 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1826 416, 0, 240, 241, 272, 273, 0,
1827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1828 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1829 496, 0, 300, 301, 332, 333, 0,
1830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1831 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1832 736, 0, 350, 351, 382, 383, 0,
1833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1834 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1835 736, 0, 400, 401, 432, 433, 0,
1836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1837 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1838 736, 0, 480, 481, 512, 513, 0,
1839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1840 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1841 800, 0, 480, 481, 512, 513, 0,
1842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1843 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1844 800, 0, 576, 577, 608, 609, 0,
1845 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1846 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1847 816, 0, 350, 351, 382, 383, 0,
1848 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1849 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1850 816, 0, 400, 401, 432, 433, 0,
1851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1852 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1853 816, 0, 480, 481, 512, 513, 0,
1854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1855 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1856 816, 0, 540, 541, 572, 573, 0,
1857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1858 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1859 816, 0, 576, 577, 608, 609, 0,
1860 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1861 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1862 864, 0, 576, 577, 608, 609, 0,
1863 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1864 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1865 896, 0, 600, 601, 632, 633, 0,
1866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1867 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1868 928, 0, 624, 625, 656, 657, 0,
1869 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1870 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1871 1016, 0, 766, 767, 798, 799, 0,
1872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1873 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1874 1120, 0, 768, 769, 800, 801, 0,
1875 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1876 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1877 1376, 0, 1024, 1025, 1056, 1057, 0,
1878 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1879 };
1880
1881 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1882 {
1883 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1884 struct intel_sdvo_sdtv_resolution_request tv_res;
1885 uint32_t reply = 0, format_map = 0;
1886 int i;
1887
1888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1889 connector->base.id, connector->name);
1890
1891 /* Read the list of supported input resolutions for the selected TV
1892 * format.
1893 */
1894 format_map = 1 << intel_sdvo->tv_format_index;
1895 memcpy(&tv_res, &format_map,
1896 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
1897
1898 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1899 return;
1900
1901 BUILD_BUG_ON(sizeof(tv_res) != 3);
1902 if (!intel_sdvo_write_cmd(intel_sdvo,
1903 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1904 &tv_res, sizeof(tv_res)))
1905 return;
1906 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
1907 return;
1908
1909 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1910 if (reply & (1 << i)) {
1911 struct drm_display_mode *nmode;
1912 nmode = drm_mode_duplicate(connector->dev,
1913 &sdvo_tv_modes[i]);
1914 if (nmode)
1915 drm_mode_probed_add(connector, nmode);
1916 }
1917 }
1918
1919 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1920 {
1921 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1922 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1923 struct drm_display_mode *newmode;
1924
1925 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1926 connector->base.id, connector->name);
1927
1928 /*
1929 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
1930 * SDVO->LVDS transcoders can't cope with the EDID mode.
1931 */
1932 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
1933 newmode = drm_mode_duplicate(connector->dev,
1934 dev_priv->vbt.sdvo_lvds_vbt_mode);
1935 if (newmode != NULL) {
1936 /* Guarantee the mode is preferred */
1937 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1938 DRM_MODE_TYPE_DRIVER);
1939 drm_mode_probed_add(connector, newmode);
1940 }
1941 }
1942
1943 /*
1944 * Attempt to get the mode list from DDC.
1945 * Assume that the preferred modes are
1946 * arranged in priority order.
1947 */
1948 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1949
1950 list_for_each_entry(newmode, &connector->probed_modes, head) {
1951 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1952 intel_sdvo->sdvo_lvds_fixed_mode =
1953 drm_mode_duplicate(connector->dev, newmode);
1954
1955 intel_sdvo->is_lvds = true;
1956 break;
1957 }
1958 }
1959 }
1960
1961 static int intel_sdvo_get_modes(struct drm_connector *connector)
1962 {
1963 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1964
1965 if (IS_TV(intel_sdvo_connector))
1966 intel_sdvo_get_tv_modes(connector);
1967 else if (IS_LVDS(intel_sdvo_connector))
1968 intel_sdvo_get_lvds_modes(connector);
1969 else
1970 intel_sdvo_get_ddc_modes(connector);
1971
1972 return !list_empty(&connector->probed_modes);
1973 }
1974
1975 static void intel_sdvo_destroy(struct drm_connector *connector)
1976 {
1977 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1978
1979 drm_connector_cleanup(connector);
1980 kfree(intel_sdvo_connector);
1981 }
1982
1983 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1984 {
1985 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1986 struct edid *edid;
1987 bool has_audio = false;
1988
1989 if (!intel_sdvo->is_hdmi)
1990 return false;
1991
1992 edid = intel_sdvo_get_edid(connector);
1993 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1994 has_audio = drm_detect_monitor_audio(edid);
1995 kfree(edid);
1996
1997 return has_audio;
1998 }
1999
2000 static int
2001 intel_sdvo_set_property(struct drm_connector *connector,
2002 struct drm_property *property,
2003 uint64_t val)
2004 {
2005 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2006 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2007 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2008 uint16_t temp_value;
2009 uint8_t cmd;
2010 int ret;
2011
2012 ret = drm_object_property_set_value(&connector->base, property, val);
2013 if (ret)
2014 return ret;
2015
2016 if (property == dev_priv->force_audio_property) {
2017 int i = val;
2018 bool has_audio;
2019
2020 if (i == intel_sdvo_connector->force_audio)
2021 return 0;
2022
2023 intel_sdvo_connector->force_audio = i;
2024
2025 if (i == HDMI_AUDIO_AUTO)
2026 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2027 else
2028 has_audio = (i == HDMI_AUDIO_ON);
2029
2030 if (has_audio == intel_sdvo->has_hdmi_audio)
2031 return 0;
2032
2033 intel_sdvo->has_hdmi_audio = has_audio;
2034 goto done;
2035 }
2036
2037 if (property == dev_priv->broadcast_rgb_property) {
2038 bool old_auto = intel_sdvo->color_range_auto;
2039 uint32_t old_range = intel_sdvo->color_range;
2040
2041 switch (val) {
2042 case INTEL_BROADCAST_RGB_AUTO:
2043 intel_sdvo->color_range_auto = true;
2044 break;
2045 case INTEL_BROADCAST_RGB_FULL:
2046 intel_sdvo->color_range_auto = false;
2047 intel_sdvo->color_range = 0;
2048 break;
2049 case INTEL_BROADCAST_RGB_LIMITED:
2050 intel_sdvo->color_range_auto = false;
2051 /* FIXME: this bit is only valid when using TMDS
2052 * encoding and 8 bit per color mode. */
2053 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
2054 break;
2055 default:
2056 return -EINVAL;
2057 }
2058
2059 if (old_auto == intel_sdvo->color_range_auto &&
2060 old_range == intel_sdvo->color_range)
2061 return 0;
2062
2063 goto done;
2064 }
2065
2066 if (property == connector->dev->mode_config.aspect_ratio_property) {
2067 switch (val) {
2068 case DRM_MODE_PICTURE_ASPECT_NONE:
2069 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2070 break;
2071 case DRM_MODE_PICTURE_ASPECT_4_3:
2072 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
2073 break;
2074 case DRM_MODE_PICTURE_ASPECT_16_9:
2075 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
2076 break;
2077 default:
2078 return -EINVAL;
2079 }
2080 goto done;
2081 }
2082
2083 #define CHECK_PROPERTY(name, NAME) \
2084 if (intel_sdvo_connector->name == property) { \
2085 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2086 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2087 cmd = SDVO_CMD_SET_##NAME; \
2088 intel_sdvo_connector->cur_##name = temp_value; \
2089 goto set_value; \
2090 }
2091
2092 if (property == intel_sdvo_connector->tv_format) {
2093 if (val >= TV_FORMAT_NUM)
2094 return -EINVAL;
2095
2096 if (intel_sdvo->tv_format_index ==
2097 intel_sdvo_connector->tv_format_supported[val])
2098 return 0;
2099
2100 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
2101 goto done;
2102 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
2103 temp_value = val;
2104 if (intel_sdvo_connector->left == property) {
2105 drm_object_property_set_value(&connector->base,
2106 intel_sdvo_connector->right, val);
2107 if (intel_sdvo_connector->left_margin == temp_value)
2108 return 0;
2109
2110 intel_sdvo_connector->left_margin = temp_value;
2111 intel_sdvo_connector->right_margin = temp_value;
2112 temp_value = intel_sdvo_connector->max_hscan -
2113 intel_sdvo_connector->left_margin;
2114 cmd = SDVO_CMD_SET_OVERSCAN_H;
2115 goto set_value;
2116 } else if (intel_sdvo_connector->right == property) {
2117 drm_object_property_set_value(&connector->base,
2118 intel_sdvo_connector->left, val);
2119 if (intel_sdvo_connector->right_margin == temp_value)
2120 return 0;
2121
2122 intel_sdvo_connector->left_margin = temp_value;
2123 intel_sdvo_connector->right_margin = temp_value;
2124 temp_value = intel_sdvo_connector->max_hscan -
2125 intel_sdvo_connector->left_margin;
2126 cmd = SDVO_CMD_SET_OVERSCAN_H;
2127 goto set_value;
2128 } else if (intel_sdvo_connector->top == property) {
2129 drm_object_property_set_value(&connector->base,
2130 intel_sdvo_connector->bottom, val);
2131 if (intel_sdvo_connector->top_margin == temp_value)
2132 return 0;
2133
2134 intel_sdvo_connector->top_margin = temp_value;
2135 intel_sdvo_connector->bottom_margin = temp_value;
2136 temp_value = intel_sdvo_connector->max_vscan -
2137 intel_sdvo_connector->top_margin;
2138 cmd = SDVO_CMD_SET_OVERSCAN_V;
2139 goto set_value;
2140 } else if (intel_sdvo_connector->bottom == property) {
2141 drm_object_property_set_value(&connector->base,
2142 intel_sdvo_connector->top, val);
2143 if (intel_sdvo_connector->bottom_margin == temp_value)
2144 return 0;
2145
2146 intel_sdvo_connector->top_margin = temp_value;
2147 intel_sdvo_connector->bottom_margin = temp_value;
2148 temp_value = intel_sdvo_connector->max_vscan -
2149 intel_sdvo_connector->top_margin;
2150 cmd = SDVO_CMD_SET_OVERSCAN_V;
2151 goto set_value;
2152 }
2153 CHECK_PROPERTY(hpos, HPOS)
2154 CHECK_PROPERTY(vpos, VPOS)
2155 CHECK_PROPERTY(saturation, SATURATION)
2156 CHECK_PROPERTY(contrast, CONTRAST)
2157 CHECK_PROPERTY(hue, HUE)
2158 CHECK_PROPERTY(brightness, BRIGHTNESS)
2159 CHECK_PROPERTY(sharpness, SHARPNESS)
2160 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2161 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2162 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2163 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2164 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
2165 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
2166 }
2167
2168 return -EINVAL; /* unknown property */
2169
2170 set_value:
2171 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2172 return -EIO;
2173
2174
2175 done:
2176 if (intel_sdvo->base.base.crtc)
2177 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
2178
2179 return 0;
2180 #undef CHECK_PROPERTY
2181 }
2182
2183 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2184 .dpms = drm_atomic_helper_connector_dpms,
2185 .detect = intel_sdvo_detect,
2186 .fill_modes = drm_helper_probe_single_connector_modes,
2187 .set_property = intel_sdvo_set_property,
2188 .atomic_get_property = intel_connector_atomic_get_property,
2189 .destroy = intel_sdvo_destroy,
2190 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2191 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2192 };
2193
2194 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2195 .get_modes = intel_sdvo_get_modes,
2196 .mode_valid = intel_sdvo_mode_valid,
2197 .best_encoder = intel_best_encoder,
2198 };
2199
2200 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2201 {
2202 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2203
2204 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
2205 drm_mode_destroy(encoder->dev,
2206 intel_sdvo->sdvo_lvds_fixed_mode);
2207
2208 i2c_del_adapter(&intel_sdvo->ddc);
2209 intel_encoder_destroy(encoder);
2210 }
2211
2212 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2213 .destroy = intel_sdvo_enc_destroy,
2214 };
2215
2216 static void
2217 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2218 {
2219 uint16_t mask = 0;
2220 unsigned int num_bits;
2221
2222 /* Make a mask of outputs less than or equal to our own priority in the
2223 * list.
2224 */
2225 switch (sdvo->controlled_output) {
2226 case SDVO_OUTPUT_LVDS1:
2227 mask |= SDVO_OUTPUT_LVDS1;
2228 case SDVO_OUTPUT_LVDS0:
2229 mask |= SDVO_OUTPUT_LVDS0;
2230 case SDVO_OUTPUT_TMDS1:
2231 mask |= SDVO_OUTPUT_TMDS1;
2232 case SDVO_OUTPUT_TMDS0:
2233 mask |= SDVO_OUTPUT_TMDS0;
2234 case SDVO_OUTPUT_RGB1:
2235 mask |= SDVO_OUTPUT_RGB1;
2236 case SDVO_OUTPUT_RGB0:
2237 mask |= SDVO_OUTPUT_RGB0;
2238 break;
2239 }
2240
2241 /* Count bits to find what number we are in the priority list. */
2242 mask &= sdvo->caps.output_flags;
2243 num_bits = hweight16(mask);
2244 /* If more than 3 outputs, default to DDC bus 3 for now. */
2245 if (num_bits > 3)
2246 num_bits = 3;
2247
2248 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2249 sdvo->ddc_bus = 1 << num_bits;
2250 }
2251
2252 /**
2253 * Choose the appropriate DDC bus for control bus switch command for this
2254 * SDVO output based on the controlled output.
2255 *
2256 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2257 * outputs, then LVDS outputs.
2258 */
2259 static void
2260 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2261 struct intel_sdvo *sdvo)
2262 {
2263 struct sdvo_device_mapping *mapping;
2264
2265 if (sdvo->is_sdvob)
2266 mapping = &(dev_priv->sdvo_mappings[0]);
2267 else
2268 mapping = &(dev_priv->sdvo_mappings[1]);
2269
2270 if (mapping->initialized)
2271 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2272 else
2273 intel_sdvo_guess_ddc_bus(sdvo);
2274 }
2275
2276 static void
2277 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2278 struct intel_sdvo *sdvo)
2279 {
2280 struct sdvo_device_mapping *mapping;
2281 u8 pin;
2282
2283 if (sdvo->is_sdvob)
2284 mapping = &dev_priv->sdvo_mappings[0];
2285 else
2286 mapping = &dev_priv->sdvo_mappings[1];
2287
2288 if (mapping->initialized &&
2289 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2290 pin = mapping->i2c_pin;
2291 else
2292 pin = GMBUS_PIN_DPB;
2293
2294 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2295
2296 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2297 * our code totally fails once we start using gmbus. Hence fall back to
2298 * bit banging for now. */
2299 intel_gmbus_force_bit(sdvo->i2c, true);
2300 }
2301
2302 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2303 static void
2304 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2305 {
2306 intel_gmbus_force_bit(sdvo->i2c, false);
2307 }
2308
2309 static bool
2310 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2311 {
2312 return intel_sdvo_check_supp_encode(intel_sdvo);
2313 }
2314
2315 static u8
2316 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
2317 {
2318 struct drm_i915_private *dev_priv = dev->dev_private;
2319 struct sdvo_device_mapping *my_mapping, *other_mapping;
2320
2321 if (sdvo->is_sdvob) {
2322 my_mapping = &dev_priv->sdvo_mappings[0];
2323 other_mapping = &dev_priv->sdvo_mappings[1];
2324 } else {
2325 my_mapping = &dev_priv->sdvo_mappings[1];
2326 other_mapping = &dev_priv->sdvo_mappings[0];
2327 }
2328
2329 /* If the BIOS described our SDVO device, take advantage of it. */
2330 if (my_mapping->slave_addr)
2331 return my_mapping->slave_addr;
2332
2333 /* If the BIOS only described a different SDVO device, use the
2334 * address that it isn't using.
2335 */
2336 if (other_mapping->slave_addr) {
2337 if (other_mapping->slave_addr == 0x70)
2338 return 0x72;
2339 else
2340 return 0x70;
2341 }
2342
2343 /* No SDVO device info is found for another DVO port,
2344 * so use mapping assumption we had before BIOS parsing.
2345 */
2346 if (sdvo->is_sdvob)
2347 return 0x70;
2348 else
2349 return 0x72;
2350 }
2351
2352 static void
2353 intel_sdvo_connector_unregister(struct intel_connector *intel_connector)
2354 {
2355 struct drm_connector *drm_connector;
2356 struct intel_sdvo *sdvo_encoder;
2357
2358 drm_connector = &intel_connector->base;
2359 sdvo_encoder = intel_attached_sdvo(&intel_connector->base);
2360
2361 sysfs_remove_link(&drm_connector->kdev->kobj,
2362 sdvo_encoder->ddc.dev.kobj.name);
2363 intel_connector_unregister(intel_connector);
2364 }
2365
2366 static int
2367 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2368 struct intel_sdvo *encoder)
2369 {
2370 struct drm_connector *drm_connector;
2371 int ret;
2372
2373 drm_connector = &connector->base.base;
2374 ret = drm_connector_init(encoder->base.base.dev,
2375 drm_connector,
2376 &intel_sdvo_connector_funcs,
2377 connector->base.base.connector_type);
2378 if (ret < 0)
2379 return ret;
2380
2381 drm_connector_helper_add(drm_connector,
2382 &intel_sdvo_connector_helper_funcs);
2383
2384 connector->base.base.interlace_allowed = 1;
2385 connector->base.base.doublescan_allowed = 0;
2386 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2387 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2388 connector->base.unregister = intel_sdvo_connector_unregister;
2389
2390 intel_connector_attach_encoder(&connector->base, &encoder->base);
2391 ret = drm_connector_register(drm_connector);
2392 if (ret < 0)
2393 goto err1;
2394
2395 ret = sysfs_create_link(&drm_connector->kdev->kobj,
2396 &encoder->ddc.dev.kobj,
2397 encoder->ddc.dev.kobj.name);
2398 if (ret < 0)
2399 goto err2;
2400
2401 return 0;
2402
2403 err2:
2404 drm_connector_unregister(drm_connector);
2405 err1:
2406 drm_connector_cleanup(drm_connector);
2407
2408 return ret;
2409 }
2410
2411 static void
2412 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2413 struct intel_sdvo_connector *connector)
2414 {
2415 struct drm_device *dev = connector->base.base.dev;
2416
2417 intel_attach_force_audio_property(&connector->base.base);
2418 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
2419 intel_attach_broadcast_rgb_property(&connector->base.base);
2420 intel_sdvo->color_range_auto = true;
2421 }
2422 intel_attach_aspect_ratio_property(&connector->base.base);
2423 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2424 }
2425
2426 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2427 {
2428 struct intel_sdvo_connector *sdvo_connector;
2429
2430 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2431 if (!sdvo_connector)
2432 return NULL;
2433
2434 if (intel_connector_init(&sdvo_connector->base) < 0) {
2435 kfree(sdvo_connector);
2436 return NULL;
2437 }
2438
2439 return sdvo_connector;
2440 }
2441
2442 static bool
2443 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2444 {
2445 struct drm_encoder *encoder = &intel_sdvo->base.base;
2446 struct drm_connector *connector;
2447 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2448 struct intel_connector *intel_connector;
2449 struct intel_sdvo_connector *intel_sdvo_connector;
2450
2451 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2452
2453 intel_sdvo_connector = intel_sdvo_connector_alloc();
2454 if (!intel_sdvo_connector)
2455 return false;
2456
2457 if (device == 0) {
2458 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2459 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2460 } else if (device == 1) {
2461 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2462 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2463 }
2464
2465 intel_connector = &intel_sdvo_connector->base;
2466 connector = &intel_connector->base;
2467 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2468 intel_sdvo_connector->output_flag) {
2469 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2470 /* Some SDVO devices have one-shot hotplug interrupts.
2471 * Ensure that they get re-enabled when an interrupt happens.
2472 */
2473 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2474 intel_sdvo_enable_hotplug(intel_encoder);
2475 } else {
2476 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2477 }
2478 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2479 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2480
2481 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2482 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2483 intel_sdvo->is_hdmi = true;
2484 }
2485
2486 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2487 kfree(intel_sdvo_connector);
2488 return false;
2489 }
2490
2491 if (intel_sdvo->is_hdmi)
2492 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2493
2494 return true;
2495 }
2496
2497 static bool
2498 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2499 {
2500 struct drm_encoder *encoder = &intel_sdvo->base.base;
2501 struct drm_connector *connector;
2502 struct intel_connector *intel_connector;
2503 struct intel_sdvo_connector *intel_sdvo_connector;
2504
2505 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2506
2507 intel_sdvo_connector = intel_sdvo_connector_alloc();
2508 if (!intel_sdvo_connector)
2509 return false;
2510
2511 intel_connector = &intel_sdvo_connector->base;
2512 connector = &intel_connector->base;
2513 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2514 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2515
2516 intel_sdvo->controlled_output |= type;
2517 intel_sdvo_connector->output_flag = type;
2518
2519 intel_sdvo->is_tv = true;
2520
2521 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2522 kfree(intel_sdvo_connector);
2523 return false;
2524 }
2525
2526 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2527 goto err;
2528
2529 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2530 goto err;
2531
2532 return true;
2533
2534 err:
2535 drm_connector_unregister(connector);
2536 intel_sdvo_destroy(connector);
2537 return false;
2538 }
2539
2540 static bool
2541 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2542 {
2543 struct drm_encoder *encoder = &intel_sdvo->base.base;
2544 struct drm_connector *connector;
2545 struct intel_connector *intel_connector;
2546 struct intel_sdvo_connector *intel_sdvo_connector;
2547
2548 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2549
2550 intel_sdvo_connector = intel_sdvo_connector_alloc();
2551 if (!intel_sdvo_connector)
2552 return false;
2553
2554 intel_connector = &intel_sdvo_connector->base;
2555 connector = &intel_connector->base;
2556 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2557 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2558 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2559
2560 if (device == 0) {
2561 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2562 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2563 } else if (device == 1) {
2564 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2565 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2566 }
2567
2568 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2569 kfree(intel_sdvo_connector);
2570 return false;
2571 }
2572
2573 return true;
2574 }
2575
2576 static bool
2577 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2578 {
2579 struct drm_encoder *encoder = &intel_sdvo->base.base;
2580 struct drm_connector *connector;
2581 struct intel_connector *intel_connector;
2582 struct intel_sdvo_connector *intel_sdvo_connector;
2583
2584 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2585
2586 intel_sdvo_connector = intel_sdvo_connector_alloc();
2587 if (!intel_sdvo_connector)
2588 return false;
2589
2590 intel_connector = &intel_sdvo_connector->base;
2591 connector = &intel_connector->base;
2592 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2593 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2594
2595 if (device == 0) {
2596 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2597 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2598 } else if (device == 1) {
2599 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2600 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2601 }
2602
2603 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2604 kfree(intel_sdvo_connector);
2605 return false;
2606 }
2607
2608 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2609 goto err;
2610
2611 return true;
2612
2613 err:
2614 drm_connector_unregister(connector);
2615 intel_sdvo_destroy(connector);
2616 return false;
2617 }
2618
2619 static bool
2620 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2621 {
2622 intel_sdvo->is_tv = false;
2623 intel_sdvo->is_lvds = false;
2624
2625 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2626
2627 if (flags & SDVO_OUTPUT_TMDS0)
2628 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2629 return false;
2630
2631 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2632 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2633 return false;
2634
2635 /* TV has no XXX1 function block */
2636 if (flags & SDVO_OUTPUT_SVID0)
2637 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2638 return false;
2639
2640 if (flags & SDVO_OUTPUT_CVBS0)
2641 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2642 return false;
2643
2644 if (flags & SDVO_OUTPUT_YPRPB0)
2645 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2646 return false;
2647
2648 if (flags & SDVO_OUTPUT_RGB0)
2649 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2650 return false;
2651
2652 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2653 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2654 return false;
2655
2656 if (flags & SDVO_OUTPUT_LVDS0)
2657 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2658 return false;
2659
2660 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2661 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2662 return false;
2663
2664 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2665 unsigned char bytes[2];
2666
2667 intel_sdvo->controlled_output = 0;
2668 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2669 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2670 SDVO_NAME(intel_sdvo),
2671 bytes[0], bytes[1]);
2672 return false;
2673 }
2674 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2675
2676 return true;
2677 }
2678
2679 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2680 {
2681 struct drm_device *dev = intel_sdvo->base.base.dev;
2682 struct drm_connector *connector, *tmp;
2683
2684 list_for_each_entry_safe(connector, tmp,
2685 &dev->mode_config.connector_list, head) {
2686 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
2687 drm_connector_unregister(connector);
2688 intel_sdvo_destroy(connector);
2689 }
2690 }
2691 }
2692
2693 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2694 struct intel_sdvo_connector *intel_sdvo_connector,
2695 int type)
2696 {
2697 struct drm_device *dev = intel_sdvo->base.base.dev;
2698 struct intel_sdvo_tv_format format;
2699 uint32_t format_map, i;
2700
2701 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2702 return false;
2703
2704 BUILD_BUG_ON(sizeof(format) != 6);
2705 if (!intel_sdvo_get_value(intel_sdvo,
2706 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2707 &format, sizeof(format)))
2708 return false;
2709
2710 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2711
2712 if (format_map == 0)
2713 return false;
2714
2715 intel_sdvo_connector->format_supported_num = 0;
2716 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2717 if (format_map & (1 << i))
2718 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2719
2720
2721 intel_sdvo_connector->tv_format =
2722 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2723 "mode", intel_sdvo_connector->format_supported_num);
2724 if (!intel_sdvo_connector->tv_format)
2725 return false;
2726
2727 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2728 drm_property_add_enum(
2729 intel_sdvo_connector->tv_format, i,
2730 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2731
2732 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
2733 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2734 intel_sdvo_connector->tv_format, 0);
2735 return true;
2736
2737 }
2738
2739 #define ENHANCEMENT(name, NAME) do { \
2740 if (enhancements.name) { \
2741 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2742 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2743 return false; \
2744 intel_sdvo_connector->max_##name = data_value[0]; \
2745 intel_sdvo_connector->cur_##name = response; \
2746 intel_sdvo_connector->name = \
2747 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2748 if (!intel_sdvo_connector->name) return false; \
2749 drm_object_attach_property(&connector->base, \
2750 intel_sdvo_connector->name, \
2751 intel_sdvo_connector->cur_##name); \
2752 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2753 data_value[0], data_value[1], response); \
2754 } \
2755 } while (0)
2756
2757 static bool
2758 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2759 struct intel_sdvo_connector *intel_sdvo_connector,
2760 struct intel_sdvo_enhancements_reply enhancements)
2761 {
2762 struct drm_device *dev = intel_sdvo->base.base.dev;
2763 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2764 uint16_t response, data_value[2];
2765
2766 /* when horizontal overscan is supported, Add the left/right property */
2767 if (enhancements.overscan_h) {
2768 if (!intel_sdvo_get_value(intel_sdvo,
2769 SDVO_CMD_GET_MAX_OVERSCAN_H,
2770 &data_value, 4))
2771 return false;
2772
2773 if (!intel_sdvo_get_value(intel_sdvo,
2774 SDVO_CMD_GET_OVERSCAN_H,
2775 &response, 2))
2776 return false;
2777
2778 intel_sdvo_connector->max_hscan = data_value[0];
2779 intel_sdvo_connector->left_margin = data_value[0] - response;
2780 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2781 intel_sdvo_connector->left =
2782 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2783 if (!intel_sdvo_connector->left)
2784 return false;
2785
2786 drm_object_attach_property(&connector->base,
2787 intel_sdvo_connector->left,
2788 intel_sdvo_connector->left_margin);
2789
2790 intel_sdvo_connector->right =
2791 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2792 if (!intel_sdvo_connector->right)
2793 return false;
2794
2795 drm_object_attach_property(&connector->base,
2796 intel_sdvo_connector->right,
2797 intel_sdvo_connector->right_margin);
2798 DRM_DEBUG_KMS("h_overscan: max %d, "
2799 "default %d, current %d\n",
2800 data_value[0], data_value[1], response);
2801 }
2802
2803 if (enhancements.overscan_v) {
2804 if (!intel_sdvo_get_value(intel_sdvo,
2805 SDVO_CMD_GET_MAX_OVERSCAN_V,
2806 &data_value, 4))
2807 return false;
2808
2809 if (!intel_sdvo_get_value(intel_sdvo,
2810 SDVO_CMD_GET_OVERSCAN_V,
2811 &response, 2))
2812 return false;
2813
2814 intel_sdvo_connector->max_vscan = data_value[0];
2815 intel_sdvo_connector->top_margin = data_value[0] - response;
2816 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2817 intel_sdvo_connector->top =
2818 drm_property_create_range(dev, 0,
2819 "top_margin", 0, data_value[0]);
2820 if (!intel_sdvo_connector->top)
2821 return false;
2822
2823 drm_object_attach_property(&connector->base,
2824 intel_sdvo_connector->top,
2825 intel_sdvo_connector->top_margin);
2826
2827 intel_sdvo_connector->bottom =
2828 drm_property_create_range(dev, 0,
2829 "bottom_margin", 0, data_value[0]);
2830 if (!intel_sdvo_connector->bottom)
2831 return false;
2832
2833 drm_object_attach_property(&connector->base,
2834 intel_sdvo_connector->bottom,
2835 intel_sdvo_connector->bottom_margin);
2836 DRM_DEBUG_KMS("v_overscan: max %d, "
2837 "default %d, current %d\n",
2838 data_value[0], data_value[1], response);
2839 }
2840
2841 ENHANCEMENT(hpos, HPOS);
2842 ENHANCEMENT(vpos, VPOS);
2843 ENHANCEMENT(saturation, SATURATION);
2844 ENHANCEMENT(contrast, CONTRAST);
2845 ENHANCEMENT(hue, HUE);
2846 ENHANCEMENT(sharpness, SHARPNESS);
2847 ENHANCEMENT(brightness, BRIGHTNESS);
2848 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2849 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2850 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2851 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2852 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
2853
2854 if (enhancements.dot_crawl) {
2855 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2856 return false;
2857
2858 intel_sdvo_connector->max_dot_crawl = 1;
2859 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2860 intel_sdvo_connector->dot_crawl =
2861 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
2862 if (!intel_sdvo_connector->dot_crawl)
2863 return false;
2864
2865 drm_object_attach_property(&connector->base,
2866 intel_sdvo_connector->dot_crawl,
2867 intel_sdvo_connector->cur_dot_crawl);
2868 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2869 }
2870
2871 return true;
2872 }
2873
2874 static bool
2875 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2876 struct intel_sdvo_connector *intel_sdvo_connector,
2877 struct intel_sdvo_enhancements_reply enhancements)
2878 {
2879 struct drm_device *dev = intel_sdvo->base.base.dev;
2880 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2881 uint16_t response, data_value[2];
2882
2883 ENHANCEMENT(brightness, BRIGHTNESS);
2884
2885 return true;
2886 }
2887 #undef ENHANCEMENT
2888
2889 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2890 struct intel_sdvo_connector *intel_sdvo_connector)
2891 {
2892 union {
2893 struct intel_sdvo_enhancements_reply reply;
2894 uint16_t response;
2895 } enhancements;
2896
2897 BUILD_BUG_ON(sizeof(enhancements) != 2);
2898
2899 enhancements.response = 0;
2900 intel_sdvo_get_value(intel_sdvo,
2901 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2902 &enhancements, sizeof(enhancements));
2903 if (enhancements.response == 0) {
2904 DRM_DEBUG_KMS("No enhancement is supported\n");
2905 return true;
2906 }
2907
2908 if (IS_TV(intel_sdvo_connector))
2909 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2910 else if (IS_LVDS(intel_sdvo_connector))
2911 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2912 else
2913 return true;
2914 }
2915
2916 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2917 struct i2c_msg *msgs,
2918 int num)
2919 {
2920 struct intel_sdvo *sdvo = adapter->algo_data;
2921
2922 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2923 return -EIO;
2924
2925 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2926 }
2927
2928 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2929 {
2930 struct intel_sdvo *sdvo = adapter->algo_data;
2931 return sdvo->i2c->algo->functionality(sdvo->i2c);
2932 }
2933
2934 static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2935 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2936 .functionality = intel_sdvo_ddc_proxy_func
2937 };
2938
2939 static bool
2940 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2941 struct drm_device *dev)
2942 {
2943 sdvo->ddc.owner = THIS_MODULE;
2944 sdvo->ddc.class = I2C_CLASS_DDC;
2945 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2946 sdvo->ddc.dev.parent = &dev->pdev->dev;
2947 sdvo->ddc.algo_data = sdvo;
2948 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2949
2950 return i2c_add_adapter(&sdvo->ddc) == 0;
2951 }
2952
2953 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2954 {
2955 struct drm_i915_private *dev_priv = dev->dev_private;
2956 struct intel_encoder *intel_encoder;
2957 struct intel_sdvo *intel_sdvo;
2958 int i;
2959 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
2960 if (!intel_sdvo)
2961 return false;
2962
2963 intel_sdvo->sdvo_reg = sdvo_reg;
2964 intel_sdvo->is_sdvob = is_sdvob;
2965 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
2966 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
2967 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2968 goto err_i2c_bus;
2969
2970 /* encoder type will be decided later */
2971 intel_encoder = &intel_sdvo->base;
2972 intel_encoder->type = INTEL_OUTPUT_SDVO;
2973 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2974
2975 /* Read the regs to test if we can talk to the device */
2976 for (i = 0; i < 0x40; i++) {
2977 u8 byte;
2978
2979 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
2980 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2981 SDVO_NAME(intel_sdvo));
2982 goto err;
2983 }
2984 }
2985
2986 intel_encoder->compute_config = intel_sdvo_compute_config;
2987 if (HAS_PCH_SPLIT(dev)) {
2988 intel_encoder->disable = pch_disable_sdvo;
2989 intel_encoder->post_disable = pch_post_disable_sdvo;
2990 } else {
2991 intel_encoder->disable = intel_disable_sdvo;
2992 }
2993 intel_encoder->pre_enable = intel_sdvo_pre_enable;
2994 intel_encoder->enable = intel_enable_sdvo;
2995 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
2996 intel_encoder->get_config = intel_sdvo_get_config;
2997
2998 /* In default case sdvo lvds is false */
2999 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
3000 goto err;
3001
3002 if (intel_sdvo_output_setup(intel_sdvo,
3003 intel_sdvo->caps.output_flags) != true) {
3004 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3005 SDVO_NAME(intel_sdvo));
3006 /* Output_setup can leave behind connectors! */
3007 goto err_output;
3008 }
3009
3010 /* Only enable the hotplug irq if we need it, to work around noisy
3011 * hotplug lines.
3012 */
3013 if (intel_sdvo->hotplug_active) {
3014 intel_encoder->hpd_pin =
3015 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
3016 }
3017
3018 /*
3019 * Cloning SDVO with anything is often impossible, since the SDVO
3020 * encoder can request a special input timing mode. And even if that's
3021 * not the case we have evidence that cloning a plain unscaled mode with
3022 * VGA doesn't really work. Furthermore the cloning flags are way too
3023 * simplistic anyway to express such constraints, so just give up on
3024 * cloning for SDVO encoders.
3025 */
3026 intel_sdvo->base.cloneable = 0;
3027
3028 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
3029
3030 /* Set the input timing to the screen. Assume always input 0. */
3031 if (!intel_sdvo_set_target_input(intel_sdvo))
3032 goto err_output;
3033
3034 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3035 &intel_sdvo->pixel_clock_min,
3036 &intel_sdvo->pixel_clock_max))
3037 goto err_output;
3038
3039 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
3040 "clock range %dMHz - %dMHz, "
3041 "input 1: %c, input 2: %c, "
3042 "output 1: %c, output 2: %c\n",
3043 SDVO_NAME(intel_sdvo),
3044 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3045 intel_sdvo->caps.device_rev_id,
3046 intel_sdvo->pixel_clock_min / 1000,
3047 intel_sdvo->pixel_clock_max / 1000,
3048 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3049 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
3050 /* check currently supported outputs */
3051 intel_sdvo->caps.output_flags &
3052 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
3053 intel_sdvo->caps.output_flags &
3054 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
3055 return true;
3056
3057 err_output:
3058 intel_sdvo_output_cleanup(intel_sdvo);
3059
3060 err:
3061 drm_encoder_cleanup(&intel_encoder->base);
3062 i2c_del_adapter(&intel_sdvo->ddc);
3063 err_i2c_bus:
3064 intel_sdvo_unselect_i2c_bus(intel_sdvo);
3065 kfree(intel_sdvo);
3066
3067 return false;
3068 }
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