]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/i915/intel_sdvo.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:


c14c05e8a5437b1417e4556670dfb566ced20c70
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/export.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_sdvo_regs.h"
40
41 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
44 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
45
46 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
47 SDVO_TV_MASK)
48
49 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
50 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
51 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
52 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
53 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
54
55
56 static const char * const tv_format_names[] = {
57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64 };
65
66 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
67
68 struct intel_sdvo {
69 struct intel_encoder base;
70
71 struct i2c_adapter *i2c;
72 u8 slave_addr;
73
74 struct i2c_adapter ddc;
75
76 /* Register for the SDVO device: SDVOB or SDVOC */
77 i915_reg_t sdvo_reg;
78
79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
81
82 /*
83 * Capabilities of the SDVO device returned by
84 * intel_sdvo_get_capabilities()
85 */
86 struct intel_sdvo_caps caps;
87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
89 int pixel_clock_min, pixel_clock_max;
90
91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
97 /*
98 * Hotplug activation bits for this device
99 */
100 uint16_t hotplug_active;
101
102 /**
103 * This is set if we're going to treat the device as TV-out.
104 *
105 * While we have these nice friendly flags for output types that ought
106 * to decide this for us, the S-Video output on our HDMI+S-Video card
107 * shows up as RGB1 (VGA).
108 */
109 bool is_tv;
110
111 enum port port;
112
113 /**
114 * This is set if we treat the device as HDMI, instead of DVI.
115 */
116 bool is_hdmi;
117 bool has_hdmi_monitor;
118 bool has_hdmi_audio;
119 bool rgb_quant_range_selectable;
120
121 /**
122 * This is set if we detect output of sdvo device as LVDS and
123 * have a valid fixed mode to use with the panel.
124 */
125 bool is_lvds;
126
127 /**
128 * This is sdvo fixed pannel mode pointer
129 */
130 struct drm_display_mode *sdvo_lvds_fixed_mode;
131
132 /* DDC bus used by this SDVO encoder */
133 uint8_t ddc_bus;
134
135 /*
136 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
137 */
138 uint8_t dtd_sdvo_flags;
139 };
140
141 struct intel_sdvo_connector {
142 struct intel_connector base;
143
144 /* Mark the type of connector */
145 uint16_t output_flag;
146
147 /* This contains all current supported TV format */
148 u8 tv_format_supported[TV_FORMAT_NUM];
149 int format_supported_num;
150 struct drm_property *tv_format;
151
152 /* add the property for the SDVO-TV */
153 struct drm_property *left;
154 struct drm_property *right;
155 struct drm_property *top;
156 struct drm_property *bottom;
157 struct drm_property *hpos;
158 struct drm_property *vpos;
159 struct drm_property *contrast;
160 struct drm_property *saturation;
161 struct drm_property *hue;
162 struct drm_property *sharpness;
163 struct drm_property *flicker_filter;
164 struct drm_property *flicker_filter_adaptive;
165 struct drm_property *flicker_filter_2d;
166 struct drm_property *tv_chroma_filter;
167 struct drm_property *tv_luma_filter;
168 struct drm_property *dot_crawl;
169
170 /* add the property for the SDVO-TV/LVDS */
171 struct drm_property *brightness;
172
173 /* this is to get the range of margin.*/
174 u32 max_hscan, max_vscan;
175 };
176
177 struct intel_sdvo_connector_state {
178 /* base.base: tv.saturation/contrast/hue/brightness */
179 struct intel_digital_connector_state base;
180
181 struct {
182 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
183 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
184 unsigned chroma_filter, luma_filter, dot_crawl;
185 } tv;
186 };
187
188 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
189 {
190 return container_of(encoder, struct intel_sdvo, base);
191 }
192
193 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
194 {
195 return to_sdvo(intel_attached_encoder(connector));
196 }
197
198 static struct intel_sdvo_connector *
199 to_intel_sdvo_connector(struct drm_connector *connector)
200 {
201 return container_of(connector, struct intel_sdvo_connector, base.base);
202 }
203
204 static struct intel_sdvo_connector_state *
205 to_intel_sdvo_connector_state(struct drm_connector_state *conn_state)
206 {
207 return container_of(conn_state, struct intel_sdvo_connector_state, base.base);
208 }
209
210 static bool
211 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
212 static bool
213 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
214 struct intel_sdvo_connector *intel_sdvo_connector,
215 int type);
216 static bool
217 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
218 struct intel_sdvo_connector *intel_sdvo_connector);
219
220 /**
221 * Writes the SDVOB or SDVOC with the given value, but always writes both
222 * SDVOB and SDVOC to work around apparent hardware issues (according to
223 * comments in the BIOS).
224 */
225 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
226 {
227 struct drm_device *dev = intel_sdvo->base.base.dev;
228 struct drm_i915_private *dev_priv = to_i915(dev);
229 u32 bval = val, cval = val;
230 int i;
231
232 if (HAS_PCH_SPLIT(dev_priv)) {
233 I915_WRITE(intel_sdvo->sdvo_reg, val);
234 POSTING_READ(intel_sdvo->sdvo_reg);
235 /*
236 * HW workaround, need to write this twice for issue
237 * that may result in first write getting masked.
238 */
239 if (HAS_PCH_IBX(dev_priv)) {
240 I915_WRITE(intel_sdvo->sdvo_reg, val);
241 POSTING_READ(intel_sdvo->sdvo_reg);
242 }
243 return;
244 }
245
246 if (intel_sdvo->port == PORT_B)
247 cval = I915_READ(GEN3_SDVOC);
248 else
249 bval = I915_READ(GEN3_SDVOB);
250
251 /*
252 * Write the registers twice for luck. Sometimes,
253 * writing them only once doesn't appear to 'stick'.
254 * The BIOS does this too. Yay, magic
255 */
256 for (i = 0; i < 2; i++)
257 {
258 I915_WRITE(GEN3_SDVOB, bval);
259 POSTING_READ(GEN3_SDVOB);
260 I915_WRITE(GEN3_SDVOC, cval);
261 POSTING_READ(GEN3_SDVOC);
262 }
263 }
264
265 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
266 {
267 struct i2c_msg msgs[] = {
268 {
269 .addr = intel_sdvo->slave_addr,
270 .flags = 0,
271 .len = 1,
272 .buf = &addr,
273 },
274 {
275 .addr = intel_sdvo->slave_addr,
276 .flags = I2C_M_RD,
277 .len = 1,
278 .buf = ch,
279 }
280 };
281 int ret;
282
283 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
284 return true;
285
286 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
287 return false;
288 }
289
290 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
291 /** Mapping of command numbers to names, for debug output */
292 static const struct _sdvo_cmd_name {
293 u8 cmd;
294 const char *name;
295 } __attribute__ ((packed)) sdvo_cmd_names[] = {
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
339
340 /* Add the op code for SDVO enhancements */
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
385
386 /* HDMI op code */
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
407 };
408
409 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
410
411 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
412 const void *args, int args_len)
413 {
414 int i, pos = 0;
415 #define BUF_LEN 256
416 char buffer[BUF_LEN];
417
418 #define BUF_PRINT(args...) \
419 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
420
421
422 for (i = 0; i < args_len; i++) {
423 BUF_PRINT("%02X ", ((u8 *)args)[i]);
424 }
425 for (; i < 8; i++) {
426 BUF_PRINT(" ");
427 }
428 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
429 if (cmd == sdvo_cmd_names[i].cmd) {
430 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
431 break;
432 }
433 }
434 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
435 BUF_PRINT("(%02X)", cmd);
436 }
437 BUG_ON(pos >= BUF_LEN - 1);
438 #undef BUF_PRINT
439 #undef BUF_LEN
440
441 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
442 }
443
444 static const char * const cmd_status_names[] = {
445 "Power on",
446 "Success",
447 "Not supported",
448 "Invalid arg",
449 "Pending",
450 "Target not specified",
451 "Scaling not supported"
452 };
453
454 static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
455 const void *args, int args_len,
456 bool unlocked)
457 {
458 u8 *buf, status;
459 struct i2c_msg *msgs;
460 int i, ret = true;
461
462 /* Would be simpler to allocate both in one go ? */
463 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
464 if (!buf)
465 return false;
466
467 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
468 if (!msgs) {
469 kfree(buf);
470 return false;
471 }
472
473 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
474
475 for (i = 0; i < args_len; i++) {
476 msgs[i].addr = intel_sdvo->slave_addr;
477 msgs[i].flags = 0;
478 msgs[i].len = 2;
479 msgs[i].buf = buf + 2 *i;
480 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
481 buf[2*i + 1] = ((u8*)args)[i];
482 }
483 msgs[i].addr = intel_sdvo->slave_addr;
484 msgs[i].flags = 0;
485 msgs[i].len = 2;
486 msgs[i].buf = buf + 2*i;
487 buf[2*i + 0] = SDVO_I2C_OPCODE;
488 buf[2*i + 1] = cmd;
489
490 /* the following two are to read the response */
491 status = SDVO_I2C_CMD_STATUS;
492 msgs[i+1].addr = intel_sdvo->slave_addr;
493 msgs[i+1].flags = 0;
494 msgs[i+1].len = 1;
495 msgs[i+1].buf = &status;
496
497 msgs[i+2].addr = intel_sdvo->slave_addr;
498 msgs[i+2].flags = I2C_M_RD;
499 msgs[i+2].len = 1;
500 msgs[i+2].buf = &status;
501
502 if (unlocked)
503 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
504 else
505 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
506 if (ret < 0) {
507 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
508 ret = false;
509 goto out;
510 }
511 if (ret != i+3) {
512 /* failure in I2C transfer */
513 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
514 ret = false;
515 }
516
517 out:
518 kfree(msgs);
519 kfree(buf);
520 return ret;
521 }
522
523 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
524 const void *args, int args_len)
525 {
526 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
527 }
528
529 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
530 void *response, int response_len)
531 {
532 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
533 u8 status;
534 int i, pos = 0;
535 #define BUF_LEN 256
536 char buffer[BUF_LEN];
537
538
539 /*
540 * The documentation states that all commands will be
541 * processed within 15µs, and that we need only poll
542 * the status byte a maximum of 3 times in order for the
543 * command to be complete.
544 *
545 * Check 5 times in case the hardware failed to read the docs.
546 *
547 * Also beware that the first response by many devices is to
548 * reply PENDING and stall for time. TVs are notorious for
549 * requiring longer than specified to complete their replies.
550 * Originally (in the DDX long ago), the delay was only ever 15ms
551 * with an additional delay of 30ms applied for TVs added later after
552 * many experiments. To accommodate both sets of delays, we do a
553 * sequence of slow checks if the device is falling behind and fails
554 * to reply within 5*15µs.
555 */
556 if (!intel_sdvo_read_byte(intel_sdvo,
557 SDVO_I2C_CMD_STATUS,
558 &status))
559 goto log_fail;
560
561 while ((status == SDVO_CMD_STATUS_PENDING ||
562 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
563 if (retry < 10)
564 msleep(15);
565 else
566 udelay(15);
567
568 if (!intel_sdvo_read_byte(intel_sdvo,
569 SDVO_I2C_CMD_STATUS,
570 &status))
571 goto log_fail;
572 }
573
574 #define BUF_PRINT(args...) \
575 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
576
577 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
578 BUF_PRINT("(%s)", cmd_status_names[status]);
579 else
580 BUF_PRINT("(??? %d)", status);
581
582 if (status != SDVO_CMD_STATUS_SUCCESS)
583 goto log_fail;
584
585 /* Read the command response */
586 for (i = 0; i < response_len; i++) {
587 if (!intel_sdvo_read_byte(intel_sdvo,
588 SDVO_I2C_RETURN_0 + i,
589 &((u8 *)response)[i]))
590 goto log_fail;
591 BUF_PRINT(" %02X", ((u8 *)response)[i]);
592 }
593 BUG_ON(pos >= BUF_LEN - 1);
594 #undef BUF_PRINT
595 #undef BUF_LEN
596
597 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
598 return true;
599
600 log_fail:
601 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
602 return false;
603 }
604
605 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
606 {
607 if (adjusted_mode->crtc_clock >= 100000)
608 return 1;
609 else if (adjusted_mode->crtc_clock >= 50000)
610 return 2;
611 else
612 return 4;
613 }
614
615 static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
616 u8 ddc_bus)
617 {
618 /* This must be the immediately preceding write before the i2c xfer */
619 return __intel_sdvo_write_cmd(intel_sdvo,
620 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
621 &ddc_bus, 1, false);
622 }
623
624 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
625 {
626 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
627 return false;
628
629 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
630 }
631
632 static bool
633 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
634 {
635 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
636 return false;
637
638 return intel_sdvo_read_response(intel_sdvo, value, len);
639 }
640
641 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
642 {
643 struct intel_sdvo_set_target_input_args targets = {0};
644 return intel_sdvo_set_value(intel_sdvo,
645 SDVO_CMD_SET_TARGET_INPUT,
646 &targets, sizeof(targets));
647 }
648
649 /**
650 * Return whether each input is trained.
651 *
652 * This function is making an assumption about the layout of the response,
653 * which should be checked against the docs.
654 */
655 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
656 {
657 struct intel_sdvo_get_trained_inputs_response response;
658
659 BUILD_BUG_ON(sizeof(response) != 1);
660 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
661 &response, sizeof(response)))
662 return false;
663
664 *input_1 = response.input0_trained;
665 *input_2 = response.input1_trained;
666 return true;
667 }
668
669 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
670 u16 outputs)
671 {
672 return intel_sdvo_set_value(intel_sdvo,
673 SDVO_CMD_SET_ACTIVE_OUTPUTS,
674 &outputs, sizeof(outputs));
675 }
676
677 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
678 u16 *outputs)
679 {
680 return intel_sdvo_get_value(intel_sdvo,
681 SDVO_CMD_GET_ACTIVE_OUTPUTS,
682 outputs, sizeof(*outputs));
683 }
684
685 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
686 int mode)
687 {
688 u8 state = SDVO_ENCODER_STATE_ON;
689
690 switch (mode) {
691 case DRM_MODE_DPMS_ON:
692 state = SDVO_ENCODER_STATE_ON;
693 break;
694 case DRM_MODE_DPMS_STANDBY:
695 state = SDVO_ENCODER_STATE_STANDBY;
696 break;
697 case DRM_MODE_DPMS_SUSPEND:
698 state = SDVO_ENCODER_STATE_SUSPEND;
699 break;
700 case DRM_MODE_DPMS_OFF:
701 state = SDVO_ENCODER_STATE_OFF;
702 break;
703 }
704
705 return intel_sdvo_set_value(intel_sdvo,
706 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
707 }
708
709 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
710 int *clock_min,
711 int *clock_max)
712 {
713 struct intel_sdvo_pixel_clock_range clocks;
714
715 BUILD_BUG_ON(sizeof(clocks) != 4);
716 if (!intel_sdvo_get_value(intel_sdvo,
717 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
718 &clocks, sizeof(clocks)))
719 return false;
720
721 /* Convert the values from units of 10 kHz to kHz. */
722 *clock_min = clocks.min * 10;
723 *clock_max = clocks.max * 10;
724 return true;
725 }
726
727 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
728 u16 outputs)
729 {
730 return intel_sdvo_set_value(intel_sdvo,
731 SDVO_CMD_SET_TARGET_OUTPUT,
732 &outputs, sizeof(outputs));
733 }
734
735 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
736 struct intel_sdvo_dtd *dtd)
737 {
738 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
739 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
740 }
741
742 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
743 struct intel_sdvo_dtd *dtd)
744 {
745 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
746 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
747 }
748
749 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
750 struct intel_sdvo_dtd *dtd)
751 {
752 return intel_sdvo_set_timing(intel_sdvo,
753 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
754 }
755
756 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
757 struct intel_sdvo_dtd *dtd)
758 {
759 return intel_sdvo_set_timing(intel_sdvo,
760 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
761 }
762
763 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
764 struct intel_sdvo_dtd *dtd)
765 {
766 return intel_sdvo_get_timing(intel_sdvo,
767 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
768 }
769
770 static bool
771 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
772 uint16_t clock,
773 uint16_t width,
774 uint16_t height)
775 {
776 struct intel_sdvo_preferred_input_timing_args args;
777
778 memset(&args, 0, sizeof(args));
779 args.clock = clock;
780 args.width = width;
781 args.height = height;
782 args.interlace = 0;
783
784 if (intel_sdvo->is_lvds &&
785 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
786 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
787 args.scaled = 1;
788
789 return intel_sdvo_set_value(intel_sdvo,
790 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
791 &args, sizeof(args));
792 }
793
794 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
795 struct intel_sdvo_dtd *dtd)
796 {
797 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
798 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
799 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
800 &dtd->part1, sizeof(dtd->part1)) &&
801 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
802 &dtd->part2, sizeof(dtd->part2));
803 }
804
805 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
806 {
807 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
808 }
809
810 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
811 const struct drm_display_mode *mode)
812 {
813 uint16_t width, height;
814 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
815 uint16_t h_sync_offset, v_sync_offset;
816 int mode_clock;
817
818 memset(dtd, 0, sizeof(*dtd));
819
820 width = mode->hdisplay;
821 height = mode->vdisplay;
822
823 /* do some mode translations */
824 h_blank_len = mode->htotal - mode->hdisplay;
825 h_sync_len = mode->hsync_end - mode->hsync_start;
826
827 v_blank_len = mode->vtotal - mode->vdisplay;
828 v_sync_len = mode->vsync_end - mode->vsync_start;
829
830 h_sync_offset = mode->hsync_start - mode->hdisplay;
831 v_sync_offset = mode->vsync_start - mode->vdisplay;
832
833 mode_clock = mode->clock;
834 mode_clock /= 10;
835 dtd->part1.clock = mode_clock;
836
837 dtd->part1.h_active = width & 0xff;
838 dtd->part1.h_blank = h_blank_len & 0xff;
839 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
840 ((h_blank_len >> 8) & 0xf);
841 dtd->part1.v_active = height & 0xff;
842 dtd->part1.v_blank = v_blank_len & 0xff;
843 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
844 ((v_blank_len >> 8) & 0xf);
845
846 dtd->part2.h_sync_off = h_sync_offset & 0xff;
847 dtd->part2.h_sync_width = h_sync_len & 0xff;
848 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
849 (v_sync_len & 0xf);
850 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
851 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
852 ((v_sync_len & 0x30) >> 4);
853
854 dtd->part2.dtd_flags = 0x18;
855 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
856 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
857 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
858 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
859 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
860 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
861
862 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
863 }
864
865 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
866 const struct intel_sdvo_dtd *dtd)
867 {
868 struct drm_display_mode mode = {};
869
870 mode.hdisplay = dtd->part1.h_active;
871 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
872 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
873 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
874 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
875 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
876 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
877 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
878
879 mode.vdisplay = dtd->part1.v_active;
880 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
881 mode.vsync_start = mode.vdisplay;
882 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
883 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
884 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
885 mode.vsync_end = mode.vsync_start +
886 (dtd->part2.v_sync_off_width & 0xf);
887 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
888 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
889 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
890
891 mode.clock = dtd->part1.clock * 10;
892
893 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
894 mode.flags |= DRM_MODE_FLAG_INTERLACE;
895 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
896 mode.flags |= DRM_MODE_FLAG_PHSYNC;
897 else
898 mode.flags |= DRM_MODE_FLAG_NHSYNC;
899 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
900 mode.flags |= DRM_MODE_FLAG_PVSYNC;
901 else
902 mode.flags |= DRM_MODE_FLAG_NVSYNC;
903
904 drm_mode_set_crtcinfo(&mode, 0);
905
906 drm_mode_copy(pmode, &mode);
907 }
908
909 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
910 {
911 struct intel_sdvo_encode encode;
912
913 BUILD_BUG_ON(sizeof(encode) != 2);
914 return intel_sdvo_get_value(intel_sdvo,
915 SDVO_CMD_GET_SUPP_ENCODE,
916 &encode, sizeof(encode));
917 }
918
919 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
920 uint8_t mode)
921 {
922 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
923 }
924
925 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
926 uint8_t mode)
927 {
928 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
929 }
930
931 #if 0
932 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
933 {
934 int i, j;
935 uint8_t set_buf_index[2];
936 uint8_t av_split;
937 uint8_t buf_size;
938 uint8_t buf[48];
939 uint8_t *pos;
940
941 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
942
943 for (i = 0; i <= av_split; i++) {
944 set_buf_index[0] = i; set_buf_index[1] = 0;
945 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
946 set_buf_index, 2);
947 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
948 intel_sdvo_read_response(encoder, &buf_size, 1);
949
950 pos = buf;
951 for (j = 0; j <= buf_size; j += 8) {
952 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
953 NULL, 0);
954 intel_sdvo_read_response(encoder, pos, 8);
955 pos += 8;
956 }
957 }
958 }
959 #endif
960
961 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
962 unsigned if_index, uint8_t tx_rate,
963 const uint8_t *data, unsigned length)
964 {
965 uint8_t set_buf_index[2] = { if_index, 0 };
966 uint8_t hbuf_size, tmp[8];
967 int i;
968
969 if (!intel_sdvo_set_value(intel_sdvo,
970 SDVO_CMD_SET_HBUF_INDEX,
971 set_buf_index, 2))
972 return false;
973
974 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
975 &hbuf_size, 1))
976 return false;
977
978 /* Buffer size is 0 based, hooray! */
979 hbuf_size++;
980
981 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
982 if_index, length, hbuf_size);
983
984 for (i = 0; i < hbuf_size; i += 8) {
985 memset(tmp, 0, 8);
986 if (i < length)
987 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
988
989 if (!intel_sdvo_set_value(intel_sdvo,
990 SDVO_CMD_SET_HBUF_DATA,
991 tmp, 8))
992 return false;
993 }
994
995 return intel_sdvo_set_value(intel_sdvo,
996 SDVO_CMD_SET_HBUF_TXRATE,
997 &tx_rate, 1);
998 }
999
1000 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1001 struct intel_crtc_state *pipe_config)
1002 {
1003 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1004 union hdmi_infoframe frame;
1005 int ret;
1006 ssize_t len;
1007
1008 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
1009 &pipe_config->base.adjusted_mode,
1010 false);
1011 if (ret < 0) {
1012 DRM_ERROR("couldn't fill AVI infoframe\n");
1013 return false;
1014 }
1015
1016 if (intel_sdvo->rgb_quant_range_selectable) {
1017 if (pipe_config->limited_color_range)
1018 frame.avi.quantization_range =
1019 HDMI_QUANTIZATION_RANGE_LIMITED;
1020 else
1021 frame.avi.quantization_range =
1022 HDMI_QUANTIZATION_RANGE_FULL;
1023 }
1024
1025 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1026 if (len < 0)
1027 return false;
1028
1029 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1030 SDVO_HBUF_TX_VSYNC,
1031 sdvo_data, sizeof(sdvo_data));
1032 }
1033
1034 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1035 struct drm_connector_state *conn_state)
1036 {
1037 struct intel_sdvo_tv_format format;
1038 uint32_t format_map;
1039
1040 format_map = 1 << conn_state->tv.mode;
1041 memset(&format, 0, sizeof(format));
1042 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1043
1044 BUILD_BUG_ON(sizeof(format) != 6);
1045 return intel_sdvo_set_value(intel_sdvo,
1046 SDVO_CMD_SET_TV_FORMAT,
1047 &format, sizeof(format));
1048 }
1049
1050 static bool
1051 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1052 const struct drm_display_mode *mode)
1053 {
1054 struct intel_sdvo_dtd output_dtd;
1055
1056 if (!intel_sdvo_set_target_output(intel_sdvo,
1057 intel_sdvo->attached_output))
1058 return false;
1059
1060 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1061 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1062 return false;
1063
1064 return true;
1065 }
1066
1067 /* Asks the sdvo controller for the preferred input mode given the output mode.
1068 * Unfortunately we have to set up the full output mode to do that. */
1069 static bool
1070 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1071 const struct drm_display_mode *mode,
1072 struct drm_display_mode *adjusted_mode)
1073 {
1074 struct intel_sdvo_dtd input_dtd;
1075
1076 /* Reset the input timing to the screen. Assume always input 0. */
1077 if (!intel_sdvo_set_target_input(intel_sdvo))
1078 return false;
1079
1080 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1081 mode->clock / 10,
1082 mode->hdisplay,
1083 mode->vdisplay))
1084 return false;
1085
1086 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1087 &input_dtd))
1088 return false;
1089
1090 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1091 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1092
1093 return true;
1094 }
1095
1096 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1097 {
1098 unsigned dotclock = pipe_config->port_clock;
1099 struct dpll *clock = &pipe_config->dpll;
1100
1101 /* SDVO TV has fixed PLL values depend on its clock range,
1102 this mirrors vbios setting. */
1103 if (dotclock >= 100000 && dotclock < 140500) {
1104 clock->p1 = 2;
1105 clock->p2 = 10;
1106 clock->n = 3;
1107 clock->m1 = 16;
1108 clock->m2 = 8;
1109 } else if (dotclock >= 140500 && dotclock <= 200000) {
1110 clock->p1 = 1;
1111 clock->p2 = 10;
1112 clock->n = 6;
1113 clock->m1 = 12;
1114 clock->m2 = 8;
1115 } else {
1116 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1117 }
1118
1119 pipe_config->clock_set = true;
1120 }
1121
1122 static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1123 struct intel_crtc_state *pipe_config,
1124 struct drm_connector_state *conn_state)
1125 {
1126 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1127 struct intel_sdvo_connector_state *intel_sdvo_state =
1128 to_intel_sdvo_connector_state(conn_state);
1129 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1130 struct drm_display_mode *mode = &pipe_config->base.mode;
1131
1132 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1133 pipe_config->pipe_bpp = 8*3;
1134
1135 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
1136 pipe_config->has_pch_encoder = true;
1137
1138 /* We need to construct preferred input timings based on our
1139 * output timings. To do that, we have to set the output
1140 * timings, even though this isn't really the right place in
1141 * the sequence to do it. Oh well.
1142 */
1143 if (intel_sdvo->is_tv) {
1144 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1145 return false;
1146
1147 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1148 mode,
1149 adjusted_mode);
1150 pipe_config->sdvo_tv_clock = true;
1151 } else if (intel_sdvo->is_lvds) {
1152 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1153 intel_sdvo->sdvo_lvds_fixed_mode))
1154 return false;
1155
1156 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1157 mode,
1158 adjusted_mode);
1159 }
1160
1161 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1162 * SDVO device will factor out the multiplier during mode_set.
1163 */
1164 pipe_config->pixel_multiplier =
1165 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1166
1167 if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI)
1168 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1169
1170 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON ||
1171 (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio))
1172 pipe_config->has_audio = true;
1173
1174 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1175 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1176 /* FIXME: This bit is only valid when using TMDS encoding and 8
1177 * bit per color mode. */
1178 if (pipe_config->has_hdmi_sink &&
1179 drm_match_cea_mode(adjusted_mode) > 1)
1180 pipe_config->limited_color_range = true;
1181 } else {
1182 if (pipe_config->has_hdmi_sink &&
1183 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED)
1184 pipe_config->limited_color_range = true;
1185 }
1186
1187 /* Clock computation needs to happen after pixel multiplier. */
1188 if (intel_sdvo->is_tv)
1189 i9xx_adjust_sdvo_tv_clock(pipe_config);
1190
1191 /* Set user selected PAR to incoming mode's member */
1192 if (intel_sdvo->is_hdmi)
1193 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1194
1195 return true;
1196 }
1197
1198 #define UPDATE_PROPERTY(input, NAME) \
1199 do { \
1200 val = input; \
1201 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1202 } while (0)
1203
1204 static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1205 struct intel_sdvo_connector_state *sdvo_state)
1206 {
1207 struct drm_connector_state *conn_state = &sdvo_state->base.base;
1208 struct intel_sdvo_connector *intel_sdvo_conn =
1209 to_intel_sdvo_connector(conn_state->connector);
1210 uint16_t val;
1211
1212 if (intel_sdvo_conn->left)
1213 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1214
1215 if (intel_sdvo_conn->top)
1216 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1217
1218 if (intel_sdvo_conn->hpos)
1219 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1220
1221 if (intel_sdvo_conn->vpos)
1222 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1223
1224 if (intel_sdvo_conn->saturation)
1225 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1226
1227 if (intel_sdvo_conn->contrast)
1228 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1229
1230 if (intel_sdvo_conn->hue)
1231 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1232
1233 if (intel_sdvo_conn->brightness)
1234 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1235
1236 if (intel_sdvo_conn->sharpness)
1237 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1238
1239 if (intel_sdvo_conn->flicker_filter)
1240 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1241
1242 if (intel_sdvo_conn->flicker_filter_2d)
1243 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1244
1245 if (intel_sdvo_conn->flicker_filter_adaptive)
1246 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1247
1248 if (intel_sdvo_conn->tv_chroma_filter)
1249 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1250
1251 if (intel_sdvo_conn->tv_luma_filter)
1252 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1253
1254 if (intel_sdvo_conn->dot_crawl)
1255 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1256
1257 #undef UPDATE_PROPERTY
1258 }
1259
1260 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
1261 struct intel_crtc_state *crtc_state,
1262 struct drm_connector_state *conn_state)
1263 {
1264 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1266 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1267 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(conn_state);
1268 struct drm_display_mode *mode = &crtc_state->base.mode;
1269 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1270 u32 sdvox;
1271 struct intel_sdvo_in_out_map in_out;
1272 struct intel_sdvo_dtd input_dtd, output_dtd;
1273 int rate;
1274
1275 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1276
1277 /* First, set the input mapping for the first input to our controlled
1278 * output. This is only correct if we're a single-input device, in
1279 * which case the first input is the output from the appropriate SDVO
1280 * channel on the motherboard. In a two-input device, the first input
1281 * will be SDVOB and the second SDVOC.
1282 */
1283 in_out.in0 = intel_sdvo->attached_output;
1284 in_out.in1 = 0;
1285
1286 intel_sdvo_set_value(intel_sdvo,
1287 SDVO_CMD_SET_IN_OUT_MAP,
1288 &in_out, sizeof(in_out));
1289
1290 /* Set the output timings to the screen */
1291 if (!intel_sdvo_set_target_output(intel_sdvo,
1292 intel_sdvo->attached_output))
1293 return;
1294
1295 /* lvds has a special fixed output timing. */
1296 if (intel_sdvo->is_lvds)
1297 intel_sdvo_get_dtd_from_mode(&output_dtd,
1298 intel_sdvo->sdvo_lvds_fixed_mode);
1299 else
1300 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1301 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1302 DRM_INFO("Setting output timings on %s failed\n",
1303 SDVO_NAME(intel_sdvo));
1304
1305 /* Set the input timing to the screen. Assume always input 0. */
1306 if (!intel_sdvo_set_target_input(intel_sdvo))
1307 return;
1308
1309 if (crtc_state->has_hdmi_sink) {
1310 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1311 intel_sdvo_set_colorimetry(intel_sdvo,
1312 SDVO_COLORIMETRY_RGB256);
1313 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
1314 } else
1315 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1316
1317 if (intel_sdvo->is_tv &&
1318 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
1319 return;
1320
1321 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1322
1323 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1324 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1325 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1326 DRM_INFO("Setting input timings on %s failed\n",
1327 SDVO_NAME(intel_sdvo));
1328
1329 switch (crtc_state->pixel_multiplier) {
1330 default:
1331 WARN(1, "unknown pixel multiplier specified\n");
1332 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1333 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1334 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1335 }
1336 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1337 return;
1338
1339 /* Set the SDVO control regs. */
1340 if (INTEL_GEN(dev_priv) >= 4) {
1341 /* The real mode polarity is set by the SDVO commands, using
1342 * struct intel_sdvo_dtd. */
1343 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1344 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1345 sdvox |= HDMI_COLOR_RANGE_16_235;
1346 if (INTEL_GEN(dev_priv) < 5)
1347 sdvox |= SDVO_BORDER_ENABLE;
1348 } else {
1349 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1350 if (intel_sdvo->port == PORT_B)
1351 sdvox &= SDVOB_PRESERVE_MASK;
1352 else
1353 sdvox &= SDVOC_PRESERVE_MASK;
1354 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1355 }
1356
1357 if (HAS_PCH_CPT(dev_priv))
1358 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1359 else
1360 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1361
1362 if (crtc_state->has_audio)
1363 sdvox |= SDVO_AUDIO_ENABLE;
1364
1365 if (INTEL_GEN(dev_priv) >= 4) {
1366 /* done in crtc_mode_set as the dpll_md reg must be written early */
1367 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1368 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1369 /* done in crtc_mode_set as it lives inside the dpll register */
1370 } else {
1371 sdvox |= (crtc_state->pixel_multiplier - 1)
1372 << SDVO_PORT_MULTIPLY_SHIFT;
1373 }
1374
1375 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1376 INTEL_GEN(dev_priv) < 5)
1377 sdvox |= SDVO_STALL_SELECT;
1378 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1379 }
1380
1381 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1382 {
1383 struct intel_sdvo_connector *intel_sdvo_connector =
1384 to_intel_sdvo_connector(&connector->base);
1385 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1386 u16 active_outputs = 0;
1387
1388 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1389
1390 if (active_outputs & intel_sdvo_connector->output_flag)
1391 return true;
1392 else
1393 return false;
1394 }
1395
1396 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1397 enum pipe *pipe)
1398 {
1399 struct drm_device *dev = encoder->base.dev;
1400 struct drm_i915_private *dev_priv = to_i915(dev);
1401 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1402 u16 active_outputs = 0;
1403 u32 tmp;
1404
1405 tmp = I915_READ(intel_sdvo->sdvo_reg);
1406 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1407
1408 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
1409 return false;
1410
1411 if (HAS_PCH_CPT(dev_priv))
1412 *pipe = PORT_TO_PIPE_CPT(tmp);
1413 else
1414 *pipe = PORT_TO_PIPE(tmp);
1415
1416 return true;
1417 }
1418
1419 static void intel_sdvo_get_config(struct intel_encoder *encoder,
1420 struct intel_crtc_state *pipe_config)
1421 {
1422 struct drm_device *dev = encoder->base.dev;
1423 struct drm_i915_private *dev_priv = to_i915(dev);
1424 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1425 struct intel_sdvo_dtd dtd;
1426 int encoder_pixel_multiplier = 0;
1427 int dotclock;
1428 u32 flags = 0, sdvox;
1429 u8 val;
1430 bool ret;
1431
1432 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1433
1434 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1435 if (!ret) {
1436 /* Some sdvo encoders are not spec compliant and don't
1437 * implement the mandatory get_timings function. */
1438 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1439 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1440 } else {
1441 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1442 flags |= DRM_MODE_FLAG_PHSYNC;
1443 else
1444 flags |= DRM_MODE_FLAG_NHSYNC;
1445
1446 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1447 flags |= DRM_MODE_FLAG_PVSYNC;
1448 else
1449 flags |= DRM_MODE_FLAG_NVSYNC;
1450 }
1451
1452 pipe_config->base.adjusted_mode.flags |= flags;
1453
1454 /*
1455 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1456 * the sdvo port register, on all other platforms it is part of the dpll
1457 * state. Since the general pipe state readout happens before the
1458 * encoder->get_config we so already have a valid pixel multplier on all
1459 * other platfroms.
1460 */
1461 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
1462 pipe_config->pixel_multiplier =
1463 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1464 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1465 }
1466
1467 dotclock = pipe_config->port_clock;
1468
1469 if (pipe_config->pixel_multiplier)
1470 dotclock /= pipe_config->pixel_multiplier;
1471
1472 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1473
1474 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1475 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1476 &val, 1)) {
1477 switch (val) {
1478 case SDVO_CLOCK_RATE_MULT_1X:
1479 encoder_pixel_multiplier = 1;
1480 break;
1481 case SDVO_CLOCK_RATE_MULT_2X:
1482 encoder_pixel_multiplier = 2;
1483 break;
1484 case SDVO_CLOCK_RATE_MULT_4X:
1485 encoder_pixel_multiplier = 4;
1486 break;
1487 }
1488 }
1489
1490 if (sdvox & HDMI_COLOR_RANGE_16_235)
1491 pipe_config->limited_color_range = true;
1492
1493 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1494 &val, 1)) {
1495 if (val == SDVO_ENCODE_HDMI)
1496 pipe_config->has_hdmi_sink = true;
1497 }
1498
1499 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1500 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1501 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1502 }
1503
1504 static void intel_disable_sdvo(struct intel_encoder *encoder,
1505 struct intel_crtc_state *old_crtc_state,
1506 struct drm_connector_state *conn_state)
1507 {
1508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1509 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1510 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1511 u32 temp;
1512
1513 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1514 if (0)
1515 intel_sdvo_set_encoder_power_state(intel_sdvo,
1516 DRM_MODE_DPMS_OFF);
1517
1518 temp = I915_READ(intel_sdvo->sdvo_reg);
1519
1520 temp &= ~SDVO_ENABLE;
1521 intel_sdvo_write_sdvox(intel_sdvo, temp);
1522
1523 /*
1524 * HW workaround for IBX, we need to move the port
1525 * to transcoder A after disabling it to allow the
1526 * matching DP port to be enabled on transcoder A.
1527 */
1528 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1529 /*
1530 * We get CPU/PCH FIFO underruns on the other pipe when
1531 * doing the workaround. Sweep them under the rug.
1532 */
1533 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1534 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1535
1536 temp &= ~SDVO_PIPE_B_SELECT;
1537 temp |= SDVO_ENABLE;
1538 intel_sdvo_write_sdvox(intel_sdvo, temp);
1539
1540 temp &= ~SDVO_ENABLE;
1541 intel_sdvo_write_sdvox(intel_sdvo, temp);
1542
1543 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1544 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1545 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1546 }
1547 }
1548
1549 static void pch_disable_sdvo(struct intel_encoder *encoder,
1550 struct intel_crtc_state *old_crtc_state,
1551 struct drm_connector_state *old_conn_state)
1552 {
1553 }
1554
1555 static void pch_post_disable_sdvo(struct intel_encoder *encoder,
1556 struct intel_crtc_state *old_crtc_state,
1557 struct drm_connector_state *old_conn_state)
1558 {
1559 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
1560 }
1561
1562 static void intel_enable_sdvo(struct intel_encoder *encoder,
1563 struct intel_crtc_state *pipe_config,
1564 struct drm_connector_state *conn_state)
1565 {
1566 struct drm_device *dev = encoder->base.dev;
1567 struct drm_i915_private *dev_priv = to_i915(dev);
1568 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1569 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1570 u32 temp;
1571 bool input1, input2;
1572 int i;
1573 bool success;
1574
1575 temp = I915_READ(intel_sdvo->sdvo_reg);
1576 temp |= SDVO_ENABLE;
1577 intel_sdvo_write_sdvox(intel_sdvo, temp);
1578
1579 for (i = 0; i < 2; i++)
1580 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
1581
1582 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1583 /* Warn if the device reported failure to sync.
1584 * A lot of SDVO devices fail to notify of sync, but it's
1585 * a given it the status is a success, we succeeded.
1586 */
1587 if (success && !input1) {
1588 DRM_DEBUG_KMS("First %s output reported failure to "
1589 "sync\n", SDVO_NAME(intel_sdvo));
1590 }
1591
1592 if (0)
1593 intel_sdvo_set_encoder_power_state(intel_sdvo,
1594 DRM_MODE_DPMS_ON);
1595 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1596 }
1597
1598 static enum drm_mode_status
1599 intel_sdvo_mode_valid(struct drm_connector *connector,
1600 struct drm_display_mode *mode)
1601 {
1602 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1603 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1604
1605 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1606 return MODE_NO_DBLESCAN;
1607
1608 if (intel_sdvo->pixel_clock_min > mode->clock)
1609 return MODE_CLOCK_LOW;
1610
1611 if (intel_sdvo->pixel_clock_max < mode->clock)
1612 return MODE_CLOCK_HIGH;
1613
1614 if (mode->clock > max_dotclk)
1615 return MODE_CLOCK_HIGH;
1616
1617 if (intel_sdvo->is_lvds) {
1618 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1619 return MODE_PANEL;
1620
1621 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1622 return MODE_PANEL;
1623 }
1624
1625 return MODE_OK;
1626 }
1627
1628 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1629 {
1630 BUILD_BUG_ON(sizeof(*caps) != 8);
1631 if (!intel_sdvo_get_value(intel_sdvo,
1632 SDVO_CMD_GET_DEVICE_CAPS,
1633 caps, sizeof(*caps)))
1634 return false;
1635
1636 DRM_DEBUG_KMS("SDVO capabilities:\n"
1637 " vendor_id: %d\n"
1638 " device_id: %d\n"
1639 " device_rev_id: %d\n"
1640 " sdvo_version_major: %d\n"
1641 " sdvo_version_minor: %d\n"
1642 " sdvo_inputs_mask: %d\n"
1643 " smooth_scaling: %d\n"
1644 " sharp_scaling: %d\n"
1645 " up_scaling: %d\n"
1646 " down_scaling: %d\n"
1647 " stall_support: %d\n"
1648 " output_flags: %d\n",
1649 caps->vendor_id,
1650 caps->device_id,
1651 caps->device_rev_id,
1652 caps->sdvo_version_major,
1653 caps->sdvo_version_minor,
1654 caps->sdvo_inputs_mask,
1655 caps->smooth_scaling,
1656 caps->sharp_scaling,
1657 caps->up_scaling,
1658 caps->down_scaling,
1659 caps->stall_support,
1660 caps->output_flags);
1661
1662 return true;
1663 }
1664
1665 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1666 {
1667 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1668 uint16_t hotplug;
1669
1670 if (!I915_HAS_HOTPLUG(dev_priv))
1671 return 0;
1672
1673 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1674 * on the line. */
1675 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1676 return 0;
1677
1678 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1679 &hotplug, sizeof(hotplug)))
1680 return 0;
1681
1682 return hotplug;
1683 }
1684
1685 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1686 {
1687 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1688
1689 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1690 &intel_sdvo->hotplug_active, 2);
1691 }
1692
1693 static bool
1694 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1695 {
1696 /* Is there more than one type of output? */
1697 return hweight16(intel_sdvo->caps.output_flags) > 1;
1698 }
1699
1700 static struct edid *
1701 intel_sdvo_get_edid(struct drm_connector *connector)
1702 {
1703 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1704 return drm_get_edid(connector, &sdvo->ddc);
1705 }
1706
1707 /* Mac mini hack -- use the same DDC as the analog connector */
1708 static struct edid *
1709 intel_sdvo_get_analog_edid(struct drm_connector *connector)
1710 {
1711 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1712
1713 return drm_get_edid(connector,
1714 intel_gmbus_get_adapter(dev_priv,
1715 dev_priv->vbt.crt_ddc_pin));
1716 }
1717
1718 static enum drm_connector_status
1719 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
1720 {
1721 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1722 enum drm_connector_status status;
1723 struct edid *edid;
1724
1725 edid = intel_sdvo_get_edid(connector);
1726
1727 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1728 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
1729
1730 /*
1731 * Don't use the 1 as the argument of DDC bus switch to get
1732 * the EDID. It is used for SDVO SPD ROM.
1733 */
1734 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1735 intel_sdvo->ddc_bus = ddc;
1736 edid = intel_sdvo_get_edid(connector);
1737 if (edid)
1738 break;
1739 }
1740 /*
1741 * If we found the EDID on the other bus,
1742 * assume that is the correct DDC bus.
1743 */
1744 if (edid == NULL)
1745 intel_sdvo->ddc_bus = saved_ddc;
1746 }
1747
1748 /*
1749 * When there is no edid and no monitor is connected with VGA
1750 * port, try to use the CRT ddc to read the EDID for DVI-connector.
1751 */
1752 if (edid == NULL)
1753 edid = intel_sdvo_get_analog_edid(connector);
1754
1755 status = connector_status_unknown;
1756 if (edid != NULL) {
1757 /* DDC bus is shared, match EDID to connector type */
1758 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1759 status = connector_status_connected;
1760 if (intel_sdvo->is_hdmi) {
1761 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1762 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1763 intel_sdvo->rgb_quant_range_selectable =
1764 drm_rgb_quant_range_selectable(edid);
1765 }
1766 } else
1767 status = connector_status_disconnected;
1768 kfree(edid);
1769 }
1770
1771 return status;
1772 }
1773
1774 static bool
1775 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1776 struct edid *edid)
1777 {
1778 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1779 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1780
1781 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1782 connector_is_digital, monitor_is_digital);
1783 return connector_is_digital == monitor_is_digital;
1784 }
1785
1786 static enum drm_connector_status
1787 intel_sdvo_detect(struct drm_connector *connector, bool force)
1788 {
1789 uint16_t response;
1790 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1791 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1792 enum drm_connector_status ret;
1793
1794 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1795 connector->base.id, connector->name);
1796
1797 if (!intel_sdvo_get_value(intel_sdvo,
1798 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1799 &response, 2))
1800 return connector_status_unknown;
1801
1802 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1803 response & 0xff, response >> 8,
1804 intel_sdvo_connector->output_flag);
1805
1806 if (response == 0)
1807 return connector_status_disconnected;
1808
1809 intel_sdvo->attached_output = response;
1810
1811 intel_sdvo->has_hdmi_monitor = false;
1812 intel_sdvo->has_hdmi_audio = false;
1813 intel_sdvo->rgb_quant_range_selectable = false;
1814
1815 if ((intel_sdvo_connector->output_flag & response) == 0)
1816 ret = connector_status_disconnected;
1817 else if (IS_TMDS(intel_sdvo_connector))
1818 ret = intel_sdvo_tmds_sink_detect(connector);
1819 else {
1820 struct edid *edid;
1821
1822 /* if we have an edid check it matches the connection */
1823 edid = intel_sdvo_get_edid(connector);
1824 if (edid == NULL)
1825 edid = intel_sdvo_get_analog_edid(connector);
1826 if (edid != NULL) {
1827 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1828 edid))
1829 ret = connector_status_connected;
1830 else
1831 ret = connector_status_disconnected;
1832
1833 kfree(edid);
1834 } else
1835 ret = connector_status_connected;
1836 }
1837
1838 /* May update encoder flag for like clock for SDVO TV, etc.*/
1839 if (ret == connector_status_connected) {
1840 intel_sdvo->is_tv = false;
1841 intel_sdvo->is_lvds = false;
1842
1843 if (response & SDVO_TV_MASK)
1844 intel_sdvo->is_tv = true;
1845 if (response & SDVO_LVDS_MASK)
1846 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1847 }
1848
1849 return ret;
1850 }
1851
1852 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1853 {
1854 struct edid *edid;
1855
1856 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1857 connector->base.id, connector->name);
1858
1859 /* set the bus switch and get the modes */
1860 edid = intel_sdvo_get_edid(connector);
1861
1862 /*
1863 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1864 * link between analog and digital outputs. So, if the regular SDVO
1865 * DDC fails, check to see if the analog output is disconnected, in
1866 * which case we'll look there for the digital DDC data.
1867 */
1868 if (edid == NULL)
1869 edid = intel_sdvo_get_analog_edid(connector);
1870
1871 if (edid != NULL) {
1872 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1873 edid)) {
1874 drm_mode_connector_update_edid_property(connector, edid);
1875 drm_add_edid_modes(connector, edid);
1876 }
1877
1878 kfree(edid);
1879 }
1880 }
1881
1882 /*
1883 * Set of SDVO TV modes.
1884 * Note! This is in reply order (see loop in get_tv_modes).
1885 * XXX: all 60Hz refresh?
1886 */
1887 static const struct drm_display_mode sdvo_tv_modes[] = {
1888 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1889 416, 0, 200, 201, 232, 233, 0,
1890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1891 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1892 416, 0, 240, 241, 272, 273, 0,
1893 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1894 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1895 496, 0, 300, 301, 332, 333, 0,
1896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1897 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1898 736, 0, 350, 351, 382, 383, 0,
1899 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1900 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1901 736, 0, 400, 401, 432, 433, 0,
1902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1903 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1904 736, 0, 480, 481, 512, 513, 0,
1905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1906 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1907 800, 0, 480, 481, 512, 513, 0,
1908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1909 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1910 800, 0, 576, 577, 608, 609, 0,
1911 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1912 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1913 816, 0, 350, 351, 382, 383, 0,
1914 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1915 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1916 816, 0, 400, 401, 432, 433, 0,
1917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1918 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1919 816, 0, 480, 481, 512, 513, 0,
1920 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1921 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1922 816, 0, 540, 541, 572, 573, 0,
1923 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1924 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1925 816, 0, 576, 577, 608, 609, 0,
1926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1927 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1928 864, 0, 576, 577, 608, 609, 0,
1929 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1930 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1931 896, 0, 600, 601, 632, 633, 0,
1932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1933 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1934 928, 0, 624, 625, 656, 657, 0,
1935 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1936 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1937 1016, 0, 766, 767, 798, 799, 0,
1938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1939 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1940 1120, 0, 768, 769, 800, 801, 0,
1941 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1942 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1943 1376, 0, 1024, 1025, 1056, 1057, 0,
1944 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1945 };
1946
1947 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1948 {
1949 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1950 const struct drm_connector_state *conn_state = connector->state;
1951 struct intel_sdvo_sdtv_resolution_request tv_res;
1952 uint32_t reply = 0, format_map = 0;
1953 int i;
1954
1955 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1956 connector->base.id, connector->name);
1957
1958 /* Read the list of supported input resolutions for the selected TV
1959 * format.
1960 */
1961 format_map = 1 << conn_state->tv.mode;
1962 memcpy(&tv_res, &format_map,
1963 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
1964
1965 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1966 return;
1967
1968 BUILD_BUG_ON(sizeof(tv_res) != 3);
1969 if (!intel_sdvo_write_cmd(intel_sdvo,
1970 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1971 &tv_res, sizeof(tv_res)))
1972 return;
1973 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
1974 return;
1975
1976 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1977 if (reply & (1 << i)) {
1978 struct drm_display_mode *nmode;
1979 nmode = drm_mode_duplicate(connector->dev,
1980 &sdvo_tv_modes[i]);
1981 if (nmode)
1982 drm_mode_probed_add(connector, nmode);
1983 }
1984 }
1985
1986 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1987 {
1988 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1989 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1990 struct drm_display_mode *newmode;
1991
1992 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1993 connector->base.id, connector->name);
1994
1995 /*
1996 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
1997 * SDVO->LVDS transcoders can't cope with the EDID mode.
1998 */
1999 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
2000 newmode = drm_mode_duplicate(connector->dev,
2001 dev_priv->vbt.sdvo_lvds_vbt_mode);
2002 if (newmode != NULL) {
2003 /* Guarantee the mode is preferred */
2004 newmode->type = (DRM_MODE_TYPE_PREFERRED |
2005 DRM_MODE_TYPE_DRIVER);
2006 drm_mode_probed_add(connector, newmode);
2007 }
2008 }
2009
2010 /*
2011 * Attempt to get the mode list from DDC.
2012 * Assume that the preferred modes are
2013 * arranged in priority order.
2014 */
2015 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2016
2017 list_for_each_entry(newmode, &connector->probed_modes, head) {
2018 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
2019 intel_sdvo->sdvo_lvds_fixed_mode =
2020 drm_mode_duplicate(connector->dev, newmode);
2021
2022 intel_sdvo->is_lvds = true;
2023 break;
2024 }
2025 }
2026 }
2027
2028 static int intel_sdvo_get_modes(struct drm_connector *connector)
2029 {
2030 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2031
2032 if (IS_TV(intel_sdvo_connector))
2033 intel_sdvo_get_tv_modes(connector);
2034 else if (IS_LVDS(intel_sdvo_connector))
2035 intel_sdvo_get_lvds_modes(connector);
2036 else
2037 intel_sdvo_get_ddc_modes(connector);
2038
2039 return !list_empty(&connector->probed_modes);
2040 }
2041
2042 static void intel_sdvo_destroy(struct drm_connector *connector)
2043 {
2044 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2045
2046 drm_connector_cleanup(connector);
2047 kfree(intel_sdvo_connector);
2048 }
2049
2050 static int
2051 intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2052 const struct drm_connector_state *state,
2053 struct drm_property *property,
2054 uint64_t *val)
2055 {
2056 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2057 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
2058
2059 if (property == intel_sdvo_connector->tv_format) {
2060 int i;
2061
2062 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2063 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2064 *val = i;
2065
2066 return 0;
2067 }
2068
2069 WARN_ON(1);
2070 *val = 0;
2071 } else if (property == intel_sdvo_connector->top ||
2072 property == intel_sdvo_connector->bottom)
2073 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2074 else if (property == intel_sdvo_connector->left ||
2075 property == intel_sdvo_connector->right)
2076 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2077 else if (property == intel_sdvo_connector->hpos)
2078 *val = sdvo_state->tv.hpos;
2079 else if (property == intel_sdvo_connector->vpos)
2080 *val = sdvo_state->tv.vpos;
2081 else if (property == intel_sdvo_connector->saturation)
2082 *val = state->tv.saturation;
2083 else if (property == intel_sdvo_connector->contrast)
2084 *val = state->tv.contrast;
2085 else if (property == intel_sdvo_connector->hue)
2086 *val = state->tv.hue;
2087 else if (property == intel_sdvo_connector->brightness)
2088 *val = state->tv.brightness;
2089 else if (property == intel_sdvo_connector->sharpness)
2090 *val = sdvo_state->tv.sharpness;
2091 else if (property == intel_sdvo_connector->flicker_filter)
2092 *val = sdvo_state->tv.flicker_filter;
2093 else if (property == intel_sdvo_connector->flicker_filter_2d)
2094 *val = sdvo_state->tv.flicker_filter_2d;
2095 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2096 *val = sdvo_state->tv.flicker_filter_adaptive;
2097 else if (property == intel_sdvo_connector->tv_chroma_filter)
2098 *val = sdvo_state->tv.chroma_filter;
2099 else if (property == intel_sdvo_connector->tv_luma_filter)
2100 *val = sdvo_state->tv.luma_filter;
2101 else if (property == intel_sdvo_connector->dot_crawl)
2102 *val = sdvo_state->tv.dot_crawl;
2103 else
2104 return intel_digital_connector_atomic_get_property(connector, state, property, val);
2105
2106 return 0;
2107 }
2108
2109 static int
2110 intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2111 struct drm_connector_state *state,
2112 struct drm_property *property,
2113 uint64_t val)
2114 {
2115 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2116 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
2117
2118 if (property == intel_sdvo_connector->tv_format) {
2119 state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
2120
2121 if (state->crtc) {
2122 struct drm_crtc_state *crtc_state =
2123 drm_atomic_get_new_crtc_state(state->state, state->crtc);
2124
2125 crtc_state->connectors_changed = true;
2126 }
2127 } else if (property == intel_sdvo_connector->top ||
2128 property == intel_sdvo_connector->bottom)
2129 /* Cannot set these independent from each other */
2130 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2131 else if (property == intel_sdvo_connector->left ||
2132 property == intel_sdvo_connector->right)
2133 /* Cannot set these independent from each other */
2134 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2135 else if (property == intel_sdvo_connector->hpos)
2136 sdvo_state->tv.hpos = val;
2137 else if (property == intel_sdvo_connector->vpos)
2138 sdvo_state->tv.vpos = val;
2139 else if (property == intel_sdvo_connector->saturation)
2140 state->tv.saturation = val;
2141 else if (property == intel_sdvo_connector->contrast)
2142 state->tv.contrast = val;
2143 else if (property == intel_sdvo_connector->hue)
2144 state->tv.hue = val;
2145 else if (property == intel_sdvo_connector->brightness)
2146 state->tv.brightness = val;
2147 else if (property == intel_sdvo_connector->sharpness)
2148 sdvo_state->tv.sharpness = val;
2149 else if (property == intel_sdvo_connector->flicker_filter)
2150 sdvo_state->tv.flicker_filter = val;
2151 else if (property == intel_sdvo_connector->flicker_filter_2d)
2152 sdvo_state->tv.flicker_filter_2d = val;
2153 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2154 sdvo_state->tv.flicker_filter_adaptive = val;
2155 else if (property == intel_sdvo_connector->tv_chroma_filter)
2156 sdvo_state->tv.chroma_filter = val;
2157 else if (property == intel_sdvo_connector->tv_luma_filter)
2158 sdvo_state->tv.luma_filter = val;
2159 else if (property == intel_sdvo_connector->dot_crawl)
2160 sdvo_state->tv.dot_crawl = val;
2161 else
2162 return intel_digital_connector_atomic_set_property(connector, state, property, val);
2163
2164 return 0;
2165 }
2166
2167 static int
2168 intel_sdvo_connector_register(struct drm_connector *connector)
2169 {
2170 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2171 int ret;
2172
2173 ret = intel_connector_register(connector);
2174 if (ret)
2175 return ret;
2176
2177 return sysfs_create_link(&connector->kdev->kobj,
2178 &sdvo->ddc.dev.kobj,
2179 sdvo->ddc.dev.kobj.name);
2180 }
2181
2182 static void
2183 intel_sdvo_connector_unregister(struct drm_connector *connector)
2184 {
2185 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2186
2187 sysfs_remove_link(&connector->kdev->kobj,
2188 sdvo->ddc.dev.kobj.name);
2189 intel_connector_unregister(connector);
2190 }
2191
2192 static struct drm_connector_state *
2193 intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2194 {
2195 struct intel_sdvo_connector_state *state;
2196
2197 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2198 if (!state)
2199 return NULL;
2200
2201 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2202 return &state->base.base;
2203 }
2204
2205 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2206 .dpms = drm_atomic_helper_connector_dpms,
2207 .detect = intel_sdvo_detect,
2208 .fill_modes = drm_helper_probe_single_connector_modes,
2209 .set_property = drm_atomic_helper_connector_set_property,
2210 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2211 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
2212 .late_register = intel_sdvo_connector_register,
2213 .early_unregister = intel_sdvo_connector_unregister,
2214 .destroy = intel_sdvo_destroy,
2215 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2216 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
2217 };
2218
2219 static int intel_sdvo_atomic_check(struct drm_connector *conn,
2220 struct drm_connector_state *new_conn_state)
2221 {
2222 struct drm_atomic_state *state = new_conn_state->state;
2223 struct drm_connector_state *old_conn_state =
2224 drm_atomic_get_old_connector_state(state, conn);
2225 struct intel_sdvo_connector_state *old_state =
2226 to_intel_sdvo_connector_state(old_conn_state);
2227 struct intel_sdvo_connector_state *new_state =
2228 to_intel_sdvo_connector_state(new_conn_state);
2229
2230 if (new_conn_state->crtc &&
2231 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2232 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2233 struct drm_crtc_state *crtc_state =
2234 drm_atomic_get_new_crtc_state(new_conn_state->state,
2235 new_conn_state->crtc);
2236
2237 crtc_state->connectors_changed = true;
2238 }
2239
2240 return intel_digital_connector_atomic_check(conn, new_conn_state);
2241 }
2242
2243 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2244 .get_modes = intel_sdvo_get_modes,
2245 .mode_valid = intel_sdvo_mode_valid,
2246 .atomic_check = intel_sdvo_atomic_check,
2247 };
2248
2249 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2250 {
2251 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2252
2253 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
2254 drm_mode_destroy(encoder->dev,
2255 intel_sdvo->sdvo_lvds_fixed_mode);
2256
2257 i2c_del_adapter(&intel_sdvo->ddc);
2258 intel_encoder_destroy(encoder);
2259 }
2260
2261 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2262 .destroy = intel_sdvo_enc_destroy,
2263 };
2264
2265 static void
2266 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2267 {
2268 uint16_t mask = 0;
2269 unsigned int num_bits;
2270
2271 /* Make a mask of outputs less than or equal to our own priority in the
2272 * list.
2273 */
2274 switch (sdvo->controlled_output) {
2275 case SDVO_OUTPUT_LVDS1:
2276 mask |= SDVO_OUTPUT_LVDS1;
2277 case SDVO_OUTPUT_LVDS0:
2278 mask |= SDVO_OUTPUT_LVDS0;
2279 case SDVO_OUTPUT_TMDS1:
2280 mask |= SDVO_OUTPUT_TMDS1;
2281 case SDVO_OUTPUT_TMDS0:
2282 mask |= SDVO_OUTPUT_TMDS0;
2283 case SDVO_OUTPUT_RGB1:
2284 mask |= SDVO_OUTPUT_RGB1;
2285 case SDVO_OUTPUT_RGB0:
2286 mask |= SDVO_OUTPUT_RGB0;
2287 break;
2288 }
2289
2290 /* Count bits to find what number we are in the priority list. */
2291 mask &= sdvo->caps.output_flags;
2292 num_bits = hweight16(mask);
2293 /* If more than 3 outputs, default to DDC bus 3 for now. */
2294 if (num_bits > 3)
2295 num_bits = 3;
2296
2297 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2298 sdvo->ddc_bus = 1 << num_bits;
2299 }
2300
2301 /**
2302 * Choose the appropriate DDC bus for control bus switch command for this
2303 * SDVO output based on the controlled output.
2304 *
2305 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2306 * outputs, then LVDS outputs.
2307 */
2308 static void
2309 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2310 struct intel_sdvo *sdvo)
2311 {
2312 struct sdvo_device_mapping *mapping;
2313
2314 if (sdvo->port == PORT_B)
2315 mapping = &dev_priv->vbt.sdvo_mappings[0];
2316 else
2317 mapping = &dev_priv->vbt.sdvo_mappings[1];
2318
2319 if (mapping->initialized)
2320 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2321 else
2322 intel_sdvo_guess_ddc_bus(sdvo);
2323 }
2324
2325 static void
2326 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2327 struct intel_sdvo *sdvo)
2328 {
2329 struct sdvo_device_mapping *mapping;
2330 u8 pin;
2331
2332 if (sdvo->port == PORT_B)
2333 mapping = &dev_priv->vbt.sdvo_mappings[0];
2334 else
2335 mapping = &dev_priv->vbt.sdvo_mappings[1];
2336
2337 if (mapping->initialized &&
2338 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2339 pin = mapping->i2c_pin;
2340 else
2341 pin = GMBUS_PIN_DPB;
2342
2343 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2344
2345 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2346 * our code totally fails once we start using gmbus. Hence fall back to
2347 * bit banging for now. */
2348 intel_gmbus_force_bit(sdvo->i2c, true);
2349 }
2350
2351 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2352 static void
2353 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2354 {
2355 intel_gmbus_force_bit(sdvo->i2c, false);
2356 }
2357
2358 static bool
2359 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2360 {
2361 return intel_sdvo_check_supp_encode(intel_sdvo);
2362 }
2363
2364 static u8
2365 intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2366 struct intel_sdvo *sdvo)
2367 {
2368 struct sdvo_device_mapping *my_mapping, *other_mapping;
2369
2370 if (sdvo->port == PORT_B) {
2371 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2372 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
2373 } else {
2374 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2375 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
2376 }
2377
2378 /* If the BIOS described our SDVO device, take advantage of it. */
2379 if (my_mapping->slave_addr)
2380 return my_mapping->slave_addr;
2381
2382 /* If the BIOS only described a different SDVO device, use the
2383 * address that it isn't using.
2384 */
2385 if (other_mapping->slave_addr) {
2386 if (other_mapping->slave_addr == 0x70)
2387 return 0x72;
2388 else
2389 return 0x70;
2390 }
2391
2392 /* No SDVO device info is found for another DVO port,
2393 * so use mapping assumption we had before BIOS parsing.
2394 */
2395 if (sdvo->port == PORT_B)
2396 return 0x70;
2397 else
2398 return 0x72;
2399 }
2400
2401 static int
2402 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2403 struct intel_sdvo *encoder)
2404 {
2405 struct drm_connector *drm_connector;
2406 int ret;
2407
2408 drm_connector = &connector->base.base;
2409 ret = drm_connector_init(encoder->base.base.dev,
2410 drm_connector,
2411 &intel_sdvo_connector_funcs,
2412 connector->base.base.connector_type);
2413 if (ret < 0)
2414 return ret;
2415
2416 drm_connector_helper_add(drm_connector,
2417 &intel_sdvo_connector_helper_funcs);
2418
2419 connector->base.base.interlace_allowed = 1;
2420 connector->base.base.doublescan_allowed = 0;
2421 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2422 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2423
2424 intel_connector_attach_encoder(&connector->base, &encoder->base);
2425
2426 return 0;
2427 }
2428
2429 static void
2430 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2431 struct intel_sdvo_connector *connector)
2432 {
2433 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
2434
2435 intel_attach_force_audio_property(&connector->base.base);
2436 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
2437 intel_attach_broadcast_rgb_property(&connector->base.base);
2438 }
2439 intel_attach_aspect_ratio_property(&connector->base.base);
2440 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2441 }
2442
2443 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2444 {
2445 struct intel_sdvo_connector *sdvo_connector;
2446 struct intel_sdvo_connector_state *conn_state;
2447
2448 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2449 if (!sdvo_connector)
2450 return NULL;
2451
2452 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2453 if (!conn_state) {
2454 kfree(sdvo_connector);
2455 return NULL;
2456 }
2457
2458 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2459 &conn_state->base.base);
2460
2461 return sdvo_connector;
2462 }
2463
2464 static bool
2465 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2466 {
2467 struct drm_encoder *encoder = &intel_sdvo->base.base;
2468 struct drm_connector *connector;
2469 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2470 struct intel_connector *intel_connector;
2471 struct intel_sdvo_connector *intel_sdvo_connector;
2472
2473 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2474
2475 intel_sdvo_connector = intel_sdvo_connector_alloc();
2476 if (!intel_sdvo_connector)
2477 return false;
2478
2479 if (device == 0) {
2480 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2481 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2482 } else if (device == 1) {
2483 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2484 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2485 }
2486
2487 intel_connector = &intel_sdvo_connector->base;
2488 connector = &intel_connector->base;
2489 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2490 intel_sdvo_connector->output_flag) {
2491 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2492 /* Some SDVO devices have one-shot hotplug interrupts.
2493 * Ensure that they get re-enabled when an interrupt happens.
2494 */
2495 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2496 intel_sdvo_enable_hotplug(intel_encoder);
2497 } else {
2498 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2499 }
2500 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2501 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2502
2503 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2504 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2505 intel_sdvo->is_hdmi = true;
2506 }
2507
2508 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2509 kfree(intel_sdvo_connector);
2510 return false;
2511 }
2512
2513 if (intel_sdvo->is_hdmi)
2514 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2515
2516 return true;
2517 }
2518
2519 static bool
2520 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2521 {
2522 struct drm_encoder *encoder = &intel_sdvo->base.base;
2523 struct drm_connector *connector;
2524 struct intel_connector *intel_connector;
2525 struct intel_sdvo_connector *intel_sdvo_connector;
2526
2527 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2528
2529 intel_sdvo_connector = intel_sdvo_connector_alloc();
2530 if (!intel_sdvo_connector)
2531 return false;
2532
2533 intel_connector = &intel_sdvo_connector->base;
2534 connector = &intel_connector->base;
2535 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2536 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2537
2538 intel_sdvo->controlled_output |= type;
2539 intel_sdvo_connector->output_flag = type;
2540
2541 intel_sdvo->is_tv = true;
2542
2543 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2544 kfree(intel_sdvo_connector);
2545 return false;
2546 }
2547
2548 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2549 goto err;
2550
2551 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2552 goto err;
2553
2554 return true;
2555
2556 err:
2557 intel_sdvo_destroy(connector);
2558 return false;
2559 }
2560
2561 static bool
2562 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2563 {
2564 struct drm_encoder *encoder = &intel_sdvo->base.base;
2565 struct drm_connector *connector;
2566 struct intel_connector *intel_connector;
2567 struct intel_sdvo_connector *intel_sdvo_connector;
2568
2569 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2570
2571 intel_sdvo_connector = intel_sdvo_connector_alloc();
2572 if (!intel_sdvo_connector)
2573 return false;
2574
2575 intel_connector = &intel_sdvo_connector->base;
2576 connector = &intel_connector->base;
2577 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2578 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2579 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2580
2581 if (device == 0) {
2582 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2583 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2584 } else if (device == 1) {
2585 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2586 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2587 }
2588
2589 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2590 kfree(intel_sdvo_connector);
2591 return false;
2592 }
2593
2594 return true;
2595 }
2596
2597 static bool
2598 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2599 {
2600 struct drm_encoder *encoder = &intel_sdvo->base.base;
2601 struct drm_connector *connector;
2602 struct intel_connector *intel_connector;
2603 struct intel_sdvo_connector *intel_sdvo_connector;
2604
2605 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2606
2607 intel_sdvo_connector = intel_sdvo_connector_alloc();
2608 if (!intel_sdvo_connector)
2609 return false;
2610
2611 intel_connector = &intel_sdvo_connector->base;
2612 connector = &intel_connector->base;
2613 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2614 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2615
2616 if (device == 0) {
2617 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2618 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2619 } else if (device == 1) {
2620 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2621 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2622 }
2623
2624 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2625 kfree(intel_sdvo_connector);
2626 return false;
2627 }
2628
2629 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2630 goto err;
2631
2632 return true;
2633
2634 err:
2635 intel_sdvo_destroy(connector);
2636 return false;
2637 }
2638
2639 static bool
2640 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2641 {
2642 intel_sdvo->is_tv = false;
2643 intel_sdvo->is_lvds = false;
2644
2645 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2646
2647 if (flags & SDVO_OUTPUT_TMDS0)
2648 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2649 return false;
2650
2651 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2652 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2653 return false;
2654
2655 /* TV has no XXX1 function block */
2656 if (flags & SDVO_OUTPUT_SVID0)
2657 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2658 return false;
2659
2660 if (flags & SDVO_OUTPUT_CVBS0)
2661 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2662 return false;
2663
2664 if (flags & SDVO_OUTPUT_YPRPB0)
2665 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2666 return false;
2667
2668 if (flags & SDVO_OUTPUT_RGB0)
2669 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2670 return false;
2671
2672 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2673 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2674 return false;
2675
2676 if (flags & SDVO_OUTPUT_LVDS0)
2677 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2678 return false;
2679
2680 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2681 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2682 return false;
2683
2684 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2685 unsigned char bytes[2];
2686
2687 intel_sdvo->controlled_output = 0;
2688 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2689 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2690 SDVO_NAME(intel_sdvo),
2691 bytes[0], bytes[1]);
2692 return false;
2693 }
2694 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2695
2696 return true;
2697 }
2698
2699 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2700 {
2701 struct drm_device *dev = intel_sdvo->base.base.dev;
2702 struct drm_connector *connector, *tmp;
2703
2704 list_for_each_entry_safe(connector, tmp,
2705 &dev->mode_config.connector_list, head) {
2706 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
2707 drm_connector_unregister(connector);
2708 intel_sdvo_destroy(connector);
2709 }
2710 }
2711 }
2712
2713 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2714 struct intel_sdvo_connector *intel_sdvo_connector,
2715 int type)
2716 {
2717 struct drm_device *dev = intel_sdvo->base.base.dev;
2718 struct intel_sdvo_tv_format format;
2719 uint32_t format_map, i;
2720
2721 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2722 return false;
2723
2724 BUILD_BUG_ON(sizeof(format) != 6);
2725 if (!intel_sdvo_get_value(intel_sdvo,
2726 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2727 &format, sizeof(format)))
2728 return false;
2729
2730 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2731
2732 if (format_map == 0)
2733 return false;
2734
2735 intel_sdvo_connector->format_supported_num = 0;
2736 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2737 if (format_map & (1 << i))
2738 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2739
2740
2741 intel_sdvo_connector->tv_format =
2742 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2743 "mode", intel_sdvo_connector->format_supported_num);
2744 if (!intel_sdvo_connector->tv_format)
2745 return false;
2746
2747 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2748 drm_property_add_enum(
2749 intel_sdvo_connector->tv_format, i,
2750 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2751
2752 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
2753 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2754 intel_sdvo_connector->tv_format, 0);
2755 return true;
2756
2757 }
2758
2759 #define _ENHANCEMENT(state_assignment, name, NAME) do { \
2760 if (enhancements.name) { \
2761 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2762 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2763 return false; \
2764 intel_sdvo_connector->name = \
2765 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2766 if (!intel_sdvo_connector->name) return false; \
2767 state_assignment = response; \
2768 drm_object_attach_property(&connector->base, \
2769 intel_sdvo_connector->name, 0); \
2770 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2771 data_value[0], data_value[1], response); \
2772 } \
2773 } while (0)
2774
2775 #define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
2776
2777 static bool
2778 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2779 struct intel_sdvo_connector *intel_sdvo_connector,
2780 struct intel_sdvo_enhancements_reply enhancements)
2781 {
2782 struct drm_device *dev = intel_sdvo->base.base.dev;
2783 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2784 struct drm_connector_state *conn_state = connector->state;
2785 struct intel_sdvo_connector_state *sdvo_state =
2786 to_intel_sdvo_connector_state(conn_state);
2787 uint16_t response, data_value[2];
2788
2789 /* when horizontal overscan is supported, Add the left/right property */
2790 if (enhancements.overscan_h) {
2791 if (!intel_sdvo_get_value(intel_sdvo,
2792 SDVO_CMD_GET_MAX_OVERSCAN_H,
2793 &data_value, 4))
2794 return false;
2795
2796 if (!intel_sdvo_get_value(intel_sdvo,
2797 SDVO_CMD_GET_OVERSCAN_H,
2798 &response, 2))
2799 return false;
2800
2801 sdvo_state->tv.overscan_h = response;
2802
2803 intel_sdvo_connector->max_hscan = data_value[0];
2804 intel_sdvo_connector->left =
2805 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2806 if (!intel_sdvo_connector->left)
2807 return false;
2808
2809 drm_object_attach_property(&connector->base,
2810 intel_sdvo_connector->left, 0);
2811
2812 intel_sdvo_connector->right =
2813 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2814 if (!intel_sdvo_connector->right)
2815 return false;
2816
2817 drm_object_attach_property(&connector->base,
2818 intel_sdvo_connector->right, 0);
2819 DRM_DEBUG_KMS("h_overscan: max %d, "
2820 "default %d, current %d\n",
2821 data_value[0], data_value[1], response);
2822 }
2823
2824 if (enhancements.overscan_v) {
2825 if (!intel_sdvo_get_value(intel_sdvo,
2826 SDVO_CMD_GET_MAX_OVERSCAN_V,
2827 &data_value, 4))
2828 return false;
2829
2830 if (!intel_sdvo_get_value(intel_sdvo,
2831 SDVO_CMD_GET_OVERSCAN_V,
2832 &response, 2))
2833 return false;
2834
2835 sdvo_state->tv.overscan_v = response;
2836
2837 intel_sdvo_connector->max_vscan = data_value[0];
2838 intel_sdvo_connector->top =
2839 drm_property_create_range(dev, 0,
2840 "top_margin", 0, data_value[0]);
2841 if (!intel_sdvo_connector->top)
2842 return false;
2843
2844 drm_object_attach_property(&connector->base,
2845 intel_sdvo_connector->top, 0);
2846
2847 intel_sdvo_connector->bottom =
2848 drm_property_create_range(dev, 0,
2849 "bottom_margin", 0, data_value[0]);
2850 if (!intel_sdvo_connector->bottom)
2851 return false;
2852
2853 drm_object_attach_property(&connector->base,
2854 intel_sdvo_connector->bottom, 0);
2855 DRM_DEBUG_KMS("v_overscan: max %d, "
2856 "default %d, current %d\n",
2857 data_value[0], data_value[1], response);
2858 }
2859
2860 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
2861 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
2862 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
2863 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
2864 ENHANCEMENT(&conn_state->tv, hue, HUE);
2865 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
2866 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
2867 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
2868 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2869 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
2870 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
2871 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
2872
2873 if (enhancements.dot_crawl) {
2874 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2875 return false;
2876
2877 sdvo_state->tv.dot_crawl = response & 0x1;
2878 intel_sdvo_connector->dot_crawl =
2879 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
2880 if (!intel_sdvo_connector->dot_crawl)
2881 return false;
2882
2883 drm_object_attach_property(&connector->base,
2884 intel_sdvo_connector->dot_crawl, 0);
2885 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2886 }
2887
2888 return true;
2889 }
2890
2891 static bool
2892 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2893 struct intel_sdvo_connector *intel_sdvo_connector,
2894 struct intel_sdvo_enhancements_reply enhancements)
2895 {
2896 struct drm_device *dev = intel_sdvo->base.base.dev;
2897 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2898 uint16_t response, data_value[2];
2899
2900 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
2901
2902 return true;
2903 }
2904 #undef ENHANCEMENT
2905 #undef _ENHANCEMENT
2906
2907 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2908 struct intel_sdvo_connector *intel_sdvo_connector)
2909 {
2910 union {
2911 struct intel_sdvo_enhancements_reply reply;
2912 uint16_t response;
2913 } enhancements;
2914
2915 BUILD_BUG_ON(sizeof(enhancements) != 2);
2916
2917 if (!intel_sdvo_get_value(intel_sdvo,
2918 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2919 &enhancements, sizeof(enhancements)) ||
2920 enhancements.response == 0) {
2921 DRM_DEBUG_KMS("No enhancement is supported\n");
2922 return true;
2923 }
2924
2925 if (IS_TV(intel_sdvo_connector))
2926 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2927 else if (IS_LVDS(intel_sdvo_connector))
2928 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2929 else
2930 return true;
2931 }
2932
2933 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2934 struct i2c_msg *msgs,
2935 int num)
2936 {
2937 struct intel_sdvo *sdvo = adapter->algo_data;
2938
2939 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2940 return -EIO;
2941
2942 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2943 }
2944
2945 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2946 {
2947 struct intel_sdvo *sdvo = adapter->algo_data;
2948 return sdvo->i2c->algo->functionality(sdvo->i2c);
2949 }
2950
2951 static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2952 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2953 .functionality = intel_sdvo_ddc_proxy_func
2954 };
2955
2956 static void proxy_lock_bus(struct i2c_adapter *adapter,
2957 unsigned int flags)
2958 {
2959 struct intel_sdvo *sdvo = adapter->algo_data;
2960 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
2961 }
2962
2963 static int proxy_trylock_bus(struct i2c_adapter *adapter,
2964 unsigned int flags)
2965 {
2966 struct intel_sdvo *sdvo = adapter->algo_data;
2967 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
2968 }
2969
2970 static void proxy_unlock_bus(struct i2c_adapter *adapter,
2971 unsigned int flags)
2972 {
2973 struct intel_sdvo *sdvo = adapter->algo_data;
2974 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
2975 }
2976
2977 const struct i2c_lock_operations proxy_lock_ops = {
2978 .lock_bus = proxy_lock_bus,
2979 .trylock_bus = proxy_trylock_bus,
2980 .unlock_bus = proxy_unlock_bus,
2981 };
2982
2983 static bool
2984 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2985 struct drm_i915_private *dev_priv)
2986 {
2987 struct pci_dev *pdev = dev_priv->drm.pdev;
2988
2989 sdvo->ddc.owner = THIS_MODULE;
2990 sdvo->ddc.class = I2C_CLASS_DDC;
2991 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2992 sdvo->ddc.dev.parent = &pdev->dev;
2993 sdvo->ddc.algo_data = sdvo;
2994 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2995 sdvo->ddc.lock_ops = &proxy_lock_ops;
2996
2997 return i2c_add_adapter(&sdvo->ddc) == 0;
2998 }
2999
3000 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3001 enum port port)
3002 {
3003 if (HAS_PCH_SPLIT(dev_priv))
3004 WARN_ON(port != PORT_B);
3005 else
3006 WARN_ON(port != PORT_B && port != PORT_C);
3007 }
3008
3009 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
3010 i915_reg_t sdvo_reg, enum port port)
3011 {
3012 struct intel_encoder *intel_encoder;
3013 struct intel_sdvo *intel_sdvo;
3014 int i;
3015
3016 assert_sdvo_port_valid(dev_priv, port);
3017
3018 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
3019 if (!intel_sdvo)
3020 return false;
3021
3022 intel_sdvo->sdvo_reg = sdvo_reg;
3023 intel_sdvo->port = port;
3024 intel_sdvo->slave_addr =
3025 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
3026 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
3027 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
3028 goto err_i2c_bus;
3029
3030 /* encoder type will be decided later */
3031 intel_encoder = &intel_sdvo->base;
3032 intel_encoder->type = INTEL_OUTPUT_SDVO;
3033 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
3034 intel_encoder->port = port;
3035 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3036 &intel_sdvo_enc_funcs, 0,
3037 "SDVO %c", port_name(port));
3038
3039 /* Read the regs to test if we can talk to the device */
3040 for (i = 0; i < 0x40; i++) {
3041 u8 byte;
3042
3043 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3044 DRM_DEBUG_KMS("No SDVO device found on %s\n",
3045 SDVO_NAME(intel_sdvo));
3046 goto err;
3047 }
3048 }
3049
3050 intel_encoder->compute_config = intel_sdvo_compute_config;
3051 if (HAS_PCH_SPLIT(dev_priv)) {
3052 intel_encoder->disable = pch_disable_sdvo;
3053 intel_encoder->post_disable = pch_post_disable_sdvo;
3054 } else {
3055 intel_encoder->disable = intel_disable_sdvo;
3056 }
3057 intel_encoder->pre_enable = intel_sdvo_pre_enable;
3058 intel_encoder->enable = intel_enable_sdvo;
3059 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
3060 intel_encoder->get_config = intel_sdvo_get_config;
3061
3062 /* In default case sdvo lvds is false */
3063 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
3064 goto err;
3065
3066 if (intel_sdvo_output_setup(intel_sdvo,
3067 intel_sdvo->caps.output_flags) != true) {
3068 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3069 SDVO_NAME(intel_sdvo));
3070 /* Output_setup can leave behind connectors! */
3071 goto err_output;
3072 }
3073
3074 /* Only enable the hotplug irq if we need it, to work around noisy
3075 * hotplug lines.
3076 */
3077 if (intel_sdvo->hotplug_active) {
3078 if (intel_sdvo->port == PORT_B)
3079 intel_encoder->hpd_pin = HPD_SDVO_B;
3080 else
3081 intel_encoder->hpd_pin = HPD_SDVO_C;
3082 }
3083
3084 /*
3085 * Cloning SDVO with anything is often impossible, since the SDVO
3086 * encoder can request a special input timing mode. And even if that's
3087 * not the case we have evidence that cloning a plain unscaled mode with
3088 * VGA doesn't really work. Furthermore the cloning flags are way too
3089 * simplistic anyway to express such constraints, so just give up on
3090 * cloning for SDVO encoders.
3091 */
3092 intel_sdvo->base.cloneable = 0;
3093
3094 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
3095
3096 /* Set the input timing to the screen. Assume always input 0. */
3097 if (!intel_sdvo_set_target_input(intel_sdvo))
3098 goto err_output;
3099
3100 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3101 &intel_sdvo->pixel_clock_min,
3102 &intel_sdvo->pixel_clock_max))
3103 goto err_output;
3104
3105 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
3106 "clock range %dMHz - %dMHz, "
3107 "input 1: %c, input 2: %c, "
3108 "output 1: %c, output 2: %c\n",
3109 SDVO_NAME(intel_sdvo),
3110 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3111 intel_sdvo->caps.device_rev_id,
3112 intel_sdvo->pixel_clock_min / 1000,
3113 intel_sdvo->pixel_clock_max / 1000,
3114 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3115 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
3116 /* check currently supported outputs */
3117 intel_sdvo->caps.output_flags &
3118 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
3119 intel_sdvo->caps.output_flags &
3120 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
3121 return true;
3122
3123 err_output:
3124 intel_sdvo_output_cleanup(intel_sdvo);
3125
3126 err:
3127 drm_encoder_cleanup(&intel_encoder->base);
3128 i2c_del_adapter(&intel_sdvo->ddc);
3129 err_i2c_bus:
3130 intel_sdvo_unselect_i2c_bus(intel_sdvo);
3131 kfree(intel_sdvo);
3132
3133 return false;
3134 }
ubuntu-bionic-kernel mirror