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1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include "drmP.h"
32 #include "drm.h"
33 #include "drm_crtc.h"
34 #include "intel_drv.h"
35 #include "drm_edid.h"
36 #include "i915_drm.h"
37 #include "i915_drv.h"
38 #include "intel_sdvo_regs.h"
39
40 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
50
51
52 static char *tv_format_names[] = {
53 "NTSC_M" , "NTSC_J" , "NTSC_443",
54 "PAL_B" , "PAL_D" , "PAL_G" ,
55 "PAL_H" , "PAL_I" , "PAL_M" ,
56 "PAL_N" , "PAL_NC" , "PAL_60" ,
57 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
58 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
59 "SECAM_60"
60 };
61
62 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
63
64 struct intel_sdvo_priv {
65 u8 slave_addr;
66
67 /* Register for the SDVO device: SDVOB or SDVOC */
68 int sdvo_reg;
69
70 /* Active outputs controlled by this SDVO output */
71 uint16_t controlled_output;
72
73 /*
74 * Capabilities of the SDVO device returned by
75 * i830_sdvo_get_capabilities()
76 */
77 struct intel_sdvo_caps caps;
78
79 /* Pixel clock limitations reported by the SDVO device, in kHz */
80 int pixel_clock_min, pixel_clock_max;
81
82 /*
83 * For multiple function SDVO device,
84 * this is for current attached outputs.
85 */
86 uint16_t attached_output;
87
88 /**
89 * This is set if we're going to treat the device as TV-out.
90 *
91 * While we have these nice friendly flags for output types that ought
92 * to decide this for us, the S-Video output on our HDMI+S-Video card
93 * shows up as RGB1 (VGA).
94 */
95 bool is_tv;
96
97 /* This is for current tv format name */
98 char *tv_format_name;
99
100 /**
101 * This is set if we treat the device as HDMI, instead of DVI.
102 */
103 bool is_hdmi;
104
105 /**
106 * This is set if we detect output of sdvo device as LVDS.
107 */
108 bool is_lvds;
109
110 /**
111 * This is sdvo flags for input timing.
112 */
113 uint8_t sdvo_flags;
114
115 /**
116 * This is sdvo fixed pannel mode pointer
117 */
118 struct drm_display_mode *sdvo_lvds_fixed_mode;
119
120 /*
121 * supported encoding mode, used to determine whether HDMI is
122 * supported
123 */
124 struct intel_sdvo_encode encode;
125
126 /* DDC bus used by this SDVO encoder */
127 uint8_t ddc_bus;
128
129 /* Mac mini hack -- use the same DDC as the analog connector */
130 struct i2c_adapter *analog_ddc_bus;
131
132 };
133
134 struct intel_sdvo_connector {
135 /* Mark the type of connector */
136 uint16_t output_flag;
137
138 /* This contains all current supported TV format */
139 char *tv_format_supported[TV_FORMAT_NUM];
140 int format_supported_num;
141 struct drm_property *tv_format_property;
142 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
143
144 /**
145 * Returned SDTV resolutions allowed for the current format, if the
146 * device reported it.
147 */
148 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
149
150 /* add the property for the SDVO-TV */
151 struct drm_property *left_property;
152 struct drm_property *right_property;
153 struct drm_property *top_property;
154 struct drm_property *bottom_property;
155 struct drm_property *hpos_property;
156 struct drm_property *vpos_property;
157
158 /* add the property for the SDVO-TV/LVDS */
159 struct drm_property *brightness_property;
160 struct drm_property *contrast_property;
161 struct drm_property *saturation_property;
162 struct drm_property *hue_property;
163
164 /* Add variable to record current setting for the above property */
165 u32 left_margin, right_margin, top_margin, bottom_margin;
166 /* this is to get the range of margin.*/
167 u32 max_hscan, max_vscan;
168 u32 max_hpos, cur_hpos;
169 u32 max_vpos, cur_vpos;
170 u32 cur_brightness, max_brightness;
171 u32 cur_contrast, max_contrast;
172 u32 cur_saturation, max_saturation;
173 u32 cur_hue, max_hue;
174 };
175
176 static bool
177 intel_sdvo_output_setup(struct intel_encoder *intel_encoder,
178 uint16_t flags);
179 static void
180 intel_sdvo_tv_create_property(struct drm_connector *connector, int type);
181 static void
182 intel_sdvo_create_enhance_property(struct drm_connector *connector);
183
184 /**
185 * Writes the SDVOB or SDVOC with the given value, but always writes both
186 * SDVOB and SDVOC to work around apparent hardware issues (according to
187 * comments in the BIOS).
188 */
189 static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val)
190 {
191 struct drm_device *dev = intel_encoder->enc.dev;
192 struct drm_i915_private *dev_priv = dev->dev_private;
193 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
194 u32 bval = val, cval = val;
195 int i;
196
197 if (sdvo_priv->sdvo_reg == PCH_SDVOB) {
198 I915_WRITE(sdvo_priv->sdvo_reg, val);
199 I915_READ(sdvo_priv->sdvo_reg);
200 return;
201 }
202
203 if (sdvo_priv->sdvo_reg == SDVOB) {
204 cval = I915_READ(SDVOC);
205 } else {
206 bval = I915_READ(SDVOB);
207 }
208 /*
209 * Write the registers twice for luck. Sometimes,
210 * writing them only once doesn't appear to 'stick'.
211 * The BIOS does this too. Yay, magic
212 */
213 for (i = 0; i < 2; i++)
214 {
215 I915_WRITE(SDVOB, bval);
216 I915_READ(SDVOB);
217 I915_WRITE(SDVOC, cval);
218 I915_READ(SDVOC);
219 }
220 }
221
222 static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr,
223 u8 *ch)
224 {
225 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
226 u8 out_buf[2];
227 u8 buf[2];
228 int ret;
229
230 struct i2c_msg msgs[] = {
231 {
232 .addr = sdvo_priv->slave_addr >> 1,
233 .flags = 0,
234 .len = 1,
235 .buf = out_buf,
236 },
237 {
238 .addr = sdvo_priv->slave_addr >> 1,
239 .flags = I2C_M_RD,
240 .len = 1,
241 .buf = buf,
242 }
243 };
244
245 out_buf[0] = addr;
246 out_buf[1] = 0;
247
248 if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2)
249 {
250 *ch = buf[0];
251 return true;
252 }
253
254 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
255 return false;
256 }
257
258 static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr,
259 u8 ch)
260 {
261 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
262 u8 out_buf[2];
263 struct i2c_msg msgs[] = {
264 {
265 .addr = sdvo_priv->slave_addr >> 1,
266 .flags = 0,
267 .len = 2,
268 .buf = out_buf,
269 }
270 };
271
272 out_buf[0] = addr;
273 out_buf[1] = ch;
274
275 if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1)
276 {
277 return true;
278 }
279 return false;
280 }
281
282 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
283 /** Mapping of command numbers to names, for debug output */
284 static const struct _sdvo_cmd_name {
285 u8 cmd;
286 char *name;
287 } sdvo_cmd_names[] = {
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
331 /* Add the op code for SDVO enhancements */
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
356 /* HDMI op code */
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
377 };
378
379 #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
380 #define SDVO_NAME(dev_priv) (IS_SDVOB((dev_priv)->sdvo_reg) ? "SDVOB" : "SDVOC")
381 #define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv)
382
383 static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd,
384 void *args, int args_len)
385 {
386 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
387 int i;
388
389 DRM_DEBUG_KMS("%s: W: %02X ",
390 SDVO_NAME(sdvo_priv), cmd);
391 for (i = 0; i < args_len; i++)
392 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
393 for (; i < 8; i++)
394 DRM_LOG_KMS(" ");
395 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
396 if (cmd == sdvo_cmd_names[i].cmd) {
397 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
398 break;
399 }
400 }
401 if (i == ARRAY_SIZE(sdvo_cmd_names))
402 DRM_LOG_KMS("(%02X)", cmd);
403 DRM_LOG_KMS("\n");
404 }
405
406 static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd,
407 void *args, int args_len)
408 {
409 int i;
410
411 intel_sdvo_debug_write(intel_encoder, cmd, args, args_len);
412
413 for (i = 0; i < args_len; i++) {
414 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i,
415 ((u8*)args)[i]);
416 }
417
418 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd);
419 }
420
421 static const char *cmd_status_names[] = {
422 "Power on",
423 "Success",
424 "Not supported",
425 "Invalid arg",
426 "Pending",
427 "Target not specified",
428 "Scaling not supported"
429 };
430
431 static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder,
432 void *response, int response_len,
433 u8 status)
434 {
435 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
436 int i;
437
438 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
439 for (i = 0; i < response_len; i++)
440 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
441 for (; i < 8; i++)
442 DRM_LOG_KMS(" ");
443 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
444 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
445 else
446 DRM_LOG_KMS("(??? %d)", status);
447 DRM_LOG_KMS("\n");
448 }
449
450 static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder,
451 void *response, int response_len)
452 {
453 int i;
454 u8 status;
455 u8 retry = 50;
456
457 while (retry--) {
458 /* Read the command response */
459 for (i = 0; i < response_len; i++) {
460 intel_sdvo_read_byte(intel_encoder,
461 SDVO_I2C_RETURN_0 + i,
462 &((u8 *)response)[i]);
463 }
464
465 /* read the return status */
466 intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS,
467 &status);
468
469 intel_sdvo_debug_response(intel_encoder, response, response_len,
470 status);
471 if (status != SDVO_CMD_STATUS_PENDING)
472 return status;
473
474 mdelay(50);
475 }
476
477 return status;
478 }
479
480 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
481 {
482 if (mode->clock >= 100000)
483 return 1;
484 else if (mode->clock >= 50000)
485 return 2;
486 else
487 return 4;
488 }
489
490 /**
491 * Try to read the response after issuie the DDC switch command. But it
492 * is noted that we must do the action of reading response and issuing DDC
493 * switch command in one I2C transaction. Otherwise when we try to start
494 * another I2C transaction after issuing the DDC bus switch, it will be
495 * switched to the internal SDVO register.
496 */
497 static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder,
498 u8 target)
499 {
500 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
501 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
502 struct i2c_msg msgs[] = {
503 {
504 .addr = sdvo_priv->slave_addr >> 1,
505 .flags = 0,
506 .len = 2,
507 .buf = out_buf,
508 },
509 /* the following two are to read the response */
510 {
511 .addr = sdvo_priv->slave_addr >> 1,
512 .flags = 0,
513 .len = 1,
514 .buf = cmd_buf,
515 },
516 {
517 .addr = sdvo_priv->slave_addr >> 1,
518 .flags = I2C_M_RD,
519 .len = 1,
520 .buf = ret_value,
521 },
522 };
523
524 intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
525 &target, 1);
526 /* write the DDC switch command argument */
527 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target);
528
529 out_buf[0] = SDVO_I2C_OPCODE;
530 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
531 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
532 cmd_buf[1] = 0;
533 ret_value[0] = 0;
534 ret_value[1] = 0;
535
536 ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3);
537 if (ret != 3) {
538 /* failure in I2C transfer */
539 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
540 return;
541 }
542 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
543 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
544 ret_value[0]);
545 return;
546 }
547 return;
548 }
549
550 static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1)
551 {
552 struct intel_sdvo_set_target_input_args targets = {0};
553 u8 status;
554
555 if (target_0 && target_1)
556 return SDVO_CMD_STATUS_NOTSUPP;
557
558 if (target_1)
559 targets.target_1 = 1;
560
561 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets,
562 sizeof(targets));
563
564 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
565
566 return (status == SDVO_CMD_STATUS_SUCCESS);
567 }
568
569 /**
570 * Return whether each input is trained.
571 *
572 * This function is making an assumption about the layout of the response,
573 * which should be checked against the docs.
574 */
575 static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2)
576 {
577 struct intel_sdvo_get_trained_inputs_response response;
578 u8 status;
579
580 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
581 status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response));
582 if (status != SDVO_CMD_STATUS_SUCCESS)
583 return false;
584
585 *input_1 = response.input0_trained;
586 *input_2 = response.input1_trained;
587 return true;
588 }
589
590 static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder,
591 u16 outputs)
592 {
593 u8 status;
594
595 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
596 sizeof(outputs));
597 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
598 return (status == SDVO_CMD_STATUS_SUCCESS);
599 }
600
601 static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder,
602 int mode)
603 {
604 u8 status, state = SDVO_ENCODER_STATE_ON;
605
606 switch (mode) {
607 case DRM_MODE_DPMS_ON:
608 state = SDVO_ENCODER_STATE_ON;
609 break;
610 case DRM_MODE_DPMS_STANDBY:
611 state = SDVO_ENCODER_STATE_STANDBY;
612 break;
613 case DRM_MODE_DPMS_SUSPEND:
614 state = SDVO_ENCODER_STATE_SUSPEND;
615 break;
616 case DRM_MODE_DPMS_OFF:
617 state = SDVO_ENCODER_STATE_OFF;
618 break;
619 }
620
621 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
622 sizeof(state));
623 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
624
625 return (status == SDVO_CMD_STATUS_SUCCESS);
626 }
627
628 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder,
629 int *clock_min,
630 int *clock_max)
631 {
632 struct intel_sdvo_pixel_clock_range clocks;
633 u8 status;
634
635 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
636 NULL, 0);
637
638 status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks));
639
640 if (status != SDVO_CMD_STATUS_SUCCESS)
641 return false;
642
643 /* Convert the values from units of 10 kHz to kHz. */
644 *clock_min = clocks.min * 10;
645 *clock_max = clocks.max * 10;
646
647 return true;
648 }
649
650 static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder,
651 u16 outputs)
652 {
653 u8 status;
654
655 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
656 sizeof(outputs));
657
658 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
659 return (status == SDVO_CMD_STATUS_SUCCESS);
660 }
661
662 static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd,
663 struct intel_sdvo_dtd *dtd)
664 {
665 u8 status;
666
667 intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1));
668 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
669 if (status != SDVO_CMD_STATUS_SUCCESS)
670 return false;
671
672 intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2));
673 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
674 if (status != SDVO_CMD_STATUS_SUCCESS)
675 return false;
676
677 return true;
678 }
679
680 static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder,
681 struct intel_sdvo_dtd *dtd)
682 {
683 return intel_sdvo_set_timing(intel_encoder,
684 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
685 }
686
687 static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder,
688 struct intel_sdvo_dtd *dtd)
689 {
690 return intel_sdvo_set_timing(intel_encoder,
691 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
692 }
693
694 static bool
695 intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder,
696 uint16_t clock,
697 uint16_t width,
698 uint16_t height)
699 {
700 struct intel_sdvo_preferred_input_timing_args args;
701 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
702 uint8_t status;
703
704 memset(&args, 0, sizeof(args));
705 args.clock = clock;
706 args.width = width;
707 args.height = height;
708 args.interlace = 0;
709
710 if (sdvo_priv->is_lvds &&
711 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
712 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
713 args.scaled = 1;
714
715 intel_sdvo_write_cmd(intel_encoder,
716 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
717 &args, sizeof(args));
718 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
719 if (status != SDVO_CMD_STATUS_SUCCESS)
720 return false;
721
722 return true;
723 }
724
725 static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder,
726 struct intel_sdvo_dtd *dtd)
727 {
728 bool status;
729
730 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
731 NULL, 0);
732
733 status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
734 sizeof(dtd->part1));
735 if (status != SDVO_CMD_STATUS_SUCCESS)
736 return false;
737
738 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
739 NULL, 0);
740
741 status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
742 sizeof(dtd->part2));
743 if (status != SDVO_CMD_STATUS_SUCCESS)
744 return false;
745
746 return false;
747 }
748
749 static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val)
750 {
751 u8 status;
752
753 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
754 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
755 if (status != SDVO_CMD_STATUS_SUCCESS)
756 return false;
757
758 return true;
759 }
760
761 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
762 struct drm_display_mode *mode)
763 {
764 uint16_t width, height;
765 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
766 uint16_t h_sync_offset, v_sync_offset;
767
768 width = mode->crtc_hdisplay;
769 height = mode->crtc_vdisplay;
770
771 /* do some mode translations */
772 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
773 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
774
775 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
776 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
777
778 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
779 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
780
781 dtd->part1.clock = mode->clock / 10;
782 dtd->part1.h_active = width & 0xff;
783 dtd->part1.h_blank = h_blank_len & 0xff;
784 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
785 ((h_blank_len >> 8) & 0xf);
786 dtd->part1.v_active = height & 0xff;
787 dtd->part1.v_blank = v_blank_len & 0xff;
788 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
789 ((v_blank_len >> 8) & 0xf);
790
791 dtd->part2.h_sync_off = h_sync_offset & 0xff;
792 dtd->part2.h_sync_width = h_sync_len & 0xff;
793 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
794 (v_sync_len & 0xf);
795 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
796 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
797 ((v_sync_len & 0x30) >> 4);
798
799 dtd->part2.dtd_flags = 0x18;
800 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
801 dtd->part2.dtd_flags |= 0x2;
802 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
803 dtd->part2.dtd_flags |= 0x4;
804
805 dtd->part2.sdvo_flags = 0;
806 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
807 dtd->part2.reserved = 0;
808 }
809
810 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
811 struct intel_sdvo_dtd *dtd)
812 {
813 mode->hdisplay = dtd->part1.h_active;
814 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
815 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
816 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
817 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
818 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
819 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
820 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
821
822 mode->vdisplay = dtd->part1.v_active;
823 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
824 mode->vsync_start = mode->vdisplay;
825 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
826 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
827 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
828 mode->vsync_end = mode->vsync_start +
829 (dtd->part2.v_sync_off_width & 0xf);
830 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
831 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
832 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
833
834 mode->clock = dtd->part1.clock * 10;
835
836 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
837 if (dtd->part2.dtd_flags & 0x2)
838 mode->flags |= DRM_MODE_FLAG_PHSYNC;
839 if (dtd->part2.dtd_flags & 0x4)
840 mode->flags |= DRM_MODE_FLAG_PVSYNC;
841 }
842
843 static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder,
844 struct intel_sdvo_encode *encode)
845 {
846 uint8_t status;
847
848 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
849 status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode));
850 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
851 memset(encode, 0, sizeof(*encode));
852 return false;
853 }
854
855 return true;
856 }
857
858 static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder,
859 uint8_t mode)
860 {
861 uint8_t status;
862
863 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1);
864 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
865
866 return (status == SDVO_CMD_STATUS_SUCCESS);
867 }
868
869 static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder,
870 uint8_t mode)
871 {
872 uint8_t status;
873
874 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
875 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
876
877 return (status == SDVO_CMD_STATUS_SUCCESS);
878 }
879
880 #if 0
881 static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)
882 {
883 int i, j;
884 uint8_t set_buf_index[2];
885 uint8_t av_split;
886 uint8_t buf_size;
887 uint8_t buf[48];
888 uint8_t *pos;
889
890 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
891 intel_sdvo_read_response(encoder, &av_split, 1);
892
893 for (i = 0; i <= av_split; i++) {
894 set_buf_index[0] = i; set_buf_index[1] = 0;
895 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
896 set_buf_index, 2);
897 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
898 intel_sdvo_read_response(encoder, &buf_size, 1);
899
900 pos = buf;
901 for (j = 0; j <= buf_size; j += 8) {
902 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
903 NULL, 0);
904 intel_sdvo_read_response(encoder, pos, 8);
905 pos += 8;
906 }
907 }
908 }
909 #endif
910
911 static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder,
912 int index,
913 uint8_t *data, int8_t size, uint8_t tx_rate)
914 {
915 uint8_t set_buf_index[2];
916
917 set_buf_index[0] = index;
918 set_buf_index[1] = 0;
919
920 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX,
921 set_buf_index, 2);
922
923 for (; size > 0; size -= 8) {
924 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8);
925 data += 8;
926 }
927
928 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
929 }
930
931 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
932 {
933 uint8_t csum = 0;
934 int i;
935
936 for (i = 0; i < size; i++)
937 csum += data[i];
938
939 return 0x100 - csum;
940 }
941
942 #define DIP_TYPE_AVI 0x82
943 #define DIP_VERSION_AVI 0x2
944 #define DIP_LEN_AVI 13
945
946 struct dip_infoframe {
947 uint8_t type;
948 uint8_t version;
949 uint8_t len;
950 uint8_t checksum;
951 union {
952 struct {
953 /* Packet Byte #1 */
954 uint8_t S:2;
955 uint8_t B:2;
956 uint8_t A:1;
957 uint8_t Y:2;
958 uint8_t rsvd1:1;
959 /* Packet Byte #2 */
960 uint8_t R:4;
961 uint8_t M:2;
962 uint8_t C:2;
963 /* Packet Byte #3 */
964 uint8_t SC:2;
965 uint8_t Q:2;
966 uint8_t EC:3;
967 uint8_t ITC:1;
968 /* Packet Byte #4 */
969 uint8_t VIC:7;
970 uint8_t rsvd2:1;
971 /* Packet Byte #5 */
972 uint8_t PR:4;
973 uint8_t rsvd3:4;
974 /* Packet Byte #6~13 */
975 uint16_t top_bar_end;
976 uint16_t bottom_bar_start;
977 uint16_t left_bar_end;
978 uint16_t right_bar_start;
979 } avi;
980 struct {
981 /* Packet Byte #1 */
982 uint8_t channel_count:3;
983 uint8_t rsvd1:1;
984 uint8_t coding_type:4;
985 /* Packet Byte #2 */
986 uint8_t sample_size:2; /* SS0, SS1 */
987 uint8_t sample_frequency:3;
988 uint8_t rsvd2:3;
989 /* Packet Byte #3 */
990 uint8_t coding_type_private:5;
991 uint8_t rsvd3:3;
992 /* Packet Byte #4 */
993 uint8_t channel_allocation;
994 /* Packet Byte #5 */
995 uint8_t rsvd4:3;
996 uint8_t level_shift:4;
997 uint8_t downmix_inhibit:1;
998 } audio;
999 uint8_t payload[28];
1000 } __attribute__ ((packed)) u;
1001 } __attribute__((packed));
1002
1003 static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder,
1004 struct drm_display_mode * mode)
1005 {
1006 struct dip_infoframe avi_if = {
1007 .type = DIP_TYPE_AVI,
1008 .version = DIP_VERSION_AVI,
1009 .len = DIP_LEN_AVI,
1010 };
1011
1012 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1013 4 + avi_if.len);
1014 intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if,
1015 4 + avi_if.len,
1016 SDVO_HBUF_TX_VSYNC);
1017 }
1018
1019 static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder)
1020 {
1021
1022 struct intel_sdvo_tv_format format;
1023 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1024 uint32_t format_map, i;
1025 uint8_t status;
1026
1027 for (i = 0; i < TV_FORMAT_NUM; i++)
1028 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1029 break;
1030
1031 format_map = 1 << i;
1032 memset(&format, 0, sizeof(format));
1033 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1034 sizeof(format) : sizeof(format_map));
1035
1036 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format,
1037 sizeof(format));
1038
1039 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
1040 if (status != SDVO_CMD_STATUS_SUCCESS)
1041 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
1042 SDVO_NAME(sdvo_priv));
1043 }
1044
1045 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1046 struct drm_display_mode *mode,
1047 struct drm_display_mode *adjusted_mode)
1048 {
1049 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1050 struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv;
1051
1052 if (dev_priv->is_tv) {
1053 struct intel_sdvo_dtd output_dtd;
1054 bool success;
1055
1056 /* We need to construct preferred input timings based on our
1057 * output timings. To do that, we have to set the output
1058 * timings, even though this isn't really the right place in
1059 * the sequence to do it. Oh well.
1060 */
1061
1062
1063 /* Set output timings */
1064 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1065 intel_sdvo_set_target_output(intel_encoder,
1066 dev_priv->attached_output);
1067 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
1068
1069 /* Set the input timing to the screen. Assume always input 0. */
1070 intel_sdvo_set_target_input(intel_encoder, true, false);
1071
1072
1073 success = intel_sdvo_create_preferred_input_timing(intel_encoder,
1074 mode->clock / 10,
1075 mode->hdisplay,
1076 mode->vdisplay);
1077 if (success) {
1078 struct intel_sdvo_dtd input_dtd;
1079
1080 intel_sdvo_get_preferred_input_timing(intel_encoder,
1081 &input_dtd);
1082 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1083 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1084
1085 drm_mode_set_crtcinfo(adjusted_mode, 0);
1086
1087 mode->clock = adjusted_mode->clock;
1088
1089 adjusted_mode->clock *=
1090 intel_sdvo_get_pixel_multiplier(mode);
1091 } else {
1092 return false;
1093 }
1094 } else if (dev_priv->is_lvds) {
1095 struct intel_sdvo_dtd output_dtd;
1096 bool success;
1097
1098 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1099 /* Set output timings */
1100 intel_sdvo_get_dtd_from_mode(&output_dtd,
1101 dev_priv->sdvo_lvds_fixed_mode);
1102
1103 intel_sdvo_set_target_output(intel_encoder,
1104 dev_priv->attached_output);
1105 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
1106
1107 /* Set the input timing to the screen. Assume always input 0. */
1108 intel_sdvo_set_target_input(intel_encoder, true, false);
1109
1110
1111 success = intel_sdvo_create_preferred_input_timing(
1112 intel_encoder,
1113 mode->clock / 10,
1114 mode->hdisplay,
1115 mode->vdisplay);
1116
1117 if (success) {
1118 struct intel_sdvo_dtd input_dtd;
1119
1120 intel_sdvo_get_preferred_input_timing(intel_encoder,
1121 &input_dtd);
1122 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1123 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1124
1125 drm_mode_set_crtcinfo(adjusted_mode, 0);
1126
1127 mode->clock = adjusted_mode->clock;
1128
1129 adjusted_mode->clock *=
1130 intel_sdvo_get_pixel_multiplier(mode);
1131 } else {
1132 return false;
1133 }
1134
1135 } else {
1136 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1137 * SDVO device will be told of the multiplier during mode_set.
1138 */
1139 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1140 }
1141 return true;
1142 }
1143
1144 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1145 struct drm_display_mode *mode,
1146 struct drm_display_mode *adjusted_mode)
1147 {
1148 struct drm_device *dev = encoder->dev;
1149 struct drm_i915_private *dev_priv = dev->dev_private;
1150 struct drm_crtc *crtc = encoder->crtc;
1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1152 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1153 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1154 u32 sdvox = 0;
1155 int sdvo_pixel_multiply;
1156 struct intel_sdvo_in_out_map in_out;
1157 struct intel_sdvo_dtd input_dtd;
1158 u8 status;
1159
1160 if (!mode)
1161 return;
1162
1163 /* First, set the input mapping for the first input to our controlled
1164 * output. This is only correct if we're a single-input device, in
1165 * which case the first input is the output from the appropriate SDVO
1166 * channel on the motherboard. In a two-input device, the first input
1167 * will be SDVOB and the second SDVOC.
1168 */
1169 in_out.in0 = sdvo_priv->attached_output;
1170 in_out.in1 = 0;
1171
1172 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP,
1173 &in_out, sizeof(in_out));
1174 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
1175
1176 if (sdvo_priv->is_hdmi) {
1177 intel_sdvo_set_avi_infoframe(intel_encoder, mode);
1178 sdvox |= SDVO_AUDIO_ENABLE;
1179 }
1180
1181 /* We have tried to get input timing in mode_fixup, and filled into
1182 adjusted_mode */
1183 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1184 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1185 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1186 } else
1187 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1188
1189 /* If it's a TV, we already set the output timing in mode_fixup.
1190 * Otherwise, the output timing is equal to the input timing.
1191 */
1192 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1193 /* Set the output timing to the screen */
1194 intel_sdvo_set_target_output(intel_encoder,
1195 sdvo_priv->attached_output);
1196 intel_sdvo_set_output_timing(intel_encoder, &input_dtd);
1197 }
1198
1199 /* Set the input timing to the screen. Assume always input 0. */
1200 intel_sdvo_set_target_input(intel_encoder, true, false);
1201
1202 if (sdvo_priv->is_tv)
1203 intel_sdvo_set_tv_format(intel_encoder);
1204
1205 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1206 * provide the device with a timing it can support, if it supports that
1207 * feature. However, presumably we would need to adjust the CRTC to
1208 * output the preferred timing, and we don't support that currently.
1209 */
1210 #if 0
1211 success = intel_sdvo_create_preferred_input_timing(encoder, clock,
1212 width, height);
1213 if (success) {
1214 struct intel_sdvo_dtd *input_dtd;
1215
1216 intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
1217 intel_sdvo_set_input_timing(encoder, &input_dtd);
1218 }
1219 #else
1220 intel_sdvo_set_input_timing(intel_encoder, &input_dtd);
1221 #endif
1222
1223 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1224 case 1:
1225 intel_sdvo_set_clock_rate_mult(intel_encoder,
1226 SDVO_CLOCK_RATE_MULT_1X);
1227 break;
1228 case 2:
1229 intel_sdvo_set_clock_rate_mult(intel_encoder,
1230 SDVO_CLOCK_RATE_MULT_2X);
1231 break;
1232 case 4:
1233 intel_sdvo_set_clock_rate_mult(intel_encoder,
1234 SDVO_CLOCK_RATE_MULT_4X);
1235 break;
1236 }
1237
1238 /* Set the SDVO control regs. */
1239 if (IS_I965G(dev)) {
1240 sdvox |= SDVO_BORDER_ENABLE;
1241 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1242 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1243 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1244 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
1245 } else {
1246 sdvox |= I915_READ(sdvo_priv->sdvo_reg);
1247 switch (sdvo_priv->sdvo_reg) {
1248 case SDVOB:
1249 sdvox &= SDVOB_PRESERVE_MASK;
1250 break;
1251 case SDVOC:
1252 sdvox &= SDVOC_PRESERVE_MASK;
1253 break;
1254 }
1255 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1256 }
1257 if (intel_crtc->pipe == 1)
1258 sdvox |= SDVO_PIPE_B_SELECT;
1259
1260 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1261 if (IS_I965G(dev)) {
1262 /* done in crtc_mode_set as the dpll_md reg must be written early */
1263 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1264 /* done in crtc_mode_set as it lives inside the dpll register */
1265 } else {
1266 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1267 }
1268
1269 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1270 sdvox |= SDVO_STALL_SELECT;
1271 intel_sdvo_write_sdvox(intel_encoder, sdvox);
1272 }
1273
1274 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1275 {
1276 struct drm_device *dev = encoder->dev;
1277 struct drm_i915_private *dev_priv = dev->dev_private;
1278 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1279 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1280 u32 temp;
1281
1282 if (mode != DRM_MODE_DPMS_ON) {
1283 intel_sdvo_set_active_outputs(intel_encoder, 0);
1284 if (0)
1285 intel_sdvo_set_encoder_power_state(intel_encoder, mode);
1286
1287 if (mode == DRM_MODE_DPMS_OFF) {
1288 temp = I915_READ(sdvo_priv->sdvo_reg);
1289 if ((temp & SDVO_ENABLE) != 0) {
1290 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE);
1291 }
1292 }
1293 } else {
1294 bool input1, input2;
1295 int i;
1296 u8 status;
1297
1298 temp = I915_READ(sdvo_priv->sdvo_reg);
1299 if ((temp & SDVO_ENABLE) == 0)
1300 intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE);
1301 for (i = 0; i < 2; i++)
1302 intel_wait_for_vblank(dev);
1303
1304 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1,
1305 &input2);
1306
1307
1308 /* Warn if the device reported failure to sync.
1309 * A lot of SDVO devices fail to notify of sync, but it's
1310 * a given it the status is a success, we succeeded.
1311 */
1312 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1313 DRM_DEBUG_KMS("First %s output reported failure to "
1314 "sync\n", SDVO_NAME(sdvo_priv));
1315 }
1316
1317 if (0)
1318 intel_sdvo_set_encoder_power_state(intel_encoder, mode);
1319 intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->attached_output);
1320 }
1321 return;
1322 }
1323
1324 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1325 struct drm_display_mode *mode)
1326 {
1327 struct drm_encoder *encoder = intel_attached_encoder(connector);
1328 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1329 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1330
1331 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1332 return MODE_NO_DBLESCAN;
1333
1334 if (sdvo_priv->pixel_clock_min > mode->clock)
1335 return MODE_CLOCK_LOW;
1336
1337 if (sdvo_priv->pixel_clock_max < mode->clock)
1338 return MODE_CLOCK_HIGH;
1339
1340 if (sdvo_priv->is_lvds == true) {
1341 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1342 return MODE_PANEL;
1343
1344 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1345 return MODE_PANEL;
1346
1347 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1348 return MODE_PANEL;
1349 }
1350
1351 return MODE_OK;
1352 }
1353
1354 static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps)
1355 {
1356 u8 status;
1357
1358 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1359 status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps));
1360 if (status != SDVO_CMD_STATUS_SUCCESS)
1361 return false;
1362
1363 return true;
1364 }
1365
1366 /* No use! */
1367 #if 0
1368 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1369 {
1370 struct drm_connector *connector = NULL;
1371 struct intel_encoder *iout = NULL;
1372 struct intel_sdvo_priv *sdvo;
1373
1374 /* find the sdvo connector */
1375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1376 iout = to_intel_encoder(connector);
1377
1378 if (iout->type != INTEL_OUTPUT_SDVO)
1379 continue;
1380
1381 sdvo = iout->dev_priv;
1382
1383 if (sdvo->sdvo_reg == SDVOB && sdvoB)
1384 return connector;
1385
1386 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
1387 return connector;
1388
1389 }
1390
1391 return NULL;
1392 }
1393
1394 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1395 {
1396 u8 response[2];
1397 u8 status;
1398 struct intel_encoder *intel_encoder;
1399 DRM_DEBUG_KMS("\n");
1400
1401 if (!connector)
1402 return 0;
1403
1404 intel_encoder = to_intel_encoder(connector);
1405
1406 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1407 status = intel_sdvo_read_response(intel_encoder, &response, 2);
1408
1409 if (response[0] !=0)
1410 return 1;
1411
1412 return 0;
1413 }
1414
1415 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1416 {
1417 u8 response[2];
1418 u8 status;
1419 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1420
1421 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1422 intel_sdvo_read_response(intel_encoder, &response, 2);
1423
1424 if (on) {
1425 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1426 status = intel_sdvo_read_response(intel_encoder, &response, 2);
1427
1428 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1429 } else {
1430 response[0] = 0;
1431 response[1] = 0;
1432 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1433 }
1434
1435 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1436 intel_sdvo_read_response(intel_encoder, &response, 2);
1437 }
1438 #endif
1439
1440 static bool
1441 intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder)
1442 {
1443 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1444 int caps = 0;
1445
1446 if (sdvo_priv->caps.output_flags &
1447 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1448 caps++;
1449 if (sdvo_priv->caps.output_flags &
1450 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1451 caps++;
1452 if (sdvo_priv->caps.output_flags &
1453 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1454 caps++;
1455 if (sdvo_priv->caps.output_flags &
1456 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1457 caps++;
1458 if (sdvo_priv->caps.output_flags &
1459 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1460 caps++;
1461
1462 if (sdvo_priv->caps.output_flags &
1463 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1464 caps++;
1465
1466 if (sdvo_priv->caps.output_flags &
1467 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1468 caps++;
1469
1470 return (caps > 1);
1471 }
1472
1473 static struct drm_connector *
1474 intel_find_analog_connector(struct drm_device *dev)
1475 {
1476 struct drm_connector *connector;
1477 struct drm_encoder *encoder;
1478 struct intel_encoder *intel_encoder;
1479
1480 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1481 intel_encoder = enc_to_intel_encoder(encoder);
1482 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
1483 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1484 if (encoder == intel_attached_encoder(connector))
1485 return connector;
1486 }
1487 }
1488 }
1489 return NULL;
1490 }
1491
1492 static int
1493 intel_analog_is_connected(struct drm_device *dev)
1494 {
1495 struct drm_connector *analog_connector;
1496 analog_connector = intel_find_analog_connector(dev);
1497
1498 if (!analog_connector)
1499 return false;
1500
1501 if (analog_connector->funcs->detect(analog_connector) ==
1502 connector_status_disconnected)
1503 return false;
1504
1505 return true;
1506 }
1507
1508 enum drm_connector_status
1509 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1510 {
1511 struct drm_encoder *encoder = intel_attached_encoder(connector);
1512 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1513 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1514 struct intel_connector *intel_connector = to_intel_connector(connector);
1515 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1516 enum drm_connector_status status = connector_status_connected;
1517 struct edid *edid = NULL;
1518
1519 edid = drm_get_edid(connector, intel_encoder->ddc_bus);
1520
1521 /* This is only applied to SDVO cards with multiple outputs */
1522 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) {
1523 uint8_t saved_ddc, temp_ddc;
1524 saved_ddc = sdvo_priv->ddc_bus;
1525 temp_ddc = sdvo_priv->ddc_bus >> 1;
1526 /*
1527 * Don't use the 1 as the argument of DDC bus switch to get
1528 * the EDID. It is used for SDVO SPD ROM.
1529 */
1530 while(temp_ddc > 1) {
1531 sdvo_priv->ddc_bus = temp_ddc;
1532 edid = drm_get_edid(connector, intel_encoder->ddc_bus);
1533 if (edid) {
1534 /*
1535 * When we can get the EDID, maybe it is the
1536 * correct DDC bus. Update it.
1537 */
1538 sdvo_priv->ddc_bus = temp_ddc;
1539 break;
1540 }
1541 temp_ddc >>= 1;
1542 }
1543 if (edid == NULL)
1544 sdvo_priv->ddc_bus = saved_ddc;
1545 }
1546 /* when there is no edid and no monitor is connected with VGA
1547 * port, try to use the CRT ddc to read the EDID for DVI-connector
1548 */
1549 if (edid == NULL && sdvo_priv->analog_ddc_bus &&
1550 !intel_analog_is_connected(connector->dev))
1551 edid = drm_get_edid(connector, sdvo_priv->analog_ddc_bus);
1552
1553 if (edid != NULL) {
1554 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1555 bool need_digital = !!(sdvo_connector->output_flag & SDVO_TMDS_MASK);
1556
1557 /* DDC bus is shared, match EDID to connector type */
1558 if (is_digital && need_digital)
1559 sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid);
1560 else if (is_digital != need_digital)
1561 status = connector_status_disconnected;
1562
1563 connector->display_info.raw_edid = NULL;
1564 } else
1565 status = connector_status_disconnected;
1566
1567 kfree(edid);
1568
1569 return status;
1570 }
1571
1572 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1573 {
1574 uint16_t response;
1575 u8 status;
1576 struct drm_encoder *encoder = intel_attached_encoder(connector);
1577 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1578 struct intel_connector *intel_connector = to_intel_connector(connector);
1579 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1580 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1581 enum drm_connector_status ret;
1582
1583 intel_sdvo_write_cmd(intel_encoder,
1584 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1585 if (sdvo_priv->is_tv) {
1586 /* add 30ms delay when the output type is SDVO-TV */
1587 mdelay(30);
1588 }
1589 status = intel_sdvo_read_response(intel_encoder, &response, 2);
1590
1591 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1592
1593 if (status != SDVO_CMD_STATUS_SUCCESS)
1594 return connector_status_unknown;
1595
1596 if (response == 0)
1597 return connector_status_disconnected;
1598
1599 sdvo_priv->attached_output = response;
1600
1601 if ((sdvo_connector->output_flag & response) == 0)
1602 ret = connector_status_disconnected;
1603 else if (response & SDVO_TMDS_MASK)
1604 ret = intel_sdvo_hdmi_sink_detect(connector);
1605 else
1606 ret = connector_status_connected;
1607
1608 /* May update encoder flag for like clock for SDVO TV, etc.*/
1609 if (ret == connector_status_connected) {
1610 sdvo_priv->is_tv = false;
1611 sdvo_priv->is_lvds = false;
1612 intel_encoder->needs_tv_clock = false;
1613
1614 if (response & SDVO_TV_MASK) {
1615 sdvo_priv->is_tv = true;
1616 intel_encoder->needs_tv_clock = true;
1617 }
1618 if (response & SDVO_LVDS_MASK)
1619 sdvo_priv->is_lvds = true;
1620 }
1621
1622 return ret;
1623 }
1624
1625 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1626 {
1627 struct drm_encoder *encoder = intel_attached_encoder(connector);
1628 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1629 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1630 int num_modes;
1631
1632 /* set the bus switch and get the modes */
1633 num_modes = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
1634
1635 /*
1636 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1637 * link between analog and digital outputs. So, if the regular SDVO
1638 * DDC fails, check to see if the analog output is disconnected, in
1639 * which case we'll look there for the digital DDC data.
1640 */
1641 if (num_modes == 0 &&
1642 sdvo_priv->analog_ddc_bus &&
1643 !intel_analog_is_connected(connector->dev)) {
1644 /* Switch to the analog ddc bus and try that
1645 */
1646 (void) intel_ddc_get_modes(connector, sdvo_priv->analog_ddc_bus);
1647 }
1648 }
1649
1650 /*
1651 * Set of SDVO TV modes.
1652 * Note! This is in reply order (see loop in get_tv_modes).
1653 * XXX: all 60Hz refresh?
1654 */
1655 struct drm_display_mode sdvo_tv_modes[] = {
1656 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1657 416, 0, 200, 201, 232, 233, 0,
1658 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1659 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1660 416, 0, 240, 241, 272, 273, 0,
1661 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1662 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1663 496, 0, 300, 301, 332, 333, 0,
1664 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1665 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1666 736, 0, 350, 351, 382, 383, 0,
1667 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1668 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1669 736, 0, 400, 401, 432, 433, 0,
1670 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1671 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1672 736, 0, 480, 481, 512, 513, 0,
1673 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1674 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1675 800, 0, 480, 481, 512, 513, 0,
1676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1677 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1678 800, 0, 576, 577, 608, 609, 0,
1679 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1680 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1681 816, 0, 350, 351, 382, 383, 0,
1682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1683 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1684 816, 0, 400, 401, 432, 433, 0,
1685 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1686 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1687 816, 0, 480, 481, 512, 513, 0,
1688 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1689 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1690 816, 0, 540, 541, 572, 573, 0,
1691 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1692 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1693 816, 0, 576, 577, 608, 609, 0,
1694 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1695 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1696 864, 0, 576, 577, 608, 609, 0,
1697 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1698 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1699 896, 0, 600, 601, 632, 633, 0,
1700 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1701 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1702 928, 0, 624, 625, 656, 657, 0,
1703 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1704 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1705 1016, 0, 766, 767, 798, 799, 0,
1706 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1707 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1708 1120, 0, 768, 769, 800, 801, 0,
1709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1710 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1711 1376, 0, 1024, 1025, 1056, 1057, 0,
1712 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1713 };
1714
1715 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1716 {
1717 struct drm_encoder *encoder = intel_attached_encoder(connector);
1718 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1719 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1720 struct intel_sdvo_sdtv_resolution_request tv_res;
1721 uint32_t reply = 0, format_map = 0;
1722 int i;
1723 uint8_t status;
1724
1725
1726 /* Read the list of supported input resolutions for the selected TV
1727 * format.
1728 */
1729 for (i = 0; i < TV_FORMAT_NUM; i++)
1730 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1731 break;
1732
1733 format_map = (1 << i);
1734 memcpy(&tv_res, &format_map,
1735 sizeof(struct intel_sdvo_sdtv_resolution_request) >
1736 sizeof(format_map) ? sizeof(format_map) :
1737 sizeof(struct intel_sdvo_sdtv_resolution_request));
1738
1739 intel_sdvo_set_target_output(intel_encoder, sdvo_priv->attached_output);
1740
1741 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1742 &tv_res, sizeof(tv_res));
1743 status = intel_sdvo_read_response(intel_encoder, &reply, 3);
1744 if (status != SDVO_CMD_STATUS_SUCCESS)
1745 return;
1746
1747 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1748 if (reply & (1 << i)) {
1749 struct drm_display_mode *nmode;
1750 nmode = drm_mode_duplicate(connector->dev,
1751 &sdvo_tv_modes[i]);
1752 if (nmode)
1753 drm_mode_probed_add(connector, nmode);
1754 }
1755
1756 }
1757
1758 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1759 {
1760 struct drm_encoder *encoder = intel_attached_encoder(connector);
1761 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1762 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1763 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1764 struct drm_display_mode *newmode;
1765
1766 /*
1767 * Attempt to get the mode list from DDC.
1768 * Assume that the preferred modes are
1769 * arranged in priority order.
1770 */
1771 intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
1772 if (list_empty(&connector->probed_modes) == false)
1773 goto end;
1774
1775 /* Fetch modes from VBT */
1776 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1777 newmode = drm_mode_duplicate(connector->dev,
1778 dev_priv->sdvo_lvds_vbt_mode);
1779 if (newmode != NULL) {
1780 /* Guarantee the mode is preferred */
1781 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1782 DRM_MODE_TYPE_DRIVER);
1783 drm_mode_probed_add(connector, newmode);
1784 }
1785 }
1786
1787 end:
1788 list_for_each_entry(newmode, &connector->probed_modes, head) {
1789 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1790 sdvo_priv->sdvo_lvds_fixed_mode =
1791 drm_mode_duplicate(connector->dev, newmode);
1792 break;
1793 }
1794 }
1795
1796 }
1797
1798 static int intel_sdvo_get_modes(struct drm_connector *connector)
1799 {
1800 struct intel_connector *intel_connector = to_intel_connector(connector);
1801 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1802
1803 if (IS_TV(sdvo_connector))
1804 intel_sdvo_get_tv_modes(connector);
1805 else if (IS_LVDS(sdvo_connector))
1806 intel_sdvo_get_lvds_modes(connector);
1807 else
1808 intel_sdvo_get_ddc_modes(connector);
1809
1810 if (list_empty(&connector->probed_modes))
1811 return 0;
1812 return 1;
1813 }
1814
1815 static
1816 void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1817 {
1818 struct intel_connector *intel_connector = to_intel_connector(connector);
1819 struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv;
1820 struct drm_device *dev = connector->dev;
1821
1822 if (IS_TV(sdvo_priv)) {
1823 if (sdvo_priv->left_property)
1824 drm_property_destroy(dev, sdvo_priv->left_property);
1825 if (sdvo_priv->right_property)
1826 drm_property_destroy(dev, sdvo_priv->right_property);
1827 if (sdvo_priv->top_property)
1828 drm_property_destroy(dev, sdvo_priv->top_property);
1829 if (sdvo_priv->bottom_property)
1830 drm_property_destroy(dev, sdvo_priv->bottom_property);
1831 if (sdvo_priv->hpos_property)
1832 drm_property_destroy(dev, sdvo_priv->hpos_property);
1833 if (sdvo_priv->vpos_property)
1834 drm_property_destroy(dev, sdvo_priv->vpos_property);
1835 if (sdvo_priv->saturation_property)
1836 drm_property_destroy(dev,
1837 sdvo_priv->saturation_property);
1838 if (sdvo_priv->contrast_property)
1839 drm_property_destroy(dev,
1840 sdvo_priv->contrast_property);
1841 if (sdvo_priv->hue_property)
1842 drm_property_destroy(dev, sdvo_priv->hue_property);
1843 }
1844 if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) {
1845 if (sdvo_priv->brightness_property)
1846 drm_property_destroy(dev,
1847 sdvo_priv->brightness_property);
1848 }
1849 return;
1850 }
1851
1852 static void intel_sdvo_destroy(struct drm_connector *connector)
1853 {
1854 struct intel_connector *intel_connector = to_intel_connector(connector);
1855 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1856
1857 if (sdvo_connector->tv_format_property)
1858 drm_property_destroy(connector->dev,
1859 sdvo_connector->tv_format_property);
1860
1861 intel_sdvo_destroy_enhance_property(connector);
1862 drm_sysfs_connector_remove(connector);
1863 drm_connector_cleanup(connector);
1864 kfree(connector);
1865 }
1866
1867 static int
1868 intel_sdvo_set_property(struct drm_connector *connector,
1869 struct drm_property *property,
1870 uint64_t val)
1871 {
1872 struct drm_encoder *encoder = intel_attached_encoder(connector);
1873 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1874 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1875 struct intel_connector *intel_connector = to_intel_connector(connector);
1876 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1877 struct drm_crtc *crtc = encoder->crtc;
1878 int ret = 0;
1879 bool changed = false;
1880 uint8_t cmd, status;
1881 uint16_t temp_value;
1882
1883 ret = drm_connector_property_set_value(connector, property, val);
1884 if (ret < 0)
1885 goto out;
1886
1887 if (property == sdvo_connector->tv_format_property) {
1888 if (val >= TV_FORMAT_NUM) {
1889 ret = -EINVAL;
1890 goto out;
1891 }
1892 if (sdvo_priv->tv_format_name ==
1893 sdvo_connector->tv_format_supported[val])
1894 goto out;
1895
1896 sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[val];
1897 changed = true;
1898 }
1899
1900 if (IS_TV(sdvo_connector) || IS_LVDS(sdvo_connector)) {
1901 cmd = 0;
1902 temp_value = val;
1903 if (sdvo_connector->left_property == property) {
1904 drm_connector_property_set_value(connector,
1905 sdvo_connector->right_property, val);
1906 if (sdvo_connector->left_margin == temp_value)
1907 goto out;
1908
1909 sdvo_connector->left_margin = temp_value;
1910 sdvo_connector->right_margin = temp_value;
1911 temp_value = sdvo_connector->max_hscan -
1912 sdvo_connector->left_margin;
1913 cmd = SDVO_CMD_SET_OVERSCAN_H;
1914 } else if (sdvo_connector->right_property == property) {
1915 drm_connector_property_set_value(connector,
1916 sdvo_connector->left_property, val);
1917 if (sdvo_connector->right_margin == temp_value)
1918 goto out;
1919
1920 sdvo_connector->left_margin = temp_value;
1921 sdvo_connector->right_margin = temp_value;
1922 temp_value = sdvo_connector->max_hscan -
1923 sdvo_connector->left_margin;
1924 cmd = SDVO_CMD_SET_OVERSCAN_H;
1925 } else if (sdvo_connector->top_property == property) {
1926 drm_connector_property_set_value(connector,
1927 sdvo_connector->bottom_property, val);
1928 if (sdvo_connector->top_margin == temp_value)
1929 goto out;
1930
1931 sdvo_connector->top_margin = temp_value;
1932 sdvo_connector->bottom_margin = temp_value;
1933 temp_value = sdvo_connector->max_vscan -
1934 sdvo_connector->top_margin;
1935 cmd = SDVO_CMD_SET_OVERSCAN_V;
1936 } else if (sdvo_connector->bottom_property == property) {
1937 drm_connector_property_set_value(connector,
1938 sdvo_connector->top_property, val);
1939 if (sdvo_connector->bottom_margin == temp_value)
1940 goto out;
1941 sdvo_connector->top_margin = temp_value;
1942 sdvo_connector->bottom_margin = temp_value;
1943 temp_value = sdvo_connector->max_vscan -
1944 sdvo_connector->top_margin;
1945 cmd = SDVO_CMD_SET_OVERSCAN_V;
1946 } else if (sdvo_connector->hpos_property == property) {
1947 if (sdvo_connector->cur_hpos == temp_value)
1948 goto out;
1949
1950 cmd = SDVO_CMD_SET_POSITION_H;
1951 sdvo_connector->cur_hpos = temp_value;
1952 } else if (sdvo_connector->vpos_property == property) {
1953 if (sdvo_connector->cur_vpos == temp_value)
1954 goto out;
1955
1956 cmd = SDVO_CMD_SET_POSITION_V;
1957 sdvo_connector->cur_vpos = temp_value;
1958 } else if (sdvo_connector->saturation_property == property) {
1959 if (sdvo_connector->cur_saturation == temp_value)
1960 goto out;
1961
1962 cmd = SDVO_CMD_SET_SATURATION;
1963 sdvo_connector->cur_saturation = temp_value;
1964 } else if (sdvo_connector->contrast_property == property) {
1965 if (sdvo_connector->cur_contrast == temp_value)
1966 goto out;
1967
1968 cmd = SDVO_CMD_SET_CONTRAST;
1969 sdvo_connector->cur_contrast = temp_value;
1970 } else if (sdvo_connector->hue_property == property) {
1971 if (sdvo_connector->cur_hue == temp_value)
1972 goto out;
1973
1974 cmd = SDVO_CMD_SET_HUE;
1975 sdvo_connector->cur_hue = temp_value;
1976 } else if (sdvo_connector->brightness_property == property) {
1977 if (sdvo_connector->cur_brightness == temp_value)
1978 goto out;
1979
1980 cmd = SDVO_CMD_SET_BRIGHTNESS;
1981 sdvo_connector->cur_brightness = temp_value;
1982 }
1983 if (cmd) {
1984 intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2);
1985 status = intel_sdvo_read_response(intel_encoder,
1986 NULL, 0);
1987 if (status != SDVO_CMD_STATUS_SUCCESS) {
1988 DRM_DEBUG_KMS("Incorrect SDVO command \n");
1989 return -EINVAL;
1990 }
1991 changed = true;
1992 }
1993 }
1994 if (changed && crtc)
1995 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1996 crtc->y, crtc->fb);
1997 out:
1998 return ret;
1999 }
2000
2001 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
2002 .dpms = intel_sdvo_dpms,
2003 .mode_fixup = intel_sdvo_mode_fixup,
2004 .prepare = intel_encoder_prepare,
2005 .mode_set = intel_sdvo_mode_set,
2006 .commit = intel_encoder_commit,
2007 };
2008
2009 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2010 .dpms = drm_helper_connector_dpms,
2011 .detect = intel_sdvo_detect,
2012 .fill_modes = drm_helper_probe_single_connector_modes,
2013 .set_property = intel_sdvo_set_property,
2014 .destroy = intel_sdvo_destroy,
2015 };
2016
2017 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2018 .get_modes = intel_sdvo_get_modes,
2019 .mode_valid = intel_sdvo_mode_valid,
2020 .best_encoder = intel_attached_encoder,
2021 };
2022
2023 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2024 {
2025 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2026 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2027
2028 if (intel_encoder->i2c_bus)
2029 intel_i2c_destroy(intel_encoder->i2c_bus);
2030 if (intel_encoder->ddc_bus)
2031 intel_i2c_destroy(intel_encoder->ddc_bus);
2032 if (sdvo_priv->analog_ddc_bus)
2033 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2034
2035 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
2036 drm_mode_destroy(encoder->dev,
2037 sdvo_priv->sdvo_lvds_fixed_mode);
2038
2039 drm_encoder_cleanup(encoder);
2040 kfree(intel_encoder);
2041 }
2042
2043 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2044 .destroy = intel_sdvo_enc_destroy,
2045 };
2046
2047
2048 /**
2049 * Choose the appropriate DDC bus for control bus switch command for this
2050 * SDVO output based on the controlled output.
2051 *
2052 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2053 * outputs, then LVDS outputs.
2054 */
2055 static void
2056 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2057 struct intel_sdvo_priv *sdvo, u32 reg)
2058 {
2059 struct sdvo_device_mapping *mapping;
2060
2061 if (IS_SDVOB(reg))
2062 mapping = &(dev_priv->sdvo_mappings[0]);
2063 else
2064 mapping = &(dev_priv->sdvo_mappings[1]);
2065
2066 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2067 }
2068
2069 static bool
2070 intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output, int device)
2071 {
2072 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2073 uint8_t status;
2074
2075 if (device == 0)
2076 intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS0);
2077 else
2078 intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS1);
2079
2080 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2081 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2082 if (status != SDVO_CMD_STATUS_SUCCESS)
2083 return false;
2084 return true;
2085 }
2086
2087 static struct intel_encoder *
2088 intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan)
2089 {
2090 struct drm_device *dev = chan->drm_dev;
2091 struct drm_encoder *encoder;
2092 struct intel_encoder *intel_encoder = NULL;
2093
2094 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2095 intel_encoder = enc_to_intel_encoder(encoder);
2096 if (intel_encoder->ddc_bus == &chan->adapter)
2097 break;
2098 }
2099 return intel_encoder;
2100 }
2101
2102 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2103 struct i2c_msg msgs[], int num)
2104 {
2105 struct intel_encoder *intel_encoder;
2106 struct intel_sdvo_priv *sdvo_priv;
2107 struct i2c_algo_bit_data *algo_data;
2108 const struct i2c_algorithm *algo;
2109
2110 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
2111 intel_encoder =
2112 intel_sdvo_chan_to_intel_encoder(
2113 (struct intel_i2c_chan *)(algo_data->data));
2114 if (intel_encoder == NULL)
2115 return -EINVAL;
2116
2117 sdvo_priv = intel_encoder->dev_priv;
2118 algo = intel_encoder->i2c_bus->algo;
2119
2120 intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus);
2121 return algo->master_xfer(i2c_adap, msgs, num);
2122 }
2123
2124 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2125 .master_xfer = intel_sdvo_master_xfer,
2126 };
2127
2128 static u8
2129 intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
2130 {
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct sdvo_device_mapping *my_mapping, *other_mapping;
2133
2134 if (IS_SDVOB(sdvo_reg)) {
2135 my_mapping = &dev_priv->sdvo_mappings[0];
2136 other_mapping = &dev_priv->sdvo_mappings[1];
2137 } else {
2138 my_mapping = &dev_priv->sdvo_mappings[1];
2139 other_mapping = &dev_priv->sdvo_mappings[0];
2140 }
2141
2142 /* If the BIOS described our SDVO device, take advantage of it. */
2143 if (my_mapping->slave_addr)
2144 return my_mapping->slave_addr;
2145
2146 /* If the BIOS only described a different SDVO device, use the
2147 * address that it isn't using.
2148 */
2149 if (other_mapping->slave_addr) {
2150 if (other_mapping->slave_addr == 0x70)
2151 return 0x72;
2152 else
2153 return 0x70;
2154 }
2155
2156 /* No SDVO device info is found for another DVO port,
2157 * so use mapping assumption we had before BIOS parsing.
2158 */
2159 if (IS_SDVOB(sdvo_reg))
2160 return 0x70;
2161 else
2162 return 0x72;
2163 }
2164
2165 static bool
2166 intel_sdvo_connector_alloc (struct intel_connector **ret)
2167 {
2168 struct intel_connector *intel_connector;
2169 struct intel_sdvo_connector *sdvo_connector;
2170
2171 *ret = kzalloc(sizeof(*intel_connector) +
2172 sizeof(*sdvo_connector), GFP_KERNEL);
2173 if (!*ret)
2174 return false;
2175
2176 intel_connector = *ret;
2177 sdvo_connector = (struct intel_sdvo_connector *)(intel_connector + 1);
2178 intel_connector->dev_priv = sdvo_connector;
2179
2180 return true;
2181 }
2182
2183 static void
2184 intel_sdvo_connector_create (struct drm_encoder *encoder,
2185 struct drm_connector *connector)
2186 {
2187 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
2188 connector->connector_type);
2189
2190 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2191
2192 connector->interlace_allowed = 0;
2193 connector->doublescan_allowed = 0;
2194 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2195
2196 drm_mode_connector_attach_encoder(connector, encoder);
2197 drm_sysfs_connector_add(connector);
2198 }
2199
2200 static bool
2201 intel_sdvo_dvi_init(struct intel_encoder *intel_encoder, int device)
2202 {
2203 struct drm_encoder *encoder = &intel_encoder->enc;
2204 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2205 struct drm_connector *connector;
2206 struct intel_connector *intel_connector;
2207 struct intel_sdvo_connector *sdvo_connector;
2208
2209 if (!intel_sdvo_connector_alloc(&intel_connector))
2210 return false;
2211
2212 sdvo_connector = intel_connector->dev_priv;
2213
2214 if (device == 0) {
2215 sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS0;
2216 sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2217 } else if (device == 1) {
2218 sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS1;
2219 sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2220 }
2221
2222 connector = &intel_connector->base;
2223 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2224 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2225 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2226
2227 if (intel_sdvo_get_supp_encode(intel_encoder, &sdvo_priv->encode)
2228 && intel_sdvo_get_digital_encoding_mode(intel_encoder, device)
2229 && sdvo_priv->is_hdmi) {
2230 /* enable hdmi encoding mode if supported */
2231 intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI);
2232 intel_sdvo_set_colorimetry(intel_encoder,
2233 SDVO_COLORIMETRY_RGB256);
2234 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2235 }
2236 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2237 (1 << INTEL_ANALOG_CLONE_BIT);
2238
2239 intel_sdvo_connector_create(encoder, connector);
2240
2241 return true;
2242 }
2243
2244 static bool
2245 intel_sdvo_tv_init(struct intel_encoder *intel_encoder, int type)
2246 {
2247 struct drm_encoder *encoder = &intel_encoder->enc;
2248 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2249 struct drm_connector *connector;
2250 struct intel_connector *intel_connector;
2251 struct intel_sdvo_connector *sdvo_connector;
2252
2253 if (!intel_sdvo_connector_alloc(&intel_connector))
2254 return false;
2255
2256 connector = &intel_connector->base;
2257 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2258 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2259 sdvo_connector = intel_connector->dev_priv;
2260
2261 sdvo_priv->controlled_output |= type;
2262 sdvo_connector->output_flag = type;
2263
2264 sdvo_priv->is_tv = true;
2265 intel_encoder->needs_tv_clock = true;
2266 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2267
2268 intel_sdvo_connector_create(encoder, connector);
2269
2270 intel_sdvo_tv_create_property(connector, type);
2271
2272 intel_sdvo_create_enhance_property(connector);
2273
2274 return true;
2275 }
2276
2277 static bool
2278 intel_sdvo_analog_init(struct intel_encoder *intel_encoder, int device)
2279 {
2280 struct drm_encoder *encoder = &intel_encoder->enc;
2281 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2282 struct drm_connector *connector;
2283 struct intel_connector *intel_connector;
2284 struct intel_sdvo_connector *sdvo_connector;
2285
2286 if (!intel_sdvo_connector_alloc(&intel_connector))
2287 return false;
2288
2289 connector = &intel_connector->base;
2290 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2291 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2292 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2293 sdvo_connector = intel_connector->dev_priv;
2294
2295 if (device == 0) {
2296 sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB0;
2297 sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2298 } else if (device == 1) {
2299 sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB1;
2300 sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2301 }
2302
2303 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2304 (1 << INTEL_ANALOG_CLONE_BIT);
2305
2306 intel_sdvo_connector_create(encoder, connector);
2307 return true;
2308 }
2309
2310 static bool
2311 intel_sdvo_lvds_init(struct intel_encoder *intel_encoder, int device)
2312 {
2313 struct drm_encoder *encoder = &intel_encoder->enc;
2314 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2315 struct drm_connector *connector;
2316 struct intel_connector *intel_connector;
2317 struct intel_sdvo_connector *sdvo_connector;
2318
2319 if (!intel_sdvo_connector_alloc(&intel_connector))
2320 return false;
2321
2322 connector = &intel_connector->base;
2323 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2324 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2325 sdvo_connector = intel_connector->dev_priv;
2326
2327 sdvo_priv->is_lvds = true;
2328
2329 if (device == 0) {
2330 sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS0;
2331 sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2332 } else if (device == 1) {
2333 sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS1;
2334 sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2335 }
2336
2337 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2338 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2339
2340 intel_sdvo_connector_create(encoder, connector);
2341 intel_sdvo_create_enhance_property(connector);
2342 return true;
2343 }
2344
2345 static bool
2346 intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags)
2347 {
2348 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2349
2350 sdvo_priv->is_tv = false;
2351 intel_encoder->needs_tv_clock = false;
2352 sdvo_priv->is_lvds = false;
2353
2354 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2355
2356 if (flags & SDVO_OUTPUT_TMDS0)
2357 if (!intel_sdvo_dvi_init(intel_encoder, 0))
2358 return false;
2359
2360 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2361 if (!intel_sdvo_dvi_init(intel_encoder, 1))
2362 return false;
2363
2364 /* TV has no XXX1 function block */
2365 if (flags & SDVO_OUTPUT_SVID0)
2366 if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_SVID0))
2367 return false;
2368
2369 if (flags & SDVO_OUTPUT_CVBS0)
2370 if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_CVBS0))
2371 return false;
2372
2373 if (flags & SDVO_OUTPUT_RGB0)
2374 if (!intel_sdvo_analog_init(intel_encoder, 0))
2375 return false;
2376
2377 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2378 if (!intel_sdvo_analog_init(intel_encoder, 1))
2379 return false;
2380
2381 if (flags & SDVO_OUTPUT_LVDS0)
2382 if (!intel_sdvo_lvds_init(intel_encoder, 0))
2383 return false;
2384
2385 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2386 if (!intel_sdvo_lvds_init(intel_encoder, 1))
2387 return false;
2388
2389 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2390 unsigned char bytes[2];
2391
2392 sdvo_priv->controlled_output = 0;
2393 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
2394 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2395 SDVO_NAME(sdvo_priv),
2396 bytes[0], bytes[1]);
2397 return false;
2398 }
2399 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2400
2401 return true;
2402 }
2403
2404 static void intel_sdvo_tv_create_property(struct drm_connector *connector, int type)
2405 {
2406 struct drm_encoder *encoder = intel_attached_encoder(connector);
2407 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2408 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2409 struct intel_connector *intel_connector = to_intel_connector(connector);
2410 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
2411 struct intel_sdvo_tv_format format;
2412 uint32_t format_map, i;
2413 uint8_t status;
2414
2415 intel_sdvo_set_target_output(intel_encoder, type);
2416
2417 intel_sdvo_write_cmd(intel_encoder,
2418 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
2419 status = intel_sdvo_read_response(intel_encoder,
2420 &format, sizeof(format));
2421 if (status != SDVO_CMD_STATUS_SUCCESS)
2422 return;
2423
2424 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2425 sizeof(format_map) : sizeof(format));
2426
2427 if (format_map == 0)
2428 return;
2429
2430 sdvo_connector->format_supported_num = 0;
2431 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2432 if (format_map & (1 << i)) {
2433 sdvo_connector->tv_format_supported
2434 [sdvo_connector->format_supported_num++] =
2435 tv_format_names[i];
2436 }
2437
2438
2439 sdvo_connector->tv_format_property =
2440 drm_property_create(
2441 connector->dev, DRM_MODE_PROP_ENUM,
2442 "mode", sdvo_connector->format_supported_num);
2443
2444 for (i = 0; i < sdvo_connector->format_supported_num; i++)
2445 drm_property_add_enum(
2446 sdvo_connector->tv_format_property, i,
2447 i, sdvo_connector->tv_format_supported[i]);
2448
2449 sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[0];
2450 drm_connector_attach_property(
2451 connector, sdvo_connector->tv_format_property, 0);
2452
2453 }
2454
2455 static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2456 {
2457 struct drm_encoder *encoder = intel_attached_encoder(connector);
2458 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2459 struct intel_connector *intel_connector = to_intel_connector(connector);
2460 struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv;
2461 struct intel_sdvo_enhancements_reply sdvo_data;
2462 struct drm_device *dev = connector->dev;
2463 uint8_t status;
2464 uint16_t response, data_value[2];
2465
2466 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2467 NULL, 0);
2468 status = intel_sdvo_read_response(intel_encoder, &sdvo_data,
2469 sizeof(sdvo_data));
2470 if (status != SDVO_CMD_STATUS_SUCCESS) {
2471 DRM_DEBUG_KMS(" incorrect response is returned\n");
2472 return;
2473 }
2474 response = *((uint16_t *)&sdvo_data);
2475 if (!response) {
2476 DRM_DEBUG_KMS("No enhancement is supported\n");
2477 return;
2478 }
2479 if (IS_TV(sdvo_priv)) {
2480 /* when horizontal overscan is supported, Add the left/right
2481 * property
2482 */
2483 if (sdvo_data.overscan_h) {
2484 intel_sdvo_write_cmd(intel_encoder,
2485 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
2486 status = intel_sdvo_read_response(intel_encoder,
2487 &data_value, 4);
2488 if (status != SDVO_CMD_STATUS_SUCCESS) {
2489 DRM_DEBUG_KMS("Incorrect SDVO max "
2490 "h_overscan\n");
2491 return;
2492 }
2493 intel_sdvo_write_cmd(intel_encoder,
2494 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
2495 status = intel_sdvo_read_response(intel_encoder,
2496 &response, 2);
2497 if (status != SDVO_CMD_STATUS_SUCCESS) {
2498 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2499 return;
2500 }
2501 sdvo_priv->max_hscan = data_value[0];
2502 sdvo_priv->left_margin = data_value[0] - response;
2503 sdvo_priv->right_margin = sdvo_priv->left_margin;
2504 sdvo_priv->left_property =
2505 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2506 "left_margin", 2);
2507 sdvo_priv->left_property->values[0] = 0;
2508 sdvo_priv->left_property->values[1] = data_value[0];
2509 drm_connector_attach_property(connector,
2510 sdvo_priv->left_property,
2511 sdvo_priv->left_margin);
2512 sdvo_priv->right_property =
2513 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2514 "right_margin", 2);
2515 sdvo_priv->right_property->values[0] = 0;
2516 sdvo_priv->right_property->values[1] = data_value[0];
2517 drm_connector_attach_property(connector,
2518 sdvo_priv->right_property,
2519 sdvo_priv->right_margin);
2520 DRM_DEBUG_KMS("h_overscan: max %d, "
2521 "default %d, current %d\n",
2522 data_value[0], data_value[1], response);
2523 }
2524 if (sdvo_data.overscan_v) {
2525 intel_sdvo_write_cmd(intel_encoder,
2526 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
2527 status = intel_sdvo_read_response(intel_encoder,
2528 &data_value, 4);
2529 if (status != SDVO_CMD_STATUS_SUCCESS) {
2530 DRM_DEBUG_KMS("Incorrect SDVO max "
2531 "v_overscan\n");
2532 return;
2533 }
2534 intel_sdvo_write_cmd(intel_encoder,
2535 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
2536 status = intel_sdvo_read_response(intel_encoder,
2537 &response, 2);
2538 if (status != SDVO_CMD_STATUS_SUCCESS) {
2539 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2540 return;
2541 }
2542 sdvo_priv->max_vscan = data_value[0];
2543 sdvo_priv->top_margin = data_value[0] - response;
2544 sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2545 sdvo_priv->top_property =
2546 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2547 "top_margin", 2);
2548 sdvo_priv->top_property->values[0] = 0;
2549 sdvo_priv->top_property->values[1] = data_value[0];
2550 drm_connector_attach_property(connector,
2551 sdvo_priv->top_property,
2552 sdvo_priv->top_margin);
2553 sdvo_priv->bottom_property =
2554 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2555 "bottom_margin", 2);
2556 sdvo_priv->bottom_property->values[0] = 0;
2557 sdvo_priv->bottom_property->values[1] = data_value[0];
2558 drm_connector_attach_property(connector,
2559 sdvo_priv->bottom_property,
2560 sdvo_priv->bottom_margin);
2561 DRM_DEBUG_KMS("v_overscan: max %d, "
2562 "default %d, current %d\n",
2563 data_value[0], data_value[1], response);
2564 }
2565 if (sdvo_data.position_h) {
2566 intel_sdvo_write_cmd(intel_encoder,
2567 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
2568 status = intel_sdvo_read_response(intel_encoder,
2569 &data_value, 4);
2570 if (status != SDVO_CMD_STATUS_SUCCESS) {
2571 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2572 return;
2573 }
2574 intel_sdvo_write_cmd(intel_encoder,
2575 SDVO_CMD_GET_POSITION_H, NULL, 0);
2576 status = intel_sdvo_read_response(intel_encoder,
2577 &response, 2);
2578 if (status != SDVO_CMD_STATUS_SUCCESS) {
2579 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2580 return;
2581 }
2582 sdvo_priv->max_hpos = data_value[0];
2583 sdvo_priv->cur_hpos = response;
2584 sdvo_priv->hpos_property =
2585 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2586 "hpos", 2);
2587 sdvo_priv->hpos_property->values[0] = 0;
2588 sdvo_priv->hpos_property->values[1] = data_value[0];
2589 drm_connector_attach_property(connector,
2590 sdvo_priv->hpos_property,
2591 sdvo_priv->cur_hpos);
2592 DRM_DEBUG_KMS("h_position: max %d, "
2593 "default %d, current %d\n",
2594 data_value[0], data_value[1], response);
2595 }
2596 if (sdvo_data.position_v) {
2597 intel_sdvo_write_cmd(intel_encoder,
2598 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
2599 status = intel_sdvo_read_response(intel_encoder,
2600 &data_value, 4);
2601 if (status != SDVO_CMD_STATUS_SUCCESS) {
2602 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2603 return;
2604 }
2605 intel_sdvo_write_cmd(intel_encoder,
2606 SDVO_CMD_GET_POSITION_V, NULL, 0);
2607 status = intel_sdvo_read_response(intel_encoder,
2608 &response, 2);
2609 if (status != SDVO_CMD_STATUS_SUCCESS) {
2610 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2611 return;
2612 }
2613 sdvo_priv->max_vpos = data_value[0];
2614 sdvo_priv->cur_vpos = response;
2615 sdvo_priv->vpos_property =
2616 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2617 "vpos", 2);
2618 sdvo_priv->vpos_property->values[0] = 0;
2619 sdvo_priv->vpos_property->values[1] = data_value[0];
2620 drm_connector_attach_property(connector,
2621 sdvo_priv->vpos_property,
2622 sdvo_priv->cur_vpos);
2623 DRM_DEBUG_KMS("v_position: max %d, "
2624 "default %d, current %d\n",
2625 data_value[0], data_value[1], response);
2626 }
2627 if (sdvo_data.saturation) {
2628 intel_sdvo_write_cmd(intel_encoder,
2629 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
2630 status = intel_sdvo_read_response(intel_encoder,
2631 &data_value, 4);
2632 if (status != SDVO_CMD_STATUS_SUCCESS) {
2633 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2634 return;
2635 }
2636 intel_sdvo_write_cmd(intel_encoder,
2637 SDVO_CMD_GET_SATURATION, NULL, 0);
2638 status = intel_sdvo_read_response(intel_encoder,
2639 &response, 2);
2640 if (status != SDVO_CMD_STATUS_SUCCESS) {
2641 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2642 return;
2643 }
2644 sdvo_priv->max_saturation = data_value[0];
2645 sdvo_priv->cur_saturation = response;
2646 sdvo_priv->saturation_property =
2647 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2648 "saturation", 2);
2649 sdvo_priv->saturation_property->values[0] = 0;
2650 sdvo_priv->saturation_property->values[1] =
2651 data_value[0];
2652 drm_connector_attach_property(connector,
2653 sdvo_priv->saturation_property,
2654 sdvo_priv->cur_saturation);
2655 DRM_DEBUG_KMS("saturation: max %d, "
2656 "default %d, current %d\n",
2657 data_value[0], data_value[1], response);
2658 }
2659 if (sdvo_data.contrast) {
2660 intel_sdvo_write_cmd(intel_encoder,
2661 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
2662 status = intel_sdvo_read_response(intel_encoder,
2663 &data_value, 4);
2664 if (status != SDVO_CMD_STATUS_SUCCESS) {
2665 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2666 return;
2667 }
2668 intel_sdvo_write_cmd(intel_encoder,
2669 SDVO_CMD_GET_CONTRAST, NULL, 0);
2670 status = intel_sdvo_read_response(intel_encoder,
2671 &response, 2);
2672 if (status != SDVO_CMD_STATUS_SUCCESS) {
2673 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2674 return;
2675 }
2676 sdvo_priv->max_contrast = data_value[0];
2677 sdvo_priv->cur_contrast = response;
2678 sdvo_priv->contrast_property =
2679 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2680 "contrast", 2);
2681 sdvo_priv->contrast_property->values[0] = 0;
2682 sdvo_priv->contrast_property->values[1] = data_value[0];
2683 drm_connector_attach_property(connector,
2684 sdvo_priv->contrast_property,
2685 sdvo_priv->cur_contrast);
2686 DRM_DEBUG_KMS("contrast: max %d, "
2687 "default %d, current %d\n",
2688 data_value[0], data_value[1], response);
2689 }
2690 if (sdvo_data.hue) {
2691 intel_sdvo_write_cmd(intel_encoder,
2692 SDVO_CMD_GET_MAX_HUE, NULL, 0);
2693 status = intel_sdvo_read_response(intel_encoder,
2694 &data_value, 4);
2695 if (status != SDVO_CMD_STATUS_SUCCESS) {
2696 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2697 return;
2698 }
2699 intel_sdvo_write_cmd(intel_encoder,
2700 SDVO_CMD_GET_HUE, NULL, 0);
2701 status = intel_sdvo_read_response(intel_encoder,
2702 &response, 2);
2703 if (status != SDVO_CMD_STATUS_SUCCESS) {
2704 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2705 return;
2706 }
2707 sdvo_priv->max_hue = data_value[0];
2708 sdvo_priv->cur_hue = response;
2709 sdvo_priv->hue_property =
2710 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2711 "hue", 2);
2712 sdvo_priv->hue_property->values[0] = 0;
2713 sdvo_priv->hue_property->values[1] =
2714 data_value[0];
2715 drm_connector_attach_property(connector,
2716 sdvo_priv->hue_property,
2717 sdvo_priv->cur_hue);
2718 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2719 data_value[0], data_value[1], response);
2720 }
2721 }
2722 if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) {
2723 if (sdvo_data.brightness) {
2724 intel_sdvo_write_cmd(intel_encoder,
2725 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
2726 status = intel_sdvo_read_response(intel_encoder,
2727 &data_value, 4);
2728 if (status != SDVO_CMD_STATUS_SUCCESS) {
2729 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2730 return;
2731 }
2732 intel_sdvo_write_cmd(intel_encoder,
2733 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
2734 status = intel_sdvo_read_response(intel_encoder,
2735 &response, 2);
2736 if (status != SDVO_CMD_STATUS_SUCCESS) {
2737 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2738 return;
2739 }
2740 sdvo_priv->max_brightness = data_value[0];
2741 sdvo_priv->cur_brightness = response;
2742 sdvo_priv->brightness_property =
2743 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2744 "brightness", 2);
2745 sdvo_priv->brightness_property->values[0] = 0;
2746 sdvo_priv->brightness_property->values[1] =
2747 data_value[0];
2748 drm_connector_attach_property(connector,
2749 sdvo_priv->brightness_property,
2750 sdvo_priv->cur_brightness);
2751 DRM_DEBUG_KMS("brightness: max %d, "
2752 "default %d, current %d\n",
2753 data_value[0], data_value[1], response);
2754 }
2755 }
2756 return;
2757 }
2758
2759 bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2760 {
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762 struct intel_encoder *intel_encoder;
2763 struct intel_sdvo_priv *sdvo_priv;
2764 u8 ch[0x40];
2765 int i;
2766 u32 i2c_reg, ddc_reg, analog_ddc_reg;
2767
2768 intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2769 if (!intel_encoder) {
2770 return false;
2771 }
2772
2773 sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1);
2774 sdvo_priv->sdvo_reg = sdvo_reg;
2775
2776 intel_encoder->dev_priv = sdvo_priv;
2777 intel_encoder->type = INTEL_OUTPUT_SDVO;
2778
2779 if (HAS_PCH_SPLIT(dev)) {
2780 i2c_reg = PCH_GPIOE;
2781 ddc_reg = PCH_GPIOE;
2782 analog_ddc_reg = PCH_GPIOA;
2783 } else {
2784 i2c_reg = GPIOE;
2785 ddc_reg = GPIOE;
2786 analog_ddc_reg = GPIOA;
2787 }
2788
2789 /* setup the DDC bus. */
2790 if (IS_SDVOB(sdvo_reg))
2791 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
2792 else
2793 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
2794
2795 if (!intel_encoder->i2c_bus)
2796 goto err_inteloutput;
2797
2798 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
2799
2800 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2801 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
2802
2803 /* Read the regs to test if we can talk to the device */
2804 for (i = 0; i < 0x40; i++) {
2805 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) {
2806 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2807 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2808 goto err_i2c;
2809 }
2810 }
2811
2812 /* setup the DDC bus. */
2813 if (IS_SDVOB(sdvo_reg)) {
2814 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
2815 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
2816 "SDVOB/VGA DDC BUS");
2817 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2818 } else {
2819 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
2820 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
2821 "SDVOC/VGA DDC BUS");
2822 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2823 }
2824
2825 if (intel_encoder->ddc_bus == NULL)
2826 goto err_i2c;
2827
2828 /* Wrap with our custom algo which switches to DDC mode */
2829 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2830
2831 /* encoder type will be decided later */
2832 drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0);
2833 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2834
2835 /* In default case sdvo lvds is false */
2836 intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps);
2837
2838 if (intel_sdvo_output_setup(intel_encoder,
2839 sdvo_priv->caps.output_flags) != true) {
2840 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2841 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2842 goto err_i2c;
2843 }
2844
2845 intel_sdvo_select_ddc_bus(dev_priv, sdvo_priv, sdvo_reg);
2846
2847 /* Set the input timing to the screen. Assume always input 0. */
2848 intel_sdvo_set_target_input(intel_encoder, true, false);
2849
2850 intel_sdvo_get_input_pixel_clock_range(intel_encoder,
2851 &sdvo_priv->pixel_clock_min,
2852 &sdvo_priv->pixel_clock_max);
2853
2854
2855 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2856 "clock range %dMHz - %dMHz, "
2857 "input 1: %c, input 2: %c, "
2858 "output 1: %c, output 2: %c\n",
2859 SDVO_NAME(sdvo_priv),
2860 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2861 sdvo_priv->caps.device_rev_id,
2862 sdvo_priv->pixel_clock_min / 1000,
2863 sdvo_priv->pixel_clock_max / 1000,
2864 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2865 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2866 /* check currently supported outputs */
2867 sdvo_priv->caps.output_flags &
2868 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2869 sdvo_priv->caps.output_flags &
2870 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2871
2872 return true;
2873
2874 err_i2c:
2875 if (sdvo_priv->analog_ddc_bus != NULL)
2876 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2877 if (intel_encoder->ddc_bus != NULL)
2878 intel_i2c_destroy(intel_encoder->ddc_bus);
2879 if (intel_encoder->i2c_bus != NULL)
2880 intel_i2c_destroy(intel_encoder->i2c_bus);
2881 err_inteloutput:
2882 kfree(intel_encoder);
2883
2884 return false;
2885 }
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