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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/export.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_sdvo_regs.h"
40
41 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
44 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
45
46 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
47 SDVO_TV_MASK)
48
49 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
50 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
51 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
52 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
53 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
54
55
56 static const char *tv_format_names[] = {
57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64 };
65
66 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
68 struct intel_sdvo {
69 struct intel_encoder base;
70
71 struct i2c_adapter *i2c;
72 u8 slave_addr;
73
74 struct i2c_adapter ddc;
75
76 /* Register for the SDVO device: SDVOB or SDVOC */
77 uint32_t sdvo_reg;
78
79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
81
82 /*
83 * Capabilities of the SDVO device returned by
84 * intel_sdvo_get_capabilities()
85 */
86 struct intel_sdvo_caps caps;
87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
89 int pixel_clock_min, pixel_clock_max;
90
91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
97 /*
98 * Hotplug activation bits for this device
99 */
100 uint16_t hotplug_active;
101
102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107 bool color_range_auto;
108
109 /**
110 * This is set if we're going to treat the device as TV-out.
111 *
112 * While we have these nice friendly flags for output types that ought
113 * to decide this for us, the S-Video output on our HDMI+S-Video card
114 * shows up as RGB1 (VGA).
115 */
116 bool is_tv;
117
118 /* On different gens SDVOB is at different places. */
119 bool is_sdvob;
120
121 /* This is for current tv format name */
122 int tv_format_index;
123
124 /**
125 * This is set if we treat the device as HDMI, instead of DVI.
126 */
127 bool is_hdmi;
128 bool has_hdmi_monitor;
129 bool has_hdmi_audio;
130 bool rgb_quant_range_selectable;
131
132 /**
133 * This is set if we detect output of sdvo device as LVDS and
134 * have a valid fixed mode to use with the panel.
135 */
136 bool is_lvds;
137
138 /**
139 * This is sdvo fixed pannel mode pointer
140 */
141 struct drm_display_mode *sdvo_lvds_fixed_mode;
142
143 /* DDC bus used by this SDVO encoder */
144 uint8_t ddc_bus;
145
146 /*
147 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
148 */
149 uint8_t dtd_sdvo_flags;
150 };
151
152 struct intel_sdvo_connector {
153 struct intel_connector base;
154
155 /* Mark the type of connector */
156 uint16_t output_flag;
157
158 enum hdmi_force_audio force_audio;
159
160 /* This contains all current supported TV format */
161 u8 tv_format_supported[TV_FORMAT_NUM];
162 int format_supported_num;
163 struct drm_property *tv_format;
164
165 /* add the property for the SDVO-TV */
166 struct drm_property *left;
167 struct drm_property *right;
168 struct drm_property *top;
169 struct drm_property *bottom;
170 struct drm_property *hpos;
171 struct drm_property *vpos;
172 struct drm_property *contrast;
173 struct drm_property *saturation;
174 struct drm_property *hue;
175 struct drm_property *sharpness;
176 struct drm_property *flicker_filter;
177 struct drm_property *flicker_filter_adaptive;
178 struct drm_property *flicker_filter_2d;
179 struct drm_property *tv_chroma_filter;
180 struct drm_property *tv_luma_filter;
181 struct drm_property *dot_crawl;
182
183 /* add the property for the SDVO-TV/LVDS */
184 struct drm_property *brightness;
185
186 /* Add variable to record current setting for the above property */
187 u32 left_margin, right_margin, top_margin, bottom_margin;
188
189 /* this is to get the range of margin.*/
190 u32 max_hscan, max_vscan;
191 u32 max_hpos, cur_hpos;
192 u32 max_vpos, cur_vpos;
193 u32 cur_brightness, max_brightness;
194 u32 cur_contrast, max_contrast;
195 u32 cur_saturation, max_saturation;
196 u32 cur_hue, max_hue;
197 u32 cur_sharpness, max_sharpness;
198 u32 cur_flicker_filter, max_flicker_filter;
199 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
200 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
201 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
202 u32 cur_tv_luma_filter, max_tv_luma_filter;
203 u32 cur_dot_crawl, max_dot_crawl;
204 };
205
206 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
207 {
208 return container_of(encoder, struct intel_sdvo, base);
209 }
210
211 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
212 {
213 return to_sdvo(intel_attached_encoder(connector));
214 }
215
216 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
217 {
218 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
219 }
220
221 static bool
222 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
223 static bool
224 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
225 struct intel_sdvo_connector *intel_sdvo_connector,
226 int type);
227 static bool
228 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
229 struct intel_sdvo_connector *intel_sdvo_connector);
230
231 /**
232 * Writes the SDVOB or SDVOC with the given value, but always writes both
233 * SDVOB and SDVOC to work around apparent hardware issues (according to
234 * comments in the BIOS).
235 */
236 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
237 {
238 struct drm_device *dev = intel_sdvo->base.base.dev;
239 struct drm_i915_private *dev_priv = dev->dev_private;
240 u32 bval = val, cval = val;
241 int i;
242
243 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
244 I915_WRITE(intel_sdvo->sdvo_reg, val);
245 I915_READ(intel_sdvo->sdvo_reg);
246 return;
247 }
248
249 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
250 cval = I915_READ(GEN3_SDVOC);
251 else
252 bval = I915_READ(GEN3_SDVOB);
253
254 /*
255 * Write the registers twice for luck. Sometimes,
256 * writing them only once doesn't appear to 'stick'.
257 * The BIOS does this too. Yay, magic
258 */
259 for (i = 0; i < 2; i++)
260 {
261 I915_WRITE(GEN3_SDVOB, bval);
262 I915_READ(GEN3_SDVOB);
263 I915_WRITE(GEN3_SDVOC, cval);
264 I915_READ(GEN3_SDVOC);
265 }
266 }
267
268 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
269 {
270 struct i2c_msg msgs[] = {
271 {
272 .addr = intel_sdvo->slave_addr,
273 .flags = 0,
274 .len = 1,
275 .buf = &addr,
276 },
277 {
278 .addr = intel_sdvo->slave_addr,
279 .flags = I2C_M_RD,
280 .len = 1,
281 .buf = ch,
282 }
283 };
284 int ret;
285
286 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
287 return true;
288
289 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
290 return false;
291 }
292
293 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
294 /** Mapping of command numbers to names, for debug output */
295 static const struct _sdvo_cmd_name {
296 u8 cmd;
297 const char *name;
298 } sdvo_cmd_names[] = {
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
342
343 /* Add the op code for SDVO enhancements */
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
388
389 /* HDMI op code */
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
410 };
411
412 #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
413
414 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
415 const void *args, int args_len)
416 {
417 int i, pos = 0;
418 #define BUF_LEN 256
419 char buffer[BUF_LEN];
420
421 #define BUF_PRINT(args...) \
422 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
423
424
425 for (i = 0; i < args_len; i++) {
426 BUF_PRINT("%02X ", ((u8 *)args)[i]);
427 }
428 for (; i < 8; i++) {
429 BUF_PRINT(" ");
430 }
431 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
432 if (cmd == sdvo_cmd_names[i].cmd) {
433 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
434 break;
435 }
436 }
437 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
438 BUF_PRINT("(%02X)", cmd);
439 }
440 BUG_ON(pos >= BUF_LEN - 1);
441 #undef BUF_PRINT
442 #undef BUF_LEN
443
444 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
445 }
446
447 static const char *cmd_status_names[] = {
448 "Power on",
449 "Success",
450 "Not supported",
451 "Invalid arg",
452 "Pending",
453 "Target not specified",
454 "Scaling not supported"
455 };
456
457 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
458 const void *args, int args_len)
459 {
460 u8 *buf, status;
461 struct i2c_msg *msgs;
462 int i, ret = true;
463
464 /* Would be simpler to allocate both in one go ? */
465 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
466 if (!buf)
467 return false;
468
469 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
470 if (!msgs) {
471 kfree(buf);
472 return false;
473 }
474
475 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
476
477 for (i = 0; i < args_len; i++) {
478 msgs[i].addr = intel_sdvo->slave_addr;
479 msgs[i].flags = 0;
480 msgs[i].len = 2;
481 msgs[i].buf = buf + 2 *i;
482 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
483 buf[2*i + 1] = ((u8*)args)[i];
484 }
485 msgs[i].addr = intel_sdvo->slave_addr;
486 msgs[i].flags = 0;
487 msgs[i].len = 2;
488 msgs[i].buf = buf + 2*i;
489 buf[2*i + 0] = SDVO_I2C_OPCODE;
490 buf[2*i + 1] = cmd;
491
492 /* the following two are to read the response */
493 status = SDVO_I2C_CMD_STATUS;
494 msgs[i+1].addr = intel_sdvo->slave_addr;
495 msgs[i+1].flags = 0;
496 msgs[i+1].len = 1;
497 msgs[i+1].buf = &status;
498
499 msgs[i+2].addr = intel_sdvo->slave_addr;
500 msgs[i+2].flags = I2C_M_RD;
501 msgs[i+2].len = 1;
502 msgs[i+2].buf = &status;
503
504 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
505 if (ret < 0) {
506 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
507 ret = false;
508 goto out;
509 }
510 if (ret != i+3) {
511 /* failure in I2C transfer */
512 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
513 ret = false;
514 }
515
516 out:
517 kfree(msgs);
518 kfree(buf);
519 return ret;
520 }
521
522 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
523 void *response, int response_len)
524 {
525 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
526 u8 status;
527 int i, pos = 0;
528 #define BUF_LEN 256
529 char buffer[BUF_LEN];
530
531
532 /*
533 * The documentation states that all commands will be
534 * processed within 15µs, and that we need only poll
535 * the status byte a maximum of 3 times in order for the
536 * command to be complete.
537 *
538 * Check 5 times in case the hardware failed to read the docs.
539 *
540 * Also beware that the first response by many devices is to
541 * reply PENDING and stall for time. TVs are notorious for
542 * requiring longer than specified to complete their replies.
543 * Originally (in the DDX long ago), the delay was only ever 15ms
544 * with an additional delay of 30ms applied for TVs added later after
545 * many experiments. To accommodate both sets of delays, we do a
546 * sequence of slow checks if the device is falling behind and fails
547 * to reply within 5*15µs.
548 */
549 if (!intel_sdvo_read_byte(intel_sdvo,
550 SDVO_I2C_CMD_STATUS,
551 &status))
552 goto log_fail;
553
554 while ((status == SDVO_CMD_STATUS_PENDING ||
555 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
556 if (retry < 10)
557 msleep(15);
558 else
559 udelay(15);
560
561 if (!intel_sdvo_read_byte(intel_sdvo,
562 SDVO_I2C_CMD_STATUS,
563 &status))
564 goto log_fail;
565 }
566
567 #define BUF_PRINT(args...) \
568 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
569
570 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
571 BUF_PRINT("(%s)", cmd_status_names[status]);
572 else
573 BUF_PRINT("(??? %d)", status);
574
575 if (status != SDVO_CMD_STATUS_SUCCESS)
576 goto log_fail;
577
578 /* Read the command response */
579 for (i = 0; i < response_len; i++) {
580 if (!intel_sdvo_read_byte(intel_sdvo,
581 SDVO_I2C_RETURN_0 + i,
582 &((u8 *)response)[i]))
583 goto log_fail;
584 BUF_PRINT(" %02X", ((u8 *)response)[i]);
585 }
586 BUG_ON(pos >= BUF_LEN - 1);
587 #undef BUF_PRINT
588 #undef BUF_LEN
589
590 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
591 return true;
592
593 log_fail:
594 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
595 return false;
596 }
597
598 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
599 {
600 if (mode->clock >= 100000)
601 return 1;
602 else if (mode->clock >= 50000)
603 return 2;
604 else
605 return 4;
606 }
607
608 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
609 u8 ddc_bus)
610 {
611 /* This must be the immediately preceding write before the i2c xfer */
612 return intel_sdvo_write_cmd(intel_sdvo,
613 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
614 &ddc_bus, 1);
615 }
616
617 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
618 {
619 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
620 return false;
621
622 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
623 }
624
625 static bool
626 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
627 {
628 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
629 return false;
630
631 return intel_sdvo_read_response(intel_sdvo, value, len);
632 }
633
634 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
635 {
636 struct intel_sdvo_set_target_input_args targets = {0};
637 return intel_sdvo_set_value(intel_sdvo,
638 SDVO_CMD_SET_TARGET_INPUT,
639 &targets, sizeof(targets));
640 }
641
642 /**
643 * Return whether each input is trained.
644 *
645 * This function is making an assumption about the layout of the response,
646 * which should be checked against the docs.
647 */
648 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
649 {
650 struct intel_sdvo_get_trained_inputs_response response;
651
652 BUILD_BUG_ON(sizeof(response) != 1);
653 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
654 &response, sizeof(response)))
655 return false;
656
657 *input_1 = response.input0_trained;
658 *input_2 = response.input1_trained;
659 return true;
660 }
661
662 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
663 u16 outputs)
664 {
665 return intel_sdvo_set_value(intel_sdvo,
666 SDVO_CMD_SET_ACTIVE_OUTPUTS,
667 &outputs, sizeof(outputs));
668 }
669
670 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
671 u16 *outputs)
672 {
673 return intel_sdvo_get_value(intel_sdvo,
674 SDVO_CMD_GET_ACTIVE_OUTPUTS,
675 outputs, sizeof(*outputs));
676 }
677
678 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
679 int mode)
680 {
681 u8 state = SDVO_ENCODER_STATE_ON;
682
683 switch (mode) {
684 case DRM_MODE_DPMS_ON:
685 state = SDVO_ENCODER_STATE_ON;
686 break;
687 case DRM_MODE_DPMS_STANDBY:
688 state = SDVO_ENCODER_STATE_STANDBY;
689 break;
690 case DRM_MODE_DPMS_SUSPEND:
691 state = SDVO_ENCODER_STATE_SUSPEND;
692 break;
693 case DRM_MODE_DPMS_OFF:
694 state = SDVO_ENCODER_STATE_OFF;
695 break;
696 }
697
698 return intel_sdvo_set_value(intel_sdvo,
699 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
700 }
701
702 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
703 int *clock_min,
704 int *clock_max)
705 {
706 struct intel_sdvo_pixel_clock_range clocks;
707
708 BUILD_BUG_ON(sizeof(clocks) != 4);
709 if (!intel_sdvo_get_value(intel_sdvo,
710 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
711 &clocks, sizeof(clocks)))
712 return false;
713
714 /* Convert the values from units of 10 kHz to kHz. */
715 *clock_min = clocks.min * 10;
716 *clock_max = clocks.max * 10;
717 return true;
718 }
719
720 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
721 u16 outputs)
722 {
723 return intel_sdvo_set_value(intel_sdvo,
724 SDVO_CMD_SET_TARGET_OUTPUT,
725 &outputs, sizeof(outputs));
726 }
727
728 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
729 struct intel_sdvo_dtd *dtd)
730 {
731 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
732 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
733 }
734
735 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
736 struct intel_sdvo_dtd *dtd)
737 {
738 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
739 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
740 }
741
742 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
743 struct intel_sdvo_dtd *dtd)
744 {
745 return intel_sdvo_set_timing(intel_sdvo,
746 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
747 }
748
749 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
750 struct intel_sdvo_dtd *dtd)
751 {
752 return intel_sdvo_set_timing(intel_sdvo,
753 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
754 }
755
756 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
757 struct intel_sdvo_dtd *dtd)
758 {
759 return intel_sdvo_get_timing(intel_sdvo,
760 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
761 }
762
763 static bool
764 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
765 uint16_t clock,
766 uint16_t width,
767 uint16_t height)
768 {
769 struct intel_sdvo_preferred_input_timing_args args;
770
771 memset(&args, 0, sizeof(args));
772 args.clock = clock;
773 args.width = width;
774 args.height = height;
775 args.interlace = 0;
776
777 if (intel_sdvo->is_lvds &&
778 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
779 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
780 args.scaled = 1;
781
782 return intel_sdvo_set_value(intel_sdvo,
783 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
784 &args, sizeof(args));
785 }
786
787 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
788 struct intel_sdvo_dtd *dtd)
789 {
790 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
791 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
792 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
793 &dtd->part1, sizeof(dtd->part1)) &&
794 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
795 &dtd->part2, sizeof(dtd->part2));
796 }
797
798 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
799 {
800 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
801 }
802
803 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
804 const struct drm_display_mode *mode)
805 {
806 uint16_t width, height;
807 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
808 uint16_t h_sync_offset, v_sync_offset;
809 int mode_clock;
810
811 memset(dtd, 0, sizeof(*dtd));
812
813 width = mode->hdisplay;
814 height = mode->vdisplay;
815
816 /* do some mode translations */
817 h_blank_len = mode->htotal - mode->hdisplay;
818 h_sync_len = mode->hsync_end - mode->hsync_start;
819
820 v_blank_len = mode->vtotal - mode->vdisplay;
821 v_sync_len = mode->vsync_end - mode->vsync_start;
822
823 h_sync_offset = mode->hsync_start - mode->hdisplay;
824 v_sync_offset = mode->vsync_start - mode->vdisplay;
825
826 mode_clock = mode->clock;
827 mode_clock /= 10;
828 dtd->part1.clock = mode_clock;
829
830 dtd->part1.h_active = width & 0xff;
831 dtd->part1.h_blank = h_blank_len & 0xff;
832 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
833 ((h_blank_len >> 8) & 0xf);
834 dtd->part1.v_active = height & 0xff;
835 dtd->part1.v_blank = v_blank_len & 0xff;
836 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
837 ((v_blank_len >> 8) & 0xf);
838
839 dtd->part2.h_sync_off = h_sync_offset & 0xff;
840 dtd->part2.h_sync_width = h_sync_len & 0xff;
841 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
842 (v_sync_len & 0xf);
843 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
844 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
845 ((v_sync_len & 0x30) >> 4);
846
847 dtd->part2.dtd_flags = 0x18;
848 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
849 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
850 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
851 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
852 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
853 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
854
855 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
856 }
857
858 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
859 const struct intel_sdvo_dtd *dtd)
860 {
861 struct drm_display_mode mode = {};
862
863 mode.hdisplay = dtd->part1.h_active;
864 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
865 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
866 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
867 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
868 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
869 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
870 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
871
872 mode.vdisplay = dtd->part1.v_active;
873 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
874 mode.vsync_start = mode.vdisplay;
875 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
876 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
877 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
878 mode.vsync_end = mode.vsync_start +
879 (dtd->part2.v_sync_off_width & 0xf);
880 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
881 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
882 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
883
884 mode.clock = dtd->part1.clock * 10;
885
886 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
887 mode.flags |= DRM_MODE_FLAG_INTERLACE;
888 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
889 mode.flags |= DRM_MODE_FLAG_PHSYNC;
890 else
891 mode.flags |= DRM_MODE_FLAG_NHSYNC;
892 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
893 mode.flags |= DRM_MODE_FLAG_PVSYNC;
894 else
895 mode.flags |= DRM_MODE_FLAG_NVSYNC;
896
897 drm_mode_set_crtcinfo(&mode, 0);
898
899 drm_mode_copy(pmode, &mode);
900 }
901
902 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
903 {
904 struct intel_sdvo_encode encode;
905
906 BUILD_BUG_ON(sizeof(encode) != 2);
907 return intel_sdvo_get_value(intel_sdvo,
908 SDVO_CMD_GET_SUPP_ENCODE,
909 &encode, sizeof(encode));
910 }
911
912 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
913 uint8_t mode)
914 {
915 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
916 }
917
918 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
919 uint8_t mode)
920 {
921 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
922 }
923
924 #if 0
925 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
926 {
927 int i, j;
928 uint8_t set_buf_index[2];
929 uint8_t av_split;
930 uint8_t buf_size;
931 uint8_t buf[48];
932 uint8_t *pos;
933
934 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
935
936 for (i = 0; i <= av_split; i++) {
937 set_buf_index[0] = i; set_buf_index[1] = 0;
938 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
939 set_buf_index, 2);
940 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
941 intel_sdvo_read_response(encoder, &buf_size, 1);
942
943 pos = buf;
944 for (j = 0; j <= buf_size; j += 8) {
945 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
946 NULL, 0);
947 intel_sdvo_read_response(encoder, pos, 8);
948 pos += 8;
949 }
950 }
951 }
952 #endif
953
954 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
955 unsigned if_index, uint8_t tx_rate,
956 const uint8_t *data, unsigned length)
957 {
958 uint8_t set_buf_index[2] = { if_index, 0 };
959 uint8_t hbuf_size, tmp[8];
960 int i;
961
962 if (!intel_sdvo_set_value(intel_sdvo,
963 SDVO_CMD_SET_HBUF_INDEX,
964 set_buf_index, 2))
965 return false;
966
967 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
968 &hbuf_size, 1))
969 return false;
970
971 /* Buffer size is 0 based, hooray! */
972 hbuf_size++;
973
974 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
975 if_index, length, hbuf_size);
976
977 for (i = 0; i < hbuf_size; i += 8) {
978 memset(tmp, 0, 8);
979 if (i < length)
980 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
981
982 if (!intel_sdvo_set_value(intel_sdvo,
983 SDVO_CMD_SET_HBUF_DATA,
984 tmp, 8))
985 return false;
986 }
987
988 return intel_sdvo_set_value(intel_sdvo,
989 SDVO_CMD_SET_HBUF_TXRATE,
990 &tx_rate, 1);
991 }
992
993 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
994 const struct drm_display_mode *adjusted_mode)
995 {
996 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
997 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
999 union hdmi_infoframe frame;
1000 int ret;
1001 ssize_t len;
1002
1003 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
1004 adjusted_mode);
1005 if (ret < 0) {
1006 DRM_ERROR("couldn't fill AVI infoframe\n");
1007 return false;
1008 }
1009
1010 if (intel_sdvo->rgb_quant_range_selectable) {
1011 if (intel_crtc->config->limited_color_range)
1012 frame.avi.quantization_range =
1013 HDMI_QUANTIZATION_RANGE_LIMITED;
1014 else
1015 frame.avi.quantization_range =
1016 HDMI_QUANTIZATION_RANGE_FULL;
1017 }
1018
1019 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1020 if (len < 0)
1021 return false;
1022
1023 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1024 SDVO_HBUF_TX_VSYNC,
1025 sdvo_data, sizeof(sdvo_data));
1026 }
1027
1028 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
1029 {
1030 struct intel_sdvo_tv_format format;
1031 uint32_t format_map;
1032
1033 format_map = 1 << intel_sdvo->tv_format_index;
1034 memset(&format, 0, sizeof(format));
1035 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1036
1037 BUILD_BUG_ON(sizeof(format) != 6);
1038 return intel_sdvo_set_value(intel_sdvo,
1039 SDVO_CMD_SET_TV_FORMAT,
1040 &format, sizeof(format));
1041 }
1042
1043 static bool
1044 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1045 const struct drm_display_mode *mode)
1046 {
1047 struct intel_sdvo_dtd output_dtd;
1048
1049 if (!intel_sdvo_set_target_output(intel_sdvo,
1050 intel_sdvo->attached_output))
1051 return false;
1052
1053 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1054 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1055 return false;
1056
1057 return true;
1058 }
1059
1060 /* Asks the sdvo controller for the preferred input mode given the output mode.
1061 * Unfortunately we have to set up the full output mode to do that. */
1062 static bool
1063 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1064 const struct drm_display_mode *mode,
1065 struct drm_display_mode *adjusted_mode)
1066 {
1067 struct intel_sdvo_dtd input_dtd;
1068
1069 /* Reset the input timing to the screen. Assume always input 0. */
1070 if (!intel_sdvo_set_target_input(intel_sdvo))
1071 return false;
1072
1073 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1074 mode->clock / 10,
1075 mode->hdisplay,
1076 mode->vdisplay))
1077 return false;
1078
1079 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1080 &input_dtd))
1081 return false;
1082
1083 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1084 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1085
1086 return true;
1087 }
1088
1089 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1090 {
1091 unsigned dotclock = pipe_config->port_clock;
1092 struct dpll *clock = &pipe_config->dpll;
1093
1094 /* SDVO TV has fixed PLL values depend on its clock range,
1095 this mirrors vbios setting. */
1096 if (dotclock >= 100000 && dotclock < 140500) {
1097 clock->p1 = 2;
1098 clock->p2 = 10;
1099 clock->n = 3;
1100 clock->m1 = 16;
1101 clock->m2 = 8;
1102 } else if (dotclock >= 140500 && dotclock <= 200000) {
1103 clock->p1 = 1;
1104 clock->p2 = 10;
1105 clock->n = 6;
1106 clock->m1 = 12;
1107 clock->m2 = 8;
1108 } else {
1109 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1110 }
1111
1112 pipe_config->clock_set = true;
1113 }
1114
1115 static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1116 struct intel_crtc_state *pipe_config)
1117 {
1118 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1119 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1120 struct drm_display_mode *mode = &pipe_config->base.mode;
1121
1122 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1123 pipe_config->pipe_bpp = 8*3;
1124
1125 if (HAS_PCH_SPLIT(encoder->base.dev))
1126 pipe_config->has_pch_encoder = true;
1127
1128 /* We need to construct preferred input timings based on our
1129 * output timings. To do that, we have to set the output
1130 * timings, even though this isn't really the right place in
1131 * the sequence to do it. Oh well.
1132 */
1133 if (intel_sdvo->is_tv) {
1134 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1135 return false;
1136
1137 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1138 mode,
1139 adjusted_mode);
1140 pipe_config->sdvo_tv_clock = true;
1141 } else if (intel_sdvo->is_lvds) {
1142 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1143 intel_sdvo->sdvo_lvds_fixed_mode))
1144 return false;
1145
1146 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1147 mode,
1148 adjusted_mode);
1149 }
1150
1151 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1152 * SDVO device will factor out the multiplier during mode_set.
1153 */
1154 pipe_config->pixel_multiplier =
1155 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1156
1157 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1158
1159 if (intel_sdvo->color_range_auto) {
1160 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1161 /* FIXME: This bit is only valid when using TMDS encoding and 8
1162 * bit per color mode. */
1163 if (pipe_config->has_hdmi_sink &&
1164 drm_match_cea_mode(adjusted_mode) > 1)
1165 pipe_config->limited_color_range = true;
1166 } else {
1167 if (pipe_config->has_hdmi_sink &&
1168 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235)
1169 pipe_config->limited_color_range = true;
1170 }
1171
1172 /* Clock computation needs to happen after pixel multiplier. */
1173 if (intel_sdvo->is_tv)
1174 i9xx_adjust_sdvo_tv_clock(pipe_config);
1175
1176 return true;
1177 }
1178
1179 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
1180 {
1181 struct drm_device *dev = intel_encoder->base.dev;
1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
1184 struct drm_display_mode *adjusted_mode =
1185 &crtc->config->base.adjusted_mode;
1186 struct drm_display_mode *mode = &crtc->config->base.mode;
1187 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1188 u32 sdvox;
1189 struct intel_sdvo_in_out_map in_out;
1190 struct intel_sdvo_dtd input_dtd, output_dtd;
1191 int rate;
1192
1193 if (!mode)
1194 return;
1195
1196 /* First, set the input mapping for the first input to our controlled
1197 * output. This is only correct if we're a single-input device, in
1198 * which case the first input is the output from the appropriate SDVO
1199 * channel on the motherboard. In a two-input device, the first input
1200 * will be SDVOB and the second SDVOC.
1201 */
1202 in_out.in0 = intel_sdvo->attached_output;
1203 in_out.in1 = 0;
1204
1205 intel_sdvo_set_value(intel_sdvo,
1206 SDVO_CMD_SET_IN_OUT_MAP,
1207 &in_out, sizeof(in_out));
1208
1209 /* Set the output timings to the screen */
1210 if (!intel_sdvo_set_target_output(intel_sdvo,
1211 intel_sdvo->attached_output))
1212 return;
1213
1214 /* lvds has a special fixed output timing. */
1215 if (intel_sdvo->is_lvds)
1216 intel_sdvo_get_dtd_from_mode(&output_dtd,
1217 intel_sdvo->sdvo_lvds_fixed_mode);
1218 else
1219 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1220 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1221 DRM_INFO("Setting output timings on %s failed\n",
1222 SDVO_NAME(intel_sdvo));
1223
1224 /* Set the input timing to the screen. Assume always input 0. */
1225 if (!intel_sdvo_set_target_input(intel_sdvo))
1226 return;
1227
1228 if (crtc->config->has_hdmi_sink) {
1229 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1230 intel_sdvo_set_colorimetry(intel_sdvo,
1231 SDVO_COLORIMETRY_RGB256);
1232 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
1233 } else
1234 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1235
1236 if (intel_sdvo->is_tv &&
1237 !intel_sdvo_set_tv_format(intel_sdvo))
1238 return;
1239
1240 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1241
1242 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1243 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1244 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1245 DRM_INFO("Setting input timings on %s failed\n",
1246 SDVO_NAME(intel_sdvo));
1247
1248 switch (crtc->config->pixel_multiplier) {
1249 default:
1250 WARN(1, "unknown pixel mutlipler specified\n");
1251 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1252 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1253 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1254 }
1255 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1256 return;
1257
1258 /* Set the SDVO control regs. */
1259 if (INTEL_INFO(dev)->gen >= 4) {
1260 /* The real mode polarity is set by the SDVO commands, using
1261 * struct intel_sdvo_dtd. */
1262 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1263 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
1264 sdvox |= HDMI_COLOR_RANGE_16_235;
1265 if (INTEL_INFO(dev)->gen < 5)
1266 sdvox |= SDVO_BORDER_ENABLE;
1267 } else {
1268 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1269 switch (intel_sdvo->sdvo_reg) {
1270 case GEN3_SDVOB:
1271 sdvox &= SDVOB_PRESERVE_MASK;
1272 break;
1273 case GEN3_SDVOC:
1274 sdvox &= SDVOC_PRESERVE_MASK;
1275 break;
1276 }
1277 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1278 }
1279
1280 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1281 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1282 else
1283 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1284
1285 if (intel_sdvo->has_hdmi_audio)
1286 sdvox |= SDVO_AUDIO_ENABLE;
1287
1288 if (INTEL_INFO(dev)->gen >= 4) {
1289 /* done in crtc_mode_set as the dpll_md reg must be written early */
1290 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1291 /* done in crtc_mode_set as it lives inside the dpll register */
1292 } else {
1293 sdvox |= (crtc->config->pixel_multiplier - 1)
1294 << SDVO_PORT_MULTIPLY_SHIFT;
1295 }
1296
1297 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1298 INTEL_INFO(dev)->gen < 5)
1299 sdvox |= SDVO_STALL_SELECT;
1300 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1301 }
1302
1303 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1304 {
1305 struct intel_sdvo_connector *intel_sdvo_connector =
1306 to_intel_sdvo_connector(&connector->base);
1307 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1308 u16 active_outputs = 0;
1309
1310 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1311
1312 if (active_outputs & intel_sdvo_connector->output_flag)
1313 return true;
1314 else
1315 return false;
1316 }
1317
1318 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1319 enum pipe *pipe)
1320 {
1321 struct drm_device *dev = encoder->base.dev;
1322 struct drm_i915_private *dev_priv = dev->dev_private;
1323 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1324 u16 active_outputs = 0;
1325 u32 tmp;
1326
1327 tmp = I915_READ(intel_sdvo->sdvo_reg);
1328 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1329
1330 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev))
1334 *pipe = PORT_TO_PIPE_CPT(tmp);
1335 else
1336 *pipe = PORT_TO_PIPE(tmp);
1337
1338 return true;
1339 }
1340
1341 static void intel_sdvo_get_config(struct intel_encoder *encoder,
1342 struct intel_crtc_state *pipe_config)
1343 {
1344 struct drm_device *dev = encoder->base.dev;
1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1347 struct intel_sdvo_dtd dtd;
1348 int encoder_pixel_multiplier = 0;
1349 int dotclock;
1350 u32 flags = 0, sdvox;
1351 u8 val;
1352 bool ret;
1353
1354 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1355
1356 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1357 if (!ret) {
1358 /* Some sdvo encoders are not spec compliant and don't
1359 * implement the mandatory get_timings function. */
1360 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1361 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1362 } else {
1363 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1364 flags |= DRM_MODE_FLAG_PHSYNC;
1365 else
1366 flags |= DRM_MODE_FLAG_NHSYNC;
1367
1368 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1369 flags |= DRM_MODE_FLAG_PVSYNC;
1370 else
1371 flags |= DRM_MODE_FLAG_NVSYNC;
1372 }
1373
1374 pipe_config->base.adjusted_mode.flags |= flags;
1375
1376 /*
1377 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1378 * the sdvo port register, on all other platforms it is part of the dpll
1379 * state. Since the general pipe state readout happens before the
1380 * encoder->get_config we so already have a valid pixel multplier on all
1381 * other platfroms.
1382 */
1383 if (IS_I915G(dev) || IS_I915GM(dev)) {
1384 pipe_config->pixel_multiplier =
1385 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1386 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1387 }
1388
1389 dotclock = pipe_config->port_clock;
1390 if (pipe_config->pixel_multiplier)
1391 dotclock /= pipe_config->pixel_multiplier;
1392
1393 if (HAS_PCH_SPLIT(dev))
1394 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1395
1396 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1397
1398 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1399 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1400 &val, 1)) {
1401 switch (val) {
1402 case SDVO_CLOCK_RATE_MULT_1X:
1403 encoder_pixel_multiplier = 1;
1404 break;
1405 case SDVO_CLOCK_RATE_MULT_2X:
1406 encoder_pixel_multiplier = 2;
1407 break;
1408 case SDVO_CLOCK_RATE_MULT_4X:
1409 encoder_pixel_multiplier = 4;
1410 break;
1411 }
1412 }
1413
1414 if (sdvox & HDMI_COLOR_RANGE_16_235)
1415 pipe_config->limited_color_range = true;
1416
1417 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1418 &val, 1)) {
1419 if (val == SDVO_ENCODE_HDMI)
1420 pipe_config->has_hdmi_sink = true;
1421 }
1422
1423 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1424 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1425 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1426 }
1427
1428 static void intel_disable_sdvo(struct intel_encoder *encoder)
1429 {
1430 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1431 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1432 u32 temp;
1433
1434 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1435 if (0)
1436 intel_sdvo_set_encoder_power_state(intel_sdvo,
1437 DRM_MODE_DPMS_OFF);
1438
1439 temp = I915_READ(intel_sdvo->sdvo_reg);
1440 if ((temp & SDVO_ENABLE) != 0) {
1441 /* HW workaround for IBX, we need to move the port to
1442 * transcoder A before disabling it. */
1443 if (HAS_PCH_IBX(encoder->base.dev)) {
1444 struct drm_crtc *crtc = encoder->base.crtc;
1445 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1446
1447 if (temp & SDVO_PIPE_B_SELECT) {
1448 temp &= ~SDVO_PIPE_B_SELECT;
1449 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1450 POSTING_READ(intel_sdvo->sdvo_reg);
1451
1452 /* Again we need to write this twice. */
1453 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1454 POSTING_READ(intel_sdvo->sdvo_reg);
1455
1456 /* Transcoder selection bits only update
1457 * effectively on vblank. */
1458 if (crtc)
1459 intel_wait_for_vblank(encoder->base.dev, pipe);
1460 else
1461 msleep(50);
1462 }
1463 }
1464
1465 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1466 }
1467 }
1468
1469 static void intel_enable_sdvo(struct intel_encoder *encoder)
1470 {
1471 struct drm_device *dev = encoder->base.dev;
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1473 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1474 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1475 u32 temp;
1476 bool input1, input2;
1477 int i;
1478 bool success;
1479
1480 temp = I915_READ(intel_sdvo->sdvo_reg);
1481 if ((temp & SDVO_ENABLE) == 0) {
1482 /* HW workaround for IBX, we need to move the port
1483 * to transcoder A before disabling it, so restore it here. */
1484 if (HAS_PCH_IBX(dev))
1485 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
1486
1487 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
1488 }
1489 for (i = 0; i < 2; i++)
1490 intel_wait_for_vblank(dev, intel_crtc->pipe);
1491
1492 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1493 /* Warn if the device reported failure to sync.
1494 * A lot of SDVO devices fail to notify of sync, but it's
1495 * a given it the status is a success, we succeeded.
1496 */
1497 if (success && !input1) {
1498 DRM_DEBUG_KMS("First %s output reported failure to "
1499 "sync\n", SDVO_NAME(intel_sdvo));
1500 }
1501
1502 if (0)
1503 intel_sdvo_set_encoder_power_state(intel_sdvo,
1504 DRM_MODE_DPMS_ON);
1505 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1506 }
1507
1508 /* Special dpms function to support cloning between dvo/sdvo/crt. */
1509 static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
1510 {
1511 struct drm_crtc *crtc;
1512 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1513
1514 /* dvo supports only 2 dpms states. */
1515 if (mode != DRM_MODE_DPMS_ON)
1516 mode = DRM_MODE_DPMS_OFF;
1517
1518 if (mode == connector->dpms)
1519 return;
1520
1521 connector->dpms = mode;
1522
1523 /* Only need to change hw state when actually enabled */
1524 crtc = intel_sdvo->base.base.crtc;
1525 if (!crtc) {
1526 intel_sdvo->base.connectors_active = false;
1527 return;
1528 }
1529
1530 /* We set active outputs manually below in case pipe dpms doesn't change
1531 * due to cloning. */
1532 if (mode != DRM_MODE_DPMS_ON) {
1533 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1534 if (0)
1535 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1536
1537 intel_sdvo->base.connectors_active = false;
1538
1539 intel_crtc_update_dpms(crtc);
1540 } else {
1541 intel_sdvo->base.connectors_active = true;
1542
1543 intel_crtc_update_dpms(crtc);
1544
1545 if (0)
1546 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1547 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1548 }
1549
1550 intel_modeset_check_state(connector->dev);
1551 }
1552
1553 static enum drm_mode_status
1554 intel_sdvo_mode_valid(struct drm_connector *connector,
1555 struct drm_display_mode *mode)
1556 {
1557 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1558
1559 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1560 return MODE_NO_DBLESCAN;
1561
1562 if (intel_sdvo->pixel_clock_min > mode->clock)
1563 return MODE_CLOCK_LOW;
1564
1565 if (intel_sdvo->pixel_clock_max < mode->clock)
1566 return MODE_CLOCK_HIGH;
1567
1568 if (intel_sdvo->is_lvds) {
1569 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1570 return MODE_PANEL;
1571
1572 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1573 return MODE_PANEL;
1574 }
1575
1576 return MODE_OK;
1577 }
1578
1579 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1580 {
1581 BUILD_BUG_ON(sizeof(*caps) != 8);
1582 if (!intel_sdvo_get_value(intel_sdvo,
1583 SDVO_CMD_GET_DEVICE_CAPS,
1584 caps, sizeof(*caps)))
1585 return false;
1586
1587 DRM_DEBUG_KMS("SDVO capabilities:\n"
1588 " vendor_id: %d\n"
1589 " device_id: %d\n"
1590 " device_rev_id: %d\n"
1591 " sdvo_version_major: %d\n"
1592 " sdvo_version_minor: %d\n"
1593 " sdvo_inputs_mask: %d\n"
1594 " smooth_scaling: %d\n"
1595 " sharp_scaling: %d\n"
1596 " up_scaling: %d\n"
1597 " down_scaling: %d\n"
1598 " stall_support: %d\n"
1599 " output_flags: %d\n",
1600 caps->vendor_id,
1601 caps->device_id,
1602 caps->device_rev_id,
1603 caps->sdvo_version_major,
1604 caps->sdvo_version_minor,
1605 caps->sdvo_inputs_mask,
1606 caps->smooth_scaling,
1607 caps->sharp_scaling,
1608 caps->up_scaling,
1609 caps->down_scaling,
1610 caps->stall_support,
1611 caps->output_flags);
1612
1613 return true;
1614 }
1615
1616 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1617 {
1618 struct drm_device *dev = intel_sdvo->base.base.dev;
1619 uint16_t hotplug;
1620
1621 if (!I915_HAS_HOTPLUG(dev))
1622 return 0;
1623
1624 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1625 * on the line. */
1626 if (IS_I945G(dev) || IS_I945GM(dev))
1627 return 0;
1628
1629 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1630 &hotplug, sizeof(hotplug)))
1631 return 0;
1632
1633 return hotplug;
1634 }
1635
1636 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1637 {
1638 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1639
1640 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1641 &intel_sdvo->hotplug_active, 2);
1642 }
1643
1644 static bool
1645 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1646 {
1647 /* Is there more than one type of output? */
1648 return hweight16(intel_sdvo->caps.output_flags) > 1;
1649 }
1650
1651 static struct edid *
1652 intel_sdvo_get_edid(struct drm_connector *connector)
1653 {
1654 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1655 return drm_get_edid(connector, &sdvo->ddc);
1656 }
1657
1658 /* Mac mini hack -- use the same DDC as the analog connector */
1659 static struct edid *
1660 intel_sdvo_get_analog_edid(struct drm_connector *connector)
1661 {
1662 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1663
1664 return drm_get_edid(connector,
1665 intel_gmbus_get_adapter(dev_priv,
1666 dev_priv->vbt.crt_ddc_pin));
1667 }
1668
1669 static enum drm_connector_status
1670 intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
1671 {
1672 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1673 enum drm_connector_status status;
1674 struct edid *edid;
1675
1676 edid = intel_sdvo_get_edid(connector);
1677
1678 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1679 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
1680
1681 /*
1682 * Don't use the 1 as the argument of DDC bus switch to get
1683 * the EDID. It is used for SDVO SPD ROM.
1684 */
1685 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1686 intel_sdvo->ddc_bus = ddc;
1687 edid = intel_sdvo_get_edid(connector);
1688 if (edid)
1689 break;
1690 }
1691 /*
1692 * If we found the EDID on the other bus,
1693 * assume that is the correct DDC bus.
1694 */
1695 if (edid == NULL)
1696 intel_sdvo->ddc_bus = saved_ddc;
1697 }
1698
1699 /*
1700 * When there is no edid and no monitor is connected with VGA
1701 * port, try to use the CRT ddc to read the EDID for DVI-connector.
1702 */
1703 if (edid == NULL)
1704 edid = intel_sdvo_get_analog_edid(connector);
1705
1706 status = connector_status_unknown;
1707 if (edid != NULL) {
1708 /* DDC bus is shared, match EDID to connector type */
1709 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1710 status = connector_status_connected;
1711 if (intel_sdvo->is_hdmi) {
1712 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1713 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1714 intel_sdvo->rgb_quant_range_selectable =
1715 drm_rgb_quant_range_selectable(edid);
1716 }
1717 } else
1718 status = connector_status_disconnected;
1719 kfree(edid);
1720 }
1721
1722 if (status == connector_status_connected) {
1723 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1724 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1725 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
1726 }
1727
1728 return status;
1729 }
1730
1731 static bool
1732 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1733 struct edid *edid)
1734 {
1735 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1736 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1737
1738 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1739 connector_is_digital, monitor_is_digital);
1740 return connector_is_digital == monitor_is_digital;
1741 }
1742
1743 static enum drm_connector_status
1744 intel_sdvo_detect(struct drm_connector *connector, bool force)
1745 {
1746 uint16_t response;
1747 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1748 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1749 enum drm_connector_status ret;
1750
1751 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1752 connector->base.id, connector->name);
1753
1754 if (!intel_sdvo_get_value(intel_sdvo,
1755 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1756 &response, 2))
1757 return connector_status_unknown;
1758
1759 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1760 response & 0xff, response >> 8,
1761 intel_sdvo_connector->output_flag);
1762
1763 if (response == 0)
1764 return connector_status_disconnected;
1765
1766 intel_sdvo->attached_output = response;
1767
1768 intel_sdvo->has_hdmi_monitor = false;
1769 intel_sdvo->has_hdmi_audio = false;
1770 intel_sdvo->rgb_quant_range_selectable = false;
1771
1772 if ((intel_sdvo_connector->output_flag & response) == 0)
1773 ret = connector_status_disconnected;
1774 else if (IS_TMDS(intel_sdvo_connector))
1775 ret = intel_sdvo_tmds_sink_detect(connector);
1776 else {
1777 struct edid *edid;
1778
1779 /* if we have an edid check it matches the connection */
1780 edid = intel_sdvo_get_edid(connector);
1781 if (edid == NULL)
1782 edid = intel_sdvo_get_analog_edid(connector);
1783 if (edid != NULL) {
1784 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1785 edid))
1786 ret = connector_status_connected;
1787 else
1788 ret = connector_status_disconnected;
1789
1790 kfree(edid);
1791 } else
1792 ret = connector_status_connected;
1793 }
1794
1795 /* May update encoder flag for like clock for SDVO TV, etc.*/
1796 if (ret == connector_status_connected) {
1797 intel_sdvo->is_tv = false;
1798 intel_sdvo->is_lvds = false;
1799
1800 if (response & SDVO_TV_MASK)
1801 intel_sdvo->is_tv = true;
1802 if (response & SDVO_LVDS_MASK)
1803 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1804 }
1805
1806 return ret;
1807 }
1808
1809 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1810 {
1811 struct edid *edid;
1812
1813 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1814 connector->base.id, connector->name);
1815
1816 /* set the bus switch and get the modes */
1817 edid = intel_sdvo_get_edid(connector);
1818
1819 /*
1820 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1821 * link between analog and digital outputs. So, if the regular SDVO
1822 * DDC fails, check to see if the analog output is disconnected, in
1823 * which case we'll look there for the digital DDC data.
1824 */
1825 if (edid == NULL)
1826 edid = intel_sdvo_get_analog_edid(connector);
1827
1828 if (edid != NULL) {
1829 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1830 edid)) {
1831 drm_mode_connector_update_edid_property(connector, edid);
1832 drm_add_edid_modes(connector, edid);
1833 }
1834
1835 kfree(edid);
1836 }
1837 }
1838
1839 /*
1840 * Set of SDVO TV modes.
1841 * Note! This is in reply order (see loop in get_tv_modes).
1842 * XXX: all 60Hz refresh?
1843 */
1844 static const struct drm_display_mode sdvo_tv_modes[] = {
1845 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1846 416, 0, 200, 201, 232, 233, 0,
1847 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1848 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1849 416, 0, 240, 241, 272, 273, 0,
1850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1851 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1852 496, 0, 300, 301, 332, 333, 0,
1853 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1854 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1855 736, 0, 350, 351, 382, 383, 0,
1856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1857 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1858 736, 0, 400, 401, 432, 433, 0,
1859 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1860 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1861 736, 0, 480, 481, 512, 513, 0,
1862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1863 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1864 800, 0, 480, 481, 512, 513, 0,
1865 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1866 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1867 800, 0, 576, 577, 608, 609, 0,
1868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1869 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1870 816, 0, 350, 351, 382, 383, 0,
1871 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1872 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1873 816, 0, 400, 401, 432, 433, 0,
1874 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1875 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1876 816, 0, 480, 481, 512, 513, 0,
1877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1878 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1879 816, 0, 540, 541, 572, 573, 0,
1880 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1882 816, 0, 576, 577, 608, 609, 0,
1883 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1884 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1885 864, 0, 576, 577, 608, 609, 0,
1886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1887 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1888 896, 0, 600, 601, 632, 633, 0,
1889 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1890 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1891 928, 0, 624, 625, 656, 657, 0,
1892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1893 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1894 1016, 0, 766, 767, 798, 799, 0,
1895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1896 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1897 1120, 0, 768, 769, 800, 801, 0,
1898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1899 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1900 1376, 0, 1024, 1025, 1056, 1057, 0,
1901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1902 };
1903
1904 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1905 {
1906 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1907 struct intel_sdvo_sdtv_resolution_request tv_res;
1908 uint32_t reply = 0, format_map = 0;
1909 int i;
1910
1911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1912 connector->base.id, connector->name);
1913
1914 /* Read the list of supported input resolutions for the selected TV
1915 * format.
1916 */
1917 format_map = 1 << intel_sdvo->tv_format_index;
1918 memcpy(&tv_res, &format_map,
1919 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
1920
1921 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1922 return;
1923
1924 BUILD_BUG_ON(sizeof(tv_res) != 3);
1925 if (!intel_sdvo_write_cmd(intel_sdvo,
1926 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1927 &tv_res, sizeof(tv_res)))
1928 return;
1929 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
1930 return;
1931
1932 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1933 if (reply & (1 << i)) {
1934 struct drm_display_mode *nmode;
1935 nmode = drm_mode_duplicate(connector->dev,
1936 &sdvo_tv_modes[i]);
1937 if (nmode)
1938 drm_mode_probed_add(connector, nmode);
1939 }
1940 }
1941
1942 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1943 {
1944 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1945 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1946 struct drm_display_mode *newmode;
1947
1948 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1949 connector->base.id, connector->name);
1950
1951 /*
1952 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
1953 * SDVO->LVDS transcoders can't cope with the EDID mode.
1954 */
1955 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
1956 newmode = drm_mode_duplicate(connector->dev,
1957 dev_priv->vbt.sdvo_lvds_vbt_mode);
1958 if (newmode != NULL) {
1959 /* Guarantee the mode is preferred */
1960 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1961 DRM_MODE_TYPE_DRIVER);
1962 drm_mode_probed_add(connector, newmode);
1963 }
1964 }
1965
1966 /*
1967 * Attempt to get the mode list from DDC.
1968 * Assume that the preferred modes are
1969 * arranged in priority order.
1970 */
1971 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1972
1973 list_for_each_entry(newmode, &connector->probed_modes, head) {
1974 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1975 intel_sdvo->sdvo_lvds_fixed_mode =
1976 drm_mode_duplicate(connector->dev, newmode);
1977
1978 intel_sdvo->is_lvds = true;
1979 break;
1980 }
1981 }
1982 }
1983
1984 static int intel_sdvo_get_modes(struct drm_connector *connector)
1985 {
1986 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1987
1988 if (IS_TV(intel_sdvo_connector))
1989 intel_sdvo_get_tv_modes(connector);
1990 else if (IS_LVDS(intel_sdvo_connector))
1991 intel_sdvo_get_lvds_modes(connector);
1992 else
1993 intel_sdvo_get_ddc_modes(connector);
1994
1995 return !list_empty(&connector->probed_modes);
1996 }
1997
1998 static void intel_sdvo_destroy(struct drm_connector *connector)
1999 {
2000 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2001
2002 drm_connector_cleanup(connector);
2003 kfree(intel_sdvo_connector);
2004 }
2005
2006 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
2007 {
2008 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2009 struct edid *edid;
2010 bool has_audio = false;
2011
2012 if (!intel_sdvo->is_hdmi)
2013 return false;
2014
2015 edid = intel_sdvo_get_edid(connector);
2016 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
2017 has_audio = drm_detect_monitor_audio(edid);
2018 kfree(edid);
2019
2020 return has_audio;
2021 }
2022
2023 static int
2024 intel_sdvo_set_property(struct drm_connector *connector,
2025 struct drm_property *property,
2026 uint64_t val)
2027 {
2028 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2029 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2030 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2031 uint16_t temp_value;
2032 uint8_t cmd;
2033 int ret;
2034
2035 ret = drm_object_property_set_value(&connector->base, property, val);
2036 if (ret)
2037 return ret;
2038
2039 if (property == dev_priv->force_audio_property) {
2040 int i = val;
2041 bool has_audio;
2042
2043 if (i == intel_sdvo_connector->force_audio)
2044 return 0;
2045
2046 intel_sdvo_connector->force_audio = i;
2047
2048 if (i == HDMI_AUDIO_AUTO)
2049 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2050 else
2051 has_audio = (i == HDMI_AUDIO_ON);
2052
2053 if (has_audio == intel_sdvo->has_hdmi_audio)
2054 return 0;
2055
2056 intel_sdvo->has_hdmi_audio = has_audio;
2057 goto done;
2058 }
2059
2060 if (property == dev_priv->broadcast_rgb_property) {
2061 bool old_auto = intel_sdvo->color_range_auto;
2062 uint32_t old_range = intel_sdvo->color_range;
2063
2064 switch (val) {
2065 case INTEL_BROADCAST_RGB_AUTO:
2066 intel_sdvo->color_range_auto = true;
2067 break;
2068 case INTEL_BROADCAST_RGB_FULL:
2069 intel_sdvo->color_range_auto = false;
2070 intel_sdvo->color_range = 0;
2071 break;
2072 case INTEL_BROADCAST_RGB_LIMITED:
2073 intel_sdvo->color_range_auto = false;
2074 /* FIXME: this bit is only valid when using TMDS
2075 * encoding and 8 bit per color mode. */
2076 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
2077 break;
2078 default:
2079 return -EINVAL;
2080 }
2081
2082 if (old_auto == intel_sdvo->color_range_auto &&
2083 old_range == intel_sdvo->color_range)
2084 return 0;
2085
2086 goto done;
2087 }
2088
2089 #define CHECK_PROPERTY(name, NAME) \
2090 if (intel_sdvo_connector->name == property) { \
2091 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2092 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2093 cmd = SDVO_CMD_SET_##NAME; \
2094 intel_sdvo_connector->cur_##name = temp_value; \
2095 goto set_value; \
2096 }
2097
2098 if (property == intel_sdvo_connector->tv_format) {
2099 if (val >= TV_FORMAT_NUM)
2100 return -EINVAL;
2101
2102 if (intel_sdvo->tv_format_index ==
2103 intel_sdvo_connector->tv_format_supported[val])
2104 return 0;
2105
2106 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
2107 goto done;
2108 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
2109 temp_value = val;
2110 if (intel_sdvo_connector->left == property) {
2111 drm_object_property_set_value(&connector->base,
2112 intel_sdvo_connector->right, val);
2113 if (intel_sdvo_connector->left_margin == temp_value)
2114 return 0;
2115
2116 intel_sdvo_connector->left_margin = temp_value;
2117 intel_sdvo_connector->right_margin = temp_value;
2118 temp_value = intel_sdvo_connector->max_hscan -
2119 intel_sdvo_connector->left_margin;
2120 cmd = SDVO_CMD_SET_OVERSCAN_H;
2121 goto set_value;
2122 } else if (intel_sdvo_connector->right == property) {
2123 drm_object_property_set_value(&connector->base,
2124 intel_sdvo_connector->left, val);
2125 if (intel_sdvo_connector->right_margin == temp_value)
2126 return 0;
2127
2128 intel_sdvo_connector->left_margin = temp_value;
2129 intel_sdvo_connector->right_margin = temp_value;
2130 temp_value = intel_sdvo_connector->max_hscan -
2131 intel_sdvo_connector->left_margin;
2132 cmd = SDVO_CMD_SET_OVERSCAN_H;
2133 goto set_value;
2134 } else if (intel_sdvo_connector->top == property) {
2135 drm_object_property_set_value(&connector->base,
2136 intel_sdvo_connector->bottom, val);
2137 if (intel_sdvo_connector->top_margin == temp_value)
2138 return 0;
2139
2140 intel_sdvo_connector->top_margin = temp_value;
2141 intel_sdvo_connector->bottom_margin = temp_value;
2142 temp_value = intel_sdvo_connector->max_vscan -
2143 intel_sdvo_connector->top_margin;
2144 cmd = SDVO_CMD_SET_OVERSCAN_V;
2145 goto set_value;
2146 } else if (intel_sdvo_connector->bottom == property) {
2147 drm_object_property_set_value(&connector->base,
2148 intel_sdvo_connector->top, val);
2149 if (intel_sdvo_connector->bottom_margin == temp_value)
2150 return 0;
2151
2152 intel_sdvo_connector->top_margin = temp_value;
2153 intel_sdvo_connector->bottom_margin = temp_value;
2154 temp_value = intel_sdvo_connector->max_vscan -
2155 intel_sdvo_connector->top_margin;
2156 cmd = SDVO_CMD_SET_OVERSCAN_V;
2157 goto set_value;
2158 }
2159 CHECK_PROPERTY(hpos, HPOS)
2160 CHECK_PROPERTY(vpos, VPOS)
2161 CHECK_PROPERTY(saturation, SATURATION)
2162 CHECK_PROPERTY(contrast, CONTRAST)
2163 CHECK_PROPERTY(hue, HUE)
2164 CHECK_PROPERTY(brightness, BRIGHTNESS)
2165 CHECK_PROPERTY(sharpness, SHARPNESS)
2166 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2167 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2168 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2169 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2170 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
2171 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
2172 }
2173
2174 return -EINVAL; /* unknown property */
2175
2176 set_value:
2177 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2178 return -EIO;
2179
2180
2181 done:
2182 if (intel_sdvo->base.base.crtc)
2183 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
2184
2185 return 0;
2186 #undef CHECK_PROPERTY
2187 }
2188
2189 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2190 .dpms = intel_sdvo_dpms,
2191 .detect = intel_sdvo_detect,
2192 .fill_modes = drm_helper_probe_single_connector_modes,
2193 .set_property = intel_sdvo_set_property,
2194 .atomic_get_property = intel_connector_atomic_get_property,
2195 .destroy = intel_sdvo_destroy,
2196 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2197 };
2198
2199 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2200 .get_modes = intel_sdvo_get_modes,
2201 .mode_valid = intel_sdvo_mode_valid,
2202 .best_encoder = intel_best_encoder,
2203 };
2204
2205 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2206 {
2207 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2208
2209 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
2210 drm_mode_destroy(encoder->dev,
2211 intel_sdvo->sdvo_lvds_fixed_mode);
2212
2213 i2c_del_adapter(&intel_sdvo->ddc);
2214 intel_encoder_destroy(encoder);
2215 }
2216
2217 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2218 .destroy = intel_sdvo_enc_destroy,
2219 };
2220
2221 static void
2222 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2223 {
2224 uint16_t mask = 0;
2225 unsigned int num_bits;
2226
2227 /* Make a mask of outputs less than or equal to our own priority in the
2228 * list.
2229 */
2230 switch (sdvo->controlled_output) {
2231 case SDVO_OUTPUT_LVDS1:
2232 mask |= SDVO_OUTPUT_LVDS1;
2233 case SDVO_OUTPUT_LVDS0:
2234 mask |= SDVO_OUTPUT_LVDS0;
2235 case SDVO_OUTPUT_TMDS1:
2236 mask |= SDVO_OUTPUT_TMDS1;
2237 case SDVO_OUTPUT_TMDS0:
2238 mask |= SDVO_OUTPUT_TMDS0;
2239 case SDVO_OUTPUT_RGB1:
2240 mask |= SDVO_OUTPUT_RGB1;
2241 case SDVO_OUTPUT_RGB0:
2242 mask |= SDVO_OUTPUT_RGB0;
2243 break;
2244 }
2245
2246 /* Count bits to find what number we are in the priority list. */
2247 mask &= sdvo->caps.output_flags;
2248 num_bits = hweight16(mask);
2249 /* If more than 3 outputs, default to DDC bus 3 for now. */
2250 if (num_bits > 3)
2251 num_bits = 3;
2252
2253 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2254 sdvo->ddc_bus = 1 << num_bits;
2255 }
2256
2257 /**
2258 * Choose the appropriate DDC bus for control bus switch command for this
2259 * SDVO output based on the controlled output.
2260 *
2261 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2262 * outputs, then LVDS outputs.
2263 */
2264 static void
2265 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2266 struct intel_sdvo *sdvo, u32 reg)
2267 {
2268 struct sdvo_device_mapping *mapping;
2269
2270 if (sdvo->is_sdvob)
2271 mapping = &(dev_priv->sdvo_mappings[0]);
2272 else
2273 mapping = &(dev_priv->sdvo_mappings[1]);
2274
2275 if (mapping->initialized)
2276 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2277 else
2278 intel_sdvo_guess_ddc_bus(sdvo);
2279 }
2280
2281 static void
2282 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2283 struct intel_sdvo *sdvo, u32 reg)
2284 {
2285 struct sdvo_device_mapping *mapping;
2286 u8 pin;
2287
2288 if (sdvo->is_sdvob)
2289 mapping = &dev_priv->sdvo_mappings[0];
2290 else
2291 mapping = &dev_priv->sdvo_mappings[1];
2292
2293 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
2294 pin = mapping->i2c_pin;
2295 else
2296 pin = GMBUS_PORT_DPB;
2297
2298 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2299
2300 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2301 * our code totally fails once we start using gmbus. Hence fall back to
2302 * bit banging for now. */
2303 intel_gmbus_force_bit(sdvo->i2c, true);
2304 }
2305
2306 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2307 static void
2308 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2309 {
2310 intel_gmbus_force_bit(sdvo->i2c, false);
2311 }
2312
2313 static bool
2314 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2315 {
2316 return intel_sdvo_check_supp_encode(intel_sdvo);
2317 }
2318
2319 static u8
2320 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
2321 {
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 struct sdvo_device_mapping *my_mapping, *other_mapping;
2324
2325 if (sdvo->is_sdvob) {
2326 my_mapping = &dev_priv->sdvo_mappings[0];
2327 other_mapping = &dev_priv->sdvo_mappings[1];
2328 } else {
2329 my_mapping = &dev_priv->sdvo_mappings[1];
2330 other_mapping = &dev_priv->sdvo_mappings[0];
2331 }
2332
2333 /* If the BIOS described our SDVO device, take advantage of it. */
2334 if (my_mapping->slave_addr)
2335 return my_mapping->slave_addr;
2336
2337 /* If the BIOS only described a different SDVO device, use the
2338 * address that it isn't using.
2339 */
2340 if (other_mapping->slave_addr) {
2341 if (other_mapping->slave_addr == 0x70)
2342 return 0x72;
2343 else
2344 return 0x70;
2345 }
2346
2347 /* No SDVO device info is found for another DVO port,
2348 * so use mapping assumption we had before BIOS parsing.
2349 */
2350 if (sdvo->is_sdvob)
2351 return 0x70;
2352 else
2353 return 0x72;
2354 }
2355
2356 static void
2357 intel_sdvo_connector_unregister(struct intel_connector *intel_connector)
2358 {
2359 struct drm_connector *drm_connector;
2360 struct intel_sdvo *sdvo_encoder;
2361
2362 drm_connector = &intel_connector->base;
2363 sdvo_encoder = intel_attached_sdvo(&intel_connector->base);
2364
2365 sysfs_remove_link(&drm_connector->kdev->kobj,
2366 sdvo_encoder->ddc.dev.kobj.name);
2367 intel_connector_unregister(intel_connector);
2368 }
2369
2370 static int
2371 intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2372 struct intel_sdvo *encoder)
2373 {
2374 struct drm_connector *drm_connector;
2375 int ret;
2376
2377 drm_connector = &connector->base.base;
2378 ret = drm_connector_init(encoder->base.base.dev,
2379 drm_connector,
2380 &intel_sdvo_connector_funcs,
2381 connector->base.base.connector_type);
2382 if (ret < 0)
2383 return ret;
2384
2385 drm_connector_helper_add(drm_connector,
2386 &intel_sdvo_connector_helper_funcs);
2387
2388 connector->base.base.interlace_allowed = 1;
2389 connector->base.base.doublescan_allowed = 0;
2390 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2391 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2392 connector->base.unregister = intel_sdvo_connector_unregister;
2393
2394 intel_connector_attach_encoder(&connector->base, &encoder->base);
2395 ret = drm_connector_register(drm_connector);
2396 if (ret < 0)
2397 goto err1;
2398
2399 ret = sysfs_create_link(&drm_connector->kdev->kobj,
2400 &encoder->ddc.dev.kobj,
2401 encoder->ddc.dev.kobj.name);
2402 if (ret < 0)
2403 goto err2;
2404
2405 return 0;
2406
2407 err2:
2408 drm_connector_unregister(drm_connector);
2409 err1:
2410 drm_connector_cleanup(drm_connector);
2411
2412 return ret;
2413 }
2414
2415 static void
2416 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2417 struct intel_sdvo_connector *connector)
2418 {
2419 struct drm_device *dev = connector->base.base.dev;
2420
2421 intel_attach_force_audio_property(&connector->base.base);
2422 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
2423 intel_attach_broadcast_rgb_property(&connector->base.base);
2424 intel_sdvo->color_range_auto = true;
2425 }
2426 }
2427
2428 static bool
2429 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2430 {
2431 struct drm_encoder *encoder = &intel_sdvo->base.base;
2432 struct drm_connector *connector;
2433 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2434 struct intel_connector *intel_connector;
2435 struct intel_sdvo_connector *intel_sdvo_connector;
2436
2437 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2438
2439 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
2440 if (!intel_sdvo_connector)
2441 return false;
2442
2443 if (device == 0) {
2444 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2445 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2446 } else if (device == 1) {
2447 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2448 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2449 }
2450
2451 intel_connector = &intel_sdvo_connector->base;
2452 connector = &intel_connector->base;
2453 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2454 intel_sdvo_connector->output_flag) {
2455 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2456 /* Some SDVO devices have one-shot hotplug interrupts.
2457 * Ensure that they get re-enabled when an interrupt happens.
2458 */
2459 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2460 intel_sdvo_enable_hotplug(intel_encoder);
2461 } else {
2462 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2463 }
2464 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2465 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2466
2467 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2468 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2469 intel_sdvo->is_hdmi = true;
2470 }
2471
2472 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2473 kfree(intel_sdvo_connector);
2474 return false;
2475 }
2476
2477 if (intel_sdvo->is_hdmi)
2478 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2479
2480 return true;
2481 }
2482
2483 static bool
2484 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2485 {
2486 struct drm_encoder *encoder = &intel_sdvo->base.base;
2487 struct drm_connector *connector;
2488 struct intel_connector *intel_connector;
2489 struct intel_sdvo_connector *intel_sdvo_connector;
2490
2491 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2492
2493 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
2494 if (!intel_sdvo_connector)
2495 return false;
2496
2497 intel_connector = &intel_sdvo_connector->base;
2498 connector = &intel_connector->base;
2499 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2500 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2501
2502 intel_sdvo->controlled_output |= type;
2503 intel_sdvo_connector->output_flag = type;
2504
2505 intel_sdvo->is_tv = true;
2506
2507 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2508 kfree(intel_sdvo_connector);
2509 return false;
2510 }
2511
2512 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2513 goto err;
2514
2515 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2516 goto err;
2517
2518 return true;
2519
2520 err:
2521 drm_connector_unregister(connector);
2522 intel_sdvo_destroy(connector);
2523 return false;
2524 }
2525
2526 static bool
2527 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2528 {
2529 struct drm_encoder *encoder = &intel_sdvo->base.base;
2530 struct drm_connector *connector;
2531 struct intel_connector *intel_connector;
2532 struct intel_sdvo_connector *intel_sdvo_connector;
2533
2534 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2535
2536 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
2537 if (!intel_sdvo_connector)
2538 return false;
2539
2540 intel_connector = &intel_sdvo_connector->base;
2541 connector = &intel_connector->base;
2542 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2543 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2544 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2545
2546 if (device == 0) {
2547 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2548 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2549 } else if (device == 1) {
2550 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2551 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2552 }
2553
2554 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2555 kfree(intel_sdvo_connector);
2556 return false;
2557 }
2558
2559 return true;
2560 }
2561
2562 static bool
2563 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2564 {
2565 struct drm_encoder *encoder = &intel_sdvo->base.base;
2566 struct drm_connector *connector;
2567 struct intel_connector *intel_connector;
2568 struct intel_sdvo_connector *intel_sdvo_connector;
2569
2570 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2571
2572 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
2573 if (!intel_sdvo_connector)
2574 return false;
2575
2576 intel_connector = &intel_sdvo_connector->base;
2577 connector = &intel_connector->base;
2578 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2579 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2580
2581 if (device == 0) {
2582 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2583 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2584 } else if (device == 1) {
2585 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2586 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2587 }
2588
2589 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2590 kfree(intel_sdvo_connector);
2591 return false;
2592 }
2593
2594 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2595 goto err;
2596
2597 return true;
2598
2599 err:
2600 drm_connector_unregister(connector);
2601 intel_sdvo_destroy(connector);
2602 return false;
2603 }
2604
2605 static bool
2606 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2607 {
2608 intel_sdvo->is_tv = false;
2609 intel_sdvo->is_lvds = false;
2610
2611 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2612
2613 if (flags & SDVO_OUTPUT_TMDS0)
2614 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2615 return false;
2616
2617 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2618 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2619 return false;
2620
2621 /* TV has no XXX1 function block */
2622 if (flags & SDVO_OUTPUT_SVID0)
2623 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2624 return false;
2625
2626 if (flags & SDVO_OUTPUT_CVBS0)
2627 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2628 return false;
2629
2630 if (flags & SDVO_OUTPUT_YPRPB0)
2631 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2632 return false;
2633
2634 if (flags & SDVO_OUTPUT_RGB0)
2635 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2636 return false;
2637
2638 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2639 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2640 return false;
2641
2642 if (flags & SDVO_OUTPUT_LVDS0)
2643 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2644 return false;
2645
2646 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2647 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2648 return false;
2649
2650 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2651 unsigned char bytes[2];
2652
2653 intel_sdvo->controlled_output = 0;
2654 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2655 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2656 SDVO_NAME(intel_sdvo),
2657 bytes[0], bytes[1]);
2658 return false;
2659 }
2660 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2661
2662 return true;
2663 }
2664
2665 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2666 {
2667 struct drm_device *dev = intel_sdvo->base.base.dev;
2668 struct drm_connector *connector, *tmp;
2669
2670 list_for_each_entry_safe(connector, tmp,
2671 &dev->mode_config.connector_list, head) {
2672 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
2673 drm_connector_unregister(connector);
2674 intel_sdvo_destroy(connector);
2675 }
2676 }
2677 }
2678
2679 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2680 struct intel_sdvo_connector *intel_sdvo_connector,
2681 int type)
2682 {
2683 struct drm_device *dev = intel_sdvo->base.base.dev;
2684 struct intel_sdvo_tv_format format;
2685 uint32_t format_map, i;
2686
2687 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2688 return false;
2689
2690 BUILD_BUG_ON(sizeof(format) != 6);
2691 if (!intel_sdvo_get_value(intel_sdvo,
2692 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2693 &format, sizeof(format)))
2694 return false;
2695
2696 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2697
2698 if (format_map == 0)
2699 return false;
2700
2701 intel_sdvo_connector->format_supported_num = 0;
2702 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2703 if (format_map & (1 << i))
2704 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2705
2706
2707 intel_sdvo_connector->tv_format =
2708 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2709 "mode", intel_sdvo_connector->format_supported_num);
2710 if (!intel_sdvo_connector->tv_format)
2711 return false;
2712
2713 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2714 drm_property_add_enum(
2715 intel_sdvo_connector->tv_format, i,
2716 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2717
2718 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
2719 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2720 intel_sdvo_connector->tv_format, 0);
2721 return true;
2722
2723 }
2724
2725 #define ENHANCEMENT(name, NAME) do { \
2726 if (enhancements.name) { \
2727 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2728 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2729 return false; \
2730 intel_sdvo_connector->max_##name = data_value[0]; \
2731 intel_sdvo_connector->cur_##name = response; \
2732 intel_sdvo_connector->name = \
2733 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2734 if (!intel_sdvo_connector->name) return false; \
2735 drm_object_attach_property(&connector->base, \
2736 intel_sdvo_connector->name, \
2737 intel_sdvo_connector->cur_##name); \
2738 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2739 data_value[0], data_value[1], response); \
2740 } \
2741 } while (0)
2742
2743 static bool
2744 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2745 struct intel_sdvo_connector *intel_sdvo_connector,
2746 struct intel_sdvo_enhancements_reply enhancements)
2747 {
2748 struct drm_device *dev = intel_sdvo->base.base.dev;
2749 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2750 uint16_t response, data_value[2];
2751
2752 /* when horizontal overscan is supported, Add the left/right property */
2753 if (enhancements.overscan_h) {
2754 if (!intel_sdvo_get_value(intel_sdvo,
2755 SDVO_CMD_GET_MAX_OVERSCAN_H,
2756 &data_value, 4))
2757 return false;
2758
2759 if (!intel_sdvo_get_value(intel_sdvo,
2760 SDVO_CMD_GET_OVERSCAN_H,
2761 &response, 2))
2762 return false;
2763
2764 intel_sdvo_connector->max_hscan = data_value[0];
2765 intel_sdvo_connector->left_margin = data_value[0] - response;
2766 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2767 intel_sdvo_connector->left =
2768 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2769 if (!intel_sdvo_connector->left)
2770 return false;
2771
2772 drm_object_attach_property(&connector->base,
2773 intel_sdvo_connector->left,
2774 intel_sdvo_connector->left_margin);
2775
2776 intel_sdvo_connector->right =
2777 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
2778 if (!intel_sdvo_connector->right)
2779 return false;
2780
2781 drm_object_attach_property(&connector->base,
2782 intel_sdvo_connector->right,
2783 intel_sdvo_connector->right_margin);
2784 DRM_DEBUG_KMS("h_overscan: max %d, "
2785 "default %d, current %d\n",
2786 data_value[0], data_value[1], response);
2787 }
2788
2789 if (enhancements.overscan_v) {
2790 if (!intel_sdvo_get_value(intel_sdvo,
2791 SDVO_CMD_GET_MAX_OVERSCAN_V,
2792 &data_value, 4))
2793 return false;
2794
2795 if (!intel_sdvo_get_value(intel_sdvo,
2796 SDVO_CMD_GET_OVERSCAN_V,
2797 &response, 2))
2798 return false;
2799
2800 intel_sdvo_connector->max_vscan = data_value[0];
2801 intel_sdvo_connector->top_margin = data_value[0] - response;
2802 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2803 intel_sdvo_connector->top =
2804 drm_property_create_range(dev, 0,
2805 "top_margin", 0, data_value[0]);
2806 if (!intel_sdvo_connector->top)
2807 return false;
2808
2809 drm_object_attach_property(&connector->base,
2810 intel_sdvo_connector->top,
2811 intel_sdvo_connector->top_margin);
2812
2813 intel_sdvo_connector->bottom =
2814 drm_property_create_range(dev, 0,
2815 "bottom_margin", 0, data_value[0]);
2816 if (!intel_sdvo_connector->bottom)
2817 return false;
2818
2819 drm_object_attach_property(&connector->base,
2820 intel_sdvo_connector->bottom,
2821 intel_sdvo_connector->bottom_margin);
2822 DRM_DEBUG_KMS("v_overscan: max %d, "
2823 "default %d, current %d\n",
2824 data_value[0], data_value[1], response);
2825 }
2826
2827 ENHANCEMENT(hpos, HPOS);
2828 ENHANCEMENT(vpos, VPOS);
2829 ENHANCEMENT(saturation, SATURATION);
2830 ENHANCEMENT(contrast, CONTRAST);
2831 ENHANCEMENT(hue, HUE);
2832 ENHANCEMENT(sharpness, SHARPNESS);
2833 ENHANCEMENT(brightness, BRIGHTNESS);
2834 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2835 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2836 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2837 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2838 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
2839
2840 if (enhancements.dot_crawl) {
2841 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2842 return false;
2843
2844 intel_sdvo_connector->max_dot_crawl = 1;
2845 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2846 intel_sdvo_connector->dot_crawl =
2847 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
2848 if (!intel_sdvo_connector->dot_crawl)
2849 return false;
2850
2851 drm_object_attach_property(&connector->base,
2852 intel_sdvo_connector->dot_crawl,
2853 intel_sdvo_connector->cur_dot_crawl);
2854 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2855 }
2856
2857 return true;
2858 }
2859
2860 static bool
2861 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2862 struct intel_sdvo_connector *intel_sdvo_connector,
2863 struct intel_sdvo_enhancements_reply enhancements)
2864 {
2865 struct drm_device *dev = intel_sdvo->base.base.dev;
2866 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2867 uint16_t response, data_value[2];
2868
2869 ENHANCEMENT(brightness, BRIGHTNESS);
2870
2871 return true;
2872 }
2873 #undef ENHANCEMENT
2874
2875 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2876 struct intel_sdvo_connector *intel_sdvo_connector)
2877 {
2878 union {
2879 struct intel_sdvo_enhancements_reply reply;
2880 uint16_t response;
2881 } enhancements;
2882
2883 BUILD_BUG_ON(sizeof(enhancements) != 2);
2884
2885 enhancements.response = 0;
2886 intel_sdvo_get_value(intel_sdvo,
2887 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2888 &enhancements, sizeof(enhancements));
2889 if (enhancements.response == 0) {
2890 DRM_DEBUG_KMS("No enhancement is supported\n");
2891 return true;
2892 }
2893
2894 if (IS_TV(intel_sdvo_connector))
2895 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2896 else if (IS_LVDS(intel_sdvo_connector))
2897 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2898 else
2899 return true;
2900 }
2901
2902 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2903 struct i2c_msg *msgs,
2904 int num)
2905 {
2906 struct intel_sdvo *sdvo = adapter->algo_data;
2907
2908 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2909 return -EIO;
2910
2911 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2912 }
2913
2914 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2915 {
2916 struct intel_sdvo *sdvo = adapter->algo_data;
2917 return sdvo->i2c->algo->functionality(sdvo->i2c);
2918 }
2919
2920 static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2921 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2922 .functionality = intel_sdvo_ddc_proxy_func
2923 };
2924
2925 static bool
2926 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2927 struct drm_device *dev)
2928 {
2929 sdvo->ddc.owner = THIS_MODULE;
2930 sdvo->ddc.class = I2C_CLASS_DDC;
2931 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2932 sdvo->ddc.dev.parent = &dev->pdev->dev;
2933 sdvo->ddc.algo_data = sdvo;
2934 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2935
2936 return i2c_add_adapter(&sdvo->ddc) == 0;
2937 }
2938
2939 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
2940 {
2941 struct drm_i915_private *dev_priv = dev->dev_private;
2942 struct intel_encoder *intel_encoder;
2943 struct intel_sdvo *intel_sdvo;
2944 int i;
2945 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
2946 if (!intel_sdvo)
2947 return false;
2948
2949 intel_sdvo->sdvo_reg = sdvo_reg;
2950 intel_sdvo->is_sdvob = is_sdvob;
2951 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
2952 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
2953 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2954 goto err_i2c_bus;
2955
2956 /* encoder type will be decided later */
2957 intel_encoder = &intel_sdvo->base;
2958 intel_encoder->type = INTEL_OUTPUT_SDVO;
2959 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2960
2961 /* Read the regs to test if we can talk to the device */
2962 for (i = 0; i < 0x40; i++) {
2963 u8 byte;
2964
2965 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
2966 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2967 SDVO_NAME(intel_sdvo));
2968 goto err;
2969 }
2970 }
2971
2972 intel_encoder->compute_config = intel_sdvo_compute_config;
2973 intel_encoder->disable = intel_disable_sdvo;
2974 intel_encoder->pre_enable = intel_sdvo_pre_enable;
2975 intel_encoder->enable = intel_enable_sdvo;
2976 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
2977 intel_encoder->get_config = intel_sdvo_get_config;
2978
2979 /* In default case sdvo lvds is false */
2980 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2981 goto err;
2982
2983 if (intel_sdvo_output_setup(intel_sdvo,
2984 intel_sdvo->caps.output_flags) != true) {
2985 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2986 SDVO_NAME(intel_sdvo));
2987 /* Output_setup can leave behind connectors! */
2988 goto err_output;
2989 }
2990
2991 /* Only enable the hotplug irq if we need it, to work around noisy
2992 * hotplug lines.
2993 */
2994 if (intel_sdvo->hotplug_active) {
2995 intel_encoder->hpd_pin =
2996 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
2997 }
2998
2999 /*
3000 * Cloning SDVO with anything is often impossible, since the SDVO
3001 * encoder can request a special input timing mode. And even if that's
3002 * not the case we have evidence that cloning a plain unscaled mode with
3003 * VGA doesn't really work. Furthermore the cloning flags are way too
3004 * simplistic anyway to express such constraints, so just give up on
3005 * cloning for SDVO encoders.
3006 */
3007 intel_sdvo->base.cloneable = 0;
3008
3009 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
3010
3011 /* Set the input timing to the screen. Assume always input 0. */
3012 if (!intel_sdvo_set_target_input(intel_sdvo))
3013 goto err_output;
3014
3015 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3016 &intel_sdvo->pixel_clock_min,
3017 &intel_sdvo->pixel_clock_max))
3018 goto err_output;
3019
3020 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
3021 "clock range %dMHz - %dMHz, "
3022 "input 1: %c, input 2: %c, "
3023 "output 1: %c, output 2: %c\n",
3024 SDVO_NAME(intel_sdvo),
3025 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3026 intel_sdvo->caps.device_rev_id,
3027 intel_sdvo->pixel_clock_min / 1000,
3028 intel_sdvo->pixel_clock_max / 1000,
3029 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3030 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
3031 /* check currently supported outputs */
3032 intel_sdvo->caps.output_flags &
3033 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
3034 intel_sdvo->caps.output_flags &
3035 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
3036 return true;
3037
3038 err_output:
3039 intel_sdvo_output_cleanup(intel_sdvo);
3040
3041 err:
3042 drm_encoder_cleanup(&intel_encoder->base);
3043 i2c_del_adapter(&intel_sdvo->ddc);
3044 err_i2c_bus:
3045 intel_sdvo_unselect_i2c_bus(intel_sdvo);
3046 kfree(intel_sdvo);
3047
3048 return false;
3049 }
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