drivers/gpu/drm/i915/intel_sdvo_regs.h

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 /**
  28  * @file SDVO command definitions and structures.
  29  */
  30
  31 #define SDVO_OUTPUT_FIRST   (0)
  32 #define SDVO_OUTPUT_TMDS0   (1 << 0)
  33 #define SDVO_OUTPUT_RGB0    (1 << 1)
  34 #define SDVO_OUTPUT_CVBS0   (1 << 2)
  35 #define SDVO_OUTPUT_SVID0   (1 << 3)
  36 #define SDVO_OUTPUT_YPRPB0  (1 << 4)
  37 #define SDVO_OUTPUT_SCART0  (1 << 5)
  38 #define SDVO_OUTPUT_LVDS0   (1 << 6)
  39 #define SDVO_OUTPUT_TMDS1   (1 << 8)
  40 #define SDVO_OUTPUT_RGB1    (1 << 9)
  41 #define SDVO_OUTPUT_CVBS1   (1 << 10)
  42 #define SDVO_OUTPUT_SVID1   (1 << 11)
  43 #define SDVO_OUTPUT_YPRPB1  (1 << 12)
  44 #define SDVO_OUTPUT_SCART1  (1 << 13)
  45 #define SDVO_OUTPUT_LVDS1   (1 << 14)
  46 #define SDVO_OUTPUT_LAST    (14)
  47
  48 struct intel_sdvo_caps {
  49     u8 vendor_id;
  50     u8 device_id;
  51     u8 device_rev_id;
  52     u8 sdvo_version_major;
  53     u8 sdvo_version_minor;
  54     unsigned int sdvo_inputs_mask:2;
  55     unsigned int smooth_scaling:1;
  56     unsigned int sharp_scaling:1;
  57     unsigned int up_scaling:1;
  58     unsigned int down_scaling:1;
  59     unsigned int stall_support:1;
  60     unsigned int pad:1;
  61     u16 output_flags;
  62 } __attribute__((packed));
  63
  64 /** This matches the EDID DTD structure, more or less */
  65 struct intel_sdvo_dtd {
  66     struct {
  67         u16 clock;              /**< pixel clock, in 10kHz units */
  68         u8 h_active;            /**< lower 8 bits (pixels) */
  69         u8 h_blank;             /**< lower 8 bits (pixels) */
  70         u8 h_high;              /**< upper 4 bits each h_active, h_blank */
  71         u8 v_active;            /**< lower 8 bits (lines) */
  72         u8 v_blank;             /**< lower 8 bits (lines) */
  73         u8 v_high;              /**< upper 4 bits each v_active, v_blank */
  74     } part1;
  75
  76     struct {
  77         u8 h_sync_off;  /**< lower 8 bits, from hblank start */
  78         u8 h_sync_width;        /**< lower 8 bits (pixels) */
  79         /** lower 4 bits each vsync offset, vsync width */
  80         u8 v_sync_off_width;
  81         /**
  82          * 2 high bits of hsync offset, 2 high bits of hsync width,
  83          * bits 4-5 of vsync offset, and 2 high bits of vsync width.
  84          */
  85         u8 sync_off_width_high;
  86         u8 dtd_flags;
  87         u8 sdvo_flags;
  88         /** bits 6-7 of vsync offset at bits 6-7 */
  89         u8 v_sync_off_high;
  90         u8 reserved;
  91     } part2;
  92 } __attribute__((packed));
  93
  94 struct intel_sdvo_pixel_clock_range {
  95     u16 min;                    /**< pixel clock, in 10kHz units */
  96     u16 max;                    /**< pixel clock, in 10kHz units */
  97 } __attribute__((packed));
  98
  99 struct intel_sdvo_preferred_input_timing_args {
 100     u16 clock;
 101     u16 width;
 102     u16 height;
 103 } __attribute__((packed));
 104
 105 /* I2C registers for SDVO */
 106 #define SDVO_I2C_ARG_0                          0x07
 107 #define SDVO_I2C_ARG_1                          0x06
 108 #define SDVO_I2C_ARG_2                          0x05
 109 #define SDVO_I2C_ARG_3                          0x04
 110 #define SDVO_I2C_ARG_4                          0x03
 111 #define SDVO_I2C_ARG_5                          0x02
 112 #define SDVO_I2C_ARG_6                          0x01
 113 #define SDVO_I2C_ARG_7                          0x00
 114 #define SDVO_I2C_OPCODE                         0x08
 115 #define SDVO_I2C_CMD_STATUS                     0x09
 116 #define SDVO_I2C_RETURN_0                       0x0a
 117 #define SDVO_I2C_RETURN_1                       0x0b
 118 #define SDVO_I2C_RETURN_2                       0x0c
 119 #define SDVO_I2C_RETURN_3                       0x0d
 120 #define SDVO_I2C_RETURN_4                       0x0e
 121 #define SDVO_I2C_RETURN_5                       0x0f
 122 #define SDVO_I2C_RETURN_6                       0x10
 123 #define SDVO_I2C_RETURN_7                       0x11
 124 #define SDVO_I2C_VENDOR_BEGIN                   0x20
 125
 126 /* Status results */
 127 #define SDVO_CMD_STATUS_POWER_ON                0x0
 128 #define SDVO_CMD_STATUS_SUCCESS                 0x1
 129 #define SDVO_CMD_STATUS_NOTSUPP                 0x2
 130 #define SDVO_CMD_STATUS_INVALID_ARG             0x3
 131 #define SDVO_CMD_STATUS_PENDING                 0x4
 132 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED    0x5
 133 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP        0x6
 134
 135 /* SDVO commands, argument/result registers */
 136
 137 #define SDVO_CMD_RESET                                  0x01
 138
 139 /** Returns a struct intel_sdvo_caps */
 140 #define SDVO_CMD_GET_DEVICE_CAPS                        0x02
 141
 142 #define SDVO_CMD_GET_FIRMWARE_REV                       0x86
 143 # define SDVO_DEVICE_FIRMWARE_MINOR                     SDVO_I2C_RETURN_0
 144 # define SDVO_DEVICE_FIRMWARE_MAJOR                     SDVO_I2C_RETURN_1
 145 # define SDVO_DEVICE_FIRMWARE_PATCH                     SDVO_I2C_RETURN_2
 146
 147 /**
 148  * Reports which inputs are trained (managed to sync).
 149  *
 150  * Devices must have trained within 2 vsyncs of a mode change.
 151  */
 152 #define SDVO_CMD_GET_TRAINED_INPUTS                     0x03
 153 struct intel_sdvo_get_trained_inputs_response {
 154     unsigned int input0_trained:1;
 155     unsigned int input1_trained:1;
 156     unsigned int pad:6;
 157 } __attribute__((packed));
 158
 159 /** Returns a struct intel_sdvo_output_flags of active outputs. */
 160 #define SDVO_CMD_GET_ACTIVE_OUTPUTS                     0x04
 161
 162 /**
 163  * Sets the current set of active outputs.
 164  *
 165  * Takes a struct intel_sdvo_output_flags.  Must be preceded by a SET_IN_OUT_MAP
 166  * on multi-output devices.
 167  */
 168 #define SDVO_CMD_SET_ACTIVE_OUTPUTS                     0x05
 169
 170 /**
 171  * Returns the current mapping of SDVO inputs to outputs on the device.
 172  *
 173  * Returns two struct intel_sdvo_output_flags structures.
 174  */
 175 #define SDVO_CMD_GET_IN_OUT_MAP                         0x06
 176
 177 /**
 178  * Sets the current mapping of SDVO inputs to outputs on the device.
 179  *
 180  * Takes two struct i380_sdvo_output_flags structures.
 181  */
 182 #define SDVO_CMD_SET_IN_OUT_MAP                         0x07
 183
 184 /**
 185  * Returns a struct intel_sdvo_output_flags of attached displays.
 186  */
 187 #define SDVO_CMD_GET_ATTACHED_DISPLAYS                  0x0b
 188
 189 /**
 190  * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging.
 191  */
 192 #define SDVO_CMD_GET_HOT_PLUG_SUPPORT                   0x0c
 193
 194 /**
 195  * Takes a struct intel_sdvo_output_flags.
 196  */
 197 #define SDVO_CMD_SET_ACTIVE_HOT_PLUG                    0x0d
 198
 199 /**
 200  * Returns a struct intel_sdvo_output_flags of displays with hot plug
 201  * interrupts enabled.
 202  */
 203 #define SDVO_CMD_GET_ACTIVE_HOT_PLUG                    0x0e
 204
 205 #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE             0x0f
 206 struct intel_sdvo_get_interrupt_event_source_response {
 207     u16 interrupt_status;
 208     unsigned int ambient_light_interrupt:1;
 209     unsigned int pad:7;
 210 } __attribute__((packed));
 211
 212 /**
 213  * Selects which input is affected by future input commands.
 214  *
 215  * Commands affected include SET_INPUT_TIMINGS_PART[12],
 216  * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],
 217  * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.
 218  */
 219 #define SDVO_CMD_SET_TARGET_INPUT                       0x10
 220 struct intel_sdvo_set_target_input_args {
 221     unsigned int target_1:1;
 222     unsigned int pad:7;
 223 } __attribute__((packed));
 224
 225 /**
 226  * Takes a struct intel_sdvo_output_flags of which outputs are targetted by
 227  * future output commands.
 228  *
 229  * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
 230  * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
 231  */
 232 #define SDVO_CMD_SET_TARGET_OUTPUT                      0x11
 233
 234 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1                0x12
 235 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2                0x13
 236 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1                0x14
 237 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2                0x15
 238 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1               0x16
 239 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2               0x17
 240 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1               0x18
 241 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2               0x19
 242 /* Part 1 */
 243 # define SDVO_DTD_CLOCK_LOW                             SDVO_I2C_ARG_0
 244 # define SDVO_DTD_CLOCK_HIGH                            SDVO_I2C_ARG_1
 245 # define SDVO_DTD_H_ACTIVE                              SDVO_I2C_ARG_2
 246 # define SDVO_DTD_H_BLANK                               SDVO_I2C_ARG_3
 247 # define SDVO_DTD_H_HIGH                                SDVO_I2C_ARG_4
 248 # define SDVO_DTD_V_ACTIVE                              SDVO_I2C_ARG_5
 249 # define SDVO_DTD_V_BLANK                               SDVO_I2C_ARG_6
 250 # define SDVO_DTD_V_HIGH                                SDVO_I2C_ARG_7
 251 /* Part 2 */
 252 # define SDVO_DTD_HSYNC_OFF                             SDVO_I2C_ARG_0
 253 # define SDVO_DTD_HSYNC_WIDTH                           SDVO_I2C_ARG_1
 254 # define SDVO_DTD_VSYNC_OFF_WIDTH                       SDVO_I2C_ARG_2
 255 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH                   SDVO_I2C_ARG_3
 256 # define SDVO_DTD_DTD_FLAGS                             SDVO_I2C_ARG_4
 257 # define SDVO_DTD_DTD_FLAG_INTERLACED                           (1 << 7)
 258 # define SDVO_DTD_DTD_FLAG_STEREO_MASK                          (3 << 5)
 259 # define SDVO_DTD_DTD_FLAG_INPUT_MASK                           (3 << 3)
 260 # define SDVO_DTD_DTD_FLAG_SYNC_MASK                            (3 << 1)
 261 # define SDVO_DTD_SDVO_FLAS                             SDVO_I2C_ARG_5
 262 # define SDVO_DTD_SDVO_FLAG_STALL                               (1 << 7)
 263 # define SDVO_DTD_SDVO_FLAG_CENTERED                            (0 << 6)
 264 # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT                          (1 << 6)
 265 # define SDVO_DTD_SDVO_FLAG_SCALING_MASK                        (3 << 4)
 266 # define SDVO_DTD_SDVO_FLAG_SCALING_NONE                        (0 << 4)
 267 # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP                       (1 << 4)
 268 # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH                      (2 << 4)
 269 # define SDVO_DTD_VSYNC_OFF_HIGH                        SDVO_I2C_ARG_6
 270
 271 /**
 272  * Generates a DTD based on the given width, height, and flags.
 273  *
 274  * This will be supported by any device supporting scaling or interlaced
 275  * modes.
 276  */
 277 #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING          0x1a
 278 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW          SDVO_I2C_ARG_0
 279 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH         SDVO_I2C_ARG_1
 280 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW          SDVO_I2C_ARG_2
 281 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH         SDVO_I2C_ARG_3
 282 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW         SDVO_I2C_ARG_4
 283 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH        SDVO_I2C_ARG_5
 284 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS              SDVO_I2C_ARG_6
 285 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED           (1 << 0)
 286 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED               (1 << 1)
 287
 288 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1       0x1b
 289 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2       0x1c
 290
 291 /** Returns a struct intel_sdvo_pixel_clock_range */
 292 #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE            0x1d
 293 /** Returns a struct intel_sdvo_pixel_clock_range */
 294 #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE           0x1e
 295
 296 /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
 297 #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS         0x1f
 298
 299 /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
 300 #define SDVO_CMD_GET_CLOCK_RATE_MULT                    0x20
 301 /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
 302 #define SDVO_CMD_SET_CLOCK_RATE_MULT                    0x21
 303 # define SDVO_CLOCK_RATE_MULT_1X                                (1 << 0)
 304 # define SDVO_CLOCK_RATE_MULT_2X                                (1 << 1)
 305 # define SDVO_CLOCK_RATE_MULT_4X                                (1 << 3)
 306
 307 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS               0x27
 308
 309 #define SDVO_CMD_GET_TV_FORMAT                          0x28
 310
 311 #define SDVO_CMD_SET_TV_FORMAT                          0x29
 312
 313 #define SDVO_CMD_GET_SUPPORTED_POWER_STATES             0x2a
 314 #define SDVO_CMD_GET_ENCODER_POWER_STATE                0x2b
 315 #define SDVO_CMD_SET_ENCODER_POWER_STATE                0x2c
 316 # define SDVO_ENCODER_STATE_ON                                  (1 << 0)
 317 # define SDVO_ENCODER_STATE_STANDBY                             (1 << 1)
 318 # define SDVO_ENCODER_STATE_SUSPEND                             (1 << 2)
 319 # define SDVO_ENCODER_STATE_OFF                                 (1 << 3)
 320
 321 #define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT              0x93
 322
 323 #define SDVO_CMD_SET_CONTROL_BUS_SWITCH                 0x7a
 324 # define SDVO_CONTROL_BUS_PROM                          0x0
 325 # define SDVO_CONTROL_BUS_DDC1                          0x1
 326 # define SDVO_CONTROL_BUS_DDC2                          0x2
 327 # define SDVO_CONTROL_BUS_DDC3                          0x3