2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_fourcc.h>
36 #include <drm/drm_rect.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_plane_helper.h>
39 #include "intel_drv.h"
40 #include "intel_frontbuffer.h"
41 #include <drm/i915_drm.h>
45 format_is_yuv(uint32_t format
)
58 int intel_usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
62 if (!adjusted_mode
->crtc_htotal
)
65 return DIV_ROUND_UP(usecs
* adjusted_mode
->crtc_clock
,
66 1000 * adjusted_mode
->crtc_htotal
);
69 #define VBLANK_EVASION_TIME_US 100
72 * intel_pipe_update_start() - start update of a set of display registers
73 * @new_crtc_state: the new crtc state
75 * Mark the start of an update to pipe registers that should be updated
76 * atomically regarding vblank. If the next vblank will happens within
77 * the next 100 us, this function waits until the vblank passes.
79 * After a successful call to this function, interrupts will be disabled
80 * until a subsequent call to intel_pipe_update_end(). That is done to
81 * avoid random delays.
83 void intel_pipe_update_start(const struct intel_crtc_state
*new_crtc_state
)
85 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
86 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
87 const struct drm_display_mode
*adjusted_mode
= &new_crtc_state
->base
.adjusted_mode
;
88 long timeout
= msecs_to_jiffies_timeout(1);
89 int scanline
, min
, max
, vblank_start
;
90 wait_queue_head_t
*wq
= drm_crtc_vblank_waitqueue(&crtc
->base
);
91 bool need_vlv_dsi_wa
= (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
92 intel_crtc_has_type(new_crtc_state
, INTEL_OUTPUT_DSI
);
95 vblank_start
= adjusted_mode
->crtc_vblank_start
;
96 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
97 vblank_start
= DIV_ROUND_UP(vblank_start
, 2);
99 /* FIXME needs to be calibrated sensibly */
100 min
= vblank_start
- intel_usecs_to_scanlines(adjusted_mode
,
101 VBLANK_EVASION_TIME_US
);
102 max
= vblank_start
- 1;
106 if (min
<= 0 || max
<= 0)
109 if (WARN_ON(drm_crtc_vblank_get(&crtc
->base
)))
112 crtc
->debug
.min_vbl
= min
;
113 crtc
->debug
.max_vbl
= max
;
114 trace_i915_pipe_update_start(crtc
);
118 * prepare_to_wait() has a memory barrier, which guarantees
119 * other CPUs can see the task state update by the time we
122 prepare_to_wait(wq
, &wait
, TASK_UNINTERRUPTIBLE
);
124 scanline
= intel_get_crtc_scanline(crtc
);
125 if (scanline
< min
|| scanline
> max
)
129 DRM_ERROR("Potential atomic update failure on pipe %c\n",
130 pipe_name(crtc
->pipe
));
136 timeout
= schedule_timeout(timeout
);
141 finish_wait(wq
, &wait
);
143 drm_crtc_vblank_put(&crtc
->base
);
146 * On VLV/CHV DSI the scanline counter would appear to
147 * increment approx. 1/3 of a scanline before start of vblank.
148 * The registers still get latched at start of vblank however.
149 * This means we must not write any registers on the first
150 * line of vblank (since not the whole line is actually in
151 * vblank). And unfortunately we can't use the interrupt to
152 * wait here since it will fire too soon. We could use the
153 * frame start interrupt instead since it will fire after the
154 * critical scanline, but that would require more changes
155 * in the interrupt code. So for now we'll just do the nasty
156 * thing and poll for the bad scanline to pass us by.
158 * FIXME figure out if BXT+ DSI suffers from this as well
160 while (need_vlv_dsi_wa
&& scanline
== vblank_start
)
161 scanline
= intel_get_crtc_scanline(crtc
);
163 crtc
->debug
.scanline_start
= scanline
;
164 crtc
->debug
.start_vbl_time
= ktime_get();
165 crtc
->debug
.start_vbl_count
= intel_crtc_get_vblank_counter(crtc
);
167 trace_i915_pipe_update_vblank_evaded(crtc
);
171 * intel_pipe_update_end() - end update of a set of display registers
172 * @new_crtc_state: the new crtc state
174 * Mark the end of an update started with intel_pipe_update_start(). This
175 * re-enables interrupts and verifies the update was actually completed
178 void intel_pipe_update_end(struct intel_crtc_state
*new_crtc_state
)
180 struct intel_crtc
*crtc
= to_intel_crtc(new_crtc_state
->base
.crtc
);
181 enum pipe pipe
= crtc
->pipe
;
182 int scanline_end
= intel_get_crtc_scanline(crtc
);
183 u32 end_vbl_count
= intel_crtc_get_vblank_counter(crtc
);
184 ktime_t end_vbl_time
= ktime_get();
185 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
187 trace_i915_pipe_update_end(crtc
, end_vbl_count
, scanline_end
);
189 /* We're still in the vblank-evade critical section, this can't race.
190 * Would be slightly nice to just grab the vblank count and arm the
191 * event outside of the critical section - the spinlock might spin for a
193 if (new_crtc_state
->base
.event
) {
194 WARN_ON(drm_crtc_vblank_get(&crtc
->base
) != 0);
196 spin_lock(&crtc
->base
.dev
->event_lock
);
197 drm_crtc_arm_vblank_event(&crtc
->base
, new_crtc_state
->base
.event
);
198 spin_unlock(&crtc
->base
.dev
->event_lock
);
200 new_crtc_state
->base
.event
= NULL
;
205 if (intel_vgpu_active(dev_priv
))
208 if (crtc
->debug
.start_vbl_count
&&
209 crtc
->debug
.start_vbl_count
!= end_vbl_count
) {
210 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
211 pipe_name(pipe
), crtc
->debug
.start_vbl_count
,
213 ktime_us_delta(end_vbl_time
, crtc
->debug
.start_vbl_time
),
214 crtc
->debug
.min_vbl
, crtc
->debug
.max_vbl
,
215 crtc
->debug
.scanline_start
, scanline_end
);
217 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
218 else if (ktime_us_delta(end_vbl_time
, crtc
->debug
.start_vbl_time
) >
219 VBLANK_EVASION_TIME_US
)
220 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
222 ktime_us_delta(end_vbl_time
, crtc
->debug
.start_vbl_time
),
223 VBLANK_EVASION_TIME_US
);
228 skl_update_plane(struct intel_plane
*plane
,
229 const struct intel_crtc_state
*crtc_state
,
230 const struct intel_plane_state
*plane_state
)
232 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
233 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
234 enum plane_id plane_id
= plane
->id
;
235 enum pipe pipe
= plane
->pipe
;
236 u32 plane_ctl
= plane_state
->ctl
;
237 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
238 u32 surf_addr
= plane_state
->main
.offset
;
239 unsigned int rotation
= plane_state
->base
.rotation
;
240 u32 stride
= skl_plane_stride(fb
, 0, rotation
);
241 u32 aux_stride
= skl_plane_stride(fb
, 1, rotation
);
242 int crtc_x
= plane_state
->base
.dst
.x1
;
243 int crtc_y
= plane_state
->base
.dst
.y1
;
244 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
245 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
246 uint32_t x
= plane_state
->main
.x
;
247 uint32_t y
= plane_state
->main
.y
;
248 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
249 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
250 unsigned long irqflags
;
252 /* Sizes are 0 based */
258 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
260 if (IS_GEMINILAKE(dev_priv
) || IS_CANNONLAKE(dev_priv
)) {
261 I915_WRITE_FW(PLANE_COLOR_CTL(pipe
, plane_id
),
262 PLANE_COLOR_PIPE_GAMMA_ENABLE
|
263 PLANE_COLOR_PIPE_CSC_ENABLE
|
264 PLANE_COLOR_PLANE_GAMMA_DISABLE
);
268 I915_WRITE_FW(PLANE_KEYVAL(pipe
, plane_id
), key
->min_value
);
269 I915_WRITE_FW(PLANE_KEYMAX(pipe
, plane_id
), key
->max_value
);
270 I915_WRITE_FW(PLANE_KEYMSK(pipe
, plane_id
), key
->channel_mask
);
273 I915_WRITE_FW(PLANE_OFFSET(pipe
, plane_id
), (y
<< 16) | x
);
274 I915_WRITE_FW(PLANE_STRIDE(pipe
, plane_id
), stride
);
275 I915_WRITE_FW(PLANE_SIZE(pipe
, plane_id
), (src_h
<< 16) | src_w
);
276 I915_WRITE_FW(PLANE_AUX_DIST(pipe
, plane_id
),
277 (plane_state
->aux
.offset
- surf_addr
) | aux_stride
);
278 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe
, plane_id
),
279 (plane_state
->aux
.y
<< 16) | plane_state
->aux
.x
);
281 /* program plane scaler */
282 if (plane_state
->scaler_id
>= 0) {
283 int scaler_id
= plane_state
->scaler_id
;
284 const struct intel_scaler
*scaler
;
286 scaler
= &crtc_state
->scaler_state
.scalers
[scaler_id
];
288 I915_WRITE_FW(SKL_PS_CTRL(pipe
, scaler_id
),
289 PS_SCALER_EN
| PS_PLANE_SEL(plane_id
) | scaler
->mode
);
290 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
291 I915_WRITE_FW(SKL_PS_WIN_POS(pipe
, scaler_id
), (crtc_x
<< 16) | crtc_y
);
292 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe
, scaler_id
),
293 ((crtc_w
+ 1) << 16)|(crtc_h
+ 1));
295 I915_WRITE_FW(PLANE_POS(pipe
, plane_id
), 0);
297 I915_WRITE_FW(PLANE_POS(pipe
, plane_id
), (crtc_y
<< 16) | crtc_x
);
300 I915_WRITE_FW(PLANE_CTL(pipe
, plane_id
), plane_ctl
);
301 I915_WRITE_FW(PLANE_SURF(pipe
, plane_id
),
302 intel_plane_ggtt_offset(plane_state
) + surf_addr
);
303 POSTING_READ_FW(PLANE_SURF(pipe
, plane_id
));
305 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
309 skl_disable_plane(struct intel_plane
*plane
, struct intel_crtc
*crtc
)
311 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
312 enum plane_id plane_id
= plane
->id
;
313 enum pipe pipe
= plane
->pipe
;
314 unsigned long irqflags
;
316 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
318 I915_WRITE_FW(PLANE_CTL(pipe
, plane_id
), 0);
320 I915_WRITE_FW(PLANE_SURF(pipe
, plane_id
), 0);
321 POSTING_READ_FW(PLANE_SURF(pipe
, plane_id
));
323 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
327 chv_update_csc(struct intel_plane
*plane
, uint32_t format
)
329 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
330 enum plane_id plane_id
= plane
->id
;
332 /* Seems RGB data bypasses the CSC always */
333 if (!format_is_yuv(format
))
337 * BT.601 limited range YCbCr -> full range RGB
339 * |r| | 6537 4769 0| |cr |
340 * |g| = |-3330 4769 -1605| x |y-64|
341 * |b| | 0 4769 8263| |cb |
343 * Cb and Cr apparently come in as signed already, so no
344 * need for any offset. For Y we need to remove the offset.
346 I915_WRITE_FW(SPCSCYGOFF(plane_id
), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
347 I915_WRITE_FW(SPCSCCBOFF(plane_id
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
348 I915_WRITE_FW(SPCSCCROFF(plane_id
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
350 I915_WRITE_FW(SPCSCC01(plane_id
), SPCSC_C1(4769) | SPCSC_C0(6537));
351 I915_WRITE_FW(SPCSCC23(plane_id
), SPCSC_C1(-3330) | SPCSC_C0(0));
352 I915_WRITE_FW(SPCSCC45(plane_id
), SPCSC_C1(-1605) | SPCSC_C0(4769));
353 I915_WRITE_FW(SPCSCC67(plane_id
), SPCSC_C1(4769) | SPCSC_C0(0));
354 I915_WRITE_FW(SPCSCC8(plane_id
), SPCSC_C0(8263));
356 I915_WRITE_FW(SPCSCYGICLAMP(plane_id
), SPCSC_IMAX(940) | SPCSC_IMIN(64));
357 I915_WRITE_FW(SPCSCCBICLAMP(plane_id
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
358 I915_WRITE_FW(SPCSCCRICLAMP(plane_id
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
360 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
361 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
362 I915_WRITE_FW(SPCSCCROCLAMP(plane_id
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
365 static u32
vlv_sprite_ctl(const struct intel_crtc_state
*crtc_state
,
366 const struct intel_plane_state
*plane_state
)
368 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
369 unsigned int rotation
= plane_state
->base
.rotation
;
370 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
373 sprctl
= SP_ENABLE
| SP_GAMMA_ENABLE
;
375 switch (fb
->format
->format
) {
376 case DRM_FORMAT_YUYV
:
377 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YUYV
;
379 case DRM_FORMAT_YVYU
:
380 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YVYU
;
382 case DRM_FORMAT_UYVY
:
383 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_UYVY
;
385 case DRM_FORMAT_VYUY
:
386 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_VYUY
;
388 case DRM_FORMAT_RGB565
:
389 sprctl
|= SP_FORMAT_BGR565
;
391 case DRM_FORMAT_XRGB8888
:
392 sprctl
|= SP_FORMAT_BGRX8888
;
394 case DRM_FORMAT_ARGB8888
:
395 sprctl
|= SP_FORMAT_BGRA8888
;
397 case DRM_FORMAT_XBGR2101010
:
398 sprctl
|= SP_FORMAT_RGBX1010102
;
400 case DRM_FORMAT_ABGR2101010
:
401 sprctl
|= SP_FORMAT_RGBA1010102
;
403 case DRM_FORMAT_XBGR8888
:
404 sprctl
|= SP_FORMAT_RGBX8888
;
406 case DRM_FORMAT_ABGR8888
:
407 sprctl
|= SP_FORMAT_RGBA8888
;
410 MISSING_CASE(fb
->format
->format
);
414 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
417 if (rotation
& DRM_MODE_ROTATE_180
)
418 sprctl
|= SP_ROTATE_180
;
420 if (rotation
& DRM_MODE_REFLECT_X
)
423 if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
424 sprctl
|= SP_SOURCE_KEY
;
430 vlv_update_plane(struct intel_plane
*plane
,
431 const struct intel_crtc_state
*crtc_state
,
432 const struct intel_plane_state
*plane_state
)
434 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
435 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
436 enum pipe pipe
= plane
->pipe
;
437 enum plane_id plane_id
= plane
->id
;
438 u32 sprctl
= plane_state
->ctl
;
439 u32 sprsurf_offset
= plane_state
->main
.offset
;
441 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
442 int crtc_x
= plane_state
->base
.dst
.x1
;
443 int crtc_y
= plane_state
->base
.dst
.y1
;
444 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
445 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
446 uint32_t x
= plane_state
->main
.x
;
447 uint32_t y
= plane_state
->main
.y
;
448 unsigned long irqflags
;
450 /* Sizes are 0 based */
454 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
456 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
458 if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
)
459 chv_update_csc(plane
, fb
->format
->format
);
462 I915_WRITE_FW(SPKEYMINVAL(pipe
, plane_id
), key
->min_value
);
463 I915_WRITE_FW(SPKEYMAXVAL(pipe
, plane_id
), key
->max_value
);
464 I915_WRITE_FW(SPKEYMSK(pipe
, plane_id
), key
->channel_mask
);
466 I915_WRITE_FW(SPSTRIDE(pipe
, plane_id
), fb
->pitches
[0]);
467 I915_WRITE_FW(SPPOS(pipe
, plane_id
), (crtc_y
<< 16) | crtc_x
);
469 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
470 I915_WRITE_FW(SPTILEOFF(pipe
, plane_id
), (y
<< 16) | x
);
472 I915_WRITE_FW(SPLINOFF(pipe
, plane_id
), linear_offset
);
474 I915_WRITE_FW(SPCONSTALPHA(pipe
, plane_id
), 0);
476 I915_WRITE_FW(SPSIZE(pipe
, plane_id
), (crtc_h
<< 16) | crtc_w
);
477 I915_WRITE_FW(SPCNTR(pipe
, plane_id
), sprctl
);
478 I915_WRITE_FW(SPSURF(pipe
, plane_id
),
479 intel_plane_ggtt_offset(plane_state
) + sprsurf_offset
);
480 POSTING_READ_FW(SPSURF(pipe
, plane_id
));
482 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
486 vlv_disable_plane(struct intel_plane
*plane
, struct intel_crtc
*crtc
)
488 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
489 enum pipe pipe
= plane
->pipe
;
490 enum plane_id plane_id
= plane
->id
;
491 unsigned long irqflags
;
493 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
495 I915_WRITE_FW(SPCNTR(pipe
, plane_id
), 0);
497 I915_WRITE_FW(SPSURF(pipe
, plane_id
), 0);
498 POSTING_READ_FW(SPSURF(pipe
, plane_id
));
500 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
503 static u32
ivb_sprite_ctl(const struct intel_crtc_state
*crtc_state
,
504 const struct intel_plane_state
*plane_state
)
506 struct drm_i915_private
*dev_priv
=
507 to_i915(plane_state
->base
.plane
->dev
);
508 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
509 unsigned int rotation
= plane_state
->base
.rotation
;
510 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
513 sprctl
= SPRITE_ENABLE
| SPRITE_GAMMA_ENABLE
;
515 if (IS_IVYBRIDGE(dev_priv
))
516 sprctl
|= SPRITE_TRICKLE_FEED_DISABLE
;
518 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
519 sprctl
|= SPRITE_PIPE_CSC_ENABLE
;
521 switch (fb
->format
->format
) {
522 case DRM_FORMAT_XBGR8888
:
523 sprctl
|= SPRITE_FORMAT_RGBX888
| SPRITE_RGB_ORDER_RGBX
;
525 case DRM_FORMAT_XRGB8888
:
526 sprctl
|= SPRITE_FORMAT_RGBX888
;
528 case DRM_FORMAT_YUYV
:
529 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YUYV
;
531 case DRM_FORMAT_YVYU
:
532 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YVYU
;
534 case DRM_FORMAT_UYVY
:
535 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_UYVY
;
537 case DRM_FORMAT_VYUY
:
538 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_VYUY
;
541 MISSING_CASE(fb
->format
->format
);
545 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
546 sprctl
|= SPRITE_TILED
;
548 if (rotation
& DRM_MODE_ROTATE_180
)
549 sprctl
|= SPRITE_ROTATE_180
;
551 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
552 sprctl
|= SPRITE_DEST_KEY
;
553 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
554 sprctl
|= SPRITE_SOURCE_KEY
;
560 ivb_update_plane(struct intel_plane
*plane
,
561 const struct intel_crtc_state
*crtc_state
,
562 const struct intel_plane_state
*plane_state
)
564 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
565 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
566 enum pipe pipe
= plane
->pipe
;
567 u32 sprctl
= plane_state
->ctl
, sprscale
= 0;
568 u32 sprsurf_offset
= plane_state
->main
.offset
;
570 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
571 int crtc_x
= plane_state
->base
.dst
.x1
;
572 int crtc_y
= plane_state
->base
.dst
.y1
;
573 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
574 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
575 uint32_t x
= plane_state
->main
.x
;
576 uint32_t y
= plane_state
->main
.y
;
577 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
578 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
579 unsigned long irqflags
;
581 /* Sizes are 0 based */
587 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
588 sprscale
= SPRITE_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
590 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
592 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
595 I915_WRITE_FW(SPRKEYVAL(pipe
), key
->min_value
);
596 I915_WRITE_FW(SPRKEYMAX(pipe
), key
->max_value
);
597 I915_WRITE_FW(SPRKEYMSK(pipe
), key
->channel_mask
);
600 I915_WRITE_FW(SPRSTRIDE(pipe
), fb
->pitches
[0]);
601 I915_WRITE_FW(SPRPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
603 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
605 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
606 I915_WRITE_FW(SPROFFSET(pipe
), (y
<< 16) | x
);
607 else if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
608 I915_WRITE_FW(SPRTILEOFF(pipe
), (y
<< 16) | x
);
610 I915_WRITE_FW(SPRLINOFF(pipe
), linear_offset
);
612 I915_WRITE_FW(SPRSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
613 if (plane
->can_scale
)
614 I915_WRITE_FW(SPRSCALE(pipe
), sprscale
);
615 I915_WRITE_FW(SPRCTL(pipe
), sprctl
);
616 I915_WRITE_FW(SPRSURF(pipe
),
617 intel_plane_ggtt_offset(plane_state
) + sprsurf_offset
);
618 POSTING_READ_FW(SPRSURF(pipe
));
620 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
624 ivb_disable_plane(struct intel_plane
*plane
, struct intel_crtc
*crtc
)
626 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
627 enum pipe pipe
= plane
->pipe
;
628 unsigned long irqflags
;
630 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
632 I915_WRITE_FW(SPRCTL(pipe
), 0);
633 /* Can't leave the scaler enabled... */
634 if (plane
->can_scale
)
635 I915_WRITE_FW(SPRSCALE(pipe
), 0);
637 I915_WRITE_FW(SPRSURF(pipe
), 0);
638 POSTING_READ_FW(SPRSURF(pipe
));
640 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
643 static u32
g4x_sprite_ctl(const struct intel_crtc_state
*crtc_state
,
644 const struct intel_plane_state
*plane_state
)
646 struct drm_i915_private
*dev_priv
=
647 to_i915(plane_state
->base
.plane
->dev
);
648 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
649 unsigned int rotation
= plane_state
->base
.rotation
;
650 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
653 dvscntr
= DVS_ENABLE
| DVS_GAMMA_ENABLE
;
655 if (IS_GEN6(dev_priv
))
656 dvscntr
|= DVS_TRICKLE_FEED_DISABLE
;
658 switch (fb
->format
->format
) {
659 case DRM_FORMAT_XBGR8888
:
660 dvscntr
|= DVS_FORMAT_RGBX888
| DVS_RGB_ORDER_XBGR
;
662 case DRM_FORMAT_XRGB8888
:
663 dvscntr
|= DVS_FORMAT_RGBX888
;
665 case DRM_FORMAT_YUYV
:
666 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YUYV
;
668 case DRM_FORMAT_YVYU
:
669 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YVYU
;
671 case DRM_FORMAT_UYVY
:
672 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_UYVY
;
674 case DRM_FORMAT_VYUY
:
675 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_VYUY
;
678 MISSING_CASE(fb
->format
->format
);
682 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
683 dvscntr
|= DVS_TILED
;
685 if (rotation
& DRM_MODE_ROTATE_180
)
686 dvscntr
|= DVS_ROTATE_180
;
688 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
689 dvscntr
|= DVS_DEST_KEY
;
690 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
691 dvscntr
|= DVS_SOURCE_KEY
;
697 g4x_update_plane(struct intel_plane
*plane
,
698 const struct intel_crtc_state
*crtc_state
,
699 const struct intel_plane_state
*plane_state
)
701 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
702 const struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
703 enum pipe pipe
= plane
->pipe
;
704 u32 dvscntr
= plane_state
->ctl
, dvsscale
= 0;
705 u32 dvssurf_offset
= plane_state
->main
.offset
;
707 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
708 int crtc_x
= plane_state
->base
.dst
.x1
;
709 int crtc_y
= plane_state
->base
.dst
.y1
;
710 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
711 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
712 uint32_t x
= plane_state
->main
.x
;
713 uint32_t y
= plane_state
->main
.y
;
714 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
715 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
716 unsigned long irqflags
;
718 /* Sizes are 0 based */
724 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
725 dvsscale
= DVS_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
727 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
729 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
732 I915_WRITE_FW(DVSKEYVAL(pipe
), key
->min_value
);
733 I915_WRITE_FW(DVSKEYMAX(pipe
), key
->max_value
);
734 I915_WRITE_FW(DVSKEYMSK(pipe
), key
->channel_mask
);
737 I915_WRITE_FW(DVSSTRIDE(pipe
), fb
->pitches
[0]);
738 I915_WRITE_FW(DVSPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
740 if (fb
->modifier
== I915_FORMAT_MOD_X_TILED
)
741 I915_WRITE_FW(DVSTILEOFF(pipe
), (y
<< 16) | x
);
743 I915_WRITE_FW(DVSLINOFF(pipe
), linear_offset
);
745 I915_WRITE_FW(DVSSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
746 I915_WRITE_FW(DVSSCALE(pipe
), dvsscale
);
747 I915_WRITE_FW(DVSCNTR(pipe
), dvscntr
);
748 I915_WRITE_FW(DVSSURF(pipe
),
749 intel_plane_ggtt_offset(plane_state
) + dvssurf_offset
);
750 POSTING_READ_FW(DVSSURF(pipe
));
752 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
756 g4x_disable_plane(struct intel_plane
*plane
, struct intel_crtc
*crtc
)
758 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
759 enum pipe pipe
= plane
->pipe
;
760 unsigned long irqflags
;
762 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
764 I915_WRITE_FW(DVSCNTR(pipe
), 0);
765 /* Disable the scaler */
766 I915_WRITE_FW(DVSSCALE(pipe
), 0);
768 I915_WRITE_FW(DVSSURF(pipe
), 0);
769 POSTING_READ_FW(DVSSURF(pipe
));
771 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
775 intel_check_sprite_plane(struct intel_plane
*plane
,
776 struct intel_crtc_state
*crtc_state
,
777 struct intel_plane_state
*state
)
779 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
780 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
781 struct drm_framebuffer
*fb
= state
->base
.fb
;
783 unsigned int crtc_w
, crtc_h
;
784 uint32_t src_x
, src_y
, src_w
, src_h
;
785 struct drm_rect
*src
= &state
->base
.src
;
786 struct drm_rect
*dst
= &state
->base
.dst
;
787 const struct drm_rect
*clip
= &state
->clip
;
789 int max_scale
, min_scale
;
793 *src
= drm_plane_state_src(&state
->base
);
794 *dst
= drm_plane_state_dest(&state
->base
);
797 state
->base
.visible
= false;
801 /* Don't modify another pipe's plane */
802 if (plane
->pipe
!= crtc
->pipe
) {
803 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
807 /* FIXME check all gen limits */
808 if (fb
->width
< 3 || fb
->height
< 3 || fb
->pitches
[0] > 16384) {
809 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
813 /* setup can_scale, min_scale, max_scale */
814 if (INTEL_GEN(dev_priv
) >= 9) {
815 /* use scaler when colorkey is not required */
816 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
819 max_scale
= skl_max_scale(crtc
, crtc_state
);
822 min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
823 max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
826 can_scale
= plane
->can_scale
;
827 max_scale
= plane
->max_downscale
<< 16;
828 min_scale
= plane
->can_scale
? 1 : (1 << 16);
832 * FIXME the following code does a bunch of fuzzy adjustments to the
833 * coordinates and sizes. We probably need some way to decide whether
834 * more strict checking should be done instead.
836 drm_rect_rotate(src
, fb
->width
<< 16, fb
->height
<< 16,
837 state
->base
.rotation
);
839 hscale
= drm_rect_calc_hscale_relaxed(src
, dst
, min_scale
, max_scale
);
842 vscale
= drm_rect_calc_vscale_relaxed(src
, dst
, min_scale
, max_scale
);
845 state
->base
.visible
= drm_rect_clip_scaled(src
, dst
, clip
, hscale
, vscale
);
849 crtc_w
= drm_rect_width(dst
);
850 crtc_h
= drm_rect_height(dst
);
852 if (state
->base
.visible
) {
853 /* check again in case clipping clamped the results */
854 hscale
= drm_rect_calc_hscale(src
, dst
, min_scale
, max_scale
);
856 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
857 drm_rect_debug_print("src: ", src
, true);
858 drm_rect_debug_print("dst: ", dst
, false);
863 vscale
= drm_rect_calc_vscale(src
, dst
, min_scale
, max_scale
);
865 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
866 drm_rect_debug_print("src: ", src
, true);
867 drm_rect_debug_print("dst: ", dst
, false);
872 /* Make the source viewport size an exact multiple of the scaling factors. */
873 drm_rect_adjust_size(src
,
874 drm_rect_width(dst
) * hscale
- drm_rect_width(src
),
875 drm_rect_height(dst
) * vscale
- drm_rect_height(src
));
877 drm_rect_rotate_inv(src
, fb
->width
<< 16, fb
->height
<< 16,
878 state
->base
.rotation
);
880 /* sanity check to make sure the src viewport wasn't enlarged */
881 WARN_ON(src
->x1
< (int) state
->base
.src_x
||
882 src
->y1
< (int) state
->base
.src_y
||
883 src
->x2
> (int) state
->base
.src_x
+ state
->base
.src_w
||
884 src
->y2
> (int) state
->base
.src_y
+ state
->base
.src_h
);
887 * Hardware doesn't handle subpixel coordinates.
888 * Adjust to (macro)pixel boundary, but be careful not to
889 * increase the source viewport size, because that could
890 * push the downscaling factor out of bounds.
892 src_x
= src
->x1
>> 16;
893 src_w
= drm_rect_width(src
) >> 16;
894 src_y
= src
->y1
>> 16;
895 src_h
= drm_rect_height(src
) >> 16;
897 if (format_is_yuv(fb
->format
->format
)) {
902 * Must keep src and dst the
903 * same if we can't scale.
909 state
->base
.visible
= false;
913 /* Check size restrictions when scaling */
914 if (state
->base
.visible
&& (src_w
!= crtc_w
|| src_h
!= crtc_h
)) {
915 unsigned int width_bytes
;
916 int cpp
= fb
->format
->cpp
[0];
920 /* FIXME interlacing min height is 6 */
922 if (crtc_w
< 3 || crtc_h
< 3)
923 state
->base
.visible
= false;
925 if (src_w
< 3 || src_h
< 3)
926 state
->base
.visible
= false;
928 width_bytes
= ((src_x
* cpp
) & 63) + src_w
* cpp
;
930 if (INTEL_GEN(dev_priv
) < 9 && (src_w
> 2048 || src_h
> 2048 ||
931 width_bytes
> 4096 || fb
->pitches
[0] > 4096)) {
932 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
937 if (state
->base
.visible
) {
938 src
->x1
= src_x
<< 16;
939 src
->x2
= (src_x
+ src_w
) << 16;
940 src
->y1
= src_y
<< 16;
941 src
->y2
= (src_y
+ src_h
) << 16;
945 dst
->x2
= crtc_x
+ crtc_w
;
947 dst
->y2
= crtc_y
+ crtc_h
;
949 if (INTEL_GEN(dev_priv
) >= 9) {
950 ret
= skl_check_plane_surface(state
);
954 state
->ctl
= skl_plane_ctl(crtc_state
, state
);
955 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
956 ret
= i9xx_check_plane_surface(state
);
960 state
->ctl
= vlv_sprite_ctl(crtc_state
, state
);
961 } else if (INTEL_GEN(dev_priv
) >= 7) {
962 ret
= i9xx_check_plane_surface(state
);
966 state
->ctl
= ivb_sprite_ctl(crtc_state
, state
);
968 ret
= i9xx_check_plane_surface(state
);
972 state
->ctl
= g4x_sprite_ctl(crtc_state
, state
);
978 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
979 struct drm_file
*file_priv
)
981 struct drm_i915_private
*dev_priv
= to_i915(dev
);
982 struct drm_intel_sprite_colorkey
*set
= data
;
983 struct drm_plane
*plane
;
984 struct drm_plane_state
*plane_state
;
985 struct drm_atomic_state
*state
;
986 struct drm_modeset_acquire_ctx ctx
;
989 /* Make sure we don't try to enable both src & dest simultaneously */
990 if ((set
->flags
& (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
)) == (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
))
993 if ((IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) &&
994 set
->flags
& I915_SET_COLORKEY_DESTINATION
)
997 plane
= drm_plane_find(dev
, file_priv
, set
->plane_id
);
998 if (!plane
|| plane
->type
!= DRM_PLANE_TYPE_OVERLAY
)
1001 drm_modeset_acquire_init(&ctx
, 0);
1003 state
= drm_atomic_state_alloc(plane
->dev
);
1008 state
->acquire_ctx
= &ctx
;
1011 plane_state
= drm_atomic_get_plane_state(state
, plane
);
1012 ret
= PTR_ERR_OR_ZERO(plane_state
);
1014 to_intel_plane_state(plane_state
)->ckey
= *set
;
1015 ret
= drm_atomic_commit(state
);
1018 if (ret
!= -EDEADLK
)
1021 drm_atomic_state_clear(state
);
1022 drm_modeset_backoff(&ctx
);
1025 drm_atomic_state_put(state
);
1027 drm_modeset_drop_locks(&ctx
);
1028 drm_modeset_acquire_fini(&ctx
);
1032 static const uint32_t g4x_plane_formats
[] = {
1033 DRM_FORMAT_XRGB8888
,
1040 static const uint64_t i9xx_plane_format_modifiers
[] = {
1041 I915_FORMAT_MOD_X_TILED
,
1042 DRM_FORMAT_MOD_LINEAR
,
1043 DRM_FORMAT_MOD_INVALID
1046 static const uint32_t snb_plane_formats
[] = {
1047 DRM_FORMAT_XBGR8888
,
1048 DRM_FORMAT_XRGB8888
,
1055 static const uint32_t vlv_plane_formats
[] = {
1057 DRM_FORMAT_ABGR8888
,
1058 DRM_FORMAT_ARGB8888
,
1059 DRM_FORMAT_XBGR8888
,
1060 DRM_FORMAT_XRGB8888
,
1061 DRM_FORMAT_XBGR2101010
,
1062 DRM_FORMAT_ABGR2101010
,
1069 static uint32_t skl_plane_formats
[] = {
1071 DRM_FORMAT_ABGR8888
,
1072 DRM_FORMAT_ARGB8888
,
1073 DRM_FORMAT_XBGR8888
,
1074 DRM_FORMAT_XRGB8888
,
1081 static const uint64_t skl_plane_format_modifiers
[] = {
1082 I915_FORMAT_MOD_X_TILED
,
1083 DRM_FORMAT_MOD_LINEAR
,
1084 DRM_FORMAT_MOD_INVALID
1087 static bool g4x_sprite_plane_format_mod_supported(struct drm_plane
*plane
,
1092 case DRM_FORMAT_XBGR8888
:
1093 case DRM_FORMAT_XRGB8888
:
1094 case DRM_FORMAT_YUYV
:
1095 case DRM_FORMAT_YVYU
:
1096 case DRM_FORMAT_UYVY
:
1097 case DRM_FORMAT_VYUY
:
1098 if (modifier
== DRM_FORMAT_MOD_LINEAR
||
1099 modifier
== I915_FORMAT_MOD_X_TILED
)
1107 static bool vlv_sprite_plane_format_mod_supported(struct drm_plane
*plane
,
1112 case DRM_FORMAT_YUYV
:
1113 case DRM_FORMAT_YVYU
:
1114 case DRM_FORMAT_UYVY
:
1115 case DRM_FORMAT_VYUY
:
1116 case DRM_FORMAT_RGB565
:
1117 case DRM_FORMAT_XRGB8888
:
1118 case DRM_FORMAT_ARGB8888
:
1119 case DRM_FORMAT_XBGR2101010
:
1120 case DRM_FORMAT_ABGR2101010
:
1121 case DRM_FORMAT_XBGR8888
:
1122 case DRM_FORMAT_ABGR8888
:
1123 if (modifier
== DRM_FORMAT_MOD_LINEAR
||
1124 modifier
== I915_FORMAT_MOD_X_TILED
)
1132 static bool skl_sprite_plane_format_mod_supported(struct drm_plane
*plane
,
1136 /* This is the same as primary plane since SKL has universal planes */
1138 case DRM_FORMAT_XRGB8888
:
1139 case DRM_FORMAT_XBGR8888
:
1140 case DRM_FORMAT_ARGB8888
:
1141 case DRM_FORMAT_ABGR8888
:
1142 case DRM_FORMAT_RGB565
:
1143 case DRM_FORMAT_XRGB2101010
:
1144 case DRM_FORMAT_XBGR2101010
:
1145 case DRM_FORMAT_YUYV
:
1146 case DRM_FORMAT_YVYU
:
1147 case DRM_FORMAT_UYVY
:
1148 case DRM_FORMAT_VYUY
:
1149 if (modifier
== I915_FORMAT_MOD_Yf_TILED
)
1153 if (modifier
== DRM_FORMAT_MOD_LINEAR
||
1154 modifier
== I915_FORMAT_MOD_X_TILED
||
1155 modifier
== I915_FORMAT_MOD_Y_TILED
)
1163 static bool intel_sprite_plane_format_mod_supported(struct drm_plane
*plane
,
1167 struct drm_i915_private
*dev_priv
= to_i915(plane
->dev
);
1169 if (WARN_ON(modifier
== DRM_FORMAT_MOD_INVALID
))
1172 if ((modifier
>> 56) != DRM_FORMAT_MOD_VENDOR_INTEL
&&
1173 modifier
!= DRM_FORMAT_MOD_LINEAR
)
1176 if (INTEL_GEN(dev_priv
) >= 9)
1177 return skl_sprite_plane_format_mod_supported(plane
, format
, modifier
);
1178 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1179 return vlv_sprite_plane_format_mod_supported(plane
, format
, modifier
);
1181 return g4x_sprite_plane_format_mod_supported(plane
, format
, modifier
);
1186 static const struct drm_plane_funcs intel_sprite_plane_funcs
= {
1187 .update_plane
= drm_atomic_helper_update_plane
,
1188 .disable_plane
= drm_atomic_helper_disable_plane
,
1189 .destroy
= intel_plane_destroy
,
1190 .atomic_get_property
= intel_plane_atomic_get_property
,
1191 .atomic_set_property
= intel_plane_atomic_set_property
,
1192 .atomic_duplicate_state
= intel_plane_duplicate_state
,
1193 .atomic_destroy_state
= intel_plane_destroy_state
,
1194 .format_mod_supported
= intel_sprite_plane_format_mod_supported
,
1197 struct intel_plane
*
1198 intel_sprite_plane_create(struct drm_i915_private
*dev_priv
,
1199 enum pipe pipe
, int plane
)
1201 struct intel_plane
*intel_plane
= NULL
;
1202 struct intel_plane_state
*state
= NULL
;
1203 unsigned long possible_crtcs
;
1204 const uint32_t *plane_formats
;
1205 const uint64_t *modifiers
;
1206 unsigned int supported_rotations
;
1207 int num_plane_formats
;
1210 intel_plane
= kzalloc(sizeof(*intel_plane
), GFP_KERNEL
);
1216 state
= intel_create_plane_state(&intel_plane
->base
);
1221 intel_plane
->base
.state
= &state
->base
;
1223 if (INTEL_GEN(dev_priv
) >= 10) {
1224 intel_plane
->can_scale
= true;
1225 state
->scaler_id
= -1;
1227 intel_plane
->update_plane
= skl_update_plane
;
1228 intel_plane
->disable_plane
= skl_disable_plane
;
1230 plane_formats
= skl_plane_formats
;
1231 num_plane_formats
= ARRAY_SIZE(skl_plane_formats
);
1232 modifiers
= skl_plane_format_modifiers
;
1233 } else if (INTEL_GEN(dev_priv
) >= 9) {
1234 intel_plane
->can_scale
= true;
1235 state
->scaler_id
= -1;
1237 intel_plane
->update_plane
= skl_update_plane
;
1238 intel_plane
->disable_plane
= skl_disable_plane
;
1240 plane_formats
= skl_plane_formats
;
1241 num_plane_formats
= ARRAY_SIZE(skl_plane_formats
);
1242 modifiers
= skl_plane_format_modifiers
;
1243 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1244 intel_plane
->can_scale
= false;
1245 intel_plane
->max_downscale
= 1;
1247 intel_plane
->update_plane
= vlv_update_plane
;
1248 intel_plane
->disable_plane
= vlv_disable_plane
;
1250 plane_formats
= vlv_plane_formats
;
1251 num_plane_formats
= ARRAY_SIZE(vlv_plane_formats
);
1252 modifiers
= i9xx_plane_format_modifiers
;
1253 } else if (INTEL_GEN(dev_priv
) >= 7) {
1254 if (IS_IVYBRIDGE(dev_priv
)) {
1255 intel_plane
->can_scale
= true;
1256 intel_plane
->max_downscale
= 2;
1258 intel_plane
->can_scale
= false;
1259 intel_plane
->max_downscale
= 1;
1262 intel_plane
->update_plane
= ivb_update_plane
;
1263 intel_plane
->disable_plane
= ivb_disable_plane
;
1265 plane_formats
= snb_plane_formats
;
1266 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1267 modifiers
= i9xx_plane_format_modifiers
;
1269 intel_plane
->can_scale
= true;
1270 intel_plane
->max_downscale
= 16;
1272 intel_plane
->update_plane
= g4x_update_plane
;
1273 intel_plane
->disable_plane
= g4x_disable_plane
;
1275 modifiers
= i9xx_plane_format_modifiers
;
1276 if (IS_GEN6(dev_priv
)) {
1277 plane_formats
= snb_plane_formats
;
1278 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1280 plane_formats
= g4x_plane_formats
;
1281 num_plane_formats
= ARRAY_SIZE(g4x_plane_formats
);
1285 if (INTEL_GEN(dev_priv
) >= 9) {
1286 supported_rotations
=
1287 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_90
|
1288 DRM_MODE_ROTATE_180
| DRM_MODE_ROTATE_270
;
1289 } else if (IS_CHERRYVIEW(dev_priv
) && pipe
== PIPE_B
) {
1290 supported_rotations
=
1291 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
|
1294 supported_rotations
=
1295 DRM_MODE_ROTATE_0
| DRM_MODE_ROTATE_180
;
1298 intel_plane
->pipe
= pipe
;
1299 intel_plane
->plane
= plane
;
1300 intel_plane
->id
= PLANE_SPRITE0
+ plane
;
1301 intel_plane
->frontbuffer_bit
= INTEL_FRONTBUFFER_SPRITE(pipe
, plane
);
1302 intel_plane
->check_plane
= intel_check_sprite_plane
;
1304 possible_crtcs
= (1 << pipe
);
1306 if (INTEL_GEN(dev_priv
) >= 9)
1307 ret
= drm_universal_plane_init(&dev_priv
->drm
, &intel_plane
->base
,
1308 possible_crtcs
, &intel_sprite_plane_funcs
,
1309 plane_formats
, num_plane_formats
,
1311 DRM_PLANE_TYPE_OVERLAY
,
1312 "plane %d%c", plane
+ 2, pipe_name(pipe
));
1314 ret
= drm_universal_plane_init(&dev_priv
->drm
, &intel_plane
->base
,
1315 possible_crtcs
, &intel_sprite_plane_funcs
,
1316 plane_formats
, num_plane_formats
,
1318 DRM_PLANE_TYPE_OVERLAY
,
1319 "sprite %c", sprite_name(pipe
, plane
));
1323 drm_plane_create_rotation_property(&intel_plane
->base
,
1325 supported_rotations
);
1327 drm_plane_helper_add(&intel_plane
->base
, &intel_plane_helper_funcs
);
1335 return ERR_PTR(ret
);