2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_fourcc.h>
35 #include <drm/drm_rect.h>
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_plane_helper.h>
38 #include "intel_drv.h"
39 #include "intel_frontbuffer.h"
40 #include <drm/i915_drm.h>
44 format_is_yuv(uint32_t format
)
57 int intel_usecs_to_scanlines(const struct drm_display_mode
*adjusted_mode
,
61 if (!adjusted_mode
->crtc_htotal
)
64 return DIV_ROUND_UP(usecs
* adjusted_mode
->crtc_clock
,
65 1000 * adjusted_mode
->crtc_htotal
);
69 * intel_pipe_update_start() - start update of a set of display registers
70 * @crtc: the crtc of which the registers are going to be updated
71 * @start_vbl_count: vblank counter return pointer used for error checking
73 * Mark the start of an update to pipe registers that should be updated
74 * atomically regarding vblank. If the next vblank will happens within
75 * the next 100 us, this function waits until the vblank passes.
77 * After a successful call to this function, interrupts will be disabled
78 * until a subsequent call to intel_pipe_update_end(). That is done to
79 * avoid random delays. The value written to @start_vbl_count should be
80 * supplied to intel_pipe_update_end() for error checking.
82 void intel_pipe_update_start(struct intel_crtc
*crtc
)
84 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
85 long timeout
= msecs_to_jiffies_timeout(1);
86 int scanline
, min
, max
, vblank_start
;
87 wait_queue_head_t
*wq
= drm_crtc_vblank_waitqueue(&crtc
->base
);
90 vblank_start
= adjusted_mode
->crtc_vblank_start
;
91 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
92 vblank_start
= DIV_ROUND_UP(vblank_start
, 2);
94 /* FIXME needs to be calibrated sensibly */
95 min
= vblank_start
- intel_usecs_to_scanlines(adjusted_mode
, 100);
96 max
= vblank_start
- 1;
100 if (min
<= 0 || max
<= 0)
103 if (WARN_ON(drm_crtc_vblank_get(&crtc
->base
)))
106 crtc
->debug
.min_vbl
= min
;
107 crtc
->debug
.max_vbl
= max
;
108 trace_i915_pipe_update_start(crtc
);
112 * prepare_to_wait() has a memory barrier, which guarantees
113 * other CPUs can see the task state update by the time we
116 prepare_to_wait(wq
, &wait
, TASK_UNINTERRUPTIBLE
);
118 scanline
= intel_get_crtc_scanline(crtc
);
119 if (scanline
< min
|| scanline
> max
)
123 DRM_ERROR("Potential atomic update failure on pipe %c\n",
124 pipe_name(crtc
->pipe
));
130 timeout
= schedule_timeout(timeout
);
135 finish_wait(wq
, &wait
);
137 drm_crtc_vblank_put(&crtc
->base
);
139 crtc
->debug
.scanline_start
= scanline
;
140 crtc
->debug
.start_vbl_time
= ktime_get();
141 crtc
->debug
.start_vbl_count
= intel_crtc_get_vblank_counter(crtc
);
143 trace_i915_pipe_update_vblank_evaded(crtc
);
147 * intel_pipe_update_end() - end update of a set of display registers
148 * @crtc: the crtc of which the registers were updated
149 * @start_vbl_count: start vblank counter (used for error checking)
151 * Mark the end of an update started with intel_pipe_update_start(). This
152 * re-enables interrupts and verifies the update was actually completed
153 * before a vblank using the value of @start_vbl_count.
155 void intel_pipe_update_end(struct intel_crtc
*crtc
, struct intel_flip_work
*work
)
157 enum pipe pipe
= crtc
->pipe
;
158 int scanline_end
= intel_get_crtc_scanline(crtc
);
159 u32 end_vbl_count
= intel_crtc_get_vblank_counter(crtc
);
160 ktime_t end_vbl_time
= ktime_get();
163 work
->flip_queued_vblank
= end_vbl_count
;
164 smp_mb__before_atomic();
165 atomic_set(&work
->pending
, 1);
168 trace_i915_pipe_update_end(crtc
, end_vbl_count
, scanline_end
);
170 /* We're still in the vblank-evade critical section, this can't race.
171 * Would be slightly nice to just grab the vblank count and arm the
172 * event outside of the critical section - the spinlock might spin for a
174 if (crtc
->base
.state
->event
) {
175 WARN_ON(drm_crtc_vblank_get(&crtc
->base
) != 0);
177 spin_lock(&crtc
->base
.dev
->event_lock
);
178 drm_crtc_arm_vblank_event(&crtc
->base
, crtc
->base
.state
->event
);
179 spin_unlock(&crtc
->base
.dev
->event_lock
);
181 crtc
->base
.state
->event
= NULL
;
186 if (crtc
->debug
.start_vbl_count
&&
187 crtc
->debug
.start_vbl_count
!= end_vbl_count
) {
188 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
189 pipe_name(pipe
), crtc
->debug
.start_vbl_count
,
191 ktime_us_delta(end_vbl_time
, crtc
->debug
.start_vbl_time
),
192 crtc
->debug
.min_vbl
, crtc
->debug
.max_vbl
,
193 crtc
->debug
.scanline_start
, scanline_end
);
198 skl_update_plane(struct drm_plane
*drm_plane
,
199 const struct intel_crtc_state
*crtc_state
,
200 const struct intel_plane_state
*plane_state
)
202 struct drm_device
*dev
= drm_plane
->dev
;
203 struct drm_i915_private
*dev_priv
= to_i915(dev
);
204 struct intel_plane
*intel_plane
= to_intel_plane(drm_plane
);
205 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
206 const int pipe
= intel_plane
->pipe
;
207 const int plane
= intel_plane
->plane
+ 1;
209 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
210 u32 surf_addr
= plane_state
->main
.offset
;
211 unsigned int rotation
= plane_state
->base
.rotation
;
212 u32 stride
= skl_plane_stride(fb
, 0, rotation
);
213 int crtc_x
= plane_state
->base
.dst
.x1
;
214 int crtc_y
= plane_state
->base
.dst
.y1
;
215 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
216 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
217 uint32_t x
= plane_state
->main
.x
;
218 uint32_t y
= plane_state
->main
.y
;
219 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
220 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
222 plane_ctl
= PLANE_CTL_ENABLE
|
223 PLANE_CTL_PIPE_GAMMA_ENABLE
|
224 PLANE_CTL_PIPE_CSC_ENABLE
;
226 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
227 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
229 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
232 I915_WRITE(PLANE_KEYVAL(pipe
, plane
), key
->min_value
);
233 I915_WRITE(PLANE_KEYMAX(pipe
, plane
), key
->max_value
);
234 I915_WRITE(PLANE_KEYMSK(pipe
, plane
), key
->channel_mask
);
237 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
238 plane_ctl
|= PLANE_CTL_KEY_ENABLE_DESTINATION
;
239 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
240 plane_ctl
|= PLANE_CTL_KEY_ENABLE_SOURCE
;
242 /* Sizes are 0 based */
248 I915_WRITE(PLANE_OFFSET(pipe
, plane
), (y
<< 16) | x
);
249 I915_WRITE(PLANE_STRIDE(pipe
, plane
), stride
);
250 I915_WRITE(PLANE_SIZE(pipe
, plane
), (src_h
<< 16) | src_w
);
252 /* program plane scaler */
253 if (plane_state
->scaler_id
>= 0) {
254 int scaler_id
= plane_state
->scaler_id
;
255 const struct intel_scaler
*scaler
;
257 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane
,
258 PS_PLANE_SEL(plane
));
260 scaler
= &crtc_state
->scaler_state
.scalers
[scaler_id
];
262 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
),
263 PS_SCALER_EN
| PS_PLANE_SEL(plane
) | scaler
->mode
);
264 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
265 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (crtc_x
<< 16) | crtc_y
);
266 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
),
267 ((crtc_w
+ 1) << 16)|(crtc_h
+ 1));
269 I915_WRITE(PLANE_POS(pipe
, plane
), 0);
271 I915_WRITE(PLANE_POS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
274 I915_WRITE(PLANE_CTL(pipe
, plane
), plane_ctl
);
275 I915_WRITE(PLANE_SURF(pipe
, plane
),
276 intel_fb_gtt_offset(fb
, rotation
) + surf_addr
);
277 POSTING_READ(PLANE_SURF(pipe
, plane
));
281 skl_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
)
283 struct drm_device
*dev
= dplane
->dev
;
284 struct drm_i915_private
*dev_priv
= to_i915(dev
);
285 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
286 const int pipe
= intel_plane
->pipe
;
287 const int plane
= intel_plane
->plane
+ 1;
289 I915_WRITE(PLANE_CTL(pipe
, plane
), 0);
291 I915_WRITE(PLANE_SURF(pipe
, plane
), 0);
292 POSTING_READ(PLANE_SURF(pipe
, plane
));
296 chv_update_csc(struct intel_plane
*intel_plane
, uint32_t format
)
298 struct drm_i915_private
*dev_priv
= to_i915(intel_plane
->base
.dev
);
299 int plane
= intel_plane
->plane
;
301 /* Seems RGB data bypasses the CSC always */
302 if (!format_is_yuv(format
))
306 * BT.601 limited range YCbCr -> full range RGB
308 * |r| | 6537 4769 0| |cr |
309 * |g| = |-3330 4769 -1605| x |y-64|
310 * |b| | 0 4769 8263| |cb |
312 * Cb and Cr apparently come in as signed already, so no
313 * need for any offset. For Y we need to remove the offset.
315 I915_WRITE(SPCSCYGOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
316 I915_WRITE(SPCSCCBOFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
317 I915_WRITE(SPCSCCROFF(plane
), SPCSC_OOFF(0) | SPCSC_IOFF(0));
319 I915_WRITE(SPCSCC01(plane
), SPCSC_C1(4769) | SPCSC_C0(6537));
320 I915_WRITE(SPCSCC23(plane
), SPCSC_C1(-3330) | SPCSC_C0(0));
321 I915_WRITE(SPCSCC45(plane
), SPCSC_C1(-1605) | SPCSC_C0(4769));
322 I915_WRITE(SPCSCC67(plane
), SPCSC_C1(4769) | SPCSC_C0(0));
323 I915_WRITE(SPCSCC8(plane
), SPCSC_C0(8263));
325 I915_WRITE(SPCSCYGICLAMP(plane
), SPCSC_IMAX(940) | SPCSC_IMIN(64));
326 I915_WRITE(SPCSCCBICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
327 I915_WRITE(SPCSCCRICLAMP(plane
), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
329 I915_WRITE(SPCSCYGOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
330 I915_WRITE(SPCSCCBOCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
331 I915_WRITE(SPCSCCROCLAMP(plane
), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
335 vlv_update_plane(struct drm_plane
*dplane
,
336 const struct intel_crtc_state
*crtc_state
,
337 const struct intel_plane_state
*plane_state
)
339 struct drm_device
*dev
= dplane
->dev
;
340 struct drm_i915_private
*dev_priv
= to_i915(dev
);
341 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
342 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
343 int pipe
= intel_plane
->pipe
;
344 int plane
= intel_plane
->plane
;
346 u32 sprsurf_offset
, linear_offset
;
347 unsigned int rotation
= dplane
->state
->rotation
;
348 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
349 int crtc_x
= plane_state
->base
.dst
.x1
;
350 int crtc_y
= plane_state
->base
.dst
.y1
;
351 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
352 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
353 uint32_t x
= plane_state
->base
.src
.x1
>> 16;
354 uint32_t y
= plane_state
->base
.src
.y1
>> 16;
355 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
356 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
360 switch (fb
->pixel_format
) {
361 case DRM_FORMAT_YUYV
:
362 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YUYV
;
364 case DRM_FORMAT_YVYU
:
365 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_YVYU
;
367 case DRM_FORMAT_UYVY
:
368 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_UYVY
;
370 case DRM_FORMAT_VYUY
:
371 sprctl
|= SP_FORMAT_YUV422
| SP_YUV_ORDER_VYUY
;
373 case DRM_FORMAT_RGB565
:
374 sprctl
|= SP_FORMAT_BGR565
;
376 case DRM_FORMAT_XRGB8888
:
377 sprctl
|= SP_FORMAT_BGRX8888
;
379 case DRM_FORMAT_ARGB8888
:
380 sprctl
|= SP_FORMAT_BGRA8888
;
382 case DRM_FORMAT_XBGR2101010
:
383 sprctl
|= SP_FORMAT_RGBX1010102
;
385 case DRM_FORMAT_ABGR2101010
:
386 sprctl
|= SP_FORMAT_RGBA1010102
;
388 case DRM_FORMAT_XBGR8888
:
389 sprctl
|= SP_FORMAT_RGBX8888
;
391 case DRM_FORMAT_ABGR8888
:
392 sprctl
|= SP_FORMAT_RGBA8888
;
396 * If we get here one of the upper layers failed to filter
397 * out the unsupported plane formats
404 * Enable gamma to match primary/cursor plane behaviour.
405 * FIXME should be user controllable via propertiesa.
407 sprctl
|= SP_GAMMA_ENABLE
;
409 if (fb
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)
412 /* Sizes are 0 based */
418 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
419 sprsurf_offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
421 if (rotation
== DRM_ROTATE_180
) {
422 sprctl
|= SP_ROTATE_180
;
428 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
431 I915_WRITE(SPKEYMINVAL(pipe
, plane
), key
->min_value
);
432 I915_WRITE(SPKEYMAXVAL(pipe
, plane
), key
->max_value
);
433 I915_WRITE(SPKEYMSK(pipe
, plane
), key
->channel_mask
);
436 if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
437 sprctl
|= SP_SOURCE_KEY
;
439 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
)
440 chv_update_csc(intel_plane
, fb
->pixel_format
);
442 I915_WRITE(SPSTRIDE(pipe
, plane
), fb
->pitches
[0]);
443 I915_WRITE(SPPOS(pipe
, plane
), (crtc_y
<< 16) | crtc_x
);
445 if (fb
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)
446 I915_WRITE(SPTILEOFF(pipe
, plane
), (y
<< 16) | x
);
448 I915_WRITE(SPLINOFF(pipe
, plane
), linear_offset
);
450 I915_WRITE(SPCONSTALPHA(pipe
, plane
), 0);
452 I915_WRITE(SPSIZE(pipe
, plane
), (crtc_h
<< 16) | crtc_w
);
453 I915_WRITE(SPCNTR(pipe
, plane
), sprctl
);
454 I915_WRITE(SPSURF(pipe
, plane
),
455 intel_fb_gtt_offset(fb
, rotation
) + sprsurf_offset
);
456 POSTING_READ(SPSURF(pipe
, plane
));
460 vlv_disable_plane(struct drm_plane
*dplane
, struct drm_crtc
*crtc
)
462 struct drm_device
*dev
= dplane
->dev
;
463 struct drm_i915_private
*dev_priv
= to_i915(dev
);
464 struct intel_plane
*intel_plane
= to_intel_plane(dplane
);
465 int pipe
= intel_plane
->pipe
;
466 int plane
= intel_plane
->plane
;
468 I915_WRITE(SPCNTR(pipe
, plane
), 0);
470 I915_WRITE(SPSURF(pipe
, plane
), 0);
471 POSTING_READ(SPSURF(pipe
, plane
));
475 ivb_update_plane(struct drm_plane
*plane
,
476 const struct intel_crtc_state
*crtc_state
,
477 const struct intel_plane_state
*plane_state
)
479 struct drm_device
*dev
= plane
->dev
;
480 struct drm_i915_private
*dev_priv
= to_i915(dev
);
481 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
482 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
483 enum pipe pipe
= intel_plane
->pipe
;
484 u32 sprctl
, sprscale
= 0;
485 u32 sprsurf_offset
, linear_offset
;
486 unsigned int rotation
= plane_state
->base
.rotation
;
487 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
488 int crtc_x
= plane_state
->base
.dst
.x1
;
489 int crtc_y
= plane_state
->base
.dst
.y1
;
490 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
491 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
492 uint32_t x
= plane_state
->base
.src
.x1
>> 16;
493 uint32_t y
= plane_state
->base
.src
.y1
>> 16;
494 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
495 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
497 sprctl
= SPRITE_ENABLE
;
499 switch (fb
->pixel_format
) {
500 case DRM_FORMAT_XBGR8888
:
501 sprctl
|= SPRITE_FORMAT_RGBX888
| SPRITE_RGB_ORDER_RGBX
;
503 case DRM_FORMAT_XRGB8888
:
504 sprctl
|= SPRITE_FORMAT_RGBX888
;
506 case DRM_FORMAT_YUYV
:
507 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YUYV
;
509 case DRM_FORMAT_YVYU
:
510 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_YVYU
;
512 case DRM_FORMAT_UYVY
:
513 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_UYVY
;
515 case DRM_FORMAT_VYUY
:
516 sprctl
|= SPRITE_FORMAT_YUV422
| SPRITE_YUV_ORDER_VYUY
;
523 * Enable gamma to match primary/cursor plane behaviour.
524 * FIXME should be user controllable via propertiesa.
526 sprctl
|= SPRITE_GAMMA_ENABLE
;
528 if (fb
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)
529 sprctl
|= SPRITE_TILED
;
531 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
532 sprctl
&= ~SPRITE_TRICKLE_FEED_DISABLE
;
534 sprctl
|= SPRITE_TRICKLE_FEED_DISABLE
;
536 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
537 sprctl
|= SPRITE_PIPE_CSC_ENABLE
;
539 /* Sizes are 0 based */
545 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
546 sprscale
= SPRITE_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
548 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
549 sprsurf_offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
551 if (rotation
== DRM_ROTATE_180
) {
552 sprctl
|= SPRITE_ROTATE_180
;
554 /* HSW and BDW does this automagically in hardware */
555 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
561 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
564 I915_WRITE(SPRKEYVAL(pipe
), key
->min_value
);
565 I915_WRITE(SPRKEYMAX(pipe
), key
->max_value
);
566 I915_WRITE(SPRKEYMSK(pipe
), key
->channel_mask
);
569 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
570 sprctl
|= SPRITE_DEST_KEY
;
571 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
572 sprctl
|= SPRITE_SOURCE_KEY
;
574 I915_WRITE(SPRSTRIDE(pipe
), fb
->pitches
[0]);
575 I915_WRITE(SPRPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
577 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
579 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
580 I915_WRITE(SPROFFSET(pipe
), (y
<< 16) | x
);
581 else if (fb
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)
582 I915_WRITE(SPRTILEOFF(pipe
), (y
<< 16) | x
);
584 I915_WRITE(SPRLINOFF(pipe
), linear_offset
);
586 I915_WRITE(SPRSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
587 if (intel_plane
->can_scale
)
588 I915_WRITE(SPRSCALE(pipe
), sprscale
);
589 I915_WRITE(SPRCTL(pipe
), sprctl
);
590 I915_WRITE(SPRSURF(pipe
),
591 intel_fb_gtt_offset(fb
, rotation
) + sprsurf_offset
);
592 POSTING_READ(SPRSURF(pipe
));
596 ivb_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
598 struct drm_device
*dev
= plane
->dev
;
599 struct drm_i915_private
*dev_priv
= to_i915(dev
);
600 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
601 int pipe
= intel_plane
->pipe
;
603 I915_WRITE(SPRCTL(pipe
), 0);
604 /* Can't leave the scaler enabled... */
605 if (intel_plane
->can_scale
)
606 I915_WRITE(SPRSCALE(pipe
), 0);
608 I915_WRITE(SPRSURF(pipe
), 0);
609 POSTING_READ(SPRSURF(pipe
));
613 ilk_update_plane(struct drm_plane
*plane
,
614 const struct intel_crtc_state
*crtc_state
,
615 const struct intel_plane_state
*plane_state
)
617 struct drm_device
*dev
= plane
->dev
;
618 struct drm_i915_private
*dev_priv
= to_i915(dev
);
619 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
620 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
621 int pipe
= intel_plane
->pipe
;
622 u32 dvscntr
, dvsscale
;
623 u32 dvssurf_offset
, linear_offset
;
624 unsigned int rotation
= plane_state
->base
.rotation
;
625 const struct drm_intel_sprite_colorkey
*key
= &plane_state
->ckey
;
626 int crtc_x
= plane_state
->base
.dst
.x1
;
627 int crtc_y
= plane_state
->base
.dst
.y1
;
628 uint32_t crtc_w
= drm_rect_width(&plane_state
->base
.dst
);
629 uint32_t crtc_h
= drm_rect_height(&plane_state
->base
.dst
);
630 uint32_t x
= plane_state
->base
.src
.x1
>> 16;
631 uint32_t y
= plane_state
->base
.src
.y1
>> 16;
632 uint32_t src_w
= drm_rect_width(&plane_state
->base
.src
) >> 16;
633 uint32_t src_h
= drm_rect_height(&plane_state
->base
.src
) >> 16;
635 dvscntr
= DVS_ENABLE
;
637 switch (fb
->pixel_format
) {
638 case DRM_FORMAT_XBGR8888
:
639 dvscntr
|= DVS_FORMAT_RGBX888
| DVS_RGB_ORDER_XBGR
;
641 case DRM_FORMAT_XRGB8888
:
642 dvscntr
|= DVS_FORMAT_RGBX888
;
644 case DRM_FORMAT_YUYV
:
645 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YUYV
;
647 case DRM_FORMAT_YVYU
:
648 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_YVYU
;
650 case DRM_FORMAT_UYVY
:
651 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_UYVY
;
653 case DRM_FORMAT_VYUY
:
654 dvscntr
|= DVS_FORMAT_YUV422
| DVS_YUV_ORDER_VYUY
;
661 * Enable gamma to match primary/cursor plane behaviour.
662 * FIXME should be user controllable via propertiesa.
664 dvscntr
|= DVS_GAMMA_ENABLE
;
666 if (fb
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)
667 dvscntr
|= DVS_TILED
;
670 dvscntr
|= DVS_TRICKLE_FEED_DISABLE
; /* must disable */
672 /* Sizes are 0 based */
679 if (crtc_w
!= src_w
|| crtc_h
!= src_h
)
680 dvsscale
= DVS_SCALE_ENABLE
| (src_w
<< 16) | src_h
;
682 intel_add_fb_offsets(&x
, &y
, plane_state
, 0);
683 dvssurf_offset
= intel_compute_tile_offset(&x
, &y
, plane_state
, 0);
685 if (rotation
== DRM_ROTATE_180
) {
686 dvscntr
|= DVS_ROTATE_180
;
692 linear_offset
= intel_fb_xy_to_linear(x
, y
, plane_state
, 0);
695 I915_WRITE(DVSKEYVAL(pipe
), key
->min_value
);
696 I915_WRITE(DVSKEYMAX(pipe
), key
->max_value
);
697 I915_WRITE(DVSKEYMSK(pipe
), key
->channel_mask
);
700 if (key
->flags
& I915_SET_COLORKEY_DESTINATION
)
701 dvscntr
|= DVS_DEST_KEY
;
702 else if (key
->flags
& I915_SET_COLORKEY_SOURCE
)
703 dvscntr
|= DVS_SOURCE_KEY
;
705 I915_WRITE(DVSSTRIDE(pipe
), fb
->pitches
[0]);
706 I915_WRITE(DVSPOS(pipe
), (crtc_y
<< 16) | crtc_x
);
708 if (fb
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)
709 I915_WRITE(DVSTILEOFF(pipe
), (y
<< 16) | x
);
711 I915_WRITE(DVSLINOFF(pipe
), linear_offset
);
713 I915_WRITE(DVSSIZE(pipe
), (crtc_h
<< 16) | crtc_w
);
714 I915_WRITE(DVSSCALE(pipe
), dvsscale
);
715 I915_WRITE(DVSCNTR(pipe
), dvscntr
);
716 I915_WRITE(DVSSURF(pipe
),
717 intel_fb_gtt_offset(fb
, rotation
) + dvssurf_offset
);
718 POSTING_READ(DVSSURF(pipe
));
722 ilk_disable_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
)
724 struct drm_device
*dev
= plane
->dev
;
725 struct drm_i915_private
*dev_priv
= to_i915(dev
);
726 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
727 int pipe
= intel_plane
->pipe
;
729 I915_WRITE(DVSCNTR(pipe
), 0);
730 /* Disable the scaler */
731 I915_WRITE(DVSSCALE(pipe
), 0);
733 I915_WRITE(DVSSURF(pipe
), 0);
734 POSTING_READ(DVSSURF(pipe
));
738 intel_check_sprite_plane(struct drm_plane
*plane
,
739 struct intel_crtc_state
*crtc_state
,
740 struct intel_plane_state
*state
)
742 struct drm_device
*dev
= plane
->dev
;
743 struct drm_crtc
*crtc
= state
->base
.crtc
;
744 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
745 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
746 struct drm_framebuffer
*fb
= state
->base
.fb
;
748 unsigned int crtc_w
, crtc_h
;
749 uint32_t src_x
, src_y
, src_w
, src_h
;
750 struct drm_rect
*src
= &state
->base
.src
;
751 struct drm_rect
*dst
= &state
->base
.dst
;
752 const struct drm_rect
*clip
= &state
->clip
;
754 int max_scale
, min_scale
;
758 src
->x1
= state
->base
.src_x
;
759 src
->y1
= state
->base
.src_y
;
760 src
->x2
= state
->base
.src_x
+ state
->base
.src_w
;
761 src
->y2
= state
->base
.src_y
+ state
->base
.src_h
;
763 dst
->x1
= state
->base
.crtc_x
;
764 dst
->y1
= state
->base
.crtc_y
;
765 dst
->x2
= state
->base
.crtc_x
+ state
->base
.crtc_w
;
766 dst
->y2
= state
->base
.crtc_y
+ state
->base
.crtc_h
;
769 state
->base
.visible
= false;
773 /* Don't modify another pipe's plane */
774 if (intel_plane
->pipe
!= intel_crtc
->pipe
) {
775 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
779 /* FIXME check all gen limits */
780 if (fb
->width
< 3 || fb
->height
< 3 || fb
->pitches
[0] > 16384) {
781 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
785 /* setup can_scale, min_scale, max_scale */
786 if (INTEL_INFO(dev
)->gen
>= 9) {
787 /* use scaler when colorkey is not required */
788 if (state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
791 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
794 min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
795 max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
798 can_scale
= intel_plane
->can_scale
;
799 max_scale
= intel_plane
->max_downscale
<< 16;
800 min_scale
= intel_plane
->can_scale
? 1 : (1 << 16);
804 * FIXME the following code does a bunch of fuzzy adjustments to the
805 * coordinates and sizes. We probably need some way to decide whether
806 * more strict checking should be done instead.
808 drm_rect_rotate(src
, fb
->width
<< 16, fb
->height
<< 16,
809 state
->base
.rotation
);
811 hscale
= drm_rect_calc_hscale_relaxed(src
, dst
, min_scale
, max_scale
);
814 vscale
= drm_rect_calc_vscale_relaxed(src
, dst
, min_scale
, max_scale
);
817 state
->base
.visible
= drm_rect_clip_scaled(src
, dst
, clip
, hscale
, vscale
);
821 crtc_w
= drm_rect_width(dst
);
822 crtc_h
= drm_rect_height(dst
);
824 if (state
->base
.visible
) {
825 /* check again in case clipping clamped the results */
826 hscale
= drm_rect_calc_hscale(src
, dst
, min_scale
, max_scale
);
828 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
829 drm_rect_debug_print("src: ", src
, true);
830 drm_rect_debug_print("dst: ", dst
, false);
835 vscale
= drm_rect_calc_vscale(src
, dst
, min_scale
, max_scale
);
837 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
838 drm_rect_debug_print("src: ", src
, true);
839 drm_rect_debug_print("dst: ", dst
, false);
844 /* Make the source viewport size an exact multiple of the scaling factors. */
845 drm_rect_adjust_size(src
,
846 drm_rect_width(dst
) * hscale
- drm_rect_width(src
),
847 drm_rect_height(dst
) * vscale
- drm_rect_height(src
));
849 drm_rect_rotate_inv(src
, fb
->width
<< 16, fb
->height
<< 16,
850 state
->base
.rotation
);
852 /* sanity check to make sure the src viewport wasn't enlarged */
853 WARN_ON(src
->x1
< (int) state
->base
.src_x
||
854 src
->y1
< (int) state
->base
.src_y
||
855 src
->x2
> (int) state
->base
.src_x
+ state
->base
.src_w
||
856 src
->y2
> (int) state
->base
.src_y
+ state
->base
.src_h
);
859 * Hardware doesn't handle subpixel coordinates.
860 * Adjust to (macro)pixel boundary, but be careful not to
861 * increase the source viewport size, because that could
862 * push the downscaling factor out of bounds.
864 src_x
= src
->x1
>> 16;
865 src_w
= drm_rect_width(src
) >> 16;
866 src_y
= src
->y1
>> 16;
867 src_h
= drm_rect_height(src
) >> 16;
869 if (format_is_yuv(fb
->pixel_format
)) {
874 * Must keep src and dst the
875 * same if we can't scale.
881 state
->base
.visible
= false;
885 /* Check size restrictions when scaling */
886 if (state
->base
.visible
&& (src_w
!= crtc_w
|| src_h
!= crtc_h
)) {
887 unsigned int width_bytes
;
888 int cpp
= drm_format_plane_cpp(fb
->pixel_format
, 0);
892 /* FIXME interlacing min height is 6 */
894 if (crtc_w
< 3 || crtc_h
< 3)
895 state
->base
.visible
= false;
897 if (src_w
< 3 || src_h
< 3)
898 state
->base
.visible
= false;
900 width_bytes
= ((src_x
* cpp
) & 63) + src_w
* cpp
;
902 if (INTEL_INFO(dev
)->gen
< 9 && (src_w
> 2048 || src_h
> 2048 ||
903 width_bytes
> 4096 || fb
->pitches
[0] > 4096)) {
904 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
909 if (state
->base
.visible
) {
910 src
->x1
= src_x
<< 16;
911 src
->x2
= (src_x
+ src_w
) << 16;
912 src
->y1
= src_y
<< 16;
913 src
->y2
= (src_y
+ src_h
) << 16;
917 dst
->x2
= crtc_x
+ crtc_w
;
919 dst
->y2
= crtc_y
+ crtc_h
;
921 if (INTEL_GEN(dev
) >= 9) {
922 ret
= skl_check_plane_surface(state
);
930 int intel_sprite_set_colorkey(struct drm_device
*dev
, void *data
,
931 struct drm_file
*file_priv
)
933 struct drm_intel_sprite_colorkey
*set
= data
;
934 struct drm_plane
*plane
;
935 struct drm_plane_state
*plane_state
;
936 struct drm_atomic_state
*state
;
937 struct drm_modeset_acquire_ctx ctx
;
940 /* Make sure we don't try to enable both src & dest simultaneously */
941 if ((set
->flags
& (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
)) == (I915_SET_COLORKEY_DESTINATION
| I915_SET_COLORKEY_SOURCE
))
944 if ((IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) &&
945 set
->flags
& I915_SET_COLORKEY_DESTINATION
)
948 plane
= drm_plane_find(dev
, set
->plane_id
);
949 if (!plane
|| plane
->type
!= DRM_PLANE_TYPE_OVERLAY
)
952 drm_modeset_acquire_init(&ctx
, 0);
954 state
= drm_atomic_state_alloc(plane
->dev
);
959 state
->acquire_ctx
= &ctx
;
962 plane_state
= drm_atomic_get_plane_state(state
, plane
);
963 ret
= PTR_ERR_OR_ZERO(plane_state
);
965 to_intel_plane_state(plane_state
)->ckey
= *set
;
966 ret
= drm_atomic_commit(state
);
972 drm_atomic_state_clear(state
);
973 drm_modeset_backoff(&ctx
);
977 drm_atomic_state_free(state
);
980 drm_modeset_drop_locks(&ctx
);
981 drm_modeset_acquire_fini(&ctx
);
985 static const uint32_t ilk_plane_formats
[] = {
993 static const uint32_t snb_plane_formats
[] = {
1002 static const uint32_t vlv_plane_formats
[] = {
1004 DRM_FORMAT_ABGR8888
,
1005 DRM_FORMAT_ARGB8888
,
1006 DRM_FORMAT_XBGR8888
,
1007 DRM_FORMAT_XRGB8888
,
1008 DRM_FORMAT_XBGR2101010
,
1009 DRM_FORMAT_ABGR2101010
,
1016 static uint32_t skl_plane_formats
[] = {
1018 DRM_FORMAT_ABGR8888
,
1019 DRM_FORMAT_ARGB8888
,
1020 DRM_FORMAT_XBGR8888
,
1021 DRM_FORMAT_XRGB8888
,
1029 intel_plane_init(struct drm_device
*dev
, enum pipe pipe
, int plane
)
1031 struct intel_plane
*intel_plane
= NULL
;
1032 struct intel_plane_state
*state
= NULL
;
1033 unsigned long possible_crtcs
;
1034 const uint32_t *plane_formats
;
1035 int num_plane_formats
;
1038 if (INTEL_INFO(dev
)->gen
< 5)
1041 intel_plane
= kzalloc(sizeof(*intel_plane
), GFP_KERNEL
);
1047 state
= intel_create_plane_state(&intel_plane
->base
);
1052 intel_plane
->base
.state
= &state
->base
;
1054 switch (INTEL_INFO(dev
)->gen
) {
1057 intel_plane
->can_scale
= true;
1058 intel_plane
->max_downscale
= 16;
1059 intel_plane
->update_plane
= ilk_update_plane
;
1060 intel_plane
->disable_plane
= ilk_disable_plane
;
1063 plane_formats
= snb_plane_formats
;
1064 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1066 plane_formats
= ilk_plane_formats
;
1067 num_plane_formats
= ARRAY_SIZE(ilk_plane_formats
);
1073 if (IS_IVYBRIDGE(dev
)) {
1074 intel_plane
->can_scale
= true;
1075 intel_plane
->max_downscale
= 2;
1077 intel_plane
->can_scale
= false;
1078 intel_plane
->max_downscale
= 1;
1081 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1082 intel_plane
->update_plane
= vlv_update_plane
;
1083 intel_plane
->disable_plane
= vlv_disable_plane
;
1085 plane_formats
= vlv_plane_formats
;
1086 num_plane_formats
= ARRAY_SIZE(vlv_plane_formats
);
1088 intel_plane
->update_plane
= ivb_update_plane
;
1089 intel_plane
->disable_plane
= ivb_disable_plane
;
1091 plane_formats
= snb_plane_formats
;
1092 num_plane_formats
= ARRAY_SIZE(snb_plane_formats
);
1096 intel_plane
->can_scale
= true;
1097 intel_plane
->update_plane
= skl_update_plane
;
1098 intel_plane
->disable_plane
= skl_disable_plane
;
1099 state
->scaler_id
= -1;
1101 plane_formats
= skl_plane_formats
;
1102 num_plane_formats
= ARRAY_SIZE(skl_plane_formats
);
1105 MISSING_CASE(INTEL_INFO(dev
)->gen
);
1110 intel_plane
->pipe
= pipe
;
1111 intel_plane
->plane
= plane
;
1112 intel_plane
->frontbuffer_bit
= INTEL_FRONTBUFFER_SPRITE(pipe
, plane
);
1113 intel_plane
->check_plane
= intel_check_sprite_plane
;
1115 possible_crtcs
= (1 << pipe
);
1117 if (INTEL_INFO(dev
)->gen
>= 9)
1118 ret
= drm_universal_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
1120 plane_formats
, num_plane_formats
,
1121 DRM_PLANE_TYPE_OVERLAY
,
1122 "plane %d%c", plane
+ 2, pipe_name(pipe
));
1124 ret
= drm_universal_plane_init(dev
, &intel_plane
->base
, possible_crtcs
,
1126 plane_formats
, num_plane_formats
,
1127 DRM_PLANE_TYPE_OVERLAY
,
1128 "sprite %c", sprite_name(pipe
, plane
));
1132 intel_create_rotation_property(dev
, intel_plane
);
1134 drm_plane_helper_add(&intel_plane
->base
, &intel_plane_helper_funcs
);