2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <asm/iosf_mbi.h>
29 #include <linux/pm_runtime.h>
31 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define GT_FIFO_TIMEOUT_MS 10
34 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
36 static const char * const forcewake_domain_names
[] = {
43 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
)
45 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names
) != FW_DOMAIN_ID_COUNT
);
47 if (id
>= 0 && id
< FW_DOMAIN_ID_COUNT
)
48 return forcewake_domain_names
[id
];
56 fw_domain_reset(struct drm_i915_private
*i915
,
57 const struct intel_uncore_forcewake_domain
*d
)
59 __raw_i915_write32(i915
, d
->reg_set
, i915
->uncore
.fw_reset
);
63 fw_domain_arm_timer(struct intel_uncore_forcewake_domain
*d
)
66 hrtimer_start_range_ns(&d
->timer
,
73 fw_domain_wait_ack_clear(const struct drm_i915_private
*i915
,
74 const struct intel_uncore_forcewake_domain
*d
)
76 if (wait_for_atomic((__raw_i915_read32(i915
, d
->reg_ack
) &
77 FORCEWAKE_KERNEL
) == 0,
78 FORCEWAKE_ACK_TIMEOUT_MS
))
79 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
80 intel_uncore_forcewake_domain_to_str(d
->id
));
84 fw_domain_get(struct drm_i915_private
*i915
,
85 const struct intel_uncore_forcewake_domain
*d
)
87 __raw_i915_write32(i915
, d
->reg_set
, i915
->uncore
.fw_set
);
91 fw_domain_wait_ack(const struct drm_i915_private
*i915
,
92 const struct intel_uncore_forcewake_domain
*d
)
94 if (wait_for_atomic((__raw_i915_read32(i915
, d
->reg_ack
) &
96 FORCEWAKE_ACK_TIMEOUT_MS
))
97 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
98 intel_uncore_forcewake_domain_to_str(d
->id
));
102 fw_domain_put(const struct drm_i915_private
*i915
,
103 const struct intel_uncore_forcewake_domain
*d
)
105 __raw_i915_write32(i915
, d
->reg_set
, i915
->uncore
.fw_clear
);
109 fw_domains_get(struct drm_i915_private
*i915
, enum forcewake_domains fw_domains
)
111 struct intel_uncore_forcewake_domain
*d
;
114 GEM_BUG_ON(fw_domains
& ~i915
->uncore
.fw_domains
);
116 for_each_fw_domain_masked(d
, fw_domains
, i915
, tmp
) {
117 fw_domain_wait_ack_clear(i915
, d
);
118 fw_domain_get(i915
, d
);
121 for_each_fw_domain_masked(d
, fw_domains
, i915
, tmp
)
122 fw_domain_wait_ack(i915
, d
);
124 i915
->uncore
.fw_domains_active
|= fw_domains
;
128 fw_domains_put(struct drm_i915_private
*i915
, enum forcewake_domains fw_domains
)
130 struct intel_uncore_forcewake_domain
*d
;
133 GEM_BUG_ON(fw_domains
& ~i915
->uncore
.fw_domains
);
135 for_each_fw_domain_masked(d
, fw_domains
, i915
, tmp
)
136 fw_domain_put(i915
, d
);
138 i915
->uncore
.fw_domains_active
&= ~fw_domains
;
142 fw_domains_reset(struct drm_i915_private
*i915
,
143 enum forcewake_domains fw_domains
)
145 struct intel_uncore_forcewake_domain
*d
;
151 GEM_BUG_ON(fw_domains
& ~i915
->uncore
.fw_domains
);
153 for_each_fw_domain_masked(d
, fw_domains
, i915
, tmp
)
154 fw_domain_reset(i915
, d
);
157 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private
*dev_priv
)
159 /* w/a for a sporadic read returning 0 by waiting for the GT
162 if (wait_for_atomic_us((__raw_i915_read32(dev_priv
, GEN6_GT_THREAD_STATUS_REG
) &
163 GEN6_GT_THREAD_STATUS_CORE_MASK
) == 0, 500))
164 DRM_ERROR("GT thread status wait timed out\n");
167 static void fw_domains_get_with_thread_status(struct drm_i915_private
*dev_priv
,
168 enum forcewake_domains fw_domains
)
170 fw_domains_get(dev_priv
, fw_domains
);
172 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
173 __gen6_gt_wait_for_thread_c0(dev_priv
);
176 static inline u32
fifo_free_entries(struct drm_i915_private
*dev_priv
)
178 u32 count
= __raw_i915_read32(dev_priv
, GTFIFOCTL
);
180 return count
& GT_FIFO_FREE_ENTRIES_MASK
;
183 static void __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
187 /* On VLV, FIFO will be shared by both SW and HW.
188 * So, we need to read the FREE_ENTRIES everytime */
189 if (IS_VALLEYVIEW(dev_priv
))
190 n
= fifo_free_entries(dev_priv
);
192 n
= dev_priv
->uncore
.fifo_count
;
194 if (n
<= GT_FIFO_NUM_RESERVED_ENTRIES
) {
195 if (wait_for_atomic((n
= fifo_free_entries(dev_priv
)) >
196 GT_FIFO_NUM_RESERVED_ENTRIES
,
197 GT_FIFO_TIMEOUT_MS
)) {
198 DRM_DEBUG("GT_FIFO timeout, entries: %u\n", n
);
203 dev_priv
->uncore
.fifo_count
= n
- 1;
206 static enum hrtimer_restart
207 intel_uncore_fw_release_timer(struct hrtimer
*timer
)
209 struct intel_uncore_forcewake_domain
*domain
=
210 container_of(timer
, struct intel_uncore_forcewake_domain
, timer
);
211 struct drm_i915_private
*dev_priv
=
212 container_of(domain
, struct drm_i915_private
, uncore
.fw_domain
[domain
->id
]);
213 unsigned long irqflags
;
215 assert_rpm_device_not_suspended(dev_priv
);
217 if (xchg(&domain
->active
, false))
218 return HRTIMER_RESTART
;
220 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
221 if (WARN_ON(domain
->wake_count
== 0))
222 domain
->wake_count
++;
224 if (--domain
->wake_count
== 0)
225 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, domain
->mask
);
227 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
229 return HRTIMER_NORESTART
;
232 static void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
235 unsigned long irqflags
;
236 struct intel_uncore_forcewake_domain
*domain
;
237 int retry_count
= 100;
238 enum forcewake_domains fw
, active_domains
;
240 /* Hold uncore.lock across reset to prevent any register access
241 * with forcewake not set correctly. Wait until all pending
242 * timers are run before holding.
249 for_each_fw_domain(domain
, dev_priv
, tmp
) {
250 smp_store_mb(domain
->active
, false);
251 if (hrtimer_cancel(&domain
->timer
) == 0)
254 intel_uncore_fw_release_timer(&domain
->timer
);
257 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
259 for_each_fw_domain(domain
, dev_priv
, tmp
) {
260 if (hrtimer_active(&domain
->timer
))
261 active_domains
|= domain
->mask
;
264 if (active_domains
== 0)
267 if (--retry_count
== 0) {
268 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
272 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
276 WARN_ON(active_domains
);
278 fw
= dev_priv
->uncore
.fw_domains_active
;
280 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, fw
);
282 fw_domains_reset(dev_priv
, dev_priv
->uncore
.fw_domains
);
284 if (restore
) { /* If reset with a user forcewake, try to restore */
286 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw
);
288 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
))
289 dev_priv
->uncore
.fifo_count
=
290 fifo_free_entries(dev_priv
);
294 assert_forcewakes_inactive(dev_priv
);
296 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
299 static u64
gen9_edram_size(struct drm_i915_private
*dev_priv
)
301 const unsigned int ways
[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
302 const unsigned int sets
[4] = { 1, 1, 2, 2 };
303 const u32 cap
= dev_priv
->edram_cap
;
305 return EDRAM_NUM_BANKS(cap
) *
306 ways
[EDRAM_WAYS_IDX(cap
)] *
307 sets
[EDRAM_SETS_IDX(cap
)] *
311 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
)
313 if (!HAS_EDRAM(dev_priv
))
316 /* The needed capability bits for size calculation
317 * are not there with pre gen9 so return 128MB always.
319 if (INTEL_GEN(dev_priv
) < 9)
320 return 128 * 1024 * 1024;
322 return gen9_edram_size(dev_priv
);
325 static void intel_uncore_edram_detect(struct drm_i915_private
*dev_priv
)
327 if (IS_HASWELL(dev_priv
) ||
328 IS_BROADWELL(dev_priv
) ||
329 INTEL_GEN(dev_priv
) >= 9) {
330 dev_priv
->edram_cap
= __raw_i915_read32(dev_priv
,
333 /* NB: We can't write IDICR yet because we do not have gt funcs
336 dev_priv
->edram_cap
= 0;
339 if (HAS_EDRAM(dev_priv
))
340 DRM_INFO("Found %lluMB of eDRAM\n",
341 intel_uncore_edram_size(dev_priv
) / (1024 * 1024));
345 fpga_check_for_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
349 dbg
= __raw_i915_read32(dev_priv
, FPGA_DBG
);
350 if (likely(!(dbg
& FPGA_DBG_RM_NOCLAIM
)))
353 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
359 vlv_check_for_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
363 cer
= __raw_i915_read32(dev_priv
, CLAIM_ER
);
364 if (likely(!(cer
& (CLAIM_ER_OVERFLOW
| CLAIM_ER_CTR_MASK
))))
367 __raw_i915_write32(dev_priv
, CLAIM_ER
, CLAIM_ER_CLR
);
373 gen6_check_for_fifo_debug(struct drm_i915_private
*dev_priv
)
377 fifodbg
= __raw_i915_read32(dev_priv
, GTFIFODBG
);
379 if (unlikely(fifodbg
)) {
380 DRM_DEBUG_DRIVER("GTFIFODBG = 0x08%x\n", fifodbg
);
381 __raw_i915_write32(dev_priv
, GTFIFODBG
, fifodbg
);
388 check_for_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
392 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv
))
393 ret
|= fpga_check_for_unclaimed_mmio(dev_priv
);
395 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
396 ret
|= vlv_check_for_unclaimed_mmio(dev_priv
);
398 if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
))
399 ret
|= gen6_check_for_fifo_debug(dev_priv
);
404 static void __intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
405 bool restore_forcewake
)
407 /* clear out unclaimed reg detection bit */
408 if (check_for_unclaimed_mmio(dev_priv
))
409 DRM_DEBUG("unclaimed mmio detected on uncore init, clearing\n");
411 /* WaDisableShadowRegForCpd:chv */
412 if (IS_CHERRYVIEW(dev_priv
)) {
413 __raw_i915_write32(dev_priv
, GTFIFOCTL
,
414 __raw_i915_read32(dev_priv
, GTFIFOCTL
) |
415 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL
|
416 GT_FIFO_CTL_RC6_POLICY_STALL
);
419 intel_uncore_forcewake_reset(dev_priv
, restore_forcewake
);
422 void intel_uncore_suspend(struct drm_i915_private
*dev_priv
)
424 iosf_mbi_unregister_pmic_bus_access_notifier(
425 &dev_priv
->uncore
.pmic_bus_access_nb
);
426 intel_uncore_forcewake_reset(dev_priv
, false);
429 void intel_uncore_resume_early(struct drm_i915_private
*dev_priv
)
431 __intel_uncore_early_sanitize(dev_priv
, true);
432 iosf_mbi_register_pmic_bus_access_notifier(
433 &dev_priv
->uncore
.pmic_bus_access_nb
);
434 i915_check_and_clear_faults(dev_priv
);
437 void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
)
439 i915_modparams
.enable_rc6
=
440 sanitize_rc6_option(dev_priv
, i915_modparams
.enable_rc6
);
442 /* BIOS often leaves RC6 enabled, but disable it for hw init */
443 intel_sanitize_gt_powersave(dev_priv
);
446 static void __intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
447 enum forcewake_domains fw_domains
)
449 struct intel_uncore_forcewake_domain
*domain
;
452 fw_domains
&= dev_priv
->uncore
.fw_domains
;
454 for_each_fw_domain_masked(domain
, fw_domains
, dev_priv
, tmp
) {
455 if (domain
->wake_count
++) {
456 fw_domains
&= ~domain
->mask
;
457 domain
->active
= true;
462 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw_domains
);
466 * intel_uncore_forcewake_get - grab forcewake domain references
467 * @dev_priv: i915 device instance
468 * @fw_domains: forcewake domains to get reference on
470 * This function can be used get GT's forcewake domain references.
471 * Normal register access will handle the forcewake domains automatically.
472 * However if some sequence requires the GT to not power down a particular
473 * forcewake domains this function should be called at the beginning of the
474 * sequence. And subsequently the reference should be dropped by symmetric
475 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
476 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
478 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
479 enum forcewake_domains fw_domains
)
481 unsigned long irqflags
;
483 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
486 assert_rpm_wakelock_held(dev_priv
);
488 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
489 __intel_uncore_forcewake_get(dev_priv
, fw_domains
);
490 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
494 * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace
495 * @dev_priv: i915 device instance
497 * This function is a wrapper around intel_uncore_forcewake_get() to acquire
498 * the GT powerwell and in the process disable our debugging for the
499 * duration of userspace's bypass.
501 void intel_uncore_forcewake_user_get(struct drm_i915_private
*dev_priv
)
503 spin_lock_irq(&dev_priv
->uncore
.lock
);
504 if (!dev_priv
->uncore
.user_forcewake
.count
++) {
505 intel_uncore_forcewake_get__locked(dev_priv
, FORCEWAKE_ALL
);
507 /* Save and disable mmio debugging for the user bypass */
508 dev_priv
->uncore
.user_forcewake
.saved_mmio_check
=
509 dev_priv
->uncore
.unclaimed_mmio_check
;
510 dev_priv
->uncore
.user_forcewake
.saved_mmio_debug
=
511 i915_modparams
.mmio_debug
;
513 dev_priv
->uncore
.unclaimed_mmio_check
= 0;
514 i915_modparams
.mmio_debug
= 0;
516 spin_unlock_irq(&dev_priv
->uncore
.lock
);
520 * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace
521 * @dev_priv: i915 device instance
523 * This function complements intel_uncore_forcewake_user_get() and releases
524 * the GT powerwell taken on behalf of the userspace bypass.
526 void intel_uncore_forcewake_user_put(struct drm_i915_private
*dev_priv
)
528 spin_lock_irq(&dev_priv
->uncore
.lock
);
529 if (!--dev_priv
->uncore
.user_forcewake
.count
) {
530 if (intel_uncore_unclaimed_mmio(dev_priv
))
531 dev_info(dev_priv
->drm
.dev
,
532 "Invalid mmio detected during user access\n");
534 dev_priv
->uncore
.unclaimed_mmio_check
=
535 dev_priv
->uncore
.user_forcewake
.saved_mmio_check
;
536 i915_modparams
.mmio_debug
=
537 dev_priv
->uncore
.user_forcewake
.saved_mmio_debug
;
539 intel_uncore_forcewake_put__locked(dev_priv
, FORCEWAKE_ALL
);
541 spin_unlock_irq(&dev_priv
->uncore
.lock
);
545 * intel_uncore_forcewake_get__locked - grab forcewake domain references
546 * @dev_priv: i915 device instance
547 * @fw_domains: forcewake domains to get reference on
549 * See intel_uncore_forcewake_get(). This variant places the onus
550 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
552 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
553 enum forcewake_domains fw_domains
)
555 lockdep_assert_held(&dev_priv
->uncore
.lock
);
557 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
560 __intel_uncore_forcewake_get(dev_priv
, fw_domains
);
563 static void __intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
564 enum forcewake_domains fw_domains
)
566 struct intel_uncore_forcewake_domain
*domain
;
569 fw_domains
&= dev_priv
->uncore
.fw_domains
;
571 for_each_fw_domain_masked(domain
, fw_domains
, dev_priv
, tmp
) {
572 if (WARN_ON(domain
->wake_count
== 0))
575 if (--domain
->wake_count
) {
576 domain
->active
= true;
580 fw_domain_arm_timer(domain
);
585 * intel_uncore_forcewake_put - release a forcewake domain reference
586 * @dev_priv: i915 device instance
587 * @fw_domains: forcewake domains to put references
589 * This function drops the device-level forcewakes for specified
590 * domains obtained by intel_uncore_forcewake_get().
592 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
593 enum forcewake_domains fw_domains
)
595 unsigned long irqflags
;
597 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
600 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
601 __intel_uncore_forcewake_put(dev_priv
, fw_domains
);
602 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
606 * intel_uncore_forcewake_put__locked - grab forcewake domain references
607 * @dev_priv: i915 device instance
608 * @fw_domains: forcewake domains to get reference on
610 * See intel_uncore_forcewake_put(). This variant places the onus
611 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
613 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
614 enum forcewake_domains fw_domains
)
616 lockdep_assert_held(&dev_priv
->uncore
.lock
);
618 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
621 __intel_uncore_forcewake_put(dev_priv
, fw_domains
);
624 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
)
626 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
629 WARN_ON(dev_priv
->uncore
.fw_domains_active
);
632 /* We give fast paths for the really cool registers */
633 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
635 #define __gen6_reg_read_fw_domains(offset) \
637 enum forcewake_domains __fwd; \
638 if (NEEDS_FORCE_WAKE(offset)) \
639 __fwd = FORCEWAKE_RENDER; \
645 static int fw_range_cmp(u32 offset
, const struct intel_forcewake_range
*entry
)
647 if (offset
< entry
->start
)
649 else if (offset
> entry
->end
)
655 /* Copied and "macroized" from lib/bsearch.c */
656 #define BSEARCH(key, base, num, cmp) ({ \
657 unsigned int start__ = 0, end__ = (num); \
658 typeof(base) result__ = NULL; \
659 while (start__ < end__) { \
660 unsigned int mid__ = start__ + (end__ - start__) / 2; \
661 int ret__ = (cmp)((key), (base) + mid__); \
664 } else if (ret__ > 0) { \
665 start__ = mid__ + 1; \
667 result__ = (base) + mid__; \
674 static enum forcewake_domains
675 find_fw_domain(struct drm_i915_private
*dev_priv
, u32 offset
)
677 const struct intel_forcewake_range
*entry
;
679 entry
= BSEARCH(offset
,
680 dev_priv
->uncore
.fw_domains_table
,
681 dev_priv
->uncore
.fw_domains_table_entries
,
687 WARN(entry
->domains
& ~dev_priv
->uncore
.fw_domains
,
688 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
689 entry
->domains
& ~dev_priv
->uncore
.fw_domains
, offset
);
691 return entry
->domains
;
694 #define GEN_FW_RANGE(s, e, d) \
695 { .start = (s), .end = (e), .domains = (d) }
697 #define HAS_FWTABLE(dev_priv) \
698 (INTEL_GEN(dev_priv) >= 9 || \
699 IS_CHERRYVIEW(dev_priv) || \
700 IS_VALLEYVIEW(dev_priv))
702 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
703 static const struct intel_forcewake_range __vlv_fw_ranges
[] = {
704 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER
),
705 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER
),
706 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER
),
707 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA
),
708 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA
),
709 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER
),
710 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA
),
713 #define __fwtable_reg_read_fw_domains(offset) \
715 enum forcewake_domains __fwd = 0; \
716 if (NEEDS_FORCE_WAKE((offset))) \
717 __fwd = find_fw_domain(dev_priv, offset); \
721 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
722 static const i915_reg_t gen8_shadowed_regs
[] = {
723 RING_TAIL(RENDER_RING_BASE
), /* 0x2000 (base) */
724 GEN6_RPNSWREQ
, /* 0xA008 */
725 GEN6_RC_VIDEO_FREQ
, /* 0xA00C */
726 RING_TAIL(GEN6_BSD_RING_BASE
), /* 0x12000 (base) */
727 RING_TAIL(VEBOX_RING_BASE
), /* 0x1a000 (base) */
728 RING_TAIL(BLT_RING_BASE
), /* 0x22000 (base) */
729 /* TODO: Other registers are not yet used */
732 static int mmio_reg_cmp(u32 key
, const i915_reg_t
*reg
)
734 u32 offset
= i915_mmio_reg_offset(*reg
);
738 else if (key
> offset
)
744 static bool is_gen8_shadowed(u32 offset
)
746 const i915_reg_t
*regs
= gen8_shadowed_regs
;
748 return BSEARCH(offset
, regs
, ARRAY_SIZE(gen8_shadowed_regs
),
752 #define __gen8_reg_write_fw_domains(offset) \
754 enum forcewake_domains __fwd; \
755 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \
756 __fwd = FORCEWAKE_RENDER; \
762 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
763 static const struct intel_forcewake_range __chv_fw_ranges
[] = {
764 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER
),
765 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER
| FORCEWAKE_MEDIA
),
766 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER
),
767 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER
| FORCEWAKE_MEDIA
),
768 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER
),
769 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER
| FORCEWAKE_MEDIA
),
770 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA
),
771 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER
| FORCEWAKE_MEDIA
),
772 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER
),
773 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA
),
774 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER
),
775 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER
| FORCEWAKE_MEDIA
),
776 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA
),
777 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA
),
778 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA
),
779 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA
),
782 #define __fwtable_reg_write_fw_domains(offset) \
784 enum forcewake_domains __fwd = 0; \
785 if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
786 __fwd = find_fw_domain(dev_priv, offset); \
790 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
791 static const struct intel_forcewake_range __gen9_fw_ranges
[] = {
792 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER
),
793 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
794 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER
),
795 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER
),
796 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER
),
797 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER
),
798 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER
),
799 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_BLITTER
),
800 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA
),
801 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER
),
802 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER
),
803 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER
),
804 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_BLITTER
),
805 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA
),
806 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_BLITTER
),
807 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER
),
808 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER
),
809 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER
| FORCEWAKE_MEDIA
),
810 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER
),
811 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER
),
812 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_BLITTER
),
813 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA
),
814 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_BLITTER
),
815 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER
),
816 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_BLITTER
),
817 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA
),
818 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_BLITTER
),
819 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA
),
820 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_BLITTER
),
821 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER
),
822 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_BLITTER
),
823 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA
),
827 ilk_dummy_write(struct drm_i915_private
*dev_priv
)
829 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
830 * the chip from rc6 before touching it for real. MI_MODE is masked,
831 * hence harmless to write 0 into. */
832 __raw_i915_write32(dev_priv
, MI_MODE
, 0);
836 __unclaimed_reg_debug(struct drm_i915_private
*dev_priv
,
837 const i915_reg_t reg
,
841 if (WARN(check_for_unclaimed_mmio(dev_priv
) && !before
,
842 "Unclaimed %s register 0x%x\n",
843 read
? "read from" : "write to",
844 i915_mmio_reg_offset(reg
)))
845 /* Only report the first N failures */
846 i915_modparams
.mmio_debug
--;
850 unclaimed_reg_debug(struct drm_i915_private
*dev_priv
,
851 const i915_reg_t reg
,
855 if (likely(!i915_modparams
.mmio_debug
))
858 __unclaimed_reg_debug(dev_priv
, reg
, read
, before
);
861 #define GEN2_READ_HEADER(x) \
863 assert_rpm_wakelock_held(dev_priv);
865 #define GEN2_READ_FOOTER \
866 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
869 #define __gen2_read(x) \
871 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
872 GEN2_READ_HEADER(x); \
873 val = __raw_i915_read##x(dev_priv, reg); \
877 #define __gen5_read(x) \
879 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
880 GEN2_READ_HEADER(x); \
881 ilk_dummy_write(dev_priv); \
882 val = __raw_i915_read##x(dev_priv, reg); \
898 #undef GEN2_READ_FOOTER
899 #undef GEN2_READ_HEADER
901 #define GEN6_READ_HEADER(x) \
902 u32 offset = i915_mmio_reg_offset(reg); \
903 unsigned long irqflags; \
905 assert_rpm_wakelock_held(dev_priv); \
906 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
907 unclaimed_reg_debug(dev_priv, reg, true, true)
909 #define GEN6_READ_FOOTER \
910 unclaimed_reg_debug(dev_priv, reg, true, false); \
911 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
912 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
915 static noinline
void ___force_wake_auto(struct drm_i915_private
*dev_priv
,
916 enum forcewake_domains fw_domains
)
918 struct intel_uncore_forcewake_domain
*domain
;
921 GEM_BUG_ON(fw_domains
& ~dev_priv
->uncore
.fw_domains
);
923 for_each_fw_domain_masked(domain
, fw_domains
, dev_priv
, tmp
)
924 fw_domain_arm_timer(domain
);
926 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw_domains
);
929 static inline void __force_wake_auto(struct drm_i915_private
*dev_priv
,
930 enum forcewake_domains fw_domains
)
932 if (WARN_ON(!fw_domains
))
935 /* Turn on all requested but inactive supported forcewake domains. */
936 fw_domains
&= dev_priv
->uncore
.fw_domains
;
937 fw_domains
&= ~dev_priv
->uncore
.fw_domains_active
;
940 ___force_wake_auto(dev_priv
, fw_domains
);
943 #define __gen_read(func, x) \
945 func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
946 enum forcewake_domains fw_engine; \
947 GEN6_READ_HEADER(x); \
948 fw_engine = __##func##_reg_read_fw_domains(offset); \
950 __force_wake_auto(dev_priv, fw_engine); \
951 val = __raw_i915_read##x(dev_priv, reg); \
954 #define __gen6_read(x) __gen_read(gen6, x)
955 #define __fwtable_read(x) __gen_read(fwtable, x)
966 #undef __fwtable_read
968 #undef GEN6_READ_FOOTER
969 #undef GEN6_READ_HEADER
971 #define GEN2_WRITE_HEADER \
972 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
973 assert_rpm_wakelock_held(dev_priv); \
975 #define GEN2_WRITE_FOOTER
977 #define __gen2_write(x) \
979 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
981 __raw_i915_write##x(dev_priv, reg, val); \
985 #define __gen5_write(x) \
987 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
989 ilk_dummy_write(dev_priv); \
990 __raw_i915_write##x(dev_priv, reg, val); \
1004 #undef GEN2_WRITE_FOOTER
1005 #undef GEN2_WRITE_HEADER
1007 #define GEN6_WRITE_HEADER \
1008 u32 offset = i915_mmio_reg_offset(reg); \
1009 unsigned long irqflags; \
1010 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1011 assert_rpm_wakelock_held(dev_priv); \
1012 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
1013 unclaimed_reg_debug(dev_priv, reg, false, true)
1015 #define GEN6_WRITE_FOOTER \
1016 unclaimed_reg_debug(dev_priv, reg, false, false); \
1017 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1019 #define __gen6_write(x) \
1021 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1022 GEN6_WRITE_HEADER; \
1023 if (NEEDS_FORCE_WAKE(offset)) \
1024 __gen6_gt_wait_for_fifo(dev_priv); \
1025 __raw_i915_write##x(dev_priv, reg, val); \
1026 GEN6_WRITE_FOOTER; \
1029 #define __gen_write(func, x) \
1031 func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
1032 enum forcewake_domains fw_engine; \
1033 GEN6_WRITE_HEADER; \
1034 fw_engine = __##func##_reg_write_fw_domains(offset); \
1036 __force_wake_auto(dev_priv, fw_engine); \
1037 __raw_i915_write##x(dev_priv, reg, val); \
1038 GEN6_WRITE_FOOTER; \
1040 #define __gen8_write(x) __gen_write(gen8, x)
1041 #define __fwtable_write(x) __gen_write(fwtable, x)
1053 #undef __fwtable_write
1056 #undef GEN6_WRITE_FOOTER
1057 #undef GEN6_WRITE_HEADER
1059 #define ASSIGN_WRITE_MMIO_VFUNCS(i915, x) \
1061 (i915)->uncore.funcs.mmio_writeb = x##_write8; \
1062 (i915)->uncore.funcs.mmio_writew = x##_write16; \
1063 (i915)->uncore.funcs.mmio_writel = x##_write32; \
1066 #define ASSIGN_READ_MMIO_VFUNCS(i915, x) \
1068 (i915)->uncore.funcs.mmio_readb = x##_read8; \
1069 (i915)->uncore.funcs.mmio_readw = x##_read16; \
1070 (i915)->uncore.funcs.mmio_readl = x##_read32; \
1071 (i915)->uncore.funcs.mmio_readq = x##_read64; \
1075 static void fw_domain_init(struct drm_i915_private
*dev_priv
,
1076 enum forcewake_domain_id domain_id
,
1080 struct intel_uncore_forcewake_domain
*d
;
1082 if (WARN_ON(domain_id
>= FW_DOMAIN_ID_COUNT
))
1085 d
= &dev_priv
->uncore
.fw_domain
[domain_id
];
1087 WARN_ON(d
->wake_count
);
1089 WARN_ON(!i915_mmio_reg_valid(reg_set
));
1090 WARN_ON(!i915_mmio_reg_valid(reg_ack
));
1093 d
->reg_set
= reg_set
;
1094 d
->reg_ack
= reg_ack
;
1098 BUILD_BUG_ON(FORCEWAKE_RENDER
!= (1 << FW_DOMAIN_ID_RENDER
));
1099 BUILD_BUG_ON(FORCEWAKE_BLITTER
!= (1 << FW_DOMAIN_ID_BLITTER
));
1100 BUILD_BUG_ON(FORCEWAKE_MEDIA
!= (1 << FW_DOMAIN_ID_MEDIA
));
1102 d
->mask
= BIT(domain_id
);
1104 hrtimer_init(&d
->timer
, CLOCK_MONOTONIC
, HRTIMER_MODE_REL
);
1105 d
->timer
.function
= intel_uncore_fw_release_timer
;
1107 dev_priv
->uncore
.fw_domains
|= BIT(domain_id
);
1109 fw_domain_reset(dev_priv
, d
);
1112 static void intel_uncore_fw_domains_init(struct drm_i915_private
*dev_priv
)
1114 if (INTEL_GEN(dev_priv
) <= 5 || intel_vgpu_active(dev_priv
))
1117 if (IS_GEN6(dev_priv
)) {
1118 dev_priv
->uncore
.fw_reset
= 0;
1119 dev_priv
->uncore
.fw_set
= FORCEWAKE_KERNEL
;
1120 dev_priv
->uncore
.fw_clear
= 0;
1122 /* WaRsClearFWBitsAtReset:bdw,skl */
1123 dev_priv
->uncore
.fw_reset
= _MASKED_BIT_DISABLE(0xffff);
1124 dev_priv
->uncore
.fw_set
= _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
);
1125 dev_priv
->uncore
.fw_clear
= _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
);
1128 if (INTEL_GEN(dev_priv
) >= 9) {
1129 dev_priv
->uncore
.funcs
.force_wake_get
= fw_domains_get
;
1130 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1131 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1132 FORCEWAKE_RENDER_GEN9
,
1133 FORCEWAKE_ACK_RENDER_GEN9
);
1134 fw_domain_init(dev_priv
, FW_DOMAIN_ID_BLITTER
,
1135 FORCEWAKE_BLITTER_GEN9
,
1136 FORCEWAKE_ACK_BLITTER_GEN9
);
1137 fw_domain_init(dev_priv
, FW_DOMAIN_ID_MEDIA
,
1138 FORCEWAKE_MEDIA_GEN9
, FORCEWAKE_ACK_MEDIA_GEN9
);
1139 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1140 dev_priv
->uncore
.funcs
.force_wake_get
= fw_domains_get
;
1141 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1142 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1143 FORCEWAKE_VLV
, FORCEWAKE_ACK_VLV
);
1144 fw_domain_init(dev_priv
, FW_DOMAIN_ID_MEDIA
,
1145 FORCEWAKE_MEDIA_VLV
, FORCEWAKE_ACK_MEDIA_VLV
);
1146 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1147 dev_priv
->uncore
.funcs
.force_wake_get
=
1148 fw_domains_get_with_thread_status
;
1149 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1150 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1151 FORCEWAKE_MT
, FORCEWAKE_ACK_HSW
);
1152 } else if (IS_IVYBRIDGE(dev_priv
)) {
1155 /* IVB configs may use multi-threaded forcewake */
1157 /* A small trick here - if the bios hasn't configured
1158 * MT forcewake, and if the device is in RC6, then
1159 * force_wake_mt_get will not wake the device and the
1160 * ECOBUS read will return zero. Which will be
1161 * (correctly) interpreted by the test below as MT
1162 * forcewake being disabled.
1164 dev_priv
->uncore
.funcs
.force_wake_get
=
1165 fw_domains_get_with_thread_status
;
1166 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1168 /* We need to init first for ECOBUS access and then
1169 * determine later if we want to reinit, in case of MT access is
1170 * not working. In this stage we don't know which flavour this
1171 * ivb is, so it is better to reset also the gen6 fw registers
1172 * before the ecobus check.
1175 __raw_i915_write32(dev_priv
, FORCEWAKE
, 0);
1176 __raw_posting_read(dev_priv
, ECOBUS
);
1178 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1179 FORCEWAKE_MT
, FORCEWAKE_MT_ACK
);
1181 spin_lock_irq(&dev_priv
->uncore
.lock
);
1182 fw_domains_get_with_thread_status(dev_priv
, FORCEWAKE_RENDER
);
1183 ecobus
= __raw_i915_read32(dev_priv
, ECOBUS
);
1184 fw_domains_put(dev_priv
, FORCEWAKE_RENDER
);
1185 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1187 if (!(ecobus
& FORCEWAKE_MT_ENABLE
)) {
1188 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1189 DRM_INFO("when using vblank-synced partial screen updates.\n");
1190 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1191 FORCEWAKE
, FORCEWAKE_ACK
);
1193 } else if (IS_GEN6(dev_priv
)) {
1194 dev_priv
->uncore
.funcs
.force_wake_get
=
1195 fw_domains_get_with_thread_status
;
1196 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1197 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1198 FORCEWAKE
, FORCEWAKE_ACK
);
1201 /* All future platforms are expected to require complex power gating */
1202 WARN_ON(dev_priv
->uncore
.fw_domains
== 0);
1205 #define ASSIGN_FW_DOMAINS_TABLE(d) \
1207 dev_priv->uncore.fw_domains_table = \
1208 (struct intel_forcewake_range *)(d); \
1209 dev_priv->uncore.fw_domains_table_entries = ARRAY_SIZE((d)); \
1212 static int i915_pmic_bus_access_notifier(struct notifier_block
*nb
,
1213 unsigned long action
, void *data
)
1215 struct drm_i915_private
*dev_priv
= container_of(nb
,
1216 struct drm_i915_private
, uncore
.pmic_bus_access_nb
);
1219 case MBI_PMIC_BUS_ACCESS_BEGIN
:
1221 * forcewake all now to make sure that we don't need to do a
1222 * forcewake later which on systems where this notifier gets
1223 * called requires the punit to access to the shared pmic i2c
1224 * bus, which will be busy after this notification, leading to:
1225 * "render: timed out waiting for forcewake ack request."
1228 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1230 case MBI_PMIC_BUS_ACCESS_END
:
1231 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1238 void intel_uncore_init(struct drm_i915_private
*dev_priv
)
1240 i915_check_vgpu(dev_priv
);
1242 intel_uncore_edram_detect(dev_priv
);
1243 intel_uncore_fw_domains_init(dev_priv
);
1244 __intel_uncore_early_sanitize(dev_priv
, false);
1246 dev_priv
->uncore
.unclaimed_mmio_check
= 1;
1247 dev_priv
->uncore
.pmic_bus_access_nb
.notifier_call
=
1248 i915_pmic_bus_access_notifier
;
1250 if (IS_GEN(dev_priv
, 2, 4) || intel_vgpu_active(dev_priv
)) {
1251 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv
, gen2
);
1252 ASSIGN_READ_MMIO_VFUNCS(dev_priv
, gen2
);
1253 } else if (IS_GEN5(dev_priv
)) {
1254 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv
, gen5
);
1255 ASSIGN_READ_MMIO_VFUNCS(dev_priv
, gen5
);
1256 } else if (IS_GEN(dev_priv
, 6, 7)) {
1257 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv
, gen6
);
1259 if (IS_VALLEYVIEW(dev_priv
)) {
1260 ASSIGN_FW_DOMAINS_TABLE(__vlv_fw_ranges
);
1261 ASSIGN_READ_MMIO_VFUNCS(dev_priv
, fwtable
);
1263 ASSIGN_READ_MMIO_VFUNCS(dev_priv
, gen6
);
1265 } else if (IS_GEN8(dev_priv
)) {
1266 if (IS_CHERRYVIEW(dev_priv
)) {
1267 ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges
);
1268 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv
, fwtable
);
1269 ASSIGN_READ_MMIO_VFUNCS(dev_priv
, fwtable
);
1272 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv
, gen8
);
1273 ASSIGN_READ_MMIO_VFUNCS(dev_priv
, gen6
);
1276 ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges
);
1277 ASSIGN_WRITE_MMIO_VFUNCS(dev_priv
, fwtable
);
1278 ASSIGN_READ_MMIO_VFUNCS(dev_priv
, fwtable
);
1281 iosf_mbi_register_pmic_bus_access_notifier(
1282 &dev_priv
->uncore
.pmic_bus_access_nb
);
1284 i915_check_and_clear_faults(dev_priv
);
1287 void intel_uncore_fini(struct drm_i915_private
*dev_priv
)
1289 iosf_mbi_unregister_pmic_bus_access_notifier(
1290 &dev_priv
->uncore
.pmic_bus_access_nb
);
1292 /* Paranoia: make sure we have disabled everything before we exit. */
1293 intel_uncore_sanitize(dev_priv
);
1294 intel_uncore_forcewake_reset(dev_priv
, false);
1297 static const struct reg_whitelist
{
1298 i915_reg_t offset_ldw
;
1299 i915_reg_t offset_udw
;
1302 } reg_read_whitelist
[] = { {
1303 .offset_ldw
= RING_TIMESTAMP(RENDER_RING_BASE
),
1304 .offset_udw
= RING_TIMESTAMP_UDW(RENDER_RING_BASE
),
1305 .gen_mask
= INTEL_GEN_MASK(4, 10),
1309 int i915_reg_read_ioctl(struct drm_device
*dev
,
1310 void *data
, struct drm_file
*file
)
1312 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1313 struct drm_i915_reg_read
*reg
= data
;
1314 struct reg_whitelist
const *entry
;
1319 entry
= reg_read_whitelist
;
1320 remain
= ARRAY_SIZE(reg_read_whitelist
);
1322 u32 entry_offset
= i915_mmio_reg_offset(entry
->offset_ldw
);
1324 GEM_BUG_ON(!is_power_of_2(entry
->size
));
1325 GEM_BUG_ON(entry
->size
> 8);
1326 GEM_BUG_ON(entry_offset
& (entry
->size
- 1));
1328 if (INTEL_INFO(dev_priv
)->gen_mask
& entry
->gen_mask
&&
1329 entry_offset
== (reg
->offset
& -entry
->size
))
1338 flags
= reg
->offset
& (entry
->size
- 1);
1340 intel_runtime_pm_get(dev_priv
);
1341 if (entry
->size
== 8 && flags
== I915_REG_READ_8B_WA
)
1342 reg
->val
= I915_READ64_2x32(entry
->offset_ldw
,
1344 else if (entry
->size
== 8 && flags
== 0)
1345 reg
->val
= I915_READ64(entry
->offset_ldw
);
1346 else if (entry
->size
== 4 && flags
== 0)
1347 reg
->val
= I915_READ(entry
->offset_ldw
);
1348 else if (entry
->size
== 2 && flags
== 0)
1349 reg
->val
= I915_READ16(entry
->offset_ldw
);
1350 else if (entry
->size
== 1 && flags
== 0)
1351 reg
->val
= I915_READ8(entry
->offset_ldw
);
1354 intel_runtime_pm_put(dev_priv
);
1359 static void gen3_stop_engine(struct intel_engine_cs
*engine
)
1361 struct drm_i915_private
*dev_priv
= engine
->i915
;
1362 const u32 base
= engine
->mmio_base
;
1363 const i915_reg_t mode
= RING_MI_MODE(base
);
1365 I915_WRITE_FW(mode
, _MASKED_BIT_ENABLE(STOP_RING
));
1366 if (intel_wait_for_register_fw(dev_priv
,
1371 DRM_DEBUG_DRIVER("%s: timed out on STOP_RING\n",
1374 I915_WRITE_FW(RING_CTL(base
), 0);
1375 I915_WRITE_FW(RING_HEAD(base
), 0);
1376 I915_WRITE_FW(RING_TAIL(base
), 0);
1378 /* Check acts as a post */
1379 if (I915_READ_FW(RING_HEAD(base
)) != 0)
1380 DRM_DEBUG_DRIVER("%s: ring head not parked\n",
1384 static void i915_stop_engines(struct drm_i915_private
*dev_priv
,
1385 unsigned engine_mask
)
1387 struct intel_engine_cs
*engine
;
1388 enum intel_engine_id id
;
1390 for_each_engine_masked(engine
, dev_priv
, engine_mask
, id
)
1391 gen3_stop_engine(engine
);
1394 static bool i915_reset_complete(struct pci_dev
*pdev
)
1398 pci_read_config_byte(pdev
, I915_GDRST
, &gdrst
);
1399 return (gdrst
& GRDOM_RESET_STATUS
) == 0;
1402 static int i915_do_reset(struct drm_i915_private
*dev_priv
, unsigned engine_mask
)
1404 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1406 /* assert reset for at least 20 usec */
1407 pci_write_config_byte(pdev
, I915_GDRST
, GRDOM_RESET_ENABLE
);
1408 usleep_range(50, 200);
1409 pci_write_config_byte(pdev
, I915_GDRST
, 0);
1411 return wait_for(i915_reset_complete(pdev
), 500);
1414 static bool g4x_reset_complete(struct pci_dev
*pdev
)
1418 pci_read_config_byte(pdev
, I915_GDRST
, &gdrst
);
1419 return (gdrst
& GRDOM_RESET_ENABLE
) == 0;
1422 static int g33_do_reset(struct drm_i915_private
*dev_priv
, unsigned engine_mask
)
1424 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1426 pci_write_config_byte(pdev
, I915_GDRST
, GRDOM_RESET_ENABLE
);
1427 return wait_for(g4x_reset_complete(pdev
), 500);
1430 static int g4x_do_reset(struct drm_i915_private
*dev_priv
, unsigned engine_mask
)
1432 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
1435 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1436 I915_WRITE(VDECCLK_GATE_D
,
1437 I915_READ(VDECCLK_GATE_D
) | VCP_UNIT_CLOCK_GATE_DISABLE
);
1438 POSTING_READ(VDECCLK_GATE_D
);
1440 pci_write_config_byte(pdev
, I915_GDRST
,
1441 GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
1442 ret
= wait_for(g4x_reset_complete(pdev
), 500);
1444 DRM_DEBUG_DRIVER("Wait for media reset failed\n");
1448 pci_write_config_byte(pdev
, I915_GDRST
,
1449 GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
1450 ret
= wait_for(g4x_reset_complete(pdev
), 500);
1452 DRM_DEBUG_DRIVER("Wait for render reset failed\n");
1457 pci_write_config_byte(pdev
, I915_GDRST
, 0);
1459 I915_WRITE(VDECCLK_GATE_D
,
1460 I915_READ(VDECCLK_GATE_D
) & ~VCP_UNIT_CLOCK_GATE_DISABLE
);
1461 POSTING_READ(VDECCLK_GATE_D
);
1466 static int ironlake_do_reset(struct drm_i915_private
*dev_priv
,
1467 unsigned engine_mask
)
1471 I915_WRITE(ILK_GDSR
, ILK_GRDOM_RENDER
| ILK_GRDOM_RESET_ENABLE
);
1472 ret
= intel_wait_for_register(dev_priv
,
1473 ILK_GDSR
, ILK_GRDOM_RESET_ENABLE
, 0,
1476 DRM_DEBUG_DRIVER("Wait for render reset failed\n");
1480 I915_WRITE(ILK_GDSR
, ILK_GRDOM_MEDIA
| ILK_GRDOM_RESET_ENABLE
);
1481 ret
= intel_wait_for_register(dev_priv
,
1482 ILK_GDSR
, ILK_GRDOM_RESET_ENABLE
, 0,
1485 DRM_DEBUG_DRIVER("Wait for media reset failed\n");
1490 I915_WRITE(ILK_GDSR
, 0);
1491 POSTING_READ(ILK_GDSR
);
1495 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
1496 static int gen6_hw_domain_reset(struct drm_i915_private
*dev_priv
,
1501 /* GEN6_GDRST is not in the gt power well, no need to check
1502 * for fifo space for the write or forcewake the chip for
1505 __raw_i915_write32(dev_priv
, GEN6_GDRST
, hw_domain_mask
);
1507 /* Wait for the device to ack the reset requests */
1508 err
= intel_wait_for_register_fw(dev_priv
,
1509 GEN6_GDRST
, hw_domain_mask
, 0,
1512 DRM_DEBUG_DRIVER("Wait for 0x%08x engines reset failed\n",
1519 * gen6_reset_engines - reset individual engines
1520 * @dev_priv: i915 device
1521 * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
1523 * This function will reset the individual engines that are set in engine_mask.
1524 * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
1526 * Note: It is responsibility of the caller to handle the difference between
1527 * asking full domain reset versus reset for all available individual engines.
1529 * Returns 0 on success, nonzero on error.
1531 static int gen6_reset_engines(struct drm_i915_private
*dev_priv
,
1532 unsigned engine_mask
)
1534 struct intel_engine_cs
*engine
;
1535 const u32 hw_engine_mask
[I915_NUM_ENGINES
] = {
1536 [RCS
] = GEN6_GRDOM_RENDER
,
1537 [BCS
] = GEN6_GRDOM_BLT
,
1538 [VCS
] = GEN6_GRDOM_MEDIA
,
1539 [VCS2
] = GEN8_GRDOM_MEDIA2
,
1540 [VECS
] = GEN6_GRDOM_VECS
,
1544 if (engine_mask
== ALL_ENGINES
) {
1545 hw_mask
= GEN6_GRDOM_FULL
;
1550 for_each_engine_masked(engine
, dev_priv
, engine_mask
, tmp
)
1551 hw_mask
|= hw_engine_mask
[engine
->id
];
1554 return gen6_hw_domain_reset(dev_priv
, hw_mask
);
1558 * __intel_wait_for_register_fw - wait until register matches expected state
1559 * @dev_priv: the i915 device
1560 * @reg: the register to read
1561 * @mask: mask to apply to register value
1562 * @value: expected value
1563 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait
1564 * @slow_timeout_ms: slow timeout in millisecond
1565 * @out_value: optional placeholder to hold registry value
1567 * This routine waits until the target register @reg contains the expected
1568 * @value after applying the @mask, i.e. it waits until ::
1570 * (I915_READ_FW(reg) & mask) == value
1572 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds.
1573 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us
1574 * must be not larger than 20,0000 microseconds.
1576 * Note that this routine assumes the caller holds forcewake asserted, it is
1577 * not suitable for very long waits. See intel_wait_for_register() if you
1578 * wish to wait without holding forcewake for the duration (i.e. you expect
1579 * the wait to be slow).
1581 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1583 int __intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
1587 unsigned int fast_timeout_us
,
1588 unsigned int slow_timeout_ms
,
1591 u32
uninitialized_var(reg_value
);
1592 #define done (((reg_value = I915_READ_FW(reg)) & mask) == value)
1595 /* Catch any overuse of this function */
1596 might_sleep_if(slow_timeout_ms
);
1597 GEM_BUG_ON(fast_timeout_us
> 20000);
1600 if (fast_timeout_us
&& fast_timeout_us
<= 20000)
1601 ret
= _wait_for_atomic(done
, fast_timeout_us
, 0);
1602 if (ret
&& slow_timeout_ms
)
1603 ret
= wait_for(done
, slow_timeout_ms
);
1606 *out_value
= reg_value
;
1613 * intel_wait_for_register - wait until register matches expected state
1614 * @dev_priv: the i915 device
1615 * @reg: the register to read
1616 * @mask: mask to apply to register value
1617 * @value: expected value
1618 * @timeout_ms: timeout in millisecond
1620 * This routine waits until the target register @reg contains the expected
1621 * @value after applying the @mask, i.e. it waits until ::
1623 * (I915_READ(reg) & mask) == value
1625 * Otherwise, the wait will timeout after @timeout_ms milliseconds.
1627 * Returns 0 if the register matches the desired condition, or -ETIMEOUT.
1629 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
1633 unsigned int timeout_ms
)
1636 intel_uncore_forcewake_for_reg(dev_priv
, reg
, FW_REG_READ
);
1641 spin_lock_irq(&dev_priv
->uncore
.lock
);
1642 intel_uncore_forcewake_get__locked(dev_priv
, fw
);
1644 ret
= __intel_wait_for_register_fw(dev_priv
,
1648 intel_uncore_forcewake_put__locked(dev_priv
, fw
);
1649 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1652 ret
= wait_for((I915_READ_NOTRACE(reg
) & mask
) == value
,
1658 static int gen8_reset_engine_start(struct intel_engine_cs
*engine
)
1660 struct drm_i915_private
*dev_priv
= engine
->i915
;
1663 I915_WRITE_FW(RING_RESET_CTL(engine
->mmio_base
),
1664 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET
));
1666 ret
= intel_wait_for_register_fw(dev_priv
,
1667 RING_RESET_CTL(engine
->mmio_base
),
1668 RESET_CTL_READY_TO_RESET
,
1669 RESET_CTL_READY_TO_RESET
,
1672 DRM_ERROR("%s: reset request timeout\n", engine
->name
);
1677 static void gen8_reset_engine_cancel(struct intel_engine_cs
*engine
)
1679 struct drm_i915_private
*dev_priv
= engine
->i915
;
1681 I915_WRITE_FW(RING_RESET_CTL(engine
->mmio_base
),
1682 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET
));
1685 static int gen8_reset_engines(struct drm_i915_private
*dev_priv
,
1686 unsigned engine_mask
)
1688 struct intel_engine_cs
*engine
;
1691 for_each_engine_masked(engine
, dev_priv
, engine_mask
, tmp
)
1692 if (gen8_reset_engine_start(engine
))
1695 return gen6_reset_engines(dev_priv
, engine_mask
);
1698 for_each_engine_masked(engine
, dev_priv
, engine_mask
, tmp
)
1699 gen8_reset_engine_cancel(engine
);
1704 typedef int (*reset_func
)(struct drm_i915_private
*, unsigned engine_mask
);
1706 static reset_func
intel_get_gpu_reset(struct drm_i915_private
*dev_priv
)
1708 if (!i915_modparams
.reset
)
1711 if (INTEL_INFO(dev_priv
)->gen
>= 8)
1712 return gen8_reset_engines
;
1713 else if (INTEL_INFO(dev_priv
)->gen
>= 6)
1714 return gen6_reset_engines
;
1715 else if (IS_GEN5(dev_priv
))
1716 return ironlake_do_reset
;
1717 else if (IS_G4X(dev_priv
))
1718 return g4x_do_reset
;
1719 else if (IS_G33(dev_priv
) || IS_PINEVIEW(dev_priv
))
1720 return g33_do_reset
;
1721 else if (INTEL_INFO(dev_priv
)->gen
>= 3)
1722 return i915_do_reset
;
1727 int intel_gpu_reset(struct drm_i915_private
*dev_priv
, unsigned engine_mask
)
1735 reset
= intel_get_gpu_reset(dev_priv
);
1739 /* If the power well sleeps during the reset, the reset
1740 * request may be dropped and never completes (causing -EIO).
1742 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1743 for (retry
= 0; retry
< 3; retry
++) {
1745 /* We stop engines, otherwise we might get failed reset and a
1746 * dead gpu (on elk). Also as modern gpu as kbl can suffer
1747 * from system hang if batchbuffer is progressing when
1748 * the reset is issued, regardless of READY_TO_RESET ack.
1749 * Thus assume it is best to stop engines on all gens
1750 * where we have a gpu reset.
1752 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
1754 * FIXME: Wa for more modern gens needs to be validated
1756 i915_stop_engines(dev_priv
, engine_mask
);
1758 ret
= reset(dev_priv
, engine_mask
);
1759 if (ret
!= -ETIMEDOUT
)
1764 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1769 bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
)
1771 return intel_get_gpu_reset(dev_priv
) != NULL
;
1775 * When GuC submission is enabled, GuC manages ELSP and can initiate the
1776 * engine reset too. For now, fall back to full GPU reset if it is enabled.
1778 bool intel_has_reset_engine(struct drm_i915_private
*dev_priv
)
1780 return (dev_priv
->info
.has_reset_engine
&&
1781 !dev_priv
->guc
.execbuf_client
&&
1782 i915_modparams
.reset
>= 2);
1785 int intel_guc_reset(struct drm_i915_private
*dev_priv
)
1789 if (!HAS_GUC(dev_priv
))
1792 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1793 ret
= gen6_hw_domain_reset(dev_priv
, GEN9_GRDOM_GUC
);
1794 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1799 bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
)
1801 return check_for_unclaimed_mmio(dev_priv
);
1805 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
)
1807 if (unlikely(i915_modparams
.mmio_debug
||
1808 dev_priv
->uncore
.unclaimed_mmio_check
<= 0))
1811 if (unlikely(intel_uncore_unclaimed_mmio(dev_priv
))) {
1812 DRM_DEBUG("Unclaimed register detected, "
1813 "enabling oneshot unclaimed register reporting. "
1814 "Please use i915.mmio_debug=N for more information.\n");
1815 i915_modparams
.mmio_debug
++;
1816 dev_priv
->uncore
.unclaimed_mmio_check
--;
1823 static enum forcewake_domains
1824 intel_uncore_forcewake_for_read(struct drm_i915_private
*dev_priv
,
1827 u32 offset
= i915_mmio_reg_offset(reg
);
1828 enum forcewake_domains fw_domains
;
1830 if (HAS_FWTABLE(dev_priv
)) {
1831 fw_domains
= __fwtable_reg_read_fw_domains(offset
);
1832 } else if (INTEL_GEN(dev_priv
) >= 6) {
1833 fw_domains
= __gen6_reg_read_fw_domains(offset
);
1835 WARN_ON(!IS_GEN(dev_priv
, 2, 5));
1839 WARN_ON(fw_domains
& ~dev_priv
->uncore
.fw_domains
);
1844 static enum forcewake_domains
1845 intel_uncore_forcewake_for_write(struct drm_i915_private
*dev_priv
,
1848 u32 offset
= i915_mmio_reg_offset(reg
);
1849 enum forcewake_domains fw_domains
;
1851 if (HAS_FWTABLE(dev_priv
) && !IS_VALLEYVIEW(dev_priv
)) {
1852 fw_domains
= __fwtable_reg_write_fw_domains(offset
);
1853 } else if (IS_GEN8(dev_priv
)) {
1854 fw_domains
= __gen8_reg_write_fw_domains(offset
);
1855 } else if (IS_GEN(dev_priv
, 6, 7)) {
1856 fw_domains
= FORCEWAKE_RENDER
;
1858 WARN_ON(!IS_GEN(dev_priv
, 2, 5));
1862 WARN_ON(fw_domains
& ~dev_priv
->uncore
.fw_domains
);
1868 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access
1870 * @dev_priv: pointer to struct drm_i915_private
1871 * @reg: register in question
1872 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE
1874 * Returns a set of forcewake domains required to be taken with for example
1875 * intel_uncore_forcewake_get for the specified register to be accessible in the
1876 * specified mode (read, write or read/write) with raw mmio accessors.
1878 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the
1879 * callers to do FIFO management on their own or risk losing writes.
1881 enum forcewake_domains
1882 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
1883 i915_reg_t reg
, unsigned int op
)
1885 enum forcewake_domains fw_domains
= 0;
1889 if (intel_vgpu_active(dev_priv
))
1892 if (op
& FW_REG_READ
)
1893 fw_domains
= intel_uncore_forcewake_for_read(dev_priv
, reg
);
1895 if (op
& FW_REG_WRITE
)
1896 fw_domains
|= intel_uncore_forcewake_for_write(dev_priv
, reg
);
1901 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1902 #include "selftests/mock_uncore.c"
1903 #include "selftests/intel_uncore.c"