2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <linux/pm_runtime.h>
30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32((dev_priv__), (reg__))
34 static const char * const forcewake_domain_names
[] = {
41 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
)
43 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names
) != FW_DOMAIN_ID_COUNT
);
45 if (id
>= 0 && id
< FW_DOMAIN_ID_COUNT
)
46 return forcewake_domain_names
[id
];
54 assert_device_not_suspended(struct drm_i915_private
*dev_priv
)
56 WARN_ONCE(HAS_RUNTIME_PM(dev_priv
->dev
) && dev_priv
->pm
.suspended
,
57 "Device suspended\n");
61 fw_domain_reset(const struct intel_uncore_forcewake_domain
*d
)
63 WARN_ON(!i915_mmio_reg_valid(d
->reg_set
));
64 __raw_i915_write32(d
->i915
, d
->reg_set
, d
->val_reset
);
68 fw_domain_arm_timer(struct intel_uncore_forcewake_domain
*d
)
70 mod_timer_pinned(&d
->timer
, jiffies
+ 1);
74 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain
*d
)
76 if (wait_for_atomic((__raw_i915_read32(d
->i915
, d
->reg_ack
) &
77 FORCEWAKE_KERNEL
) == 0,
78 FORCEWAKE_ACK_TIMEOUT_MS
))
79 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
80 intel_uncore_forcewake_domain_to_str(d
->id
));
84 fw_domain_get(const struct intel_uncore_forcewake_domain
*d
)
86 __raw_i915_write32(d
->i915
, d
->reg_set
, d
->val_set
);
90 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain
*d
)
92 if (wait_for_atomic((__raw_i915_read32(d
->i915
, d
->reg_ack
) &
94 FORCEWAKE_ACK_TIMEOUT_MS
))
95 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
96 intel_uncore_forcewake_domain_to_str(d
->id
));
100 fw_domain_put(const struct intel_uncore_forcewake_domain
*d
)
102 __raw_i915_write32(d
->i915
, d
->reg_set
, d
->val_clear
);
106 fw_domain_posting_read(const struct intel_uncore_forcewake_domain
*d
)
108 /* something from same cacheline, but not from the set register */
109 if (i915_mmio_reg_valid(d
->reg_post
))
110 __raw_posting_read(d
->i915
, d
->reg_post
);
114 fw_domains_get(struct drm_i915_private
*dev_priv
, enum forcewake_domains fw_domains
)
116 struct intel_uncore_forcewake_domain
*d
;
117 enum forcewake_domain_id id
;
119 for_each_fw_domain_mask(d
, fw_domains
, dev_priv
, id
) {
120 fw_domain_wait_ack_clear(d
);
122 fw_domain_wait_ack(d
);
127 fw_domains_put(struct drm_i915_private
*dev_priv
, enum forcewake_domains fw_domains
)
129 struct intel_uncore_forcewake_domain
*d
;
130 enum forcewake_domain_id id
;
132 for_each_fw_domain_mask(d
, fw_domains
, dev_priv
, id
) {
134 fw_domain_posting_read(d
);
139 fw_domains_posting_read(struct drm_i915_private
*dev_priv
)
141 struct intel_uncore_forcewake_domain
*d
;
142 enum forcewake_domain_id id
;
144 /* No need to do for all, just do for first found */
145 for_each_fw_domain(d
, dev_priv
, id
) {
146 fw_domain_posting_read(d
);
152 fw_domains_reset(struct drm_i915_private
*dev_priv
, enum forcewake_domains fw_domains
)
154 struct intel_uncore_forcewake_domain
*d
;
155 enum forcewake_domain_id id
;
157 if (dev_priv
->uncore
.fw_domains
== 0)
160 for_each_fw_domain_mask(d
, fw_domains
, dev_priv
, id
)
163 fw_domains_posting_read(dev_priv
);
166 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private
*dev_priv
)
168 /* w/a for a sporadic read returning 0 by waiting for the GT
171 if (wait_for_atomic_us((__raw_i915_read32(dev_priv
, GEN6_GT_THREAD_STATUS_REG
) &
172 GEN6_GT_THREAD_STATUS_CORE_MASK
) == 0, 500))
173 DRM_ERROR("GT thread status wait timed out\n");
176 static void fw_domains_get_with_thread_status(struct drm_i915_private
*dev_priv
,
177 enum forcewake_domains fw_domains
)
179 fw_domains_get(dev_priv
, fw_domains
);
181 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
182 __gen6_gt_wait_for_thread_c0(dev_priv
);
185 static void gen6_gt_check_fifodbg(struct drm_i915_private
*dev_priv
)
189 gtfifodbg
= __raw_i915_read32(dev_priv
, GTFIFODBG
);
190 if (WARN(gtfifodbg
, "GT wake FIFO error 0x%x\n", gtfifodbg
))
191 __raw_i915_write32(dev_priv
, GTFIFODBG
, gtfifodbg
);
194 static void fw_domains_put_with_fifo(struct drm_i915_private
*dev_priv
,
195 enum forcewake_domains fw_domains
)
197 fw_domains_put(dev_priv
, fw_domains
);
198 gen6_gt_check_fifodbg(dev_priv
);
201 static inline u32
fifo_free_entries(struct drm_i915_private
*dev_priv
)
203 u32 count
= __raw_i915_read32(dev_priv
, GTFIFOCTL
);
205 return count
& GT_FIFO_FREE_ENTRIES_MASK
;
208 static int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
212 /* On VLV, FIFO will be shared by both SW and HW.
213 * So, we need to read the FREE_ENTRIES everytime */
214 if (IS_VALLEYVIEW(dev_priv
->dev
))
215 dev_priv
->uncore
.fifo_count
= fifo_free_entries(dev_priv
);
217 if (dev_priv
->uncore
.fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
219 u32 fifo
= fifo_free_entries(dev_priv
);
221 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
223 fifo
= fifo_free_entries(dev_priv
);
225 if (WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
))
227 dev_priv
->uncore
.fifo_count
= fifo
;
229 dev_priv
->uncore
.fifo_count
--;
234 static void intel_uncore_fw_release_timer(unsigned long arg
)
236 struct intel_uncore_forcewake_domain
*domain
= (void *)arg
;
237 unsigned long irqflags
;
239 assert_device_not_suspended(domain
->i915
);
241 spin_lock_irqsave(&domain
->i915
->uncore
.lock
, irqflags
);
242 if (WARN_ON(domain
->wake_count
== 0))
243 domain
->wake_count
++;
245 if (--domain
->wake_count
== 0)
246 domain
->i915
->uncore
.funcs
.force_wake_put(domain
->i915
,
249 spin_unlock_irqrestore(&domain
->i915
->uncore
.lock
, irqflags
);
252 void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
)
254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
255 unsigned long irqflags
;
256 struct intel_uncore_forcewake_domain
*domain
;
257 int retry_count
= 100;
258 enum forcewake_domain_id id
;
259 enum forcewake_domains fw
= 0, active_domains
;
261 /* Hold uncore.lock across reset to prevent any register access
262 * with forcewake not set correctly. Wait until all pending
263 * timers are run before holding.
268 for_each_fw_domain(domain
, dev_priv
, id
) {
269 if (del_timer_sync(&domain
->timer
) == 0)
272 intel_uncore_fw_release_timer((unsigned long)domain
);
275 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
277 for_each_fw_domain(domain
, dev_priv
, id
) {
278 if (timer_pending(&domain
->timer
))
279 active_domains
|= (1 << id
);
282 if (active_domains
== 0)
285 if (--retry_count
== 0) {
286 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
290 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
294 WARN_ON(active_domains
);
296 for_each_fw_domain(domain
, dev_priv
, id
)
297 if (domain
->wake_count
)
301 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, fw
);
303 fw_domains_reset(dev_priv
, FORCEWAKE_ALL
);
305 if (restore
) { /* If reset with a user forcewake, try to restore */
307 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw
);
309 if (IS_GEN6(dev
) || IS_GEN7(dev
))
310 dev_priv
->uncore
.fifo_count
=
311 fifo_free_entries(dev_priv
);
315 assert_forcewakes_inactive(dev_priv
);
317 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
320 static void intel_uncore_ellc_detect(struct drm_device
*dev
)
322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
324 if ((IS_HASWELL(dev
) || IS_BROADWELL(dev
) ||
325 INTEL_INFO(dev
)->gen
>= 9) &&
326 (__raw_i915_read32(dev_priv
, HSW_EDRAM_PRESENT
) & EDRAM_ENABLED
)) {
327 /* The docs do not explain exactly how the calculation can be
328 * made. It is somewhat guessable, but for now, it's always
330 * NB: We can't write IDICR yet because we do not have gt funcs
332 dev_priv
->ellc_size
= 128;
333 DRM_INFO("Found %zuMB of eLLC\n", dev_priv
->ellc_size
);
337 static void __intel_uncore_early_sanitize(struct drm_device
*dev
,
338 bool restore_forcewake
)
340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
342 if (HAS_FPGA_DBG_UNCLAIMED(dev
))
343 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
345 /* clear out old GT FIFO errors */
346 if (IS_GEN6(dev
) || IS_GEN7(dev
))
347 __raw_i915_write32(dev_priv
, GTFIFODBG
,
348 __raw_i915_read32(dev_priv
, GTFIFODBG
));
350 /* WaDisableShadowRegForCpd:chv */
351 if (IS_CHERRYVIEW(dev
)) {
352 __raw_i915_write32(dev_priv
, GTFIFOCTL
,
353 __raw_i915_read32(dev_priv
, GTFIFOCTL
) |
354 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL
|
355 GT_FIFO_CTL_RC6_POLICY_STALL
);
358 intel_uncore_forcewake_reset(dev
, restore_forcewake
);
361 void intel_uncore_early_sanitize(struct drm_device
*dev
, bool restore_forcewake
)
363 __intel_uncore_early_sanitize(dev
, restore_forcewake
);
364 i915_check_and_clear_faults(dev
);
367 void intel_uncore_sanitize(struct drm_device
*dev
)
369 /* BIOS often leaves RC6 enabled, but disable it for hw init */
370 intel_disable_gt_powersave(dev
);
373 static void __intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
374 enum forcewake_domains fw_domains
)
376 struct intel_uncore_forcewake_domain
*domain
;
377 enum forcewake_domain_id id
;
379 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
382 fw_domains
&= dev_priv
->uncore
.fw_domains
;
384 for_each_fw_domain_mask(domain
, fw_domains
, dev_priv
, id
) {
385 if (domain
->wake_count
++)
386 fw_domains
&= ~(1 << id
);
390 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw_domains
);
394 * intel_uncore_forcewake_get - grab forcewake domain references
395 * @dev_priv: i915 device instance
396 * @fw_domains: forcewake domains to get reference on
398 * This function can be used get GT's forcewake domain references.
399 * Normal register access will handle the forcewake domains automatically.
400 * However if some sequence requires the GT to not power down a particular
401 * forcewake domains this function should be called at the beginning of the
402 * sequence. And subsequently the reference should be dropped by symmetric
403 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
404 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
406 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
407 enum forcewake_domains fw_domains
)
409 unsigned long irqflags
;
411 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
414 WARN_ON(dev_priv
->pm
.suspended
);
416 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
417 __intel_uncore_forcewake_get(dev_priv
, fw_domains
);
418 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
422 * intel_uncore_forcewake_get__locked - grab forcewake domain references
423 * @dev_priv: i915 device instance
424 * @fw_domains: forcewake domains to get reference on
426 * See intel_uncore_forcewake_get(). This variant places the onus
427 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
429 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
430 enum forcewake_domains fw_domains
)
432 assert_spin_locked(&dev_priv
->uncore
.lock
);
434 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
437 __intel_uncore_forcewake_get(dev_priv
, fw_domains
);
440 static void __intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
441 enum forcewake_domains fw_domains
)
443 struct intel_uncore_forcewake_domain
*domain
;
444 enum forcewake_domain_id id
;
446 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
449 fw_domains
&= dev_priv
->uncore
.fw_domains
;
451 for_each_fw_domain_mask(domain
, fw_domains
, dev_priv
, id
) {
452 if (WARN_ON(domain
->wake_count
== 0))
455 if (--domain
->wake_count
)
458 domain
->wake_count
++;
459 fw_domain_arm_timer(domain
);
464 * intel_uncore_forcewake_put - release a forcewake domain reference
465 * @dev_priv: i915 device instance
466 * @fw_domains: forcewake domains to put references
468 * This function drops the device-level forcewakes for specified
469 * domains obtained by intel_uncore_forcewake_get().
471 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
472 enum forcewake_domains fw_domains
)
474 unsigned long irqflags
;
476 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
479 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
480 __intel_uncore_forcewake_put(dev_priv
, fw_domains
);
481 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
485 * intel_uncore_forcewake_put__locked - grab forcewake domain references
486 * @dev_priv: i915 device instance
487 * @fw_domains: forcewake domains to get reference on
489 * See intel_uncore_forcewake_put(). This variant places the onus
490 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
492 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
493 enum forcewake_domains fw_domains
)
495 assert_spin_locked(&dev_priv
->uncore
.lock
);
497 if (!dev_priv
->uncore
.funcs
.force_wake_put
)
500 __intel_uncore_forcewake_put(dev_priv
, fw_domains
);
503 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
)
505 struct intel_uncore_forcewake_domain
*domain
;
506 enum forcewake_domain_id id
;
508 if (!dev_priv
->uncore
.funcs
.force_wake_get
)
511 for_each_fw_domain(domain
, dev_priv
, id
)
512 WARN_ON(domain
->wake_count
);
515 /* We give fast paths for the really cool registers */
516 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
518 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
520 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
521 (REG_RANGE((reg), 0x2000, 0x4000) || \
522 REG_RANGE((reg), 0x5000, 0x8000) || \
523 REG_RANGE((reg), 0xB000, 0x12000) || \
524 REG_RANGE((reg), 0x2E000, 0x30000))
526 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
527 (REG_RANGE((reg), 0x12000, 0x14000) || \
528 REG_RANGE((reg), 0x22000, 0x24000) || \
529 REG_RANGE((reg), 0x30000, 0x40000))
531 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
532 (REG_RANGE((reg), 0x2000, 0x4000) || \
533 REG_RANGE((reg), 0x5200, 0x8000) || \
534 REG_RANGE((reg), 0x8300, 0x8500) || \
535 REG_RANGE((reg), 0xB000, 0xB480) || \
536 REG_RANGE((reg), 0xE000, 0xE800))
538 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
539 (REG_RANGE((reg), 0x8800, 0x8900) || \
540 REG_RANGE((reg), 0xD000, 0xD800) || \
541 REG_RANGE((reg), 0x12000, 0x14000) || \
542 REG_RANGE((reg), 0x1A000, 0x1C000) || \
543 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
544 REG_RANGE((reg), 0x30000, 0x38000))
546 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
547 (REG_RANGE((reg), 0x4000, 0x5000) || \
548 REG_RANGE((reg), 0x8000, 0x8300) || \
549 REG_RANGE((reg), 0x8500, 0x8600) || \
550 REG_RANGE((reg), 0x9000, 0xB000) || \
551 REG_RANGE((reg), 0xF000, 0x10000))
553 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
554 REG_RANGE((reg), 0xB00, 0x2000)
556 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
557 (REG_RANGE((reg), 0x2000, 0x2700) || \
558 REG_RANGE((reg), 0x3000, 0x4000) || \
559 REG_RANGE((reg), 0x5200, 0x8000) || \
560 REG_RANGE((reg), 0x8140, 0x8160) || \
561 REG_RANGE((reg), 0x8300, 0x8500) || \
562 REG_RANGE((reg), 0x8C00, 0x8D00) || \
563 REG_RANGE((reg), 0xB000, 0xB480) || \
564 REG_RANGE((reg), 0xE000, 0xE900) || \
565 REG_RANGE((reg), 0x24400, 0x24800))
567 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
568 (REG_RANGE((reg), 0x8130, 0x8140) || \
569 REG_RANGE((reg), 0x8800, 0x8A00) || \
570 REG_RANGE((reg), 0xD000, 0xD800) || \
571 REG_RANGE((reg), 0x12000, 0x14000) || \
572 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
573 REG_RANGE((reg), 0x30000, 0x40000))
575 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
576 REG_RANGE((reg), 0x9400, 0x9800)
578 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
579 ((reg) < 0x40000 && \
580 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
581 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
582 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
583 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
586 ilk_dummy_write(struct drm_i915_private
*dev_priv
)
588 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
589 * the chip from rc6 before touching it for real. MI_MODE is masked,
590 * hence harmless to write 0 into. */
591 __raw_i915_write32(dev_priv
, MI_MODE
, 0);
595 hsw_unclaimed_reg_debug(struct drm_i915_private
*dev_priv
,
596 i915_reg_t reg
, bool read
, bool before
)
598 const char *op
= read
? "reading" : "writing to";
599 const char *when
= before
? "before" : "after";
601 if (!i915
.mmio_debug
)
604 if (__raw_i915_read32(dev_priv
, FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
) {
605 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
606 when
, op
, i915_mmio_reg_offset(reg
));
607 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
608 i915
.mmio_debug
--; /* Only report the first N failures */
613 hsw_unclaimed_reg_detect(struct drm_i915_private
*dev_priv
)
615 static bool mmio_debug_once
= true;
617 if (i915
.mmio_debug
|| !mmio_debug_once
)
620 if (__raw_i915_read32(dev_priv
, FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
) {
621 DRM_DEBUG("Unclaimed register detected, "
622 "enabling oneshot unclaimed register reporting. "
623 "Please use i915.mmio_debug=N for more information.\n");
624 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);
625 i915
.mmio_debug
= mmio_debug_once
--;
629 #define GEN2_READ_HEADER(x) \
631 assert_device_not_suspended(dev_priv);
633 #define GEN2_READ_FOOTER \
634 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
637 #define __gen2_read(x) \
639 gen2_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
640 GEN2_READ_HEADER(x); \
641 val = __raw_i915_read##x(dev_priv, reg); \
645 #define __gen5_read(x) \
647 gen5_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
648 GEN2_READ_HEADER(x); \
649 ilk_dummy_write(dev_priv); \
650 val = __raw_i915_read##x(dev_priv, reg); \
666 #undef GEN2_READ_FOOTER
667 #undef GEN2_READ_HEADER
669 #define GEN6_READ_HEADER(x) \
670 u32 offset = i915_mmio_reg_offset(reg); \
671 unsigned long irqflags; \
673 assert_device_not_suspended(dev_priv); \
674 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
676 #define GEN6_READ_FOOTER \
677 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
678 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
681 static inline void __force_wake_get(struct drm_i915_private
*dev_priv
,
682 enum forcewake_domains fw_domains
)
684 struct intel_uncore_forcewake_domain
*domain
;
685 enum forcewake_domain_id id
;
687 if (WARN_ON(!fw_domains
))
690 /* Ideally GCC would be constant-fold and eliminate this loop */
691 for_each_fw_domain_mask(domain
, fw_domains
, dev_priv
, id
) {
692 if (domain
->wake_count
) {
693 fw_domains
&= ~(1 << id
);
697 domain
->wake_count
++;
698 fw_domain_arm_timer(domain
);
702 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, fw_domains
);
705 #define __gen6_read(x) \
707 gen6_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
708 GEN6_READ_HEADER(x); \
709 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
710 if (NEEDS_FORCE_WAKE(offset)) \
711 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
712 val = __raw_i915_read##x(dev_priv, reg); \
713 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
717 #define __vlv_read(x) \
719 vlv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
720 enum forcewake_domains fw_engine = 0; \
721 GEN6_READ_HEADER(x); \
722 if (!NEEDS_FORCE_WAKE(offset)) \
724 else if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(offset)) \
725 fw_engine = FORCEWAKE_RENDER; \
726 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(offset)) \
727 fw_engine = FORCEWAKE_MEDIA; \
729 __force_wake_get(dev_priv, fw_engine); \
730 val = __raw_i915_read##x(dev_priv, reg); \
734 #define __chv_read(x) \
736 chv_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
737 enum forcewake_domains fw_engine = 0; \
738 GEN6_READ_HEADER(x); \
739 if (!NEEDS_FORCE_WAKE(offset)) \
741 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
742 fw_engine = FORCEWAKE_RENDER; \
743 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
744 fw_engine = FORCEWAKE_MEDIA; \
745 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
746 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
748 __force_wake_get(dev_priv, fw_engine); \
749 val = __raw_i915_read##x(dev_priv, reg); \
753 #define SKL_NEEDS_FORCE_WAKE(reg) \
754 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
756 #define __gen9_read(x) \
758 gen9_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
759 enum forcewake_domains fw_engine; \
760 GEN6_READ_HEADER(x); \
761 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
762 if (!SKL_NEEDS_FORCE_WAKE(offset)) \
764 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
765 fw_engine = FORCEWAKE_RENDER; \
766 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
767 fw_engine = FORCEWAKE_MEDIA; \
768 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
769 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
771 fw_engine = FORCEWAKE_BLITTER; \
773 __force_wake_get(dev_priv, fw_engine); \
774 val = __raw_i915_read##x(dev_priv, reg); \
775 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
800 #undef GEN6_READ_FOOTER
801 #undef GEN6_READ_HEADER
803 #define VGPU_READ_HEADER(x) \
804 unsigned long irqflags; \
806 assert_device_not_suspended(dev_priv); \
807 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
809 #define VGPU_READ_FOOTER \
810 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
811 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
814 #define __vgpu_read(x) \
816 vgpu_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) { \
817 VGPU_READ_HEADER(x); \
818 val = __raw_i915_read##x(dev_priv, reg); \
828 #undef VGPU_READ_FOOTER
829 #undef VGPU_READ_HEADER
831 #define GEN2_WRITE_HEADER \
832 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
833 assert_device_not_suspended(dev_priv); \
835 #define GEN2_WRITE_FOOTER
837 #define __gen2_write(x) \
839 gen2_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
841 __raw_i915_write##x(dev_priv, reg, val); \
845 #define __gen5_write(x) \
847 gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
849 ilk_dummy_write(dev_priv); \
850 __raw_i915_write##x(dev_priv, reg, val); \
866 #undef GEN2_WRITE_FOOTER
867 #undef GEN2_WRITE_HEADER
869 #define GEN6_WRITE_HEADER \
870 u32 offset = i915_mmio_reg_offset(reg); \
871 unsigned long irqflags; \
872 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
873 assert_device_not_suspended(dev_priv); \
874 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
876 #define GEN6_WRITE_FOOTER \
877 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
879 #define __gen6_write(x) \
881 gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
882 u32 __fifo_ret = 0; \
884 if (NEEDS_FORCE_WAKE(offset)) { \
885 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
887 __raw_i915_write##x(dev_priv, reg, val); \
888 if (unlikely(__fifo_ret)) { \
889 gen6_gt_check_fifodbg(dev_priv); \
894 #define __hsw_write(x) \
896 hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
897 u32 __fifo_ret = 0; \
899 if (NEEDS_FORCE_WAKE(offset)) { \
900 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
902 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
903 __raw_i915_write##x(dev_priv, reg, val); \
904 if (unlikely(__fifo_ret)) { \
905 gen6_gt_check_fifodbg(dev_priv); \
907 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
908 hsw_unclaimed_reg_detect(dev_priv); \
912 static const i915_reg_t gen8_shadowed_regs
[] = {
916 RING_TAIL(RENDER_RING_BASE
),
917 RING_TAIL(GEN6_BSD_RING_BASE
),
918 RING_TAIL(VEBOX_RING_BASE
),
919 RING_TAIL(BLT_RING_BASE
),
920 /* TODO: Other registers are not yet used */
923 static bool is_gen8_shadowed(struct drm_i915_private
*dev_priv
,
927 for (i
= 0; i
< ARRAY_SIZE(gen8_shadowed_regs
); i
++)
928 if (i915_mmio_reg_equal(reg
, gen8_shadowed_regs
[i
]))
934 #define __gen8_write(x) \
936 gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
938 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
939 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(dev_priv, reg)) \
940 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
941 __raw_i915_write##x(dev_priv, reg, val); \
942 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
943 hsw_unclaimed_reg_detect(dev_priv); \
947 #define __chv_write(x) \
949 chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
950 enum forcewake_domains fw_engine = 0; \
952 if (!NEEDS_FORCE_WAKE(offset) || \
953 is_gen8_shadowed(dev_priv, reg)) \
955 else if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(offset)) \
956 fw_engine = FORCEWAKE_RENDER; \
957 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(offset)) \
958 fw_engine = FORCEWAKE_MEDIA; \
959 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(offset)) \
960 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
962 __force_wake_get(dev_priv, fw_engine); \
963 __raw_i915_write##x(dev_priv, reg, val); \
967 static const i915_reg_t gen9_shadowed_regs
[] = {
968 RING_TAIL(RENDER_RING_BASE
),
969 RING_TAIL(GEN6_BSD_RING_BASE
),
970 RING_TAIL(VEBOX_RING_BASE
),
971 RING_TAIL(BLT_RING_BASE
),
972 FORCEWAKE_BLITTER_GEN9
,
973 FORCEWAKE_RENDER_GEN9
,
974 FORCEWAKE_MEDIA_GEN9
,
977 /* TODO: Other registers are not yet used */
980 static bool is_gen9_shadowed(struct drm_i915_private
*dev_priv
,
984 for (i
= 0; i
< ARRAY_SIZE(gen9_shadowed_regs
); i
++)
985 if (i915_mmio_reg_equal(reg
, gen9_shadowed_regs
[i
]))
991 #define __gen9_write(x) \
993 gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
995 enum forcewake_domains fw_engine; \
997 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
998 if (!SKL_NEEDS_FORCE_WAKE(offset) || \
999 is_gen9_shadowed(dev_priv, reg)) \
1001 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(offset)) \
1002 fw_engine = FORCEWAKE_RENDER; \
1003 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(offset)) \
1004 fw_engine = FORCEWAKE_MEDIA; \
1005 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(offset)) \
1006 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
1008 fw_engine = FORCEWAKE_BLITTER; \
1010 __force_wake_get(dev_priv, fw_engine); \
1011 __raw_i915_write##x(dev_priv, reg, val); \
1012 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
1013 hsw_unclaimed_reg_detect(dev_priv); \
1014 GEN6_WRITE_FOOTER; \
1043 #undef GEN6_WRITE_FOOTER
1044 #undef GEN6_WRITE_HEADER
1046 #define VGPU_WRITE_HEADER \
1047 unsigned long irqflags; \
1048 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
1049 assert_device_not_suspended(dev_priv); \
1050 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
1052 #define VGPU_WRITE_FOOTER \
1053 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
1055 #define __vgpu_write(x) \
1056 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
1057 i915_reg_t reg, u##x val, bool trace) { \
1058 VGPU_WRITE_HEADER; \
1059 __raw_i915_write##x(dev_priv, reg, val); \
1060 VGPU_WRITE_FOOTER; \
1069 #undef VGPU_WRITE_FOOTER
1070 #undef VGPU_WRITE_HEADER
1072 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1074 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1075 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1076 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1077 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1080 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1082 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1083 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1084 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1085 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1089 static void fw_domain_init(struct drm_i915_private
*dev_priv
,
1090 enum forcewake_domain_id domain_id
,
1094 struct intel_uncore_forcewake_domain
*d
;
1096 if (WARN_ON(domain_id
>= FW_DOMAIN_ID_COUNT
))
1099 d
= &dev_priv
->uncore
.fw_domain
[domain_id
];
1101 WARN_ON(d
->wake_count
);
1104 d
->reg_set
= reg_set
;
1105 d
->reg_ack
= reg_ack
;
1107 if (IS_GEN6(dev_priv
)) {
1109 d
->val_set
= FORCEWAKE_KERNEL
;
1112 /* WaRsClearFWBitsAtReset:bdw,skl */
1113 d
->val_reset
= _MASKED_BIT_DISABLE(0xffff);
1114 d
->val_set
= _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL
);
1115 d
->val_clear
= _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL
);
1118 if (IS_VALLEYVIEW(dev_priv
))
1119 d
->reg_post
= FORCEWAKE_ACK_VLV
;
1120 else if (IS_GEN6(dev_priv
) || IS_GEN7(dev_priv
) || IS_GEN8(dev_priv
))
1121 d
->reg_post
= ECOBUS
;
1126 setup_timer(&d
->timer
, intel_uncore_fw_release_timer
, (unsigned long)d
);
1128 dev_priv
->uncore
.fw_domains
|= (1 << domain_id
);
1133 static void intel_uncore_fw_domains_init(struct drm_device
*dev
)
1135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1137 if (INTEL_INFO(dev_priv
->dev
)->gen
<= 5)
1141 dev_priv
->uncore
.funcs
.force_wake_get
= fw_domains_get
;
1142 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1143 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1144 FORCEWAKE_RENDER_GEN9
,
1145 FORCEWAKE_ACK_RENDER_GEN9
);
1146 fw_domain_init(dev_priv
, FW_DOMAIN_ID_BLITTER
,
1147 FORCEWAKE_BLITTER_GEN9
,
1148 FORCEWAKE_ACK_BLITTER_GEN9
);
1149 fw_domain_init(dev_priv
, FW_DOMAIN_ID_MEDIA
,
1150 FORCEWAKE_MEDIA_GEN9
, FORCEWAKE_ACK_MEDIA_GEN9
);
1151 } else if (IS_VALLEYVIEW(dev
)) {
1152 dev_priv
->uncore
.funcs
.force_wake_get
= fw_domains_get
;
1153 if (!IS_CHERRYVIEW(dev
))
1154 dev_priv
->uncore
.funcs
.force_wake_put
=
1155 fw_domains_put_with_fifo
;
1157 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1158 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1159 FORCEWAKE_VLV
, FORCEWAKE_ACK_VLV
);
1160 fw_domain_init(dev_priv
, FW_DOMAIN_ID_MEDIA
,
1161 FORCEWAKE_MEDIA_VLV
, FORCEWAKE_ACK_MEDIA_VLV
);
1162 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
1163 dev_priv
->uncore
.funcs
.force_wake_get
=
1164 fw_domains_get_with_thread_status
;
1165 dev_priv
->uncore
.funcs
.force_wake_put
= fw_domains_put
;
1166 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1167 FORCEWAKE_MT
, FORCEWAKE_ACK_HSW
);
1168 } else if (IS_IVYBRIDGE(dev
)) {
1171 /* IVB configs may use multi-threaded forcewake */
1173 /* A small trick here - if the bios hasn't configured
1174 * MT forcewake, and if the device is in RC6, then
1175 * force_wake_mt_get will not wake the device and the
1176 * ECOBUS read will return zero. Which will be
1177 * (correctly) interpreted by the test below as MT
1178 * forcewake being disabled.
1180 dev_priv
->uncore
.funcs
.force_wake_get
=
1181 fw_domains_get_with_thread_status
;
1182 dev_priv
->uncore
.funcs
.force_wake_put
=
1183 fw_domains_put_with_fifo
;
1185 /* We need to init first for ECOBUS access and then
1186 * determine later if we want to reinit, in case of MT access is
1187 * not working. In this stage we don't know which flavour this
1188 * ivb is, so it is better to reset also the gen6 fw registers
1189 * before the ecobus check.
1192 __raw_i915_write32(dev_priv
, FORCEWAKE
, 0);
1193 __raw_posting_read(dev_priv
, ECOBUS
);
1195 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1196 FORCEWAKE_MT
, FORCEWAKE_MT_ACK
);
1198 mutex_lock(&dev
->struct_mutex
);
1199 fw_domains_get_with_thread_status(dev_priv
, FORCEWAKE_ALL
);
1200 ecobus
= __raw_i915_read32(dev_priv
, ECOBUS
);
1201 fw_domains_put_with_fifo(dev_priv
, FORCEWAKE_ALL
);
1202 mutex_unlock(&dev
->struct_mutex
);
1204 if (!(ecobus
& FORCEWAKE_MT_ENABLE
)) {
1205 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1206 DRM_INFO("when using vblank-synced partial screen updates.\n");
1207 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1208 FORCEWAKE
, FORCEWAKE_ACK
);
1210 } else if (IS_GEN6(dev
)) {
1211 dev_priv
->uncore
.funcs
.force_wake_get
=
1212 fw_domains_get_with_thread_status
;
1213 dev_priv
->uncore
.funcs
.force_wake_put
=
1214 fw_domains_put_with_fifo
;
1215 fw_domain_init(dev_priv
, FW_DOMAIN_ID_RENDER
,
1216 FORCEWAKE
, FORCEWAKE_ACK
);
1219 /* All future platforms are expected to require complex power gating */
1220 WARN_ON(dev_priv
->uncore
.fw_domains
== 0);
1223 void intel_uncore_init(struct drm_device
*dev
)
1225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1227 i915_check_vgpu(dev
);
1229 intel_uncore_ellc_detect(dev
);
1230 intel_uncore_fw_domains_init(dev
);
1231 __intel_uncore_early_sanitize(dev
, false);
1233 switch (INTEL_INFO(dev
)->gen
) {
1236 ASSIGN_WRITE_MMIO_VFUNCS(gen9
);
1237 ASSIGN_READ_MMIO_VFUNCS(gen9
);
1240 if (IS_CHERRYVIEW(dev
)) {
1241 ASSIGN_WRITE_MMIO_VFUNCS(chv
);
1242 ASSIGN_READ_MMIO_VFUNCS(chv
);
1245 ASSIGN_WRITE_MMIO_VFUNCS(gen8
);
1246 ASSIGN_READ_MMIO_VFUNCS(gen6
);
1251 if (IS_HASWELL(dev
)) {
1252 ASSIGN_WRITE_MMIO_VFUNCS(hsw
);
1254 ASSIGN_WRITE_MMIO_VFUNCS(gen6
);
1257 if (IS_VALLEYVIEW(dev
)) {
1258 ASSIGN_READ_MMIO_VFUNCS(vlv
);
1260 ASSIGN_READ_MMIO_VFUNCS(gen6
);
1264 ASSIGN_WRITE_MMIO_VFUNCS(gen5
);
1265 ASSIGN_READ_MMIO_VFUNCS(gen5
);
1270 ASSIGN_WRITE_MMIO_VFUNCS(gen2
);
1271 ASSIGN_READ_MMIO_VFUNCS(gen2
);
1275 if (intel_vgpu_active(dev
)) {
1276 ASSIGN_WRITE_MMIO_VFUNCS(vgpu
);
1277 ASSIGN_READ_MMIO_VFUNCS(vgpu
);
1280 i915_check_and_clear_faults(dev
);
1282 #undef ASSIGN_WRITE_MMIO_VFUNCS
1283 #undef ASSIGN_READ_MMIO_VFUNCS
1285 void intel_uncore_fini(struct drm_device
*dev
)
1287 /* Paranoia: make sure we have disabled everything before we exit. */
1288 intel_uncore_sanitize(dev
);
1289 intel_uncore_forcewake_reset(dev
, false);
1292 #define GEN_RANGE(l, h) GENMASK(h, l)
1294 static const struct register_whitelist
{
1295 i915_reg_t offset_ldw
, offset_udw
;
1297 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1298 uint32_t gen_bitmask
;
1300 { .offset_ldw
= RING_TIMESTAMP(RENDER_RING_BASE
),
1301 .offset_udw
= RING_TIMESTAMP_UDW(RENDER_RING_BASE
),
1302 .size
= 8, .gen_bitmask
= GEN_RANGE(4, 9) },
1305 int i915_reg_read_ioctl(struct drm_device
*dev
,
1306 void *data
, struct drm_file
*file
)
1308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1309 struct drm_i915_reg_read
*reg
= data
;
1310 struct register_whitelist
const *entry
= whitelist
;
1312 i915_reg_t offset_ldw
, offset_udw
;
1315 for (i
= 0; i
< ARRAY_SIZE(whitelist
); i
++, entry
++) {
1316 if (i915_mmio_reg_offset(entry
->offset_ldw
) == (reg
->offset
& -entry
->size
) &&
1317 (1 << INTEL_INFO(dev
)->gen
& entry
->gen_bitmask
))
1321 if (i
== ARRAY_SIZE(whitelist
))
1324 /* We use the low bits to encode extra flags as the register should
1325 * be naturally aligned (and those that are not so aligned merely
1326 * limit the available flags for that register).
1328 offset_ldw
= entry
->offset_ldw
;
1329 offset_udw
= entry
->offset_udw
;
1331 size
|= reg
->offset
^ i915_mmio_reg_offset(offset_ldw
);
1333 intel_runtime_pm_get(dev_priv
);
1337 reg
->val
= I915_READ64_2x32(offset_ldw
, offset_udw
);
1340 reg
->val
= I915_READ64(offset_ldw
);
1343 reg
->val
= I915_READ(offset_ldw
);
1346 reg
->val
= I915_READ16(offset_ldw
);
1349 reg
->val
= I915_READ8(offset_ldw
);
1357 intel_runtime_pm_put(dev_priv
);
1361 int i915_get_reset_stats_ioctl(struct drm_device
*dev
,
1362 void *data
, struct drm_file
*file
)
1364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1365 struct drm_i915_reset_stats
*args
= data
;
1366 struct i915_ctx_hang_stats
*hs
;
1367 struct intel_context
*ctx
;
1370 if (args
->flags
|| args
->pad
)
1373 if (args
->ctx_id
== DEFAULT_CONTEXT_HANDLE
&& !capable(CAP_SYS_ADMIN
))
1376 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1380 ctx
= i915_gem_context_get(file
->driver_priv
, args
->ctx_id
);
1382 mutex_unlock(&dev
->struct_mutex
);
1383 return PTR_ERR(ctx
);
1385 hs
= &ctx
->hang_stats
;
1387 if (capable(CAP_SYS_ADMIN
))
1388 args
->reset_count
= i915_reset_count(&dev_priv
->gpu_error
);
1390 args
->reset_count
= 0;
1392 args
->batch_active
= hs
->batch_active
;
1393 args
->batch_pending
= hs
->batch_pending
;
1395 mutex_unlock(&dev
->struct_mutex
);
1400 static int i915_reset_complete(struct drm_device
*dev
)
1403 pci_read_config_byte(dev
->pdev
, I915_GDRST
, &gdrst
);
1404 return (gdrst
& GRDOM_RESET_STATUS
) == 0;
1407 static int i915_do_reset(struct drm_device
*dev
)
1409 /* assert reset for at least 20 usec */
1410 pci_write_config_byte(dev
->pdev
, I915_GDRST
, GRDOM_RESET_ENABLE
);
1412 pci_write_config_byte(dev
->pdev
, I915_GDRST
, 0);
1414 return wait_for(i915_reset_complete(dev
), 500);
1417 static int g4x_reset_complete(struct drm_device
*dev
)
1420 pci_read_config_byte(dev
->pdev
, I915_GDRST
, &gdrst
);
1421 return (gdrst
& GRDOM_RESET_ENABLE
) == 0;
1424 static int g33_do_reset(struct drm_device
*dev
)
1426 pci_write_config_byte(dev
->pdev
, I915_GDRST
, GRDOM_RESET_ENABLE
);
1427 return wait_for(g4x_reset_complete(dev
), 500);
1430 static int g4x_do_reset(struct drm_device
*dev
)
1432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1435 pci_write_config_byte(dev
->pdev
, I915_GDRST
,
1436 GRDOM_RENDER
| GRDOM_RESET_ENABLE
);
1437 ret
= wait_for(g4x_reset_complete(dev
), 500);
1441 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1442 I915_WRITE(VDECCLK_GATE_D
, I915_READ(VDECCLK_GATE_D
) | VCP_UNIT_CLOCK_GATE_DISABLE
);
1443 POSTING_READ(VDECCLK_GATE_D
);
1445 pci_write_config_byte(dev
->pdev
, I915_GDRST
,
1446 GRDOM_MEDIA
| GRDOM_RESET_ENABLE
);
1447 ret
= wait_for(g4x_reset_complete(dev
), 500);
1451 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1452 I915_WRITE(VDECCLK_GATE_D
, I915_READ(VDECCLK_GATE_D
) & ~VCP_UNIT_CLOCK_GATE_DISABLE
);
1453 POSTING_READ(VDECCLK_GATE_D
);
1455 pci_write_config_byte(dev
->pdev
, I915_GDRST
, 0);
1460 static int ironlake_do_reset(struct drm_device
*dev
)
1462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1465 I915_WRITE(ILK_GDSR
,
1466 ILK_GRDOM_RENDER
| ILK_GRDOM_RESET_ENABLE
);
1467 ret
= wait_for((I915_READ(ILK_GDSR
) &
1468 ILK_GRDOM_RESET_ENABLE
) == 0, 500);
1472 I915_WRITE(ILK_GDSR
,
1473 ILK_GRDOM_MEDIA
| ILK_GRDOM_RESET_ENABLE
);
1474 ret
= wait_for((I915_READ(ILK_GDSR
) &
1475 ILK_GRDOM_RESET_ENABLE
) == 0, 500);
1479 I915_WRITE(ILK_GDSR
, 0);
1484 static int gen6_do_reset(struct drm_device
*dev
)
1486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1489 /* Reset the chip */
1491 /* GEN6_GDRST is not in the gt power well, no need to check
1492 * for fifo space for the write or forcewake the chip for
1495 __raw_i915_write32(dev_priv
, GEN6_GDRST
, GEN6_GRDOM_FULL
);
1497 /* Spin waiting for the device to ack the reset request */
1498 ret
= wait_for((__raw_i915_read32(dev_priv
, GEN6_GDRST
) & GEN6_GRDOM_FULL
) == 0, 500);
1500 intel_uncore_forcewake_reset(dev
, true);
1505 static int wait_for_register(struct drm_i915_private
*dev_priv
,
1509 const unsigned long timeout_ms
)
1511 return wait_for((I915_READ(reg
) & mask
) == value
, timeout_ms
);
1514 static int gen8_do_reset(struct drm_device
*dev
)
1516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1517 struct intel_engine_cs
*engine
;
1520 for_each_ring(engine
, dev_priv
, i
) {
1521 I915_WRITE(RING_RESET_CTL(engine
->mmio_base
),
1522 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET
));
1524 if (wait_for_register(dev_priv
,
1525 RING_RESET_CTL(engine
->mmio_base
),
1526 RESET_CTL_READY_TO_RESET
,
1527 RESET_CTL_READY_TO_RESET
,
1529 DRM_ERROR("%s: reset request timeout\n", engine
->name
);
1534 return gen6_do_reset(dev
);
1537 for_each_ring(engine
, dev_priv
, i
)
1538 I915_WRITE(RING_RESET_CTL(engine
->mmio_base
),
1539 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET
));
1544 static int (*intel_get_gpu_reset(struct drm_device
*dev
))(struct drm_device
*)
1549 if (INTEL_INFO(dev
)->gen
>= 8)
1550 return gen8_do_reset
;
1551 else if (INTEL_INFO(dev
)->gen
>= 6)
1552 return gen6_do_reset
;
1553 else if (IS_GEN5(dev
))
1554 return ironlake_do_reset
;
1555 else if (IS_G4X(dev
))
1556 return g4x_do_reset
;
1557 else if (IS_G33(dev
))
1558 return g33_do_reset
;
1559 else if (INTEL_INFO(dev
)->gen
>= 3)
1560 return i915_do_reset
;
1565 int intel_gpu_reset(struct drm_device
*dev
)
1567 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1568 int (*reset
)(struct drm_device
*);
1571 reset
= intel_get_gpu_reset(dev
);
1575 /* If the power well sleeps during the reset, the reset
1576 * request may be dropped and never completes (causing -EIO).
1578 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1580 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1585 bool intel_has_gpu_reset(struct drm_device
*dev
)
1587 return intel_get_gpu_reset(dev
) != NULL
;
1590 void intel_uncore_check_errors(struct drm_device
*dev
)
1592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1594 if (HAS_FPGA_DBG_UNCLAIMED(dev
) &&
1595 (__raw_i915_read32(dev_priv
, FPGA_DBG
) & FPGA_DBG_RM_NOCLAIM
)) {
1596 DRM_ERROR("Unclaimed register before interrupt\n");
1597 __raw_i915_write32(dev_priv
, FPGA_DBG
, FPGA_DBG_RM_NOCLAIM
);