drivers/gpu/drm/i915/intel_vbt_defs.h

   1 /*
   2  * Copyright © 2006-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 /*
  29  * This information is private to VBT parsing in intel_bios.c.
  30  *
  31  * Please do NOT include anywhere else.
  32  */
  33 #ifndef _INTEL_BIOS_PRIVATE
  34 #error "intel_vbt_defs.h is private to intel_bios.c"
  35 #endif
  36
  37 #ifndef _INTEL_VBT_DEFS_H_
  38 #define _INTEL_VBT_DEFS_H_
  39
  40 #include "intel_bios.h"
  41
  42 /**
  43  * struct vbt_header - VBT Header structure
  44  * @signature:          VBT signature, always starts with "$VBT"
  45  * @version:            Version of this structure
  46  * @header_size:        Size of this structure
  47  * @vbt_size:           Size of VBT (VBT Header, BDB Header and data blocks)
  48  * @vbt_checksum:       Checksum
  49  * @reserved0:          Reserved
  50  * @bdb_offset:         Offset of &struct bdb_header from beginning of VBT
  51  * @aim_offset:         Offsets of add-in data blocks from beginning of VBT
  52  */
  53 struct vbt_header {
  54         u8 signature[20];
  55         u16 version;
  56         u16 header_size;
  57         u16 vbt_size;
  58         u8 vbt_checksum;
  59         u8 reserved0;
  60         u32 bdb_offset;
  61         u32 aim_offset[4];
  62 } __packed;
  63
  64 /**
  65  * struct bdb_header - BDB Header structure
  66  * @signature:          BDB signature "BIOS_DATA_BLOCK"
  67  * @version:            Version of the data block definitions
  68  * @header_size:        Size of this structure
  69  * @bdb_size:           Size of BDB (BDB Header and data blocks)
  70  */
  71 struct bdb_header {
  72         u8 signature[16];
  73         u16 version;
  74         u16 header_size;
  75         u16 bdb_size;
  76 } __packed;
  77
  78 /* strictly speaking, this is a "skip" block, but it has interesting info */
  79 struct vbios_data {
  80         u8 type; /* 0 == desktop, 1 == mobile */
  81         u8 relstage;
  82         u8 chipset;
  83         u8 lvds_present:1;
  84         u8 tv_present:1;
  85         u8 rsvd2:6; /* finish byte */
  86         u8 rsvd3[4];
  87         u8 signon[155];
  88         u8 copyright[61];
  89         u16 code_segment;
  90         u8 dos_boot_mode;
  91         u8 bandwidth_percent;
  92         u8 rsvd4; /* popup memory size */
  93         u8 resize_pci_bios;
  94         u8 rsvd5; /* is crt already on ddc2 */
  95 } __packed;
  96
  97 /*
  98  * There are several types of BIOS data blocks (BDBs), each block has
  99  * an ID and size in the first 3 bytes (ID in first, size in next 2).
 100  * Known types are listed below.
 101  */
 102 #define BDB_GENERAL_FEATURES      1
 103 #define BDB_GENERAL_DEFINITIONS   2
 104 #define BDB_OLD_TOGGLE_LIST       3
 105 #define BDB_MODE_SUPPORT_LIST     4
 106 #define BDB_GENERIC_MODE_TABLE    5
 107 #define BDB_EXT_MMIO_REGS         6
 108 #define BDB_SWF_IO                7
 109 #define BDB_SWF_MMIO              8
 110 #define BDB_PSR                   9
 111 #define BDB_MODE_REMOVAL_TABLE   10
 112 #define BDB_CHILD_DEVICE_TABLE   11
 113 #define BDB_DRIVER_FEATURES      12
 114 #define BDB_DRIVER_PERSISTENCE   13
 115 #define BDB_EXT_TABLE_PTRS       14
 116 #define BDB_DOT_CLOCK_OVERRIDE   15
 117 #define BDB_DISPLAY_SELECT       16
 118 /* 17 rsvd */
 119 #define BDB_DRIVER_ROTATION      18
 120 #define BDB_DISPLAY_REMOVE       19
 121 #define BDB_OEM_CUSTOM           20
 122 #define BDB_EFP_LIST             21 /* workarounds for VGA hsync/vsync */
 123 #define BDB_SDVO_LVDS_OPTIONS    22
 124 #define BDB_SDVO_PANEL_DTDS      23
 125 #define BDB_SDVO_LVDS_PNP_IDS    24
 126 #define BDB_SDVO_LVDS_POWER_SEQ  25
 127 #define BDB_TV_OPTIONS           26
 128 #define BDB_EDP                  27
 129 #define BDB_LVDS_OPTIONS         40
 130 #define BDB_LVDS_LFP_DATA_PTRS   41
 131 #define BDB_LVDS_LFP_DATA        42
 132 #define BDB_LVDS_BACKLIGHT       43
 133 #define BDB_LVDS_POWER           44
 134 #define BDB_MIPI_CONFIG          52
 135 #define BDB_MIPI_SEQUENCE        53
 136 #define BDB_SKIP                254 /* VBIOS private block, ignore */
 137
 138 struct bdb_general_features {
 139         /* bits 1 */
 140         u8 panel_fitting:2;
 141         u8 flexaim:1;
 142         u8 msg_enable:1;
 143         u8 clear_screen:3;
 144         u8 color_flip:1;
 145
 146         /* bits 2 */
 147         u8 download_ext_vbt:1;
 148         u8 enable_ssc:1;
 149         u8 ssc_freq:1;
 150         u8 enable_lfp_on_override:1;
 151         u8 disable_ssc_ddt:1;
 152         u8 rsvd7:1;
 153         u8 display_clock_mode:1;
 154         u8 rsvd8:1; /* finish byte */
 155
 156         /* bits 3 */
 157         u8 disable_smooth_vision:1;
 158         u8 single_dvi:1;
 159         u8 rsvd9:1;
 160         u8 fdi_rx_polarity_inverted:1;
 161         u8 rsvd10:4; /* finish byte */
 162
 163         /* bits 4 */
 164         u8 legacy_monitor_detect;
 165
 166         /* bits 5 */
 167         u8 int_crt_support:1;
 168         u8 int_tv_support:1;
 169         u8 int_efp_support:1;
 170         u8 dp_ssc_enb:1;        /* PCH attached eDP supports SSC */
 171         u8 dp_ssc_freq:1;       /* SSC freq for PCH attached eDP */
 172         u8 rsvd11:3; /* finish byte */
 173 } __packed;
 174
 175 /* pre-915 */
 176 #define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
 177 #define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
 178 #define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
 179 #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
 180
 181 /* Pre 915 */
 182 #define DEVICE_TYPE_NONE        0x00
 183 #define DEVICE_TYPE_CRT         0x01
 184 #define DEVICE_TYPE_TV          0x09
 185 #define DEVICE_TYPE_EFP         0x12
 186 #define DEVICE_TYPE_LFP         0x22
 187 /* On 915+ */
 188 #define DEVICE_TYPE_CRT_DPMS            0x6001
 189 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
 190 #define DEVICE_TYPE_TV_COMPOSITE        0x0209
 191 #define DEVICE_TYPE_TV_MACROVISION      0x0289
 192 #define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
 193 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
 194 #define DEVICE_TYPE_TV_SCART            0x0209
 195 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
 196 #define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
 197 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
 198 #define DEVICE_TYPE_EFP_DVI_I           0x6053
 199 #define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
 200 #define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
 201 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
 202 #define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
 203 #define DEVICE_TYPE_LFP_PANELLINK       0x5012
 204 #define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
 205 #define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
 206 #define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
 207 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
 208
 209 #define DEVICE_CFG_NONE         0x00
 210 #define DEVICE_CFG_12BIT_DVOB   0x01
 211 #define DEVICE_CFG_12BIT_DVOC   0x02
 212 #define DEVICE_CFG_24BIT_DVOBC  0x09
 213 #define DEVICE_CFG_24BIT_DVOCB  0x0a
 214 #define DEVICE_CFG_DUAL_DVOB    0x11
 215 #define DEVICE_CFG_DUAL_DVOC    0x12
 216 #define DEVICE_CFG_DUAL_DVOBC   0x13
 217 #define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
 218 #define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
 219
 220 #define DEVICE_WIRE_NONE        0x00
 221 #define DEVICE_WIRE_DVOB        0x01
 222 #define DEVICE_WIRE_DVOC        0x02
 223 #define DEVICE_WIRE_DVOBC       0x03
 224 #define DEVICE_WIRE_DVOBB       0x05
 225 #define DEVICE_WIRE_DVOCC       0x06
 226 #define DEVICE_WIRE_DVOB_MASTER 0x0d
 227 #define DEVICE_WIRE_DVOC_MASTER 0x0e
 228
 229 #define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
 230 #define DEVICE_PORT_DVOB        0x01
 231 #define DEVICE_PORT_DVOC        0x02
 232
 233 /*
 234  * We used to keep this struct but without any version control. We should avoid
 235  * using it in the future, but it should be safe to keep using it in the old
 236  * code. Do not change; we rely on its size.
 237  */
 238 struct old_child_dev_config {
 239         u16 handle;
 240         u16 device_type;
 241         u8  device_id[10]; /* ascii string */
 242         u16 addin_offset;
 243         u8  dvo_port; /* See Device_PORT_* above */
 244         u8  i2c_pin;
 245         u8  slave_addr;
 246         u8  ddc_pin;
 247         u16 edid_ptr;
 248         u8  dvo_cfg; /* See DEVICE_CFG_* above */
 249         u8  dvo2_port;
 250         u8  i2c2_pin;
 251         u8  slave2_addr;
 252         u8  ddc2_pin;
 253         u8  capabilities;
 254         u8  dvo_wiring;/* See DEVICE_WIRE_* above */
 255         u8  dvo2_wiring;
 256         u16 extended_type;
 257         u8  dvo_function;
 258 } __packed;
 259
 260 /* This one contains field offsets that are known to be common for all BDB
 261  * versions. Notice that the meaning of the contents contents may still change,
 262  * but at least the offsets are consistent. */
 263
 264 struct common_child_dev_config {
 265         u16 handle;
 266         u16 device_type;
 267         u8 not_common1[12];
 268         u8 dvo_port;
 269         u8 not_common2[2];
 270         u8 ddc_pin;
 271         u16 edid_ptr;
 272         u8 dvo_cfg; /* See DEVICE_CFG_* above */
 273         u8 efp_routed:1;
 274         u8 lane_reversal:1;
 275         u8 lspcon:1;
 276         u8 iboost:1;
 277         u8 hpd_invert:1;
 278         u8 flag_reserved:3;
 279         u8 hdmi_support:1;
 280         u8 dp_support:1;
 281         u8 tmds_support:1;
 282         u8 support_reserved:5;
 283         u8 not_common3[12];
 284         u8 iboost_level;
 285 } __packed;
 286
 287
 288 /* This field changes depending on the BDB version, so the most reliable way to
 289  * read it is by checking the BDB version and reading the raw pointer. */
 290 union child_device_config {
 291         /* This one is safe to be used anywhere, but the code should still check
 292          * the BDB version. */
 293         u8 raw[33];
 294         /* This one should only be kept for legacy code. */
 295         struct old_child_dev_config old;
 296         /* This one should also be safe to use anywhere, even without version
 297          * checks. */
 298         struct common_child_dev_config common;
 299 } __packed;
 300
 301 struct bdb_general_definitions {
 302         /* DDC GPIO */
 303         u8 crt_ddc_gmbus_pin;
 304
 305         /* DPMS bits */
 306         u8 dpms_acpi:1;
 307         u8 skip_boot_crt_detect:1;
 308         u8 dpms_aim:1;
 309         u8 rsvd1:5; /* finish byte */
 310
 311         /* boot device bits */
 312         u8 boot_display[2];
 313         u8 child_dev_size;
 314
 315         /*
 316          * Device info:
 317          * If TV is present, it'll be at devices[0].
 318          * LVDS will be next, either devices[0] or [1], if present.
 319          * On some platforms the number of device is 6. But could be as few as
 320          * 4 if both TV and LVDS are missing.
 321          * And the device num is related with the size of general definition
 322          * block. It is obtained by using the following formula:
 323          * number = (block_size - sizeof(bdb_general_definitions))/
 324          *           defs->child_dev_size;
 325          */
 326         uint8_t devices[0];
 327 } __packed;
 328
 329 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */
 330 #define MODE_MASK               0x3
 331
 332 struct bdb_lvds_options {
 333         u8 panel_type;
 334         u8 rsvd1;
 335         /* LVDS capabilities, stored in a dword */
 336         u8 pfit_mode:2;
 337         u8 pfit_text_mode_enhanced:1;
 338         u8 pfit_gfx_mode_enhanced:1;
 339         u8 pfit_ratio_auto:1;
 340         u8 pixel_dither:1;
 341         u8 lvds_edid:1;
 342         u8 rsvd2:1;
 343         u8 rsvd4;
 344         /* LVDS Panel channel bits stored here */
 345         u32 lvds_panel_channel_bits;
 346         /* LVDS SSC (Spread Spectrum Clock) bits stored here. */
 347         u16 ssc_bits;
 348         u16 ssc_freq;
 349         u16 ssc_ddt;
 350         /* Panel color depth defined here */
 351         u16 panel_color_depth;
 352         /* LVDS panel type bits stored here */
 353         u32 dps_panel_type_bits;
 354         /* LVDS backlight control type bits stored here */
 355         u32 blt_control_type_bits;
 356 } __packed;
 357
 358 /* LFP pointer table contains entries to the struct below */
 359 struct bdb_lvds_lfp_data_ptr {
 360         u16 fp_timing_offset; /* offsets are from start of bdb */
 361         u8 fp_table_size;
 362         u16 dvo_timing_offset;
 363         u8 dvo_table_size;
 364         u16 panel_pnp_id_offset;
 365         u8 pnp_table_size;
 366 } __packed;
 367
 368 struct bdb_lvds_lfp_data_ptrs {
 369         u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
 370         struct bdb_lvds_lfp_data_ptr ptr[16];
 371 } __packed;
 372
 373 /* LFP data has 3 blocks per entry */
 374 struct lvds_fp_timing {
 375         u16 x_res;
 376         u16 y_res;
 377         u32 lvds_reg;
 378         u32 lvds_reg_val;
 379         u32 pp_on_reg;
 380         u32 pp_on_reg_val;
 381         u32 pp_off_reg;
 382         u32 pp_off_reg_val;
 383         u32 pp_cycle_reg;
 384         u32 pp_cycle_reg_val;
 385         u32 pfit_reg;
 386         u32 pfit_reg_val;
 387         u16 terminator;
 388 } __packed;
 389
 390 struct lvds_dvo_timing {
 391         u16 clock;              /**< In 10khz */
 392         u8 hactive_lo;
 393         u8 hblank_lo;
 394         u8 hblank_hi:4;
 395         u8 hactive_hi:4;
 396         u8 vactive_lo;
 397         u8 vblank_lo;
 398         u8 vblank_hi:4;
 399         u8 vactive_hi:4;
 400         u8 hsync_off_lo;
 401         u8 hsync_pulse_width;
 402         u8 vsync_pulse_width:4;
 403         u8 vsync_off:4;
 404         u8 rsvd0:6;
 405         u8 hsync_off_hi:2;
 406         u8 himage_lo;
 407         u8 vimage_lo;
 408         u8 vimage_hi:4;
 409         u8 himage_hi:4;
 410         u8 h_border;
 411         u8 v_border;
 412         u8 rsvd1:3;
 413         u8 digital:2;
 414         u8 vsync_positive:1;
 415         u8 hsync_positive:1;
 416         u8 rsvd2:1;
 417 } __packed;
 418
 419 struct lvds_pnp_id {
 420         u16 mfg_name;
 421         u16 product_code;
 422         u32 serial;
 423         u8 mfg_week;
 424         u8 mfg_year;
 425 } __packed;
 426
 427 struct bdb_lvds_lfp_data_entry {
 428         struct lvds_fp_timing fp_timing;
 429         struct lvds_dvo_timing dvo_timing;
 430         struct lvds_pnp_id pnp_id;
 431 } __packed;
 432
 433 struct bdb_lvds_lfp_data {
 434         struct bdb_lvds_lfp_data_entry data[16];
 435 } __packed;
 436
 437 #define BDB_BACKLIGHT_TYPE_NONE 0
 438 #define BDB_BACKLIGHT_TYPE_PWM  2
 439
 440 struct bdb_lfp_backlight_data_entry {
 441         u8 type:2;
 442         u8 active_low_pwm:1;
 443         u8 obsolete1:5;
 444         u16 pwm_freq_hz;
 445         u8 min_brightness;
 446         u8 obsolete2;
 447         u8 obsolete3;
 448 } __packed;
 449
 450 struct bdb_lfp_backlight_data {
 451         u8 entry_size;
 452         struct bdb_lfp_backlight_data_entry data[16];
 453         u8 level[16];
 454 } __packed;
 455
 456 struct aimdb_header {
 457         char signature[16];
 458         char oem_device[20];
 459         u16 aimdb_version;
 460         u16 aimdb_header_size;
 461         u16 aimdb_size;
 462 } __packed;
 463
 464 struct aimdb_block {
 465         u8 aimdb_id;
 466         u16 aimdb_size;
 467 } __packed;
 468
 469 struct vch_panel_data {
 470         u16 fp_timing_offset;
 471         u8 fp_timing_size;
 472         u16 dvo_timing_offset;
 473         u8 dvo_timing_size;
 474         u16 text_fitting_offset;
 475         u8 text_fitting_size;
 476         u16 graphics_fitting_offset;
 477         u8 graphics_fitting_size;
 478 } __packed;
 479
 480 struct vch_bdb_22 {
 481         struct aimdb_block aimdb_block;
 482         struct vch_panel_data panels[16];
 483 } __packed;
 484
 485 struct bdb_sdvo_lvds_options {
 486         u8 panel_backlight;
 487         u8 h40_set_panel_type;
 488         u8 panel_type;
 489         u8 ssc_clk_freq;
 490         u16 als_low_trip;
 491         u16 als_high_trip;
 492         u8 sclalarcoeff_tab_row_num;
 493         u8 sclalarcoeff_tab_row_size;
 494         u8 coefficient[8];
 495         u8 panel_misc_bits_1;
 496         u8 panel_misc_bits_2;
 497         u8 panel_misc_bits_3;
 498         u8 panel_misc_bits_4;
 499 } __packed;
 500
 501
 502 #define BDB_DRIVER_FEATURE_NO_LVDS              0
 503 #define BDB_DRIVER_FEATURE_INT_LVDS             1
 504 #define BDB_DRIVER_FEATURE_SDVO_LVDS            2
 505 #define BDB_DRIVER_FEATURE_EDP                  3
 506
 507 struct bdb_driver_features {
 508         u8 boot_dev_algorithm:1;
 509         u8 block_display_switch:1;
 510         u8 allow_display_switch:1;
 511         u8 hotplug_dvo:1;
 512         u8 dual_view_zoom:1;
 513         u8 int15h_hook:1;
 514         u8 sprite_in_clone:1;
 515         u8 primary_lfp_id:1;
 516
 517         u16 boot_mode_x;
 518         u16 boot_mode_y;
 519         u8 boot_mode_bpp;
 520         u8 boot_mode_refresh;
 521
 522         u16 enable_lfp_primary:1;
 523         u16 selective_mode_pruning:1;
 524         u16 dual_frequency:1;
 525         u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
 526         u16 nt_clone_support:1;
 527         u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
 528         u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
 529         u16 cui_aspect_scaling:1;
 530         u16 preserve_aspect_ratio:1;
 531         u16 sdvo_device_power_down:1;
 532         u16 crt_hotplug:1;
 533         u16 lvds_config:2;
 534         u16 tv_hotplug:1;
 535         u16 hdmi_config:2;
 536
 537         u8 static_display:1;
 538         u8 reserved2:7;
 539         u16 legacy_crt_max_x;
 540         u16 legacy_crt_max_y;
 541         u8 legacy_crt_max_refresh;
 542
 543         u8 hdmi_termination;
 544         u8 custom_vbt_version;
 545         /* Driver features data block */
 546         u16 rmpm_enabled:1;
 547         u16 s2ddt_enabled:1;
 548         u16 dpst_enabled:1;
 549         u16 bltclt_enabled:1;
 550         u16 adb_enabled:1;
 551         u16 drrs_enabled:1;
 552         u16 grs_enabled:1;
 553         u16 gpmt_enabled:1;
 554         u16 tbt_enabled:1;
 555         u16 psr_enabled:1;
 556         u16 ips_enabled:1;
 557         u16 reserved3:4;
 558         u16 pc_feature_valid:1;
 559 } __packed;
 560
 561 #define EDP_18BPP       0
 562 #define EDP_24BPP       1
 563 #define EDP_30BPP       2
 564 #define EDP_RATE_1_62   0
 565 #define EDP_RATE_2_7    1
 566 #define EDP_LANE_1      0
 567 #define EDP_LANE_2      1
 568 #define EDP_LANE_4      3
 569 #define EDP_PREEMPHASIS_NONE    0
 570 #define EDP_PREEMPHASIS_3_5dB   1
 571 #define EDP_PREEMPHASIS_6dB     2
 572 #define EDP_PREEMPHASIS_9_5dB   3
 573 #define EDP_VSWING_0_4V         0
 574 #define EDP_VSWING_0_6V         1
 575 #define EDP_VSWING_0_8V         2
 576 #define EDP_VSWING_1_2V         3
 577
 578
 579 struct edp_link_params {
 580         u8 rate:4;
 581         u8 lanes:4;
 582         u8 preemphasis:4;
 583         u8 vswing:4;
 584 } __packed;
 585
 586 struct bdb_edp {
 587         struct edp_power_seq power_seqs[16];
 588         u32 color_depth;
 589         struct edp_link_params link_params[16];
 590         u32 sdrrs_msa_timing_delay;
 591
 592         /* ith bit indicates enabled/disabled for (i+1)th panel */
 593         u16 edp_s3d_feature;
 594         u16 edp_t3_optimization;
 595         u64 edp_vswing_preemph;         /* v173 */
 596 } __packed;
 597
 598 struct psr_table {
 599         /* Feature bits */
 600         u8 full_link:1;
 601         u8 require_aux_to_wakeup:1;
 602         u8 feature_bits_rsvd:6;
 603
 604         /* Wait times */
 605         u8 idle_frames:4;
 606         u8 lines_to_wait:3;
 607         u8 wait_times_rsvd:1;
 608
 609         /* TP wake up time in multiple of 100 */
 610         u16 tp1_wakeup_time;
 611         u16 tp2_tp3_wakeup_time;
 612 } __packed;
 613
 614 struct bdb_psr {
 615         struct psr_table psr_table[16];
 616 } __packed;
 617
 618 /*
 619  * Driver<->VBIOS interaction occurs through scratch bits in
 620  * GR18 & SWF*.
 621  */
 622
 623 /* GR18 bits are set on display switch and hotkey events */
 624 #define GR18_DRIVER_SWITCH_EN   (1<<7) /* 0: VBIOS control, 1: driver control */
 625 #define GR18_HOTKEY_MASK        0x78 /* See also SWF4 15:0 */
 626 #define   GR18_HK_NONE          (0x0<<3)
 627 #define   GR18_HK_LFP_STRETCH   (0x1<<3)
 628 #define   GR18_HK_TOGGLE_DISP   (0x2<<3)
 629 #define   GR18_HK_DISP_SWITCH   (0x4<<3) /* see SWF14 15:0 for what to enable */
 630 #define   GR18_HK_POPUP_DISABLED (0x6<<3)
 631 #define   GR18_HK_POPUP_ENABLED (0x7<<3)
 632 #define   GR18_HK_PFIT          (0x8<<3)
 633 #define   GR18_HK_APM_CHANGE    (0xa<<3)
 634 #define   GR18_HK_MULTIPLE      (0xc<<3)
 635 #define GR18_USER_INT_EN        (1<<2)
 636 #define GR18_A0000_FLUSH_EN     (1<<1)
 637 #define GR18_SMM_EN             (1<<0)
 638
 639 /* Set by driver, cleared by VBIOS */
 640 #define SWF00_YRES_SHIFT        16
 641 #define SWF00_XRES_SHIFT        0
 642 #define SWF00_RES_MASK          0xffff
 643
 644 /* Set by VBIOS at boot time and driver at runtime */
 645 #define SWF01_TV2_FORMAT_SHIFT  8
 646 #define SWF01_TV1_FORMAT_SHIFT  0
 647 #define SWF01_TV_FORMAT_MASK    0xffff
 648
 649 #define SWF10_VBIOS_BLC_I2C_EN  (1<<29)
 650 #define SWF10_GTT_OVERRIDE_EN   (1<<28)
 651 #define SWF10_LFP_DPMS_OVR      (1<<27) /* override DPMS on display switch */
 652 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
 653 #define   SWF10_OLD_TOGGLE      0x0
 654 #define   SWF10_TOGGLE_LIST_1   0x1
 655 #define   SWF10_TOGGLE_LIST_2   0x2
 656 #define   SWF10_TOGGLE_LIST_3   0x3
 657 #define   SWF10_TOGGLE_LIST_4   0x4
 658 #define SWF10_PANNING_EN        (1<<23)
 659 #define SWF10_DRIVER_LOADED     (1<<22)
 660 #define SWF10_EXTENDED_DESKTOP  (1<<21)
 661 #define SWF10_EXCLUSIVE_MODE    (1<<20)
 662 #define SWF10_OVERLAY_EN        (1<<19)
 663 #define SWF10_PLANEB_HOLDOFF    (1<<18)
 664 #define SWF10_PLANEA_HOLDOFF    (1<<17)
 665 #define SWF10_VGA_HOLDOFF       (1<<16)
 666 #define SWF10_ACTIVE_DISP_MASK  0xffff
 667 #define   SWF10_PIPEB_LFP2      (1<<15)
 668 #define   SWF10_PIPEB_EFP2      (1<<14)
 669 #define   SWF10_PIPEB_TV2       (1<<13)
 670 #define   SWF10_PIPEB_CRT2      (1<<12)
 671 #define   SWF10_PIPEB_LFP       (1<<11)
 672 #define   SWF10_PIPEB_EFP       (1<<10)
 673 #define   SWF10_PIPEB_TV        (1<<9)
 674 #define   SWF10_PIPEB_CRT       (1<<8)
 675 #define   SWF10_PIPEA_LFP2      (1<<7)
 676 #define   SWF10_PIPEA_EFP2      (1<<6)
 677 #define   SWF10_PIPEA_TV2       (1<<5)
 678 #define   SWF10_PIPEA_CRT2      (1<<4)
 679 #define   SWF10_PIPEA_LFP       (1<<3)
 680 #define   SWF10_PIPEA_EFP       (1<<2)
 681 #define   SWF10_PIPEA_TV        (1<<1)
 682 #define   SWF10_PIPEA_CRT       (1<<0)
 683
 684 #define SWF11_MEMORY_SIZE_SHIFT 16
 685 #define SWF11_SV_TEST_EN        (1<<15)
 686 #define SWF11_IS_AGP            (1<<14)
 687 #define SWF11_DISPLAY_HOLDOFF   (1<<13)
 688 #define SWF11_DPMS_REDUCED      (1<<12)
 689 #define SWF11_IS_VBE_MODE       (1<<11)
 690 #define SWF11_PIPEB_ACCESS      (1<<10) /* 0 here means pipe a */
 691 #define SWF11_DPMS_MASK         0x07
 692 #define   SWF11_DPMS_OFF        (1<<2)
 693 #define   SWF11_DPMS_SUSPEND    (1<<1)
 694 #define   SWF11_DPMS_STANDBY    (1<<0)
 695 #define   SWF11_DPMS_ON         0
 696
 697 #define SWF14_GFX_PFIT_EN       (1<<31)
 698 #define SWF14_TEXT_PFIT_EN      (1<<30)
 699 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
 700 #define SWF14_POPUP_EN          (1<<28)
 701 #define SWF14_DISPLAY_HOLDOFF   (1<<27)
 702 #define SWF14_DISP_DETECT_EN    (1<<26)
 703 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
 704 #define SWF14_DRIVER_STATUS     (1<<24)
 705 #define SWF14_OS_TYPE_WIN9X     (1<<23)
 706 #define SWF14_OS_TYPE_WINNT     (1<<22)
 707 /* 21:19 rsvd */
 708 #define SWF14_PM_TYPE_MASK      0x00070000
 709 #define   SWF14_PM_ACPI_VIDEO   (0x4 << 16)
 710 #define   SWF14_PM_ACPI         (0x3 << 16)
 711 #define   SWF14_PM_APM_12       (0x2 << 16)
 712 #define   SWF14_PM_APM_11       (0x1 << 16)
 713 #define SWF14_HK_REQUEST_MASK   0x0000ffff /* see GR18 6:3 for event type */
 714           /* if GR18 indicates a display switch */
 715 #define   SWF14_DS_PIPEB_LFP2_EN (1<<15)
 716 #define   SWF14_DS_PIPEB_EFP2_EN (1<<14)
 717 #define   SWF14_DS_PIPEB_TV2_EN  (1<<13)
 718 #define   SWF14_DS_PIPEB_CRT2_EN (1<<12)
 719 #define   SWF14_DS_PIPEB_LFP_EN  (1<<11)
 720 #define   SWF14_DS_PIPEB_EFP_EN  (1<<10)
 721 #define   SWF14_DS_PIPEB_TV_EN   (1<<9)
 722 #define   SWF14_DS_PIPEB_CRT_EN  (1<<8)
 723 #define   SWF14_DS_PIPEA_LFP2_EN (1<<7)
 724 #define   SWF14_DS_PIPEA_EFP2_EN (1<<6)
 725 #define   SWF14_DS_PIPEA_TV2_EN  (1<<5)
 726 #define   SWF14_DS_PIPEA_CRT2_EN (1<<4)
 727 #define   SWF14_DS_PIPEA_LFP_EN  (1<<3)
 728 #define   SWF14_DS_PIPEA_EFP_EN  (1<<2)
 729 #define   SWF14_DS_PIPEA_TV_EN   (1<<1)
 730 #define   SWF14_DS_PIPEA_CRT_EN  (1<<0)
 731           /* if GR18 indicates a panel fitting request */
 732 #define   SWF14_PFIT_EN         (1<<0) /* 0 means disable */
 733           /* if GR18 indicates an APM change request */
 734 #define   SWF14_APM_HIBERNATE   0x4
 735 #define   SWF14_APM_SUSPEND     0x3
 736 #define   SWF14_APM_STANDBY     0x1
 737 #define   SWF14_APM_RESTORE     0x0
 738
 739 /* Add the device class for LFP, TV, HDMI */
 740 #define  DEVICE_TYPE_INT_LFP    0x1022
 741 #define  DEVICE_TYPE_INT_TV     0x1009
 742 #define  DEVICE_TYPE_HDMI       0x60D2
 743 #define  DEVICE_TYPE_DP         0x68C6
 744 #define  DEVICE_TYPE_DP_DUAL_MODE       0x60D6
 745 #define  DEVICE_TYPE_eDP        0x78C6
 746
 747 #define  DEVICE_TYPE_CLASS_EXTENSION    (1 << 15)
 748 #define  DEVICE_TYPE_POWER_MANAGEMENT   (1 << 14)
 749 #define  DEVICE_TYPE_HOTPLUG_SIGNALING  (1 << 13)
 750 #define  DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12)
 751 #define  DEVICE_TYPE_NOT_HDMI_OUTPUT    (1 << 11)
 752 #define  DEVICE_TYPE_MIPI_OUTPUT        (1 << 10)
 753 #define  DEVICE_TYPE_COMPOSITE_OUTPUT   (1 << 9)
 754 #define  DEVICE_TYPE_DUAL_CHANNEL       (1 << 8)
 755 #define  DEVICE_TYPE_HIGH_SPEED_LINK    (1 << 6)
 756 #define  DEVICE_TYPE_LVDS_SINGALING     (1 << 5)
 757 #define  DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4)
 758 #define  DEVICE_TYPE_VIDEO_SIGNALING    (1 << 3)
 759 #define  DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2)
 760 #define  DEVICE_TYPE_DIGITAL_OUTPUT     (1 << 1)
 761 #define  DEVICE_TYPE_ANALOG_OUTPUT      (1 << 0)
 762
 763 /*
 764  * Bits we care about when checking for DEVICE_TYPE_eDP
 765  * Depending on the system, the other bits may or may not
 766  * be set for eDP outputs.
 767  */
 768 #define DEVICE_TYPE_eDP_BITS \
 769         (DEVICE_TYPE_INTERNAL_CONNECTOR | \
 770          DEVICE_TYPE_MIPI_OUTPUT | \
 771          DEVICE_TYPE_COMPOSITE_OUTPUT | \
 772          DEVICE_TYPE_DUAL_CHANNEL | \
 773          DEVICE_TYPE_LVDS_SINGALING | \
 774          DEVICE_TYPE_TMDS_DVI_SIGNALING | \
 775          DEVICE_TYPE_VIDEO_SIGNALING | \
 776          DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
 777          DEVICE_TYPE_ANALOG_OUTPUT)
 778
 779 #define DEVICE_TYPE_DP_DUAL_MODE_BITS \
 780         (DEVICE_TYPE_INTERNAL_CONNECTOR | \
 781          DEVICE_TYPE_MIPI_OUTPUT | \
 782          DEVICE_TYPE_COMPOSITE_OUTPUT | \
 783          DEVICE_TYPE_LVDS_SINGALING | \
 784          DEVICE_TYPE_TMDS_DVI_SIGNALING | \
 785          DEVICE_TYPE_VIDEO_SIGNALING | \
 786          DEVICE_TYPE_DISPLAYPORT_OUTPUT | \
 787          DEVICE_TYPE_DIGITAL_OUTPUT | \
 788          DEVICE_TYPE_ANALOG_OUTPUT)
 789
 790 /* define the DVO port for HDMI output type */
 791 #define         DVO_B           1
 792 #define         DVO_C           2
 793 #define         DVO_D           3
 794
 795 /* Possible values for the "DVO Port" field for versions >= 155: */
 796 #define DVO_PORT_HDMIA  0
 797 #define DVO_PORT_HDMIB  1
 798 #define DVO_PORT_HDMIC  2
 799 #define DVO_PORT_HDMID  3
 800 #define DVO_PORT_LVDS   4
 801 #define DVO_PORT_TV     5
 802 #define DVO_PORT_CRT    6
 803 #define DVO_PORT_DPB    7
 804 #define DVO_PORT_DPC    8
 805 #define DVO_PORT_DPD    9
 806 #define DVO_PORT_DPA    10
 807 #define DVO_PORT_DPE    11
 808 #define DVO_PORT_HDMIE  12
 809 #define DVO_PORT_MIPIA  21
 810 #define DVO_PORT_MIPIB  22
 811 #define DVO_PORT_MIPIC  23
 812 #define DVO_PORT_MIPID  24
 813
 814 /* Block 52 contains MIPI configuration block
 815  * 6 * bdb_mipi_config, followed by 6 pps data block
 816  * block below
 817  */
 818 #define MAX_MIPI_CONFIGURATIONS 6
 819
 820 struct bdb_mipi_config {
 821         struct mipi_config config[MAX_MIPI_CONFIGURATIONS];
 822         struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS];
 823 } __packed;
 824
 825 /* Block 53 contains MIPI sequences as needed by the panel
 826  * for enabling it. This block can be variable in size and
 827  * can be maximum of 6 blocks
 828  */
 829 struct bdb_mipi_sequence {
 830         u8 version;
 831         u8 data[0];
 832 } __packed;
 833
 834 enum mipi_gpio_pin_index {
 835         MIPI_GPIO_UNDEFINED = 0,
 836         MIPI_GPIO_PANEL_ENABLE,
 837         MIPI_GPIO_BL_ENABLE,
 838         MIPI_GPIO_PWM_ENABLE,
 839         MIPI_GPIO_RESET_N,
 840         MIPI_GPIO_PWR_DOWN_R,
 841         MIPI_GPIO_STDBY_RST_N,
 842         MIPI_GPIO_MAX
 843 };
 844
 845 #endif /* _INTEL_VBT_DEFS_H_ */