drivers/gpu/drm/imx/imx-tve.c

   1 /*
   2  * i.MX drm driver - Television Encoder (TVEv2)
   3  *
   4  * Copyright (C) 2013 Philipp Zabel, Pengutronix
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/clk-provider.h>
  18 #include <linux/component.h>
  19 #include <linux/module.h>
  20 #include <linux/i2c.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/videodev2.h>
  25 #include <drm/drmP.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_fb_helper.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <video/imx-ipu-v3.h>
  30
  31 #include "imx-drm.h"
  32
  33 #define TVE_COM_CONF_REG        0x00
  34 #define TVE_TVDAC0_CONT_REG     0x28
  35 #define TVE_TVDAC1_CONT_REG     0x2c
  36 #define TVE_TVDAC2_CONT_REG     0x30
  37 #define TVE_CD_CONT_REG         0x34
  38 #define TVE_INT_CONT_REG        0x64
  39 #define TVE_STAT_REG            0x68
  40 #define TVE_TST_MODE_REG        0x6c
  41 #define TVE_MV_CONT_REG         0xdc
  42
  43 /* TVE_COM_CONF_REG */
  44 #define TVE_SYNC_CH_2_EN        BIT(22)
  45 #define TVE_SYNC_CH_1_EN        BIT(21)
  46 #define TVE_SYNC_CH_0_EN        BIT(20)
  47 #define TVE_TV_OUT_MODE_MASK    (0x7 << 12)
  48 #define TVE_TV_OUT_DISABLE      (0x0 << 12)
  49 #define TVE_TV_OUT_CVBS_0       (0x1 << 12)
  50 #define TVE_TV_OUT_CVBS_2       (0x2 << 12)
  51 #define TVE_TV_OUT_CVBS_0_2     (0x3 << 12)
  52 #define TVE_TV_OUT_SVIDEO_0_1   (0x4 << 12)
  53 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2   (0x5 << 12)
  54 #define TVE_TV_OUT_YPBPR        (0x6 << 12)
  55 #define TVE_TV_OUT_RGB          (0x7 << 12)
  56 #define TVE_TV_STAND_MASK       (0xf << 8)
  57 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
  58 #define TVE_P2I_CONV_EN         BIT(7)
  59 #define TVE_INP_VIDEO_FORM      BIT(6)
  60 #define TVE_INP_YCBCR_422       (0x0 << 6)
  61 #define TVE_INP_YCBCR_444       (0x1 << 6)
  62 #define TVE_DATA_SOURCE_MASK    (0x3 << 4)
  63 #define TVE_DATA_SOURCE_BUS1    (0x0 << 4)
  64 #define TVE_DATA_SOURCE_BUS2    (0x1 << 4)
  65 #define TVE_DATA_SOURCE_EXT     (0x2 << 4)
  66 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
  67 #define TVE_IPU_CLK_EN_OFS      3
  68 #define TVE_IPU_CLK_EN          BIT(3)
  69 #define TVE_DAC_SAMP_RATE_OFS   1
  70 #define TVE_DAC_SAMP_RATE_WIDTH 2
  71 #define TVE_DAC_SAMP_RATE_MASK  (0x3 << 1)
  72 #define TVE_DAC_FULL_RATE       (0x0 << 1)
  73 #define TVE_DAC_DIV2_RATE       (0x1 << 1)
  74 #define TVE_DAC_DIV4_RATE       (0x2 << 1)
  75 #define TVE_EN                  BIT(0)
  76
  77 /* TVE_TVDACx_CONT_REG */
  78 #define TVE_TVDAC_GAIN_MASK     (0x3f << 0)
  79
  80 /* TVE_CD_CONT_REG */
  81 #define TVE_CD_CH_2_SM_EN       BIT(22)
  82 #define TVE_CD_CH_1_SM_EN       BIT(21)
  83 #define TVE_CD_CH_0_SM_EN       BIT(20)
  84 #define TVE_CD_CH_2_LM_EN       BIT(18)
  85 #define TVE_CD_CH_1_LM_EN       BIT(17)
  86 #define TVE_CD_CH_0_LM_EN       BIT(16)
  87 #define TVE_CD_CH_2_REF_LVL     BIT(10)
  88 #define TVE_CD_CH_1_REF_LVL     BIT(9)
  89 #define TVE_CD_CH_0_REF_LVL     BIT(8)
  90 #define TVE_CD_EN               BIT(0)
  91
  92 /* TVE_INT_CONT_REG */
  93 #define TVE_FRAME_END_IEN       BIT(13)
  94 #define TVE_CD_MON_END_IEN      BIT(2)
  95 #define TVE_CD_SM_IEN           BIT(1)
  96 #define TVE_CD_LM_IEN           BIT(0)
  97
  98 /* TVE_TST_MODE_REG */
  99 #define TVE_TVDAC_TEST_MODE_MASK        (0x7 << 0)
 100
 101 #define IMX_TVE_DAC_VOLTAGE     2750000
 102
 103 enum {
 104         TVE_MODE_TVOUT,
 105         TVE_MODE_VGA,
 106 };
 107
 108 struct imx_tve {
 109         struct drm_connector connector;
 110         struct drm_encoder encoder;
 111         struct device *dev;
 112         spinlock_t lock;        /* register lock */
 113         bool enabled;
 114         int mode;
 115         int di_hsync_pin;
 116         int di_vsync_pin;
 117
 118         struct regmap *regmap;
 119         struct regulator *dac_reg;
 120         struct i2c_adapter *ddc;
 121         struct clk *clk;
 122         struct clk *di_sel_clk;
 123         struct clk_hw clk_hw_di;
 124         struct clk *di_clk;
 125 };
 126
 127 static inline struct imx_tve *con_to_tve(struct drm_connector *c)
 128 {
 129         return container_of(c, struct imx_tve, connector);
 130 }
 131
 132 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
 133 {
 134         return container_of(e, struct imx_tve, encoder);
 135 }
 136
 137 static void tve_lock(void *__tve)
 138 __acquires(&tve->lock)
 139 {
 140         struct imx_tve *tve = __tve;
 141
 142         spin_lock(&tve->lock);
 143 }
 144
 145 static void tve_unlock(void *__tve)
 146 __releases(&tve->lock)
 147 {
 148         struct imx_tve *tve = __tve;
 149
 150         spin_unlock(&tve->lock);
 151 }
 152
 153 static void tve_enable(struct imx_tve *tve)
 154 {
 155         int ret;
 156
 157         if (!tve->enabled) {
 158                 tve->enabled = true;
 159                 clk_prepare_enable(tve->clk);
 160                 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 161                                          TVE_EN, TVE_EN);
 162         }
 163
 164         /* clear interrupt status register */
 165         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
 166
 167         /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
 168         if (tve->mode == TVE_MODE_VGA)
 169                 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
 170         else
 171                 regmap_write(tve->regmap, TVE_INT_CONT_REG,
 172                              TVE_CD_SM_IEN |
 173                              TVE_CD_LM_IEN |
 174                              TVE_CD_MON_END_IEN);
 175 }
 176
 177 static void tve_disable(struct imx_tve *tve)
 178 {
 179         int ret;
 180
 181         if (tve->enabled) {
 182                 tve->enabled = false;
 183                 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 184                                          TVE_EN, 0);
 185                 clk_disable_unprepare(tve->clk);
 186         }
 187 }
 188
 189 static int tve_setup_tvout(struct imx_tve *tve)
 190 {
 191         return -ENOTSUPP;
 192 }
 193
 194 static int tve_setup_vga(struct imx_tve *tve)
 195 {
 196         unsigned int mask;
 197         unsigned int val;
 198         int ret;
 199
 200         /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
 201         ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
 202                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 203         if (ret)
 204                 return ret;
 205
 206         ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
 207                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 208         if (ret)
 209                 return ret;
 210
 211         ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
 212                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 213         if (ret)
 214                 return ret;
 215
 216         /* set configuration register */
 217         mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
 218         val  = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
 219         mask |= TVE_TV_STAND_MASK       | TVE_P2I_CONV_EN;
 220         val  |= TVE_TV_STAND_HD_1080P30 | 0;
 221         mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
 222         val  |= TVE_TV_OUT_RGB       | TVE_SYNC_CH_0_EN;
 223         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
 224         if (ret)
 225                 return ret;
 226
 227         /* set test mode (as documented) */
 228         return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
 229                                  TVE_TVDAC_TEST_MODE_MASK, 1);
 230 }
 231
 232 static int imx_tve_connector_get_modes(struct drm_connector *connector)
 233 {
 234         struct imx_tve *tve = con_to_tve(connector);
 235         struct edid *edid;
 236         int ret = 0;
 237
 238         if (!tve->ddc)
 239                 return 0;
 240
 241         edid = drm_get_edid(connector, tve->ddc);
 242         if (edid) {
 243                 drm_mode_connector_update_edid_property(connector, edid);
 244                 ret = drm_add_edid_modes(connector, edid);
 245                 kfree(edid);
 246         }
 247
 248         return ret;
 249 }
 250
 251 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
 252                                         struct drm_display_mode *mode)
 253 {
 254         struct imx_tve *tve = con_to_tve(connector);
 255         unsigned long rate;
 256
 257         /* pixel clock with 2x oversampling */
 258         rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
 259         if (rate == mode->clock)
 260                 return MODE_OK;
 261
 262         /* pixel clock without oversampling */
 263         rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
 264         if (rate == mode->clock)
 265                 return MODE_OK;
 266
 267         dev_warn(tve->dev, "ignoring mode %dx%d\n",
 268                  mode->hdisplay, mode->vdisplay);
 269
 270         return MODE_BAD;
 271 }
 272
 273 static struct drm_encoder *imx_tve_connector_best_encoder(
 274                 struct drm_connector *connector)
 275 {
 276         struct imx_tve *tve = con_to_tve(connector);
 277
 278         return &tve->encoder;
 279 }
 280
 281 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
 282                                      struct drm_display_mode *orig_mode,
 283                                      struct drm_display_mode *mode)
 284 {
 285         struct imx_tve *tve = enc_to_tve(encoder);
 286         unsigned long rounded_rate;
 287         unsigned long rate;
 288         int div = 1;
 289         int ret;
 290
 291         /*
 292          * FIXME
 293          * we should try 4k * mode->clock first,
 294          * and enable 4x oversampling for lower resolutions
 295          */
 296         rate = 2000UL * mode->clock;
 297         clk_set_rate(tve->clk, rate);
 298         rounded_rate = clk_get_rate(tve->clk);
 299         if (rounded_rate >= rate)
 300                 div = 2;
 301         clk_set_rate(tve->di_clk, rounded_rate / div);
 302
 303         ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
 304         if (ret < 0) {
 305                 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
 306                         ret);
 307         }
 308
 309         regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 310                            TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
 311
 312         if (tve->mode == TVE_MODE_VGA)
 313                 ret = tve_setup_vga(tve);
 314         else
 315                 ret = tve_setup_tvout(tve);
 316         if (ret)
 317                 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
 318 }
 319
 320 static void imx_tve_encoder_enable(struct drm_encoder *encoder)
 321 {
 322         struct imx_tve *tve = enc_to_tve(encoder);
 323
 324         tve_enable(tve);
 325 }
 326
 327 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
 328 {
 329         struct imx_tve *tve = enc_to_tve(encoder);
 330
 331         tve_disable(tve);
 332 }
 333
 334 static int imx_tve_atomic_check(struct drm_encoder *encoder,
 335                                 struct drm_crtc_state *crtc_state,
 336                                 struct drm_connector_state *conn_state)
 337 {
 338         struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
 339         struct imx_tve *tve = enc_to_tve(encoder);
 340
 341         imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
 342         imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
 343         imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
 344
 345         return 0;
 346 }
 347
 348 static const struct drm_connector_funcs imx_tve_connector_funcs = {
 349         .dpms = drm_atomic_helper_connector_dpms,
 350         .fill_modes = drm_helper_probe_single_connector_modes,
 351         .destroy = imx_drm_connector_destroy,
 352         .reset = drm_atomic_helper_connector_reset,
 353         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 354         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 355 };
 356
 357 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
 358         .get_modes = imx_tve_connector_get_modes,
 359         .best_encoder = imx_tve_connector_best_encoder,
 360         .mode_valid = imx_tve_connector_mode_valid,
 361 };
 362
 363 static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
 364         .destroy = imx_drm_encoder_destroy,
 365 };
 366
 367 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
 368         .mode_set = imx_tve_encoder_mode_set,
 369         .enable = imx_tve_encoder_enable,
 370         .disable = imx_tve_encoder_disable,
 371         .atomic_check = imx_tve_atomic_check,
 372 };
 373
 374 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
 375 {
 376         struct imx_tve *tve = data;
 377         unsigned int val;
 378
 379         regmap_read(tve->regmap, TVE_STAT_REG, &val);
 380
 381         /* clear interrupt status register */
 382         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
 383
 384         return IRQ_HANDLED;
 385 }
 386
 387 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
 388                                             unsigned long parent_rate)
 389 {
 390         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
 391         unsigned int val;
 392         int ret;
 393
 394         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
 395         if (ret < 0)
 396                 return 0;
 397
 398         switch (val & TVE_DAC_SAMP_RATE_MASK) {
 399         case TVE_DAC_DIV4_RATE:
 400                 return parent_rate / 4;
 401         case TVE_DAC_DIV2_RATE:
 402                 return parent_rate / 2;
 403         case TVE_DAC_FULL_RATE:
 404         default:
 405                 return parent_rate;
 406         }
 407
 408         return 0;
 409 }
 410
 411 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
 412                                   unsigned long *prate)
 413 {
 414         unsigned long div;
 415
 416         div = *prate / rate;
 417         if (div >= 4)
 418                 return *prate / 4;
 419         else if (div >= 2)
 420                 return *prate / 2;
 421         return *prate;
 422 }
 423
 424 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
 425                                unsigned long parent_rate)
 426 {
 427         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
 428         unsigned long div;
 429         u32 val;
 430         int ret;
 431
 432         div = parent_rate / rate;
 433         if (div >= 4)
 434                 val = TVE_DAC_DIV4_RATE;
 435         else if (div >= 2)
 436                 val = TVE_DAC_DIV2_RATE;
 437         else
 438                 val = TVE_DAC_FULL_RATE;
 439
 440         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 441                                  TVE_DAC_SAMP_RATE_MASK, val);
 442
 443         if (ret < 0) {
 444                 dev_err(tve->dev, "failed to set divider: %d\n", ret);
 445                 return ret;
 446         }
 447
 448         return 0;
 449 }
 450
 451 static struct clk_ops clk_tve_di_ops = {
 452         .round_rate = clk_tve_di_round_rate,
 453         .set_rate = clk_tve_di_set_rate,
 454         .recalc_rate = clk_tve_di_recalc_rate,
 455 };
 456
 457 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
 458 {
 459         const char *tve_di_parent[1];
 460         struct clk_init_data init = {
 461                 .name = "tve_di",
 462                 .ops = &clk_tve_di_ops,
 463                 .num_parents = 1,
 464                 .flags = 0,
 465         };
 466
 467         tve_di_parent[0] = __clk_get_name(tve->clk);
 468         init.parent_names = (const char **)&tve_di_parent;
 469
 470         tve->clk_hw_di.init = &init;
 471         tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
 472         if (IS_ERR(tve->di_clk)) {
 473                 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
 474                         PTR_ERR(tve->di_clk));
 475                 return PTR_ERR(tve->di_clk);
 476         }
 477
 478         return 0;
 479 }
 480
 481 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
 482 {
 483         int encoder_type;
 484         int ret;
 485
 486         encoder_type = tve->mode == TVE_MODE_VGA ?
 487                                 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
 488
 489         ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
 490         if (ret)
 491                 return ret;
 492
 493         drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
 494         drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
 495                          encoder_type, NULL);
 496
 497         drm_connector_helper_add(&tve->connector,
 498                         &imx_tve_connector_helper_funcs);
 499         drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
 500                            DRM_MODE_CONNECTOR_VGA);
 501
 502         drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
 503
 504         return 0;
 505 }
 506
 507 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
 508 {
 509         return (reg % 4 == 0) && (reg <= 0xdc);
 510 }
 511
 512 static struct regmap_config tve_regmap_config = {
 513         .reg_bits = 32,
 514         .val_bits = 32,
 515         .reg_stride = 4,
 516
 517         .readable_reg = imx_tve_readable_reg,
 518
 519         .lock = tve_lock,
 520         .unlock = tve_unlock,
 521
 522         .max_register = 0xdc,
 523 };
 524
 525 static const char * const imx_tve_modes[] = {
 526         [TVE_MODE_TVOUT]  = "tvout",
 527         [TVE_MODE_VGA] = "vga",
 528 };
 529
 530 static const int of_get_tve_mode(struct device_node *np)
 531 {
 532         const char *bm;
 533         int ret, i;
 534
 535         ret = of_property_read_string(np, "fsl,tve-mode", &bm);
 536         if (ret < 0)
 537                 return ret;
 538
 539         for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
 540                 if (!strcasecmp(bm, imx_tve_modes[i]))
 541                         return i;
 542
 543         return -EINVAL;
 544 }
 545
 546 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
 547 {
 548         struct platform_device *pdev = to_platform_device(dev);
 549         struct drm_device *drm = data;
 550         struct device_node *np = dev->of_node;
 551         struct device_node *ddc_node;
 552         struct imx_tve *tve;
 553         struct resource *res;
 554         void __iomem *base;
 555         unsigned int val;
 556         int irq;
 557         int ret;
 558
 559         tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
 560         if (!tve)
 561                 return -ENOMEM;
 562
 563         tve->dev = dev;
 564         spin_lock_init(&tve->lock);
 565
 566         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
 567         if (ddc_node) {
 568                 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
 569                 of_node_put(ddc_node);
 570         }
 571
 572         tve->mode = of_get_tve_mode(np);
 573         if (tve->mode != TVE_MODE_VGA) {
 574                 dev_err(dev, "only VGA mode supported, currently\n");
 575                 return -EINVAL;
 576         }
 577
 578         if (tve->mode == TVE_MODE_VGA) {
 579                 ret = of_property_read_u32(np, "fsl,hsync-pin",
 580                                            &tve->di_hsync_pin);
 581
 582                 if (ret < 0) {
 583                         dev_err(dev, "failed to get hsync pin\n");
 584                         return ret;
 585                 }
 586
 587                 ret = of_property_read_u32(np, "fsl,vsync-pin",
 588                                            &tve->di_vsync_pin);
 589
 590                 if (ret < 0) {
 591                         dev_err(dev, "failed to get vsync pin\n");
 592                         return ret;
 593                 }
 594         }
 595
 596         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 597         base = devm_ioremap_resource(dev, res);
 598         if (IS_ERR(base))
 599                 return PTR_ERR(base);
 600
 601         tve_regmap_config.lock_arg = tve;
 602         tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
 603                                                 &tve_regmap_config);
 604         if (IS_ERR(tve->regmap)) {
 605                 dev_err(dev, "failed to init regmap: %ld\n",
 606                         PTR_ERR(tve->regmap));
 607                 return PTR_ERR(tve->regmap);
 608         }
 609
 610         irq = platform_get_irq(pdev, 0);
 611         if (irq < 0) {
 612                 dev_err(dev, "failed to get irq\n");
 613                 return irq;
 614         }
 615
 616         ret = devm_request_threaded_irq(dev, irq, NULL,
 617                                         imx_tve_irq_handler, IRQF_ONESHOT,
 618                                         "imx-tve", tve);
 619         if (ret < 0) {
 620                 dev_err(dev, "failed to request irq: %d\n", ret);
 621                 return ret;
 622         }
 623
 624         tve->dac_reg = devm_regulator_get(dev, "dac");
 625         if (!IS_ERR(tve->dac_reg)) {
 626                 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
 627                         dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
 628                 ret = regulator_enable(tve->dac_reg);
 629                 if (ret)
 630                         return ret;
 631         }
 632
 633         tve->clk = devm_clk_get(dev, "tve");
 634         if (IS_ERR(tve->clk)) {
 635                 dev_err(dev, "failed to get high speed tve clock: %ld\n",
 636                         PTR_ERR(tve->clk));
 637                 return PTR_ERR(tve->clk);
 638         }
 639
 640         /* this is the IPU DI clock input selector, can be parented to tve_di */
 641         tve->di_sel_clk = devm_clk_get(dev, "di_sel");
 642         if (IS_ERR(tve->di_sel_clk)) {
 643                 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
 644                         PTR_ERR(tve->di_sel_clk));
 645                 return PTR_ERR(tve->di_sel_clk);
 646         }
 647
 648         ret = tve_clk_init(tve, base);
 649         if (ret < 0)
 650                 return ret;
 651
 652         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
 653         if (ret < 0) {
 654                 dev_err(dev, "failed to read configuration register: %d\n",
 655                         ret);
 656                 return ret;
 657         }
 658         if (val != 0x00100000) {
 659                 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
 660                 return -ENODEV;
 661         }
 662
 663         /* disable cable detection for VGA mode */
 664         ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
 665         if (ret)
 666                 return ret;
 667
 668         ret = imx_tve_register(drm, tve);
 669         if (ret)
 670                 return ret;
 671
 672         dev_set_drvdata(dev, tve);
 673
 674         return 0;
 675 }
 676
 677 static void imx_tve_unbind(struct device *dev, struct device *master,
 678         void *data)
 679 {
 680         struct imx_tve *tve = dev_get_drvdata(dev);
 681
 682         if (!IS_ERR(tve->dac_reg))
 683                 regulator_disable(tve->dac_reg);
 684 }
 685
 686 static const struct component_ops imx_tve_ops = {
 687         .bind   = imx_tve_bind,
 688         .unbind = imx_tve_unbind,
 689 };
 690
 691 static int imx_tve_probe(struct platform_device *pdev)
 692 {
 693         return component_add(&pdev->dev, &imx_tve_ops);
 694 }
 695
 696 static int imx_tve_remove(struct platform_device *pdev)
 697 {
 698         component_del(&pdev->dev, &imx_tve_ops);
 699         return 0;
 700 }
 701
 702 static const struct of_device_id imx_tve_dt_ids[] = {
 703         { .compatible = "fsl,imx53-tve", },
 704         { /* sentinel */ }
 705 };
 706 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
 707
 708 static struct platform_driver imx_tve_driver = {
 709         .probe          = imx_tve_probe,
 710         .remove         = imx_tve_remove,
 711         .driver         = {
 712                 .of_match_table = imx_tve_dt_ids,
 713                 .name   = "imx-tve",
 714         },
 715 };
 716
 717 module_platform_driver(imx_tve_driver);
 718
 719 MODULE_DESCRIPTION("i.MX Television Encoder driver");
 720 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
 721 MODULE_LICENSE("GPL");
 722 MODULE_ALIAS("platform:imx-tve");