2 * i.MX IPUv3 Graphics driver
4 * Copyright (C) 2011 Sascha Hauer, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/component.h>
16 #include <linux/module.h>
17 #include <linux/export.h>
18 #include <linux/device.h>
19 #include <linux/platform_device.h>
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_crtc_helper.h>
24 #include <linux/clk.h>
25 #include <linux/errno.h>
26 #include <drm/drm_gem_cma_helper.h>
27 #include <drm/drm_fb_cma_helper.h>
29 #include <video/imx-ipu-v3.h>
31 #include "ipuv3-plane.h"
33 #define DRIVER_DESC "i.MX IPUv3 Graphics"
38 struct imx_drm_crtc
*imx_crtc
;
40 /* plane[0] is the full plane, plane[1] is the partial plane */
41 struct ipu_plane
*plane
[2];
48 static inline struct ipu_crtc
*to_ipu_crtc(struct drm_crtc
*crtc
)
50 return container_of(crtc
, struct ipu_crtc
, base
);
53 static void ipu_crtc_atomic_enable(struct drm_crtc
*crtc
,
54 struct drm_crtc_state
*old_state
)
56 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
57 struct ipu_soc
*ipu
= dev_get_drvdata(ipu_crtc
->dev
->parent
);
61 ipu_dc_enable_channel(ipu_crtc
->dc
);
62 ipu_di_enable(ipu_crtc
->di
);
65 static void ipu_crtc_disable_planes(struct ipu_crtc
*ipu_crtc
,
66 struct drm_crtc_state
*old_crtc_state
)
68 bool disable_partial
= false;
69 bool disable_full
= false;
70 struct drm_plane
*plane
;
72 drm_atomic_crtc_state_for_each_plane(plane
, old_crtc_state
) {
73 if (plane
== &ipu_crtc
->plane
[0]->base
)
75 if (&ipu_crtc
->plane
[1] && plane
== &ipu_crtc
->plane
[1]->base
)
76 disable_partial
= true;
80 ipu_plane_disable(ipu_crtc
->plane
[1], true);
82 ipu_plane_disable(ipu_crtc
->plane
[0], false);
85 static void ipu_crtc_atomic_disable(struct drm_crtc
*crtc
,
86 struct drm_crtc_state
*old_crtc_state
)
88 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
89 struct ipu_soc
*ipu
= dev_get_drvdata(ipu_crtc
->dev
->parent
);
91 ipu_dc_disable_channel(ipu_crtc
->dc
);
92 ipu_di_disable(ipu_crtc
->di
);
94 * Planes must be disabled before DC clock is removed, as otherwise the
95 * attached IDMACs will be left in undefined state, possibly hanging
96 * the IPU or even system.
98 ipu_crtc_disable_planes(ipu_crtc
, old_crtc_state
);
100 ipu_prg_disable(ipu
);
102 spin_lock_irq(&crtc
->dev
->event_lock
);
103 if (crtc
->state
->event
) {
104 drm_crtc_send_vblank_event(crtc
, crtc
->state
->event
);
105 crtc
->state
->event
= NULL
;
107 spin_unlock_irq(&crtc
->dev
->event_lock
);
109 drm_crtc_vblank_off(crtc
);
112 static void imx_drm_crtc_reset(struct drm_crtc
*crtc
)
114 struct imx_crtc_state
*state
;
117 if (crtc
->state
->mode_blob
)
118 drm_property_blob_put(crtc
->state
->mode_blob
);
120 state
= to_imx_crtc_state(crtc
->state
);
121 memset(state
, 0, sizeof(*state
));
123 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
126 crtc
->state
= &state
->base
;
129 state
->base
.crtc
= crtc
;
132 static struct drm_crtc_state
*imx_drm_crtc_duplicate_state(struct drm_crtc
*crtc
)
134 struct imx_crtc_state
*state
;
136 state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
140 __drm_atomic_helper_crtc_duplicate_state(crtc
, &state
->base
);
142 WARN_ON(state
->base
.crtc
!= crtc
);
143 state
->base
.crtc
= crtc
;
148 static void imx_drm_crtc_destroy_state(struct drm_crtc
*crtc
,
149 struct drm_crtc_state
*state
)
151 __drm_atomic_helper_crtc_destroy_state(state
);
152 kfree(to_imx_crtc_state(state
));
155 static int ipu_enable_vblank(struct drm_crtc
*crtc
)
157 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
159 enable_irq(ipu_crtc
->irq
);
164 static void ipu_disable_vblank(struct drm_crtc
*crtc
)
166 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
168 disable_irq_nosync(ipu_crtc
->irq
);
171 static const struct drm_crtc_funcs ipu_crtc_funcs
= {
172 .set_config
= drm_atomic_helper_set_config
,
173 .destroy
= drm_crtc_cleanup
,
174 .page_flip
= drm_atomic_helper_page_flip
,
175 .reset
= imx_drm_crtc_reset
,
176 .atomic_duplicate_state
= imx_drm_crtc_duplicate_state
,
177 .atomic_destroy_state
= imx_drm_crtc_destroy_state
,
178 .enable_vblank
= ipu_enable_vblank
,
179 .disable_vblank
= ipu_disable_vblank
,
182 static irqreturn_t
ipu_irq_handler(int irq
, void *dev_id
)
184 struct ipu_crtc
*ipu_crtc
= dev_id
;
186 drm_crtc_handle_vblank(&ipu_crtc
->base
);
191 static bool ipu_crtc_mode_fixup(struct drm_crtc
*crtc
,
192 const struct drm_display_mode
*mode
,
193 struct drm_display_mode
*adjusted_mode
)
195 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
199 drm_display_mode_to_videomode(adjusted_mode
, &vm
);
201 ret
= ipu_di_adjust_videomode(ipu_crtc
->di
, &vm
);
205 if ((vm
.vsync_len
== 0) || (vm
.hsync_len
== 0))
208 drm_display_mode_from_videomode(&vm
, adjusted_mode
);
213 static int ipu_crtc_atomic_check(struct drm_crtc
*crtc
,
214 struct drm_crtc_state
*state
)
216 u32 primary_plane_mask
= 1 << drm_plane_index(crtc
->primary
);
218 if (state
->active
&& (primary_plane_mask
& state
->plane_mask
) == 0)
224 static void ipu_crtc_atomic_begin(struct drm_crtc
*crtc
,
225 struct drm_crtc_state
*old_crtc_state
)
227 drm_crtc_vblank_on(crtc
);
229 spin_lock_irq(&crtc
->dev
->event_lock
);
230 if (crtc
->state
->event
) {
231 WARN_ON(drm_crtc_vblank_get(crtc
));
232 drm_crtc_arm_vblank_event(crtc
, crtc
->state
->event
);
233 crtc
->state
->event
= NULL
;
235 spin_unlock_irq(&crtc
->dev
->event_lock
);
238 static void ipu_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
240 struct drm_device
*dev
= crtc
->dev
;
241 struct drm_encoder
*encoder
;
242 struct ipu_crtc
*ipu_crtc
= to_ipu_crtc(crtc
);
243 struct drm_display_mode
*mode
= &crtc
->state
->adjusted_mode
;
244 struct imx_crtc_state
*imx_crtc_state
= to_imx_crtc_state(crtc
->state
);
245 struct ipu_di_signal_cfg sig_cfg
= {};
246 unsigned long encoder_types
= 0;
248 dev_dbg(ipu_crtc
->dev
, "%s: mode->hdisplay: %d\n", __func__
,
250 dev_dbg(ipu_crtc
->dev
, "%s: mode->vdisplay: %d\n", __func__
,
253 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
254 if (encoder
->crtc
== crtc
)
255 encoder_types
|= BIT(encoder
->encoder_type
);
258 dev_dbg(ipu_crtc
->dev
, "%s: attached to encoder types 0x%lx\n",
259 __func__
, encoder_types
);
262 * If we have DAC or LDB, then we need the IPU DI clock to be
263 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
264 * clock from 27 MHz TVE_DI clock, but allow to divide it.
266 if (encoder_types
& (BIT(DRM_MODE_ENCODER_DAC
) |
267 BIT(DRM_MODE_ENCODER_LVDS
)))
268 sig_cfg
.clkflags
= IPU_DI_CLKMODE_SYNC
| IPU_DI_CLKMODE_EXT
;
269 else if (encoder_types
& BIT(DRM_MODE_ENCODER_TVDAC
))
270 sig_cfg
.clkflags
= IPU_DI_CLKMODE_EXT
;
272 sig_cfg
.clkflags
= 0;
274 sig_cfg
.enable_pol
= !(imx_crtc_state
->bus_flags
& DRM_BUS_FLAG_DE_LOW
);
275 /* Default to driving pixel data on negative clock edges */
276 sig_cfg
.clk_pol
= !!(imx_crtc_state
->bus_flags
&
277 DRM_BUS_FLAG_PIXDATA_POSEDGE
);
278 sig_cfg
.bus_format
= imx_crtc_state
->bus_format
;
279 sig_cfg
.v_to_h_sync
= 0;
280 sig_cfg
.hsync_pin
= imx_crtc_state
->di_hsync_pin
;
281 sig_cfg
.vsync_pin
= imx_crtc_state
->di_vsync_pin
;
283 drm_display_mode_to_videomode(mode
, &sig_cfg
.mode
);
285 ipu_dc_init_sync(ipu_crtc
->dc
, ipu_crtc
->di
,
286 mode
->flags
& DRM_MODE_FLAG_INTERLACE
,
287 imx_crtc_state
->bus_format
, mode
->hdisplay
);
288 ipu_di_init_sync_panel(ipu_crtc
->di
, &sig_cfg
);
291 static const struct drm_crtc_helper_funcs ipu_helper_funcs
= {
292 .mode_fixup
= ipu_crtc_mode_fixup
,
293 .mode_set_nofb
= ipu_crtc_mode_set_nofb
,
294 .atomic_check
= ipu_crtc_atomic_check
,
295 .atomic_begin
= ipu_crtc_atomic_begin
,
296 .atomic_disable
= ipu_crtc_atomic_disable
,
297 .atomic_enable
= ipu_crtc_atomic_enable
,
300 static void ipu_put_resources(struct ipu_crtc
*ipu_crtc
)
302 if (!IS_ERR_OR_NULL(ipu_crtc
->dc
))
303 ipu_dc_put(ipu_crtc
->dc
);
304 if (!IS_ERR_OR_NULL(ipu_crtc
->di
))
305 ipu_di_put(ipu_crtc
->di
);
308 static int ipu_get_resources(struct ipu_crtc
*ipu_crtc
,
309 struct ipu_client_platformdata
*pdata
)
311 struct ipu_soc
*ipu
= dev_get_drvdata(ipu_crtc
->dev
->parent
);
314 ipu_crtc
->dc
= ipu_dc_get(ipu
, pdata
->dc
);
315 if (IS_ERR(ipu_crtc
->dc
)) {
316 ret
= PTR_ERR(ipu_crtc
->dc
);
320 ipu_crtc
->di
= ipu_di_get(ipu
, pdata
->di
);
321 if (IS_ERR(ipu_crtc
->di
)) {
322 ret
= PTR_ERR(ipu_crtc
->di
);
328 ipu_put_resources(ipu_crtc
);
333 static int ipu_crtc_init(struct ipu_crtc
*ipu_crtc
,
334 struct ipu_client_platformdata
*pdata
, struct drm_device
*drm
)
336 struct ipu_soc
*ipu
= dev_get_drvdata(ipu_crtc
->dev
->parent
);
337 struct drm_crtc
*crtc
= &ipu_crtc
->base
;
341 ret
= ipu_get_resources(ipu_crtc
, pdata
);
343 dev_err(ipu_crtc
->dev
, "getting resources failed with %d.\n",
349 dp
= IPU_DP_FLOW_SYNC_BG
;
350 ipu_crtc
->plane
[0] = ipu_plane_init(drm
, ipu
, pdata
->dma
[0], dp
, 0,
351 DRM_PLANE_TYPE_PRIMARY
);
352 if (IS_ERR(ipu_crtc
->plane
[0])) {
353 ret
= PTR_ERR(ipu_crtc
->plane
[0]);
354 goto err_put_resources
;
357 crtc
->port
= pdata
->of_node
;
358 drm_crtc_helper_add(crtc
, &ipu_helper_funcs
);
359 drm_crtc_init_with_planes(drm
, crtc
, &ipu_crtc
->plane
[0]->base
, NULL
,
360 &ipu_crtc_funcs
, NULL
);
362 ret
= ipu_plane_get_resources(ipu_crtc
->plane
[0]);
364 dev_err(ipu_crtc
->dev
, "getting plane 0 resources failed with %d.\n",
366 goto err_put_resources
;
369 /* If this crtc is using the DP, add an overlay plane */
370 if (pdata
->dp
>= 0 && pdata
->dma
[1] > 0) {
371 ipu_crtc
->plane
[1] = ipu_plane_init(drm
, ipu
, pdata
->dma
[1],
373 drm_crtc_mask(&ipu_crtc
->base
),
374 DRM_PLANE_TYPE_OVERLAY
);
375 if (IS_ERR(ipu_crtc
->plane
[1])) {
376 ipu_crtc
->plane
[1] = NULL
;
378 ret
= ipu_plane_get_resources(ipu_crtc
->plane
[1]);
380 dev_err(ipu_crtc
->dev
, "getting plane 1 "
381 "resources failed with %d.\n", ret
);
382 goto err_put_plane0_res
;
387 ipu_crtc
->irq
= ipu_plane_irq(ipu_crtc
->plane
[0]);
388 ret
= devm_request_irq(ipu_crtc
->dev
, ipu_crtc
->irq
, ipu_irq_handler
, 0,
389 "imx_drm", ipu_crtc
);
391 dev_err(ipu_crtc
->dev
, "irq request failed with %d.\n", ret
);
392 goto err_put_plane1_res
;
394 /* Only enable IRQ when we actually need it to trigger work. */
395 disable_irq(ipu_crtc
->irq
);
400 if (ipu_crtc
->plane
[1])
401 ipu_plane_put_resources(ipu_crtc
->plane
[1]);
403 ipu_plane_put_resources(ipu_crtc
->plane
[0]);
405 ipu_put_resources(ipu_crtc
);
410 static int ipu_drm_bind(struct device
*dev
, struct device
*master
, void *data
)
412 struct ipu_client_platformdata
*pdata
= dev
->platform_data
;
413 struct drm_device
*drm
= data
;
414 struct ipu_crtc
*ipu_crtc
;
417 ipu_crtc
= devm_kzalloc(dev
, sizeof(*ipu_crtc
), GFP_KERNEL
);
423 ret
= ipu_crtc_init(ipu_crtc
, pdata
, drm
);
427 dev_set_drvdata(dev
, ipu_crtc
);
432 static void ipu_drm_unbind(struct device
*dev
, struct device
*master
,
435 struct ipu_crtc
*ipu_crtc
= dev_get_drvdata(dev
);
437 ipu_put_resources(ipu_crtc
);
438 if (ipu_crtc
->plane
[1])
439 ipu_plane_put_resources(ipu_crtc
->plane
[1]);
440 ipu_plane_put_resources(ipu_crtc
->plane
[0]);
443 static const struct component_ops ipu_crtc_ops
= {
444 .bind
= ipu_drm_bind
,
445 .unbind
= ipu_drm_unbind
,
448 static int ipu_drm_probe(struct platform_device
*pdev
)
450 struct device
*dev
= &pdev
->dev
;
453 if (!dev
->platform_data
)
456 ret
= dma_set_coherent_mask(dev
, DMA_BIT_MASK(32));
460 return component_add(dev
, &ipu_crtc_ops
);
463 static int ipu_drm_remove(struct platform_device
*pdev
)
465 component_del(&pdev
->dev
, &ipu_crtc_ops
);
469 struct platform_driver ipu_drm_driver
= {
471 .name
= "imx-ipuv3-crtc",
473 .probe
= ipu_drm_probe
,
474 .remove
= ipu_drm_remove
,