2 * Copyright (C) 2016 BayLibre, SAS
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
4 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/component.h>
23 #include <linux/of_graph.h>
24 #include <linux/reset.h>
25 #include <linux/clk.h>
26 #include <linux/regulator/consumer.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_probe_helper.h>
32 #include <drm/bridge/dw_hdmi.h>
34 #include <uapi/linux/media-bus-format.h>
35 #include <uapi/linux/videodev2.h>
37 #include "meson_drv.h"
38 #include "meson_venc.h"
39 #include "meson_vclk.h"
40 #include "meson_dw_hdmi.h"
41 #include "meson_registers.h"
43 #define DRIVER_NAME "meson-dw-hdmi"
44 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
49 * HDMI Output is composed of :
51 * - A Synopsys DesignWare HDMI Controller IP
52 * - A TOP control block controlling the Clocks and PHY
53 * - A custom HDMI PHY in order convert video to TMDS signal
57 * ___________________________________
59 * |___________________________________|
61 * | Synopsys HDMI | HDMI PHY |=> TMDS
62 * | Controller |________________|
63 * |___________________________________|<=> DDC
66 * The HDMI TOP block only supports HPD sensing.
67 * The Synopsys HDMI Controller interrupt is routed
68 * through the TOP Block interrupt.
69 * Communication to the TOP Block and the Synopsys
70 * HDMI Controller is done a pair of addr+read/write
72 * The HDMI PHY is configured by registers in the
75 * Pixel data arrives in 4:4:4 format from the VENC
76 * block and the VPU HDMI mux selects either the ENCI
77 * encoder for the 576i or 480i formats or the ENCP
78 * encoder for all the other formats including
79 * interlaced HD formats.
80 * The VENC uses a DVI encoder on top of the ENCI
81 * or ENCP encoders to generate DVI timings for the
84 * GXBB, GXL and GXM embeds the Synopsys DesignWare
85 * HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
86 * audio source interfaces.
88 * We handle the following features :
90 * - HPD Rise & Fall interrupt
91 * - HDMI Controller Interrupt
92 * - HDMI PHY Init for 480i to 1080p60
93 * - VENC & HDMI Clock setup for 480i to 1080p60
94 * - VENC Mode setup for 480i to 1080p60
98 * - PHY, Clock and Mode setup for 2k && 4k modes
99 * - SDDC Scrambling mode for HDMI 2.0a
104 /* TOP Block Communication Channel */
105 #define HDMITX_TOP_ADDR_REG 0x0
106 #define HDMITX_TOP_DATA_REG 0x4
107 #define HDMITX_TOP_CTRL_REG 0x8
109 /* Controller Communication Channel */
110 #define HDMITX_DWC_ADDR_REG 0x10
111 #define HDMITX_DWC_DATA_REG 0x14
112 #define HDMITX_DWC_CTRL_REG 0x18
115 #define HHI_MEM_PD_REG0 0x100 /* 0x40 */
116 #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
117 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
118 #define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
119 #define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
120 #define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
122 static DEFINE_SPINLOCK(reg_lock
);
124 enum meson_venc_source
{
125 MESON_VENC_SOURCE_NONE
= 0,
126 MESON_VENC_SOURCE_ENCI
= 1,
127 MESON_VENC_SOURCE_ENCP
= 2,
130 struct meson_dw_hdmi
{
131 struct drm_encoder encoder
;
132 struct dw_hdmi_plat_data dw_plat_data
;
133 struct meson_drm
*priv
;
135 void __iomem
*hdmitx
;
136 struct reset_control
*hdmitx_apb
;
137 struct reset_control
*hdmitx_ctrl
;
138 struct reset_control
*hdmitx_phy
;
139 struct clk
*hdmi_pclk
;
140 struct clk
*venci_clk
;
141 struct regulator
*hdmi_supply
;
143 struct dw_hdmi
*hdmi
;
145 #define encoder_to_meson_dw_hdmi(x) \
146 container_of(x, struct meson_dw_hdmi, encoder)
148 static inline int dw_hdmi_is_compatible(struct meson_dw_hdmi
*dw_hdmi
,
151 return of_device_is_compatible(dw_hdmi
->dev
->of_node
, compat
);
154 /* PHY (via TOP bridge) and Controller dedicated register interface */
156 static unsigned int dw_hdmi_top_read(struct meson_dw_hdmi
*dw_hdmi
,
162 spin_lock_irqsave(®_lock
, flags
);
164 /* ADDR must be written twice */
165 writel(addr
& 0xffff, dw_hdmi
->hdmitx
+ HDMITX_TOP_ADDR_REG
);
166 writel(addr
& 0xffff, dw_hdmi
->hdmitx
+ HDMITX_TOP_ADDR_REG
);
168 /* Read needs a second DATA read */
169 data
= readl(dw_hdmi
->hdmitx
+ HDMITX_TOP_DATA_REG
);
170 data
= readl(dw_hdmi
->hdmitx
+ HDMITX_TOP_DATA_REG
);
172 spin_unlock_irqrestore(®_lock
, flags
);
177 static inline void dw_hdmi_top_write(struct meson_dw_hdmi
*dw_hdmi
,
178 unsigned int addr
, unsigned int data
)
182 spin_lock_irqsave(®_lock
, flags
);
184 /* ADDR must be written twice */
185 writel(addr
& 0xffff, dw_hdmi
->hdmitx
+ HDMITX_TOP_ADDR_REG
);
186 writel(addr
& 0xffff, dw_hdmi
->hdmitx
+ HDMITX_TOP_ADDR_REG
);
188 /* Write needs single DATA write */
189 writel(data
, dw_hdmi
->hdmitx
+ HDMITX_TOP_DATA_REG
);
191 spin_unlock_irqrestore(®_lock
, flags
);
194 /* Helper to change specific bits in PHY registers */
195 static inline void dw_hdmi_top_write_bits(struct meson_dw_hdmi
*dw_hdmi
,
200 unsigned int data
= dw_hdmi_top_read(dw_hdmi
, addr
);
205 dw_hdmi_top_write(dw_hdmi
, addr
, data
);
208 static unsigned int dw_hdmi_dwc_read(struct meson_dw_hdmi
*dw_hdmi
,
214 spin_lock_irqsave(®_lock
, flags
);
216 /* ADDR must be written twice */
217 writel(addr
& 0xffff, dw_hdmi
->hdmitx
+ HDMITX_DWC_ADDR_REG
);
218 writel(addr
& 0xffff, dw_hdmi
->hdmitx
+ HDMITX_DWC_ADDR_REG
);
220 /* Read needs a second DATA read */
221 data
= readl(dw_hdmi
->hdmitx
+ HDMITX_DWC_DATA_REG
);
222 data
= readl(dw_hdmi
->hdmitx
+ HDMITX_DWC_DATA_REG
);
224 spin_unlock_irqrestore(®_lock
, flags
);
229 static inline void dw_hdmi_dwc_write(struct meson_dw_hdmi
*dw_hdmi
,
230 unsigned int addr
, unsigned int data
)
234 spin_lock_irqsave(®_lock
, flags
);
236 /* ADDR must be written twice */
237 writel(addr
& 0xffff, dw_hdmi
->hdmitx
+ HDMITX_DWC_ADDR_REG
);
238 writel(addr
& 0xffff, dw_hdmi
->hdmitx
+ HDMITX_DWC_ADDR_REG
);
240 /* Write needs single DATA write */
241 writel(data
, dw_hdmi
->hdmitx
+ HDMITX_DWC_DATA_REG
);
243 spin_unlock_irqrestore(®_lock
, flags
);
246 /* Helper to change specific bits in controller registers */
247 static inline void dw_hdmi_dwc_write_bits(struct meson_dw_hdmi
*dw_hdmi
,
252 unsigned int data
= dw_hdmi_dwc_read(dw_hdmi
, addr
);
257 dw_hdmi_dwc_write(dw_hdmi
, addr
, data
);
262 /* Setup PHY bandwidth modes */
263 static void meson_hdmi_phy_setup_mode(struct meson_dw_hdmi
*dw_hdmi
,
264 struct drm_display_mode
*mode
)
266 struct meson_drm
*priv
= dw_hdmi
->priv
;
267 unsigned int pixel_clock
= mode
->clock
;
269 if (dw_hdmi_is_compatible(dw_hdmi
, "amlogic,meson-gxl-dw-hdmi") ||
270 dw_hdmi_is_compatible(dw_hdmi
, "amlogic,meson-gxm-dw-hdmi")) {
271 if (pixel_clock
>= 371250) {
272 /* 5.94Gbps, 3.7125Gbps */
273 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL0
, 0x333d3282);
274 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL3
, 0x2136315b);
275 } else if (pixel_clock
>= 297000) {
277 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL0
, 0x33303382);
278 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL3
, 0x2036315b);
279 } else if (pixel_clock
>= 148500) {
281 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL0
, 0x33303362);
282 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL3
, 0x2016315b);
284 /* 742.5Mbps, and below */
285 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL0
, 0x33604142);
286 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL3
, 0x0016315b);
288 } else if (dw_hdmi_is_compatible(dw_hdmi
,
289 "amlogic,meson-gxbb-dw-hdmi")) {
290 if (pixel_clock
>= 371250) {
291 /* 5.94Gbps, 3.7125Gbps */
292 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL0
, 0x33353245);
293 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL3
, 0x2100115b);
294 } else if (pixel_clock
>= 297000) {
296 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL0
, 0x33634283);
297 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL3
, 0xb000115b);
299 /* 1.485Gbps, and below */
300 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL0
, 0x33632122);
301 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL3
, 0x2000115b);
306 static inline void meson_dw_hdmi_phy_reset(struct meson_dw_hdmi
*dw_hdmi
)
308 struct meson_drm
*priv
= dw_hdmi
->priv
;
310 /* Enable and software reset */
311 regmap_update_bits(priv
->hhi
, HHI_HDMI_PHY_CNTL1
, 0xf, 0xf);
315 /* Enable and unreset */
316 regmap_update_bits(priv
->hhi
, HHI_HDMI_PHY_CNTL1
, 0xf, 0xe);
321 static void dw_hdmi_set_vclk(struct meson_dw_hdmi
*dw_hdmi
,
322 struct drm_display_mode
*mode
)
324 struct meson_drm
*priv
= dw_hdmi
->priv
;
325 int vic
= drm_match_cea_mode(mode
);
326 unsigned int vclk_freq
;
327 unsigned int venc_freq
;
328 unsigned int hdmi_freq
;
330 vclk_freq
= mode
->clock
;
333 meson_vclk_setup(priv
, MESON_VCLK_TARGET_DMT
, vclk_freq
,
334 vclk_freq
, vclk_freq
, false);
338 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
341 venc_freq
= vclk_freq
;
342 hdmi_freq
= vclk_freq
;
344 if (meson_venc_hdmi_venc_repeat(vic
))
347 vclk_freq
= max(venc_freq
, hdmi_freq
);
349 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
352 DRM_DEBUG_DRIVER("vclk:%d venc=%d hdmi=%d enci=%d\n",
353 vclk_freq
, venc_freq
, hdmi_freq
,
354 priv
->venc
.hdmi_use_enci
);
356 meson_vclk_setup(priv
, MESON_VCLK_TARGET_HDMI
, vclk_freq
,
357 venc_freq
, hdmi_freq
, priv
->venc
.hdmi_use_enci
);
360 static int dw_hdmi_phy_init(struct dw_hdmi
*hdmi
, void *data
,
361 struct drm_display_mode
*mode
)
363 struct meson_dw_hdmi
*dw_hdmi
= (struct meson_dw_hdmi
*)data
;
364 struct meson_drm
*priv
= dw_hdmi
->priv
;
365 unsigned int wr_clk
=
366 readl_relaxed(priv
->io_base
+ _REG(VPU_HDMI_SETTING
));
368 DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode
->name
,
369 mode
->clock
> 340000 ? 40 : 10);
372 regmap_update_bits(priv
->hhi
, HHI_HDMI_CLK_CNTL
, 0xffff, 0x100);
374 /* Bring HDMITX MEM output of power down */
375 regmap_update_bits(priv
->hhi
, HHI_MEM_PD_REG0
, 0xff << 8, 0);
377 /* Bring out of reset */
378 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_SW_RESET
, 0);
380 /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
381 dw_hdmi_top_write_bits(dw_hdmi
, HDMITX_TOP_CLK_CNTL
,
383 dw_hdmi_top_write_bits(dw_hdmi
, HDMITX_TOP_CLK_CNTL
,
386 /* Enable normal output to PHY */
387 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_BIST_CNTL
, BIT(12));
389 /* TMDS pattern setup (TOFIX Handle the YUV420 case) */
390 if (mode
->clock
> 340000) {
391 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_TMDS_CLK_PTTN_01
, 0);
392 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_TMDS_CLK_PTTN_23
,
395 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_TMDS_CLK_PTTN_01
,
397 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_TMDS_CLK_PTTN_23
,
401 /* Load TMDS pattern */
402 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_TMDS_CLK_PTTN_CNTL
, 0x1);
404 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_TMDS_CLK_PTTN_CNTL
, 0x2);
406 /* Setup PHY parameters */
407 meson_hdmi_phy_setup_mode(dw_hdmi
, mode
);
410 regmap_update_bits(priv
->hhi
, HHI_HDMI_PHY_CNTL1
,
411 0xffff << 16, 0x0390 << 16);
414 if (dw_hdmi_is_compatible(dw_hdmi
, "amlogic,meson-gxl-dw-hdmi") ||
415 dw_hdmi_is_compatible(dw_hdmi
, "amlogic,meson-gxm-dw-hdmi"))
416 regmap_update_bits(priv
->hhi
, HHI_HDMI_PHY_CNTL1
,
419 regmap_update_bits(priv
->hhi
, HHI_HDMI_PHY_CNTL1
,
422 /* Disable clock, fifo, fifo_wr */
423 regmap_update_bits(priv
->hhi
, HHI_HDMI_PHY_CNTL1
, 0xf, 0);
425 dw_hdmi_set_high_tmds_clock_ratio(hdmi
);
429 /* Reset PHY 3 times in a row */
430 meson_dw_hdmi_phy_reset(dw_hdmi
);
431 meson_dw_hdmi_phy_reset(dw_hdmi
);
432 meson_dw_hdmi_phy_reset(dw_hdmi
);
434 /* Temporary Disable VENC video stream */
435 if (priv
->venc
.hdmi_use_enci
)
436 writel_relaxed(0, priv
->io_base
+ _REG(ENCI_VIDEO_EN
));
438 writel_relaxed(0, priv
->io_base
+ _REG(ENCP_VIDEO_EN
));
440 /* Temporary Disable HDMI video stream to HDMI-TX */
441 writel_bits_relaxed(0x3, 0,
442 priv
->io_base
+ _REG(VPU_HDMI_SETTING
));
443 writel_bits_relaxed(0xf << 8, 0,
444 priv
->io_base
+ _REG(VPU_HDMI_SETTING
));
446 /* Re-Enable VENC video stream */
447 if (priv
->venc
.hdmi_use_enci
)
448 writel_relaxed(1, priv
->io_base
+ _REG(ENCI_VIDEO_EN
));
450 writel_relaxed(1, priv
->io_base
+ _REG(ENCP_VIDEO_EN
));
452 /* Push back HDMI clock settings */
453 writel_bits_relaxed(0xf << 8, wr_clk
& (0xf << 8),
454 priv
->io_base
+ _REG(VPU_HDMI_SETTING
));
456 /* Enable and Select HDMI video source for HDMI-TX */
457 if (priv
->venc
.hdmi_use_enci
)
458 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI
,
459 priv
->io_base
+ _REG(VPU_HDMI_SETTING
));
461 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP
,
462 priv
->io_base
+ _REG(VPU_HDMI_SETTING
));
467 static void dw_hdmi_phy_disable(struct dw_hdmi
*hdmi
,
470 struct meson_dw_hdmi
*dw_hdmi
= (struct meson_dw_hdmi
*)data
;
471 struct meson_drm
*priv
= dw_hdmi
->priv
;
473 DRM_DEBUG_DRIVER("\n");
475 regmap_write(priv
->hhi
, HHI_HDMI_PHY_CNTL0
, 0);
478 static enum drm_connector_status
dw_hdmi_read_hpd(struct dw_hdmi
*hdmi
,
481 struct meson_dw_hdmi
*dw_hdmi
= (struct meson_dw_hdmi
*)data
;
483 return !!dw_hdmi_top_read(dw_hdmi
, HDMITX_TOP_STAT0
) ?
484 connector_status_connected
: connector_status_disconnected
;
487 static void dw_hdmi_setup_hpd(struct dw_hdmi
*hdmi
,
490 struct meson_dw_hdmi
*dw_hdmi
= (struct meson_dw_hdmi
*)data
;
492 /* Setup HPD Filter */
493 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_HPD_FILTER
,
496 /* Clear interrupts */
497 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_INTR_STAT_CLR
,
498 HDMITX_TOP_INTR_HPD_RISE
| HDMITX_TOP_INTR_HPD_FALL
);
500 /* Unmask interrupts */
501 dw_hdmi_top_write_bits(dw_hdmi
, HDMITX_TOP_INTR_MASKN
,
502 HDMITX_TOP_INTR_HPD_RISE
| HDMITX_TOP_INTR_HPD_FALL
,
503 HDMITX_TOP_INTR_HPD_RISE
| HDMITX_TOP_INTR_HPD_FALL
);
506 static const struct dw_hdmi_phy_ops meson_dw_hdmi_phy_ops
= {
507 .init
= dw_hdmi_phy_init
,
508 .disable
= dw_hdmi_phy_disable
,
509 .read_hpd
= dw_hdmi_read_hpd
,
510 .setup_hpd
= dw_hdmi_setup_hpd
,
513 static irqreturn_t
dw_hdmi_top_irq(int irq
, void *dev_id
)
515 struct meson_dw_hdmi
*dw_hdmi
= dev_id
;
518 stat
= dw_hdmi_top_read(dw_hdmi
, HDMITX_TOP_INTR_STAT
);
519 dw_hdmi_top_write(dw_hdmi
, HDMITX_TOP_INTR_STAT_CLR
, stat
);
521 /* HPD Events, handle in the threaded interrupt handler */
522 if (stat
& (HDMITX_TOP_INTR_HPD_RISE
| HDMITX_TOP_INTR_HPD_FALL
)) {
523 dw_hdmi
->irq_stat
= stat
;
524 return IRQ_WAKE_THREAD
;
527 /* HDMI Controller Interrupt */
531 /* TOFIX Handle HDCP Interrupts */
536 /* Threaded interrupt handler to manage HPD events */
537 static irqreturn_t
dw_hdmi_top_thread_irq(int irq
, void *dev_id
)
539 struct meson_dw_hdmi
*dw_hdmi
= dev_id
;
540 u32 stat
= dw_hdmi
->irq_stat
;
543 if (stat
& (HDMITX_TOP_INTR_HPD_RISE
| HDMITX_TOP_INTR_HPD_FALL
)) {
544 bool hpd_connected
= false;
546 if (stat
& HDMITX_TOP_INTR_HPD_RISE
)
547 hpd_connected
= true;
549 dw_hdmi_setup_rx_sense(dw_hdmi
->hdmi
, hpd_connected
,
552 drm_helper_hpd_irq_event(dw_hdmi
->encoder
.dev
);
558 static enum drm_mode_status
559 dw_hdmi_mode_valid(struct drm_connector
*connector
,
560 const struct drm_display_mode
*mode
)
562 struct meson_drm
*priv
= connector
->dev
->dev_private
;
563 unsigned int vclk_freq
;
564 unsigned int venc_freq
;
565 unsigned int hdmi_freq
;
566 int vic
= drm_match_cea_mode(mode
);
567 enum drm_mode_status status
;
569 DRM_DEBUG_DRIVER("Modeline " DRM_MODE_FMT
"\n", DRM_MODE_ARG(mode
));
571 /* If sink max TMDS clock, we reject the mode */
572 if (mode
->clock
> connector
->display_info
.max_tmds_clock
)
575 /* Check against non-VIC supported modes */
577 status
= meson_venc_hdmi_supported_mode(mode
);
578 if (status
!= MODE_OK
)
581 return meson_vclk_dmt_supported_freq(priv
, mode
->clock
);
582 /* Check against supported VIC modes */
583 } else if (!meson_venc_hdmi_supported_vic(vic
))
586 vclk_freq
= mode
->clock
;
588 /* 480i/576i needs global pixel doubling */
589 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
592 venc_freq
= vclk_freq
;
593 hdmi_freq
= vclk_freq
;
595 /* VENC double pixels for 1080i and 720p modes */
596 if (meson_venc_hdmi_venc_repeat(vic
))
599 vclk_freq
= max(venc_freq
, hdmi_freq
);
601 if (mode
->flags
& DRM_MODE_FLAG_DBLCLK
)
604 dev_dbg(connector
->dev
->dev
, "%s: vclk:%d venc=%d hdmi=%d\n", __func__
,
605 vclk_freq
, venc_freq
, hdmi_freq
);
607 return meson_vclk_vic_supported_freq(vclk_freq
);
612 static void meson_venc_hdmi_encoder_destroy(struct drm_encoder
*encoder
)
614 drm_encoder_cleanup(encoder
);
617 static const struct drm_encoder_funcs meson_venc_hdmi_encoder_funcs
= {
618 .destroy
= meson_venc_hdmi_encoder_destroy
,
621 static int meson_venc_hdmi_encoder_atomic_check(struct drm_encoder
*encoder
,
622 struct drm_crtc_state
*crtc_state
,
623 struct drm_connector_state
*conn_state
)
628 static void meson_venc_hdmi_encoder_disable(struct drm_encoder
*encoder
)
630 struct meson_dw_hdmi
*dw_hdmi
= encoder_to_meson_dw_hdmi(encoder
);
631 struct meson_drm
*priv
= dw_hdmi
->priv
;
633 DRM_DEBUG_DRIVER("\n");
635 writel_bits_relaxed(0x3, 0,
636 priv
->io_base
+ _REG(VPU_HDMI_SETTING
));
638 writel_relaxed(0, priv
->io_base
+ _REG(ENCI_VIDEO_EN
));
639 writel_relaxed(0, priv
->io_base
+ _REG(ENCP_VIDEO_EN
));
642 static void meson_venc_hdmi_encoder_enable(struct drm_encoder
*encoder
)
644 struct meson_dw_hdmi
*dw_hdmi
= encoder_to_meson_dw_hdmi(encoder
);
645 struct meson_drm
*priv
= dw_hdmi
->priv
;
647 DRM_DEBUG_DRIVER("%s\n", priv
->venc
.hdmi_use_enci
? "VENCI" : "VENCP");
649 if (priv
->venc
.hdmi_use_enci
)
650 writel_relaxed(1, priv
->io_base
+ _REG(ENCI_VIDEO_EN
));
652 writel_relaxed(1, priv
->io_base
+ _REG(ENCP_VIDEO_EN
));
655 static void meson_venc_hdmi_encoder_mode_set(struct drm_encoder
*encoder
,
656 struct drm_display_mode
*mode
,
657 struct drm_display_mode
*adjusted_mode
)
659 struct meson_dw_hdmi
*dw_hdmi
= encoder_to_meson_dw_hdmi(encoder
);
660 struct meson_drm
*priv
= dw_hdmi
->priv
;
661 int vic
= drm_match_cea_mode(mode
);
663 DRM_DEBUG_DRIVER("\"%s\" vic %d\n", mode
->name
, vic
);
665 /* VENC + VENC-DVI Mode setup */
666 meson_venc_hdmi_mode_set(priv
, vic
, mode
);
669 dw_hdmi_set_vclk(dw_hdmi
, mode
);
671 /* Setup YUV444 to HDMI-TX, no 10bit diphering */
672 writel_relaxed(0, priv
->io_base
+ _REG(VPU_HDMI_FMT_CTRL
));
675 static const struct drm_encoder_helper_funcs
676 meson_venc_hdmi_encoder_helper_funcs
= {
677 .atomic_check
= meson_venc_hdmi_encoder_atomic_check
,
678 .disable
= meson_venc_hdmi_encoder_disable
,
679 .enable
= meson_venc_hdmi_encoder_enable
,
680 .mode_set
= meson_venc_hdmi_encoder_mode_set
,
685 static int meson_dw_hdmi_reg_read(void *context
, unsigned int reg
,
686 unsigned int *result
)
688 *result
= dw_hdmi_dwc_read(context
, reg
);
694 static int meson_dw_hdmi_reg_write(void *context
, unsigned int reg
,
697 dw_hdmi_dwc_write(context
, reg
, val
);
702 static const struct regmap_config meson_dw_hdmi_regmap_config
= {
705 .reg_read
= meson_dw_hdmi_reg_read
,
706 .reg_write
= meson_dw_hdmi_reg_write
,
707 .max_register
= 0x10000,
711 static bool meson_hdmi_connector_is_available(struct device
*dev
)
713 struct device_node
*ep
, *remote
;
715 /* HDMI Connector is on the second port, first endpoint */
716 ep
= of_graph_get_endpoint_by_regs(dev
->of_node
, 1, 0);
720 /* If the endpoint node exists, consider it enabled */
721 remote
= of_graph_get_remote_port(ep
);
733 static int meson_dw_hdmi_bind(struct device
*dev
, struct device
*master
,
736 struct platform_device
*pdev
= to_platform_device(dev
);
737 struct meson_dw_hdmi
*meson_dw_hdmi
;
738 struct drm_device
*drm
= data
;
739 struct meson_drm
*priv
= drm
->dev_private
;
740 struct dw_hdmi_plat_data
*dw_plat_data
;
741 struct drm_encoder
*encoder
;
742 struct resource
*res
;
746 DRM_DEBUG_DRIVER("\n");
748 if (!meson_hdmi_connector_is_available(dev
)) {
749 dev_info(drm
->dev
, "HDMI Output connector not available\n");
753 meson_dw_hdmi
= devm_kzalloc(dev
, sizeof(*meson_dw_hdmi
),
758 meson_dw_hdmi
->priv
= priv
;
759 meson_dw_hdmi
->dev
= dev
;
760 dw_plat_data
= &meson_dw_hdmi
->dw_plat_data
;
761 encoder
= &meson_dw_hdmi
->encoder
;
763 meson_dw_hdmi
->hdmi_supply
= devm_regulator_get_optional(dev
, "hdmi");
764 if (IS_ERR(meson_dw_hdmi
->hdmi_supply
)) {
765 if (PTR_ERR(meson_dw_hdmi
->hdmi_supply
) == -EPROBE_DEFER
)
766 return -EPROBE_DEFER
;
767 meson_dw_hdmi
->hdmi_supply
= NULL
;
769 ret
= regulator_enable(meson_dw_hdmi
->hdmi_supply
);
774 meson_dw_hdmi
->hdmitx_apb
= devm_reset_control_get_exclusive(dev
,
776 if (IS_ERR(meson_dw_hdmi
->hdmitx_apb
)) {
777 dev_err(dev
, "Failed to get hdmitx_apb reset\n");
778 return PTR_ERR(meson_dw_hdmi
->hdmitx_apb
);
781 meson_dw_hdmi
->hdmitx_ctrl
= devm_reset_control_get_exclusive(dev
,
783 if (IS_ERR(meson_dw_hdmi
->hdmitx_ctrl
)) {
784 dev_err(dev
, "Failed to get hdmitx reset\n");
785 return PTR_ERR(meson_dw_hdmi
->hdmitx_ctrl
);
788 meson_dw_hdmi
->hdmitx_phy
= devm_reset_control_get_exclusive(dev
,
790 if (IS_ERR(meson_dw_hdmi
->hdmitx_phy
)) {
791 dev_err(dev
, "Failed to get hdmitx_phy reset\n");
792 return PTR_ERR(meson_dw_hdmi
->hdmitx_phy
);
795 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
796 meson_dw_hdmi
->hdmitx
= devm_ioremap_resource(dev
, res
);
797 if (IS_ERR(meson_dw_hdmi
->hdmitx
))
798 return PTR_ERR(meson_dw_hdmi
->hdmitx
);
800 meson_dw_hdmi
->hdmi_pclk
= devm_clk_get(dev
, "isfr");
801 if (IS_ERR(meson_dw_hdmi
->hdmi_pclk
)) {
802 dev_err(dev
, "Unable to get HDMI pclk\n");
803 return PTR_ERR(meson_dw_hdmi
->hdmi_pclk
);
805 clk_prepare_enable(meson_dw_hdmi
->hdmi_pclk
);
807 meson_dw_hdmi
->venci_clk
= devm_clk_get(dev
, "venci");
808 if (IS_ERR(meson_dw_hdmi
->venci_clk
)) {
809 dev_err(dev
, "Unable to get venci clk\n");
810 return PTR_ERR(meson_dw_hdmi
->venci_clk
);
812 clk_prepare_enable(meson_dw_hdmi
->venci_clk
);
814 dw_plat_data
->regm
= devm_regmap_init(dev
, NULL
, meson_dw_hdmi
,
815 &meson_dw_hdmi_regmap_config
);
816 if (IS_ERR(dw_plat_data
->regm
))
817 return PTR_ERR(dw_plat_data
->regm
);
819 irq
= platform_get_irq(pdev
, 0);
821 dev_err(dev
, "Failed to get hdmi top irq\n");
825 ret
= devm_request_threaded_irq(dev
, irq
, dw_hdmi_top_irq
,
826 dw_hdmi_top_thread_irq
, IRQF_SHARED
,
827 "dw_hdmi_top_irq", meson_dw_hdmi
);
829 dev_err(dev
, "Failed to request hdmi top irq\n");
835 drm_encoder_helper_add(encoder
, &meson_venc_hdmi_encoder_helper_funcs
);
837 ret
= drm_encoder_init(drm
, encoder
, &meson_venc_hdmi_encoder_funcs
,
838 DRM_MODE_ENCODER_TMDS
, "meson_hdmi");
840 dev_err(priv
->dev
, "Failed to init HDMI encoder\n");
844 encoder
->possible_crtcs
= BIT(0);
846 DRM_DEBUG_DRIVER("encoder initialized\n");
849 regmap_update_bits(priv
->hhi
, HHI_HDMI_CLK_CNTL
, 0xffff, 0x100);
851 /* Bring HDMITX MEM output of power down */
852 regmap_update_bits(priv
->hhi
, HHI_MEM_PD_REG0
, 0xff << 8, 0);
854 /* Reset HDMITX APB & TX & PHY */
855 reset_control_reset(meson_dw_hdmi
->hdmitx_apb
);
856 reset_control_reset(meson_dw_hdmi
->hdmitx_ctrl
);
857 reset_control_reset(meson_dw_hdmi
->hdmitx_phy
);
859 /* Enable APB3 fail on error */
860 writel_bits_relaxed(BIT(15), BIT(15),
861 meson_dw_hdmi
->hdmitx
+ HDMITX_TOP_CTRL_REG
);
862 writel_bits_relaxed(BIT(15), BIT(15),
863 meson_dw_hdmi
->hdmitx
+ HDMITX_DWC_CTRL_REG
);
865 /* Bring out of reset */
866 dw_hdmi_top_write(meson_dw_hdmi
, HDMITX_TOP_SW_RESET
, 0);
870 dw_hdmi_top_write(meson_dw_hdmi
, HDMITX_TOP_CLK_CNTL
, 0xff);
872 /* Enable HDMI-TX Interrupt */
873 dw_hdmi_top_write(meson_dw_hdmi
, HDMITX_TOP_INTR_STAT_CLR
,
874 HDMITX_TOP_INTR_CORE
);
876 dw_hdmi_top_write(meson_dw_hdmi
, HDMITX_TOP_INTR_MASKN
,
877 HDMITX_TOP_INTR_CORE
);
879 /* Bridge / Connector */
881 dw_plat_data
->mode_valid
= dw_hdmi_mode_valid
;
882 dw_plat_data
->phy_ops
= &meson_dw_hdmi_phy_ops
;
883 dw_plat_data
->phy_name
= "meson_dw_hdmi_phy";
884 dw_plat_data
->phy_data
= meson_dw_hdmi
;
885 dw_plat_data
->input_bus_format
= MEDIA_BUS_FMT_YUV8_1X24
;
886 dw_plat_data
->input_bus_encoding
= V4L2_YCBCR_ENC_709
;
888 platform_set_drvdata(pdev
, meson_dw_hdmi
);
890 meson_dw_hdmi
->hdmi
= dw_hdmi_bind(pdev
, encoder
,
891 &meson_dw_hdmi
->dw_plat_data
);
892 if (IS_ERR(meson_dw_hdmi
->hdmi
))
893 return PTR_ERR(meson_dw_hdmi
->hdmi
);
895 DRM_DEBUG_DRIVER("HDMI controller initialized\n");
900 static void meson_dw_hdmi_unbind(struct device
*dev
, struct device
*master
,
903 struct meson_dw_hdmi
*meson_dw_hdmi
= dev_get_drvdata(dev
);
905 dw_hdmi_unbind(meson_dw_hdmi
->hdmi
);
908 static const struct component_ops meson_dw_hdmi_ops
= {
909 .bind
= meson_dw_hdmi_bind
,
910 .unbind
= meson_dw_hdmi_unbind
,
913 static int meson_dw_hdmi_probe(struct platform_device
*pdev
)
915 return component_add(&pdev
->dev
, &meson_dw_hdmi_ops
);
918 static int meson_dw_hdmi_remove(struct platform_device
*pdev
)
920 component_del(&pdev
->dev
, &meson_dw_hdmi_ops
);
925 static const struct of_device_id meson_dw_hdmi_of_table
[] = {
926 { .compatible
= "amlogic,meson-gxbb-dw-hdmi" },
927 { .compatible
= "amlogic,meson-gxl-dw-hdmi" },
928 { .compatible
= "amlogic,meson-gxm-dw-hdmi" },
931 MODULE_DEVICE_TABLE(of
, meson_dw_hdmi_of_table
);
933 static struct platform_driver meson_dw_hdmi_platform_driver
= {
934 .probe
= meson_dw_hdmi_probe
,
935 .remove
= meson_dw_hdmi_remove
,
938 .of_match_table
= meson_dw_hdmi_of_table
,
941 module_platform_driver(meson_dw_hdmi_platform_driver
);
943 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
944 MODULE_DESCRIPTION(DRIVER_DESC
);
945 MODULE_LICENSE("GPL");