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drm: Move drm_crtc_init from drm_crtc.h to drm_plane_helper.h
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / mgag200 / mgag200_mode.c
1 /*
2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
4 *
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
8 *
9 * Authors: Matthew Garrett
10 * Matt Turner
11 * Dave Airlie
12 */
13
14 #include <linux/delay.h>
15
16 #include <drm/drmP.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_plane_helper.h>
19
20 #include "mgag200_drv.h"
21
22 #define MGAG200_LUT_SIZE 256
23
24 /*
25 * This file contains setup code for the CRTC.
26 */
27
28 static void mga_crtc_load_lut(struct drm_crtc *crtc)
29 {
30 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
31 struct drm_device *dev = crtc->dev;
32 struct mga_device *mdev = dev->dev_private;
33 struct drm_framebuffer *fb = crtc->primary->fb;
34 int i;
35
36 if (!crtc->enabled)
37 return;
38
39 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
40
41 if (fb && fb->bits_per_pixel == 16) {
42 int inc = (fb->depth == 15) ? 8 : 4;
43 u8 r, b;
44 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
45 if (fb->depth == 16) {
46 if (i > (MGAG200_LUT_SIZE >> 1)) {
47 r = b = 0;
48 } else {
49 r = mga_crtc->lut_r[i << 1];
50 b = mga_crtc->lut_b[i << 1];
51 }
52 } else {
53 r = mga_crtc->lut_r[i];
54 b = mga_crtc->lut_b[i];
55 }
56 /* VGA registers */
57 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
58 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
59 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
60 }
61 return;
62 }
63 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
64 /* VGA registers */
65 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
66 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
67 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
68 }
69 }
70
71 static inline void mga_wait_vsync(struct mga_device *mdev)
72 {
73 unsigned long timeout = jiffies + HZ/10;
74 unsigned int status = 0;
75
76 do {
77 status = RREG32(MGAREG_Status);
78 } while ((status & 0x08) && time_before(jiffies, timeout));
79 timeout = jiffies + HZ/10;
80 status = 0;
81 do {
82 status = RREG32(MGAREG_Status);
83 } while (!(status & 0x08) && time_before(jiffies, timeout));
84 }
85
86 static inline void mga_wait_busy(struct mga_device *mdev)
87 {
88 unsigned long timeout = jiffies + HZ;
89 unsigned int status = 0;
90 do {
91 status = RREG8(MGAREG_Status + 2);
92 } while ((status & 0x01) && time_before(jiffies, timeout));
93 }
94
95 /*
96 * The core passes the desired mode to the CRTC code to see whether any
97 * CRTC-specific modifications need to be made to it. We're in a position
98 * to just pass that straight through, so this does nothing
99 */
100 static bool mga_crtc_mode_fixup(struct drm_crtc *crtc,
101 const struct drm_display_mode *mode,
102 struct drm_display_mode *adjusted_mode)
103 {
104 return true;
105 }
106
107 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
108 {
109 unsigned int vcomax, vcomin, pllreffreq;
110 unsigned int delta, tmpdelta, permitteddelta;
111 unsigned int testp, testm, testn;
112 unsigned int p, m, n;
113 unsigned int computed;
114
115 m = n = p = 0;
116 vcomax = 320000;
117 vcomin = 160000;
118 pllreffreq = 25000;
119
120 delta = 0xffffffff;
121 permitteddelta = clock * 5 / 1000;
122
123 for (testp = 8; testp > 0; testp /= 2) {
124 if (clock * testp > vcomax)
125 continue;
126 if (clock * testp < vcomin)
127 continue;
128
129 for (testn = 17; testn < 256; testn++) {
130 for (testm = 1; testm < 32; testm++) {
131 computed = (pllreffreq * testn) /
132 (testm * testp);
133 if (computed > clock)
134 tmpdelta = computed - clock;
135 else
136 tmpdelta = clock - computed;
137 if (tmpdelta < delta) {
138 delta = tmpdelta;
139 m = testm - 1;
140 n = testn - 1;
141 p = testp - 1;
142 }
143 }
144 }
145 }
146
147 if (delta > permitteddelta) {
148 printk(KERN_WARNING "PLL delta too large\n");
149 return 1;
150 }
151
152 WREG_DAC(MGA1064_PIX_PLLC_M, m);
153 WREG_DAC(MGA1064_PIX_PLLC_N, n);
154 WREG_DAC(MGA1064_PIX_PLLC_P, p);
155 return 0;
156 }
157
158 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
159 {
160 unsigned int vcomax, vcomin, pllreffreq;
161 unsigned int delta, tmpdelta, permitteddelta;
162 unsigned int testp, testm, testn;
163 unsigned int p, m, n;
164 unsigned int computed;
165 int i, j, tmpcount, vcount;
166 bool pll_locked = false;
167 u8 tmp;
168
169 m = n = p = 0;
170 vcomax = 550000;
171 vcomin = 150000;
172 pllreffreq = 48000;
173
174 delta = 0xffffffff;
175 permitteddelta = clock * 5 / 1000;
176
177 for (testp = 1; testp < 9; testp++) {
178 if (clock * testp > vcomax)
179 continue;
180 if (clock * testp < vcomin)
181 continue;
182
183 for (testm = 1; testm < 17; testm++) {
184 for (testn = 1; testn < 151; testn++) {
185 computed = (pllreffreq * testn) /
186 (testm * testp);
187 if (computed > clock)
188 tmpdelta = computed - clock;
189 else
190 tmpdelta = clock - computed;
191 if (tmpdelta < delta) {
192 delta = tmpdelta;
193 n = testn - 1;
194 m = (testm - 1) | ((n >> 1) & 0x80);
195 p = testp - 1;
196 }
197 }
198 }
199 }
200
201 for (i = 0; i <= 32 && pll_locked == false; i++) {
202 if (i > 0) {
203 WREG8(MGAREG_CRTC_INDEX, 0x1e);
204 tmp = RREG8(MGAREG_CRTC_DATA);
205 if (tmp < 0xff)
206 WREG8(MGAREG_CRTC_DATA, tmp+1);
207 }
208
209 /* set pixclkdis to 1 */
210 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
211 tmp = RREG8(DAC_DATA);
212 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
213 WREG8(DAC_DATA, tmp);
214
215 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
216 tmp = RREG8(DAC_DATA);
217 tmp |= MGA1064_REMHEADCTL_CLKDIS;
218 WREG8(DAC_DATA, tmp);
219
220 /* select PLL Set C */
221 tmp = RREG8(MGAREG_MEM_MISC_READ);
222 tmp |= 0x3 << 2;
223 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
224
225 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
226 tmp = RREG8(DAC_DATA);
227 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
228 WREG8(DAC_DATA, tmp);
229
230 udelay(500);
231
232 /* reset the PLL */
233 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
234 tmp = RREG8(DAC_DATA);
235 tmp &= ~0x04;
236 WREG8(DAC_DATA, tmp);
237
238 udelay(50);
239
240 /* program pixel pll register */
241 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
242 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
243 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
244
245 udelay(50);
246
247 /* turn pll on */
248 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
249 tmp = RREG8(DAC_DATA);
250 tmp |= 0x04;
251 WREG_DAC(MGA1064_VREF_CTL, tmp);
252
253 udelay(500);
254
255 /* select the pixel pll */
256 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
257 tmp = RREG8(DAC_DATA);
258 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
259 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
260 WREG8(DAC_DATA, tmp);
261
262 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
263 tmp = RREG8(DAC_DATA);
264 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
265 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
266 WREG8(DAC_DATA, tmp);
267
268 /* reset dotclock rate bit */
269 WREG8(MGAREG_SEQ_INDEX, 1);
270 tmp = RREG8(MGAREG_SEQ_DATA);
271 tmp &= ~0x8;
272 WREG8(MGAREG_SEQ_DATA, tmp);
273
274 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
275 tmp = RREG8(DAC_DATA);
276 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
277 WREG8(DAC_DATA, tmp);
278
279 vcount = RREG8(MGAREG_VCOUNT);
280
281 for (j = 0; j < 30 && pll_locked == false; j++) {
282 tmpcount = RREG8(MGAREG_VCOUNT);
283 if (tmpcount < vcount)
284 vcount = 0;
285 if ((tmpcount - vcount) > 2)
286 pll_locked = true;
287 else
288 udelay(5);
289 }
290 }
291 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
292 tmp = RREG8(DAC_DATA);
293 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
294 WREG_DAC(MGA1064_REMHEADCTL, tmp);
295 return 0;
296 }
297
298 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
299 {
300 unsigned int vcomax, vcomin, pllreffreq;
301 unsigned int delta, tmpdelta, permitteddelta;
302 unsigned int testp, testm, testn;
303 unsigned int p, m, n;
304 unsigned int computed;
305 u8 tmp;
306
307 m = n = p = 0;
308 vcomax = 550000;
309 vcomin = 150000;
310 pllreffreq = 50000;
311
312 delta = 0xffffffff;
313 permitteddelta = clock * 5 / 1000;
314
315 for (testp = 16; testp > 0; testp--) {
316 if (clock * testp > vcomax)
317 continue;
318 if (clock * testp < vcomin)
319 continue;
320
321 for (testn = 1; testn < 257; testn++) {
322 for (testm = 1; testm < 17; testm++) {
323 computed = (pllreffreq * testn) /
324 (testm * testp);
325 if (computed > clock)
326 tmpdelta = computed - clock;
327 else
328 tmpdelta = clock - computed;
329 if (tmpdelta < delta) {
330 delta = tmpdelta;
331 n = testn - 1;
332 m = testm - 1;
333 p = testp - 1;
334 }
335 }
336 }
337 }
338
339 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
340 tmp = RREG8(DAC_DATA);
341 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
342 WREG8(DAC_DATA, tmp);
343
344 tmp = RREG8(MGAREG_MEM_MISC_READ);
345 tmp |= 0x3 << 2;
346 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
347
348 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
349 tmp = RREG8(DAC_DATA);
350 WREG8(DAC_DATA, tmp & ~0x40);
351
352 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
353 tmp = RREG8(DAC_DATA);
354 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
355 WREG8(DAC_DATA, tmp);
356
357 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
358 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
359 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
360
361 udelay(50);
362
363 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
364 tmp = RREG8(DAC_DATA);
365 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
366 WREG8(DAC_DATA, tmp);
367
368 udelay(500);
369
370 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
371 tmp = RREG8(DAC_DATA);
372 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
373 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
374 WREG8(DAC_DATA, tmp);
375
376 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
377 tmp = RREG8(DAC_DATA);
378 WREG8(DAC_DATA, tmp | 0x40);
379
380 tmp = RREG8(MGAREG_MEM_MISC_READ);
381 tmp |= (0x3 << 2);
382 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
383
384 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
385 tmp = RREG8(DAC_DATA);
386 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
387 WREG8(DAC_DATA, tmp);
388
389 return 0;
390 }
391
392 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
393 {
394 unsigned int vcomax, vcomin, pllreffreq;
395 unsigned int delta, tmpdelta, permitteddelta;
396 unsigned int testp, testm, testn;
397 unsigned int p, m, n;
398 unsigned int computed;
399 int i, j, tmpcount, vcount;
400 u8 tmp;
401 bool pll_locked = false;
402
403 m = n = p = 0;
404 vcomax = 800000;
405 vcomin = 400000;
406 pllreffreq = 33333;
407
408 delta = 0xffffffff;
409 permitteddelta = clock * 5 / 1000;
410
411 for (testp = 16; testp > 0; testp >>= 1) {
412 if (clock * testp > vcomax)
413 continue;
414 if (clock * testp < vcomin)
415 continue;
416
417 for (testm = 1; testm < 33; testm++) {
418 for (testn = 17; testn < 257; testn++) {
419 computed = (pllreffreq * testn) /
420 (testm * testp);
421 if (computed > clock)
422 tmpdelta = computed - clock;
423 else
424 tmpdelta = clock - computed;
425 if (tmpdelta < delta) {
426 delta = tmpdelta;
427 n = testn - 1;
428 m = (testm - 1);
429 p = testp - 1;
430 }
431 if ((clock * testp) >= 600000)
432 p |= 0x80;
433 }
434 }
435 }
436 for (i = 0; i <= 32 && pll_locked == false; i++) {
437 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
438 tmp = RREG8(DAC_DATA);
439 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
440 WREG8(DAC_DATA, tmp);
441
442 tmp = RREG8(MGAREG_MEM_MISC_READ);
443 tmp |= 0x3 << 2;
444 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
445
446 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
447 tmp = RREG8(DAC_DATA);
448 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
449 WREG8(DAC_DATA, tmp);
450
451 udelay(500);
452
453 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
454 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
455 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
456
457 udelay(500);
458
459 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
460 tmp = RREG8(DAC_DATA);
461 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
462 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
463 WREG8(DAC_DATA, tmp);
464
465 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
466 tmp = RREG8(DAC_DATA);
467 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
468 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
469 WREG8(DAC_DATA, tmp);
470
471 vcount = RREG8(MGAREG_VCOUNT);
472
473 for (j = 0; j < 30 && pll_locked == false; j++) {
474 tmpcount = RREG8(MGAREG_VCOUNT);
475 if (tmpcount < vcount)
476 vcount = 0;
477 if ((tmpcount - vcount) > 2)
478 pll_locked = true;
479 else
480 udelay(5);
481 }
482 }
483
484 return 0;
485 }
486
487 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
488 {
489 unsigned int vcomax, vcomin, pllreffreq;
490 unsigned int delta, tmpdelta;
491 int testr, testn, testm, testo;
492 unsigned int p, m, n;
493 unsigned int computed, vco;
494 int tmp;
495 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
496
497 m = n = p = 0;
498 vcomax = 1488000;
499 vcomin = 1056000;
500 pllreffreq = 48000;
501
502 delta = 0xffffffff;
503
504 for (testr = 0; testr < 4; testr++) {
505 if (delta == 0)
506 break;
507 for (testn = 5; testn < 129; testn++) {
508 if (delta == 0)
509 break;
510 for (testm = 3; testm >= 0; testm--) {
511 if (delta == 0)
512 break;
513 for (testo = 5; testo < 33; testo++) {
514 vco = pllreffreq * (testn + 1) /
515 (testr + 1);
516 if (vco < vcomin)
517 continue;
518 if (vco > vcomax)
519 continue;
520 computed = vco / (m_div_val[testm] * (testo + 1));
521 if (computed > clock)
522 tmpdelta = computed - clock;
523 else
524 tmpdelta = clock - computed;
525 if (tmpdelta < delta) {
526 delta = tmpdelta;
527 m = testm | (testo << 3);
528 n = testn;
529 p = testr | (testr << 3);
530 }
531 }
532 }
533 }
534 }
535
536 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
537 tmp = RREG8(DAC_DATA);
538 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
539 WREG8(DAC_DATA, tmp);
540
541 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
542 tmp = RREG8(DAC_DATA);
543 tmp |= MGA1064_REMHEADCTL_CLKDIS;
544 WREG8(DAC_DATA, tmp);
545
546 tmp = RREG8(MGAREG_MEM_MISC_READ);
547 tmp |= (0x3<<2) | 0xc0;
548 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
549
550 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
551 tmp = RREG8(DAC_DATA);
552 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
553 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
554 WREG8(DAC_DATA, tmp);
555
556 udelay(500);
557
558 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
559 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
560 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
561
562 udelay(50);
563
564 return 0;
565 }
566
567 static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
568 {
569 switch(mdev->type) {
570 case G200_SE_A:
571 case G200_SE_B:
572 return mga_g200se_set_plls(mdev, clock);
573 break;
574 case G200_WB:
575 return mga_g200wb_set_plls(mdev, clock);
576 break;
577 case G200_EV:
578 return mga_g200ev_set_plls(mdev, clock);
579 break;
580 case G200_EH:
581 return mga_g200eh_set_plls(mdev, clock);
582 break;
583 case G200_ER:
584 return mga_g200er_set_plls(mdev, clock);
585 break;
586 }
587 return 0;
588 }
589
590 static void mga_g200wb_prepare(struct drm_crtc *crtc)
591 {
592 struct mga_device *mdev = crtc->dev->dev_private;
593 u8 tmp;
594 int iter_max;
595
596 /* 1- The first step is to warn the BMC of an upcoming mode change.
597 * We are putting the misc<0> to output.*/
598
599 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
600 tmp = RREG8(DAC_DATA);
601 tmp |= 0x10;
602 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
603
604 /* we are putting a 1 on the misc<0> line */
605 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
606 tmp = RREG8(DAC_DATA);
607 tmp |= 0x10;
608 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
609
610 /* 2- Second step to mask and further scan request
611 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
612 */
613 WREG8(DAC_INDEX, MGA1064_SPAREREG);
614 tmp = RREG8(DAC_DATA);
615 tmp |= 0x80;
616 WREG_DAC(MGA1064_SPAREREG, tmp);
617
618 /* 3a- the third step is to verifu if there is an active scan
619 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
620 */
621 iter_max = 300;
622 while (!(tmp & 0x1) && iter_max) {
623 WREG8(DAC_INDEX, MGA1064_SPAREREG);
624 tmp = RREG8(DAC_DATA);
625 udelay(1000);
626 iter_max--;
627 }
628
629 /* 3b- this step occurs only if the remove is actually scanning
630 * we are waiting for the end of the frame which is a 1 on
631 * remvsyncsts (XSPAREREG<1>)
632 */
633 if (iter_max) {
634 iter_max = 300;
635 while ((tmp & 0x2) && iter_max) {
636 WREG8(DAC_INDEX, MGA1064_SPAREREG);
637 tmp = RREG8(DAC_DATA);
638 udelay(1000);
639 iter_max--;
640 }
641 }
642 }
643
644 static void mga_g200wb_commit(struct drm_crtc *crtc)
645 {
646 u8 tmp;
647 struct mga_device *mdev = crtc->dev->dev_private;
648
649 /* 1- The first step is to ensure that the vrsten and hrsten are set */
650 WREG8(MGAREG_CRTCEXT_INDEX, 1);
651 tmp = RREG8(MGAREG_CRTCEXT_DATA);
652 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
653
654 /* 2- second step is to assert the rstlvl2 */
655 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
656 tmp = RREG8(DAC_DATA);
657 tmp |= 0x8;
658 WREG8(DAC_DATA, tmp);
659
660 /* wait 10 us */
661 udelay(10);
662
663 /* 3- deassert rstlvl2 */
664 tmp &= ~0x08;
665 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
666 WREG8(DAC_DATA, tmp);
667
668 /* 4- remove mask of scan request */
669 WREG8(DAC_INDEX, MGA1064_SPAREREG);
670 tmp = RREG8(DAC_DATA);
671 tmp &= ~0x80;
672 WREG8(DAC_DATA, tmp);
673
674 /* 5- put back a 0 on the misc<0> line */
675 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
676 tmp = RREG8(DAC_DATA);
677 tmp &= ~0x10;
678 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
679 }
680
681 /*
682 This is how the framebuffer base address is stored in g200 cards:
683 * Assume @offset is the gpu_addr variable of the framebuffer object
684 * Then addr is the number of _pixels_ (not bytes) from the start of
685 VRAM to the first pixel we want to display. (divided by 2 for 32bit
686 framebuffers)
687 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
688 addr<20> -> CRTCEXT0<6>
689 addr<19-16> -> CRTCEXT0<3-0>
690 addr<15-8> -> CRTCC<7-0>
691 addr<7-0> -> CRTCD<7-0>
692 CRTCEXT0 has to be programmed last to trigger an update and make the
693 new addr variable take effect.
694 */
695 static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
696 {
697 struct mga_device *mdev = crtc->dev->dev_private;
698 u32 addr;
699 int count;
700 u8 crtcext0;
701
702 while (RREG8(0x1fda) & 0x08);
703 while (!(RREG8(0x1fda) & 0x08));
704
705 count = RREG8(MGAREG_VCOUNT) + 2;
706 while (RREG8(MGAREG_VCOUNT) < count);
707
708 WREG8(MGAREG_CRTCEXT_INDEX, 0);
709 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
710 crtcext0 &= 0xB0;
711 addr = offset / 8;
712 /* Can't store addresses any higher than that...
713 but we also don't have more than 16MB of memory, so it should be fine. */
714 WARN_ON(addr > 0x1fffff);
715 crtcext0 |= (!!(addr & (1<<20)))<<6;
716 WREG_CRT(0x0d, (u8)(addr & 0xff));
717 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
718 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
719 }
720
721
722 /* ast is different - we will force move buffers out of VRAM */
723 static int mga_crtc_do_set_base(struct drm_crtc *crtc,
724 struct drm_framebuffer *fb,
725 int x, int y, int atomic)
726 {
727 struct mga_device *mdev = crtc->dev->dev_private;
728 struct drm_gem_object *obj;
729 struct mga_framebuffer *mga_fb;
730 struct mgag200_bo *bo;
731 int ret;
732 u64 gpu_addr;
733
734 /* push the previous fb to system ram */
735 if (!atomic && fb) {
736 mga_fb = to_mga_framebuffer(fb);
737 obj = mga_fb->obj;
738 bo = gem_to_mga_bo(obj);
739 ret = mgag200_bo_reserve(bo, false);
740 if (ret)
741 return ret;
742 mgag200_bo_push_sysram(bo);
743 mgag200_bo_unreserve(bo);
744 }
745
746 mga_fb = to_mga_framebuffer(crtc->primary->fb);
747 obj = mga_fb->obj;
748 bo = gem_to_mga_bo(obj);
749
750 ret = mgag200_bo_reserve(bo, false);
751 if (ret)
752 return ret;
753
754 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
755 if (ret) {
756 mgag200_bo_unreserve(bo);
757 return ret;
758 }
759
760 if (&mdev->mfbdev->mfb == mga_fb) {
761 /* if pushing console in kmap it */
762 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
763 if (ret)
764 DRM_ERROR("failed to kmap fbcon\n");
765
766 }
767 mgag200_bo_unreserve(bo);
768
769 mga_set_start_address(crtc, (u32)gpu_addr);
770
771 return 0;
772 }
773
774 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
775 struct drm_framebuffer *old_fb)
776 {
777 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
778 }
779
780 static int mga_crtc_mode_set(struct drm_crtc *crtc,
781 struct drm_display_mode *mode,
782 struct drm_display_mode *adjusted_mode,
783 int x, int y, struct drm_framebuffer *old_fb)
784 {
785 struct drm_device *dev = crtc->dev;
786 struct mga_device *mdev = dev->dev_private;
787 int hdisplay, hsyncstart, hsyncend, htotal;
788 int vdisplay, vsyncstart, vsyncend, vtotal;
789 int pitch;
790 int option = 0, option2 = 0;
791 int i;
792 unsigned char misc = 0;
793 unsigned char ext_vga[6];
794 u8 bppshift;
795
796 static unsigned char dacvalue[] = {
797 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
798 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
799 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
800 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
801 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
802 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
803 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
804 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
805 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
806 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
807 };
808
809 bppshift = mdev->bpp_shifts[(crtc->primary->fb->bits_per_pixel >> 3) - 1];
810
811 switch (mdev->type) {
812 case G200_SE_A:
813 case G200_SE_B:
814 dacvalue[MGA1064_VREF_CTL] = 0x03;
815 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
816 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
817 MGA1064_MISC_CTL_VGA8 |
818 MGA1064_MISC_CTL_DAC_RAM_CS;
819 if (mdev->has_sdram)
820 option = 0x40049120;
821 else
822 option = 0x4004d120;
823 option2 = 0x00008000;
824 break;
825 case G200_WB:
826 dacvalue[MGA1064_VREF_CTL] = 0x07;
827 option = 0x41049120;
828 option2 = 0x0000b000;
829 break;
830 case G200_EV:
831 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
832 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
833 MGA1064_MISC_CTL_DAC_RAM_CS;
834 option = 0x00000120;
835 option2 = 0x0000b000;
836 break;
837 case G200_EH:
838 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
839 MGA1064_MISC_CTL_DAC_RAM_CS;
840 option = 0x00000120;
841 option2 = 0x0000b000;
842 break;
843 case G200_ER:
844 break;
845 }
846
847 switch (crtc->primary->fb->bits_per_pixel) {
848 case 8:
849 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
850 break;
851 case 16:
852 if (crtc->primary->fb->depth == 15)
853 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
854 else
855 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
856 break;
857 case 24:
858 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
859 break;
860 case 32:
861 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
862 break;
863 }
864
865 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
866 misc |= 0x40;
867 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
868 misc |= 0x80;
869
870
871 for (i = 0; i < sizeof(dacvalue); i++) {
872 if ((i <= 0x17) ||
873 (i == 0x1b) ||
874 (i == 0x1c) ||
875 ((i >= 0x1f) && (i <= 0x29)) ||
876 ((i >= 0x30) && (i <= 0x37)))
877 continue;
878 if (IS_G200_SE(mdev) &&
879 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
880 continue;
881 if ((mdev->type == G200_EV || mdev->type == G200_WB || mdev->type == G200_EH) &&
882 (i >= 0x44) && (i <= 0x4e))
883 continue;
884
885 WREG_DAC(i, dacvalue[i]);
886 }
887
888 if (mdev->type == G200_ER)
889 WREG_DAC(0x90, 0);
890
891 if (option)
892 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
893 if (option2)
894 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
895
896 WREG_SEQ(2, 0xf);
897 WREG_SEQ(3, 0);
898 WREG_SEQ(4, 0xe);
899
900 pitch = crtc->primary->fb->pitches[0] / (crtc->primary->fb->bits_per_pixel / 8);
901 if (crtc->primary->fb->bits_per_pixel == 24)
902 pitch = (pitch * 3) >> (4 - bppshift);
903 else
904 pitch = pitch >> (4 - bppshift);
905
906 hdisplay = mode->hdisplay / 8 - 1;
907 hsyncstart = mode->hsync_start / 8 - 1;
908 hsyncend = mode->hsync_end / 8 - 1;
909 htotal = mode->htotal / 8 - 1;
910
911 /* Work around hardware quirk */
912 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
913 htotal++;
914
915 vdisplay = mode->vdisplay - 1;
916 vsyncstart = mode->vsync_start - 1;
917 vsyncend = mode->vsync_end - 1;
918 vtotal = mode->vtotal - 2;
919
920 WREG_GFX(0, 0);
921 WREG_GFX(1, 0);
922 WREG_GFX(2, 0);
923 WREG_GFX(3, 0);
924 WREG_GFX(4, 0);
925 WREG_GFX(5, 0x40);
926 WREG_GFX(6, 0x5);
927 WREG_GFX(7, 0xf);
928 WREG_GFX(8, 0xf);
929
930 WREG_CRT(0, htotal - 4);
931 WREG_CRT(1, hdisplay);
932 WREG_CRT(2, hdisplay);
933 WREG_CRT(3, (htotal & 0x1F) | 0x80);
934 WREG_CRT(4, hsyncstart);
935 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
936 WREG_CRT(6, vtotal & 0xFF);
937 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
938 ((vdisplay & 0x100) >> 7) |
939 ((vsyncstart & 0x100) >> 6) |
940 ((vdisplay & 0x100) >> 5) |
941 ((vdisplay & 0x100) >> 4) | /* linecomp */
942 ((vtotal & 0x200) >> 4)|
943 ((vdisplay & 0x200) >> 3) |
944 ((vsyncstart & 0x200) >> 2));
945 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
946 ((vdisplay & 0x200) >> 3));
947 WREG_CRT(10, 0);
948 WREG_CRT(11, 0);
949 WREG_CRT(12, 0);
950 WREG_CRT(13, 0);
951 WREG_CRT(14, 0);
952 WREG_CRT(15, 0);
953 WREG_CRT(16, vsyncstart & 0xFF);
954 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
955 WREG_CRT(18, vdisplay & 0xFF);
956 WREG_CRT(19, pitch & 0xFF);
957 WREG_CRT(20, 0);
958 WREG_CRT(21, vdisplay & 0xFF);
959 WREG_CRT(22, (vtotal + 1) & 0xFF);
960 WREG_CRT(23, 0xc3);
961 WREG_CRT(24, vdisplay & 0xFF);
962
963 ext_vga[0] = 0;
964 ext_vga[5] = 0;
965
966 /* TODO interlace */
967
968 ext_vga[0] |= (pitch & 0x300) >> 4;
969 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
970 ((hdisplay & 0x100) >> 7) |
971 ((hsyncstart & 0x100) >> 6) |
972 (htotal & 0x40);
973 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
974 ((vdisplay & 0x400) >> 8) |
975 ((vdisplay & 0xc00) >> 7) |
976 ((vsyncstart & 0xc00) >> 5) |
977 ((vdisplay & 0x400) >> 3);
978 if (crtc->primary->fb->bits_per_pixel == 24)
979 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
980 else
981 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
982 ext_vga[4] = 0;
983 if (mdev->type == G200_WB)
984 ext_vga[1] |= 0x88;
985
986 /* Set pixel clocks */
987 misc = 0x2d;
988 WREG8(MGA_MISC_OUT, misc);
989
990 mga_crtc_set_plls(mdev, mode->clock);
991
992 for (i = 0; i < 6; i++) {
993 WREG_ECRT(i, ext_vga[i]);
994 }
995
996 if (mdev->type == G200_ER)
997 WREG_ECRT(0x24, 0x5);
998
999 if (mdev->type == G200_EV) {
1000 WREG_ECRT(6, 0);
1001 }
1002
1003 WREG_ECRT(0, ext_vga[0]);
1004 /* Enable mga pixel clock */
1005 misc = 0x2d;
1006
1007 WREG8(MGA_MISC_OUT, misc);
1008
1009 if (adjusted_mode)
1010 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
1011
1012 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
1013
1014 /* reset tagfifo */
1015 if (mdev->type == G200_ER) {
1016 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
1017 u8 seq1;
1018
1019 /* screen off */
1020 WREG8(MGAREG_SEQ_INDEX, 0x01);
1021 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
1022 WREG8(MGAREG_SEQ_DATA, seq1);
1023
1024 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
1025 udelay(1000);
1026 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1027
1028 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1029 }
1030
1031
1032 if (IS_G200_SE(mdev)) {
1033 if (mdev->unique_rev_id >= 0x02) {
1034 u8 hi_pri_lvl;
1035 u32 bpp;
1036 u32 mb;
1037
1038 if (crtc->primary->fb->bits_per_pixel > 16)
1039 bpp = 32;
1040 else if (crtc->primary->fb->bits_per_pixel > 8)
1041 bpp = 16;
1042 else
1043 bpp = 8;
1044
1045 mb = (mode->clock * bpp) / 1000;
1046 if (mb > 3100)
1047 hi_pri_lvl = 0;
1048 else if (mb > 2600)
1049 hi_pri_lvl = 1;
1050 else if (mb > 1900)
1051 hi_pri_lvl = 2;
1052 else if (mb > 1160)
1053 hi_pri_lvl = 3;
1054 else if (mb > 440)
1055 hi_pri_lvl = 4;
1056 else
1057 hi_pri_lvl = 5;
1058
1059 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1060 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
1061 } else {
1062 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1063 if (mdev->unique_rev_id >= 0x01)
1064 WREG8(MGAREG_CRTCEXT_DATA, 0x03);
1065 else
1066 WREG8(MGAREG_CRTCEXT_DATA, 0x04);
1067 }
1068 }
1069 return 0;
1070 }
1071
1072 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1073 static int mga_suspend(struct drm_crtc *crtc)
1074 {
1075 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1076 struct drm_device *dev = crtc->dev;
1077 struct mga_device *mdev = dev->dev_private;
1078 struct pci_dev *pdev = dev->pdev;
1079 int option;
1080
1081 if (mdev->suspended)
1082 return 0;
1083
1084 WREG_SEQ(1, 0x20);
1085 WREG_ECRT(1, 0x30);
1086 /* Disable the pixel clock */
1087 WREG_DAC(0x1a, 0x05);
1088 /* Power down the DAC */
1089 WREG_DAC(0x1e, 0x18);
1090 /* Power down the pixel PLL */
1091 WREG_DAC(0x1a, 0x0d);
1092
1093 /* Disable PLLs and clocks */
1094 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1095 option &= ~(0x1F8024);
1096 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1097 pci_set_power_state(pdev, PCI_D3hot);
1098 pci_disable_device(pdev);
1099
1100 mdev->suspended = true;
1101
1102 return 0;
1103 }
1104
1105 static int mga_resume(struct drm_crtc *crtc)
1106 {
1107 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1108 struct drm_device *dev = crtc->dev;
1109 struct mga_device *mdev = dev->dev_private;
1110 struct pci_dev *pdev = dev->pdev;
1111 int option;
1112
1113 if (!mdev->suspended)
1114 return 0;
1115
1116 pci_set_power_state(pdev, PCI_D0);
1117 pci_enable_device(pdev);
1118
1119 /* Disable sysclk */
1120 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1121 option &= ~(0x4);
1122 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1123
1124 mdev->suspended = false;
1125
1126 return 0;
1127 }
1128
1129 #endif
1130
1131 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1132 {
1133 struct drm_device *dev = crtc->dev;
1134 struct mga_device *mdev = dev->dev_private;
1135 u8 seq1 = 0, crtcext1 = 0;
1136
1137 switch (mode) {
1138 case DRM_MODE_DPMS_ON:
1139 seq1 = 0;
1140 crtcext1 = 0;
1141 mga_crtc_load_lut(crtc);
1142 break;
1143 case DRM_MODE_DPMS_STANDBY:
1144 seq1 = 0x20;
1145 crtcext1 = 0x10;
1146 break;
1147 case DRM_MODE_DPMS_SUSPEND:
1148 seq1 = 0x20;
1149 crtcext1 = 0x20;
1150 break;
1151 case DRM_MODE_DPMS_OFF:
1152 seq1 = 0x20;
1153 crtcext1 = 0x30;
1154 break;
1155 }
1156
1157 #if 0
1158 if (mode == DRM_MODE_DPMS_OFF) {
1159 mga_suspend(crtc);
1160 }
1161 #endif
1162 WREG8(MGAREG_SEQ_INDEX, 0x01);
1163 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1164 mga_wait_vsync(mdev);
1165 mga_wait_busy(mdev);
1166 WREG8(MGAREG_SEQ_DATA, seq1);
1167 msleep(20);
1168 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1169 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1170 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1171
1172 #if 0
1173 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1174 mga_resume(crtc);
1175 drm_helper_resume_force_mode(dev);
1176 }
1177 #endif
1178 }
1179
1180 /*
1181 * This is called before a mode is programmed. A typical use might be to
1182 * enable DPMS during the programming to avoid seeing intermediate stages,
1183 * but that's not relevant to us
1184 */
1185 static void mga_crtc_prepare(struct drm_crtc *crtc)
1186 {
1187 struct drm_device *dev = crtc->dev;
1188 struct mga_device *mdev = dev->dev_private;
1189 u8 tmp;
1190
1191 /* mga_resume(crtc);*/
1192
1193 WREG8(MGAREG_CRTC_INDEX, 0x11);
1194 tmp = RREG8(MGAREG_CRTC_DATA);
1195 WREG_CRT(0x11, tmp | 0x80);
1196
1197 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1198 WREG_SEQ(0, 1);
1199 msleep(50);
1200 WREG_SEQ(1, 0x20);
1201 msleep(20);
1202 } else {
1203 WREG8(MGAREG_SEQ_INDEX, 0x1);
1204 tmp = RREG8(MGAREG_SEQ_DATA);
1205
1206 /* start sync reset */
1207 WREG_SEQ(0, 1);
1208 WREG_SEQ(1, tmp | 0x20);
1209 }
1210
1211 if (mdev->type == G200_WB)
1212 mga_g200wb_prepare(crtc);
1213
1214 WREG_CRT(17, 0);
1215 }
1216
1217 /*
1218 * This is called after a mode is programmed. It should reverse anything done
1219 * by the prepare function
1220 */
1221 static void mga_crtc_commit(struct drm_crtc *crtc)
1222 {
1223 struct drm_device *dev = crtc->dev;
1224 struct mga_device *mdev = dev->dev_private;
1225 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1226 u8 tmp;
1227
1228 if (mdev->type == G200_WB)
1229 mga_g200wb_commit(crtc);
1230
1231 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1232 msleep(50);
1233 WREG_SEQ(1, 0x0);
1234 msleep(20);
1235 WREG_SEQ(0, 0x3);
1236 } else {
1237 WREG8(MGAREG_SEQ_INDEX, 0x1);
1238 tmp = RREG8(MGAREG_SEQ_DATA);
1239
1240 tmp &= ~0x20;
1241 WREG_SEQ(0x1, tmp);
1242 WREG_SEQ(0, 3);
1243 }
1244 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1245 }
1246
1247 /*
1248 * The core can pass us a set of gamma values to program. We actually only
1249 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1250 * but it's a requirement that we provide the function
1251 */
1252 static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1253 u16 *blue, uint32_t start, uint32_t size)
1254 {
1255 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1256 int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size;
1257 int i;
1258
1259 for (i = start; i < end; i++) {
1260 mga_crtc->lut_r[i] = red[i] >> 8;
1261 mga_crtc->lut_g[i] = green[i] >> 8;
1262 mga_crtc->lut_b[i] = blue[i] >> 8;
1263 }
1264 mga_crtc_load_lut(crtc);
1265 }
1266
1267 /* Simple cleanup function */
1268 static void mga_crtc_destroy(struct drm_crtc *crtc)
1269 {
1270 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1271
1272 drm_crtc_cleanup(crtc);
1273 kfree(mga_crtc);
1274 }
1275
1276 static void mga_crtc_disable(struct drm_crtc *crtc)
1277 {
1278 int ret;
1279 DRM_DEBUG_KMS("\n");
1280 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1281 if (crtc->primary->fb) {
1282 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb);
1283 struct drm_gem_object *obj = mga_fb->obj;
1284 struct mgag200_bo *bo = gem_to_mga_bo(obj);
1285 ret = mgag200_bo_reserve(bo, false);
1286 if (ret)
1287 return;
1288 mgag200_bo_push_sysram(bo);
1289 mgag200_bo_unreserve(bo);
1290 }
1291 crtc->primary->fb = NULL;
1292 }
1293
1294 /* These provide the minimum set of functions required to handle a CRTC */
1295 static const struct drm_crtc_funcs mga_crtc_funcs = {
1296 .cursor_set = mga_crtc_cursor_set,
1297 .cursor_move = mga_crtc_cursor_move,
1298 .gamma_set = mga_crtc_gamma_set,
1299 .set_config = drm_crtc_helper_set_config,
1300 .destroy = mga_crtc_destroy,
1301 };
1302
1303 static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1304 .disable = mga_crtc_disable,
1305 .dpms = mga_crtc_dpms,
1306 .mode_fixup = mga_crtc_mode_fixup,
1307 .mode_set = mga_crtc_mode_set,
1308 .mode_set_base = mga_crtc_mode_set_base,
1309 .prepare = mga_crtc_prepare,
1310 .commit = mga_crtc_commit,
1311 .load_lut = mga_crtc_load_lut,
1312 };
1313
1314 /* CRTC setup */
1315 static void mga_crtc_init(struct mga_device *mdev)
1316 {
1317 struct mga_crtc *mga_crtc;
1318 int i;
1319
1320 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1321 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1322 GFP_KERNEL);
1323
1324 if (mga_crtc == NULL)
1325 return;
1326
1327 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
1328
1329 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1330 mdev->mode_info.crtc = mga_crtc;
1331
1332 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1333 mga_crtc->lut_r[i] = i;
1334 mga_crtc->lut_g[i] = i;
1335 mga_crtc->lut_b[i] = i;
1336 }
1337
1338 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1339 }
1340
1341 /** Sets the color ramps on behalf of fbcon */
1342 void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1343 u16 blue, int regno)
1344 {
1345 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1346
1347 mga_crtc->lut_r[regno] = red >> 8;
1348 mga_crtc->lut_g[regno] = green >> 8;
1349 mga_crtc->lut_b[regno] = blue >> 8;
1350 }
1351
1352 /** Gets the color ramps on behalf of fbcon */
1353 void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1354 u16 *blue, int regno)
1355 {
1356 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1357
1358 *red = (u16)mga_crtc->lut_r[regno] << 8;
1359 *green = (u16)mga_crtc->lut_g[regno] << 8;
1360 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1361 }
1362
1363 /*
1364 * The encoder comes after the CRTC in the output pipeline, but before
1365 * the connector. It's responsible for ensuring that the digital
1366 * stream is appropriately converted into the output format. Setup is
1367 * very simple in this case - all we have to do is inform qemu of the
1368 * colour depth in order to ensure that it displays appropriately
1369 */
1370
1371 /*
1372 * These functions are analagous to those in the CRTC code, but are intended
1373 * to handle any encoder-specific limitations
1374 */
1375 static bool mga_encoder_mode_fixup(struct drm_encoder *encoder,
1376 const struct drm_display_mode *mode,
1377 struct drm_display_mode *adjusted_mode)
1378 {
1379 return true;
1380 }
1381
1382 static void mga_encoder_mode_set(struct drm_encoder *encoder,
1383 struct drm_display_mode *mode,
1384 struct drm_display_mode *adjusted_mode)
1385 {
1386
1387 }
1388
1389 static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1390 {
1391 return;
1392 }
1393
1394 static void mga_encoder_prepare(struct drm_encoder *encoder)
1395 {
1396 }
1397
1398 static void mga_encoder_commit(struct drm_encoder *encoder)
1399 {
1400 }
1401
1402 static void mga_encoder_destroy(struct drm_encoder *encoder)
1403 {
1404 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1405 drm_encoder_cleanup(encoder);
1406 kfree(mga_encoder);
1407 }
1408
1409 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1410 .dpms = mga_encoder_dpms,
1411 .mode_fixup = mga_encoder_mode_fixup,
1412 .mode_set = mga_encoder_mode_set,
1413 .prepare = mga_encoder_prepare,
1414 .commit = mga_encoder_commit,
1415 };
1416
1417 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1418 .destroy = mga_encoder_destroy,
1419 };
1420
1421 static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1422 {
1423 struct drm_encoder *encoder;
1424 struct mga_encoder *mga_encoder;
1425
1426 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1427 if (!mga_encoder)
1428 return NULL;
1429
1430 encoder = &mga_encoder->base;
1431 encoder->possible_crtcs = 0x1;
1432
1433 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
1434 DRM_MODE_ENCODER_DAC);
1435 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1436
1437 return encoder;
1438 }
1439
1440
1441 static int mga_vga_get_modes(struct drm_connector *connector)
1442 {
1443 struct mga_connector *mga_connector = to_mga_connector(connector);
1444 struct edid *edid;
1445 int ret = 0;
1446
1447 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1448 if (edid) {
1449 drm_mode_connector_update_edid_property(connector, edid);
1450 ret = drm_add_edid_modes(connector, edid);
1451 kfree(edid);
1452 }
1453 return ret;
1454 }
1455
1456 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1457 int bits_per_pixel)
1458 {
1459 uint32_t total_area, divisor;
1460 int64_t active_area, pixels_per_second, bandwidth;
1461 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1462
1463 divisor = 1024;
1464
1465 if (!mode->htotal || !mode->vtotal || !mode->clock)
1466 return 0;
1467
1468 active_area = mode->hdisplay * mode->vdisplay;
1469 total_area = mode->htotal * mode->vtotal;
1470
1471 pixels_per_second = active_area * mode->clock * 1000;
1472 do_div(pixels_per_second, total_area);
1473
1474 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1475 do_div(bandwidth, divisor);
1476
1477 return (uint32_t)(bandwidth);
1478 }
1479
1480 #define MODE_BANDWIDTH MODE_BAD
1481
1482 static int mga_vga_mode_valid(struct drm_connector *connector,
1483 struct drm_display_mode *mode)
1484 {
1485 struct drm_device *dev = connector->dev;
1486 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
1487 int bpp = 32;
1488
1489 if (IS_G200_SE(mdev)) {
1490 if (mdev->unique_rev_id == 0x01) {
1491 if (mode->hdisplay > 1600)
1492 return MODE_VIRTUAL_X;
1493 if (mode->vdisplay > 1200)
1494 return MODE_VIRTUAL_Y;
1495 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1496 > (24400 * 1024))
1497 return MODE_BANDWIDTH;
1498 } else if (mdev->unique_rev_id >= 0x02) {
1499 if (mode->hdisplay > 1920)
1500 return MODE_VIRTUAL_X;
1501 if (mode->vdisplay > 1200)
1502 return MODE_VIRTUAL_Y;
1503 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1504 > (30100 * 1024))
1505 return MODE_BANDWIDTH;
1506 }
1507 } else if (mdev->type == G200_WB) {
1508 if (mode->hdisplay > 1280)
1509 return MODE_VIRTUAL_X;
1510 if (mode->vdisplay > 1024)
1511 return MODE_VIRTUAL_Y;
1512 if (mga_vga_calculate_mode_bandwidth(mode,
1513 bpp > (31877 * 1024)))
1514 return MODE_BANDWIDTH;
1515 } else if (mdev->type == G200_EV &&
1516 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1517 > (32700 * 1024))) {
1518 return MODE_BANDWIDTH;
1519 } else if (mdev->type == G200_EH &&
1520 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1521 > (37500 * 1024))) {
1522 return MODE_BANDWIDTH;
1523 } else if (mdev->type == G200_ER &&
1524 (mga_vga_calculate_mode_bandwidth(mode,
1525 bpp) > (55000 * 1024))) {
1526 return MODE_BANDWIDTH;
1527 }
1528
1529 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1530 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1531 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1532 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1533 return MODE_BAD;
1534 }
1535
1536 /* Validate the mode input by the user */
1537 if (connector->cmdline_mode.specified) {
1538 if (connector->cmdline_mode.bpp_specified)
1539 bpp = connector->cmdline_mode.bpp;
1540 }
1541
1542 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
1543 if (connector->cmdline_mode.specified)
1544 connector->cmdline_mode.specified = false;
1545 return MODE_BAD;
1546 }
1547
1548 return MODE_OK;
1549 }
1550
1551 static struct drm_encoder *mga_connector_best_encoder(struct drm_connector
1552 *connector)
1553 {
1554 int enc_id = connector->encoder_ids[0];
1555 /* pick the encoder ids */
1556 if (enc_id)
1557 return drm_encoder_find(connector->dev, enc_id);
1558 return NULL;
1559 }
1560
1561 static enum drm_connector_status mga_vga_detect(struct drm_connector
1562 *connector, bool force)
1563 {
1564 return connector_status_connected;
1565 }
1566
1567 static void mga_connector_destroy(struct drm_connector *connector)
1568 {
1569 struct mga_connector *mga_connector = to_mga_connector(connector);
1570 mgag200_i2c_destroy(mga_connector->i2c);
1571 drm_connector_cleanup(connector);
1572 kfree(connector);
1573 }
1574
1575 struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1576 .get_modes = mga_vga_get_modes,
1577 .mode_valid = mga_vga_mode_valid,
1578 .best_encoder = mga_connector_best_encoder,
1579 };
1580
1581 struct drm_connector_funcs mga_vga_connector_funcs = {
1582 .dpms = drm_helper_connector_dpms,
1583 .detect = mga_vga_detect,
1584 .fill_modes = drm_helper_probe_single_connector_modes,
1585 .destroy = mga_connector_destroy,
1586 };
1587
1588 static struct drm_connector *mga_vga_init(struct drm_device *dev)
1589 {
1590 struct drm_connector *connector;
1591 struct mga_connector *mga_connector;
1592
1593 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1594 if (!mga_connector)
1595 return NULL;
1596
1597 connector = &mga_connector->base;
1598
1599 drm_connector_init(dev, connector,
1600 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1601
1602 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1603
1604 drm_connector_register(connector);
1605
1606 mga_connector->i2c = mgag200_i2c_create(dev);
1607 if (!mga_connector->i2c)
1608 DRM_ERROR("failed to add ddc bus\n");
1609
1610 return connector;
1611 }
1612
1613
1614 int mgag200_modeset_init(struct mga_device *mdev)
1615 {
1616 struct drm_encoder *encoder;
1617 struct drm_connector *connector;
1618 int ret;
1619
1620 mdev->mode_info.mode_config_initialized = true;
1621
1622 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1623 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1624
1625 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1626
1627 mga_crtc_init(mdev);
1628
1629 encoder = mga_encoder_init(mdev->dev);
1630 if (!encoder) {
1631 DRM_ERROR("mga_encoder_init failed\n");
1632 return -1;
1633 }
1634
1635 connector = mga_vga_init(mdev->dev);
1636 if (!connector) {
1637 DRM_ERROR("mga_vga_init failed\n");
1638 return -1;
1639 }
1640
1641 drm_mode_connector_attach_encoder(connector, encoder);
1642
1643 ret = mgag200_fbdev_init(mdev);
1644 if (ret) {
1645 DRM_ERROR("mga_fbdev_init failed\n");
1646 return ret;
1647 }
1648
1649 return 0;
1650 }
1651
1652 void mgag200_modeset_fini(struct mga_device *mdev)
1653 {
1654
1655 }
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