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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / mgag200 / mgag200_mode.c
1 /*
2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
4 *
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
8 *
9 * Authors: Matthew Garrett
10 * Matt Turner
11 * Dave Airlie
12 */
13
14 #include <linux/delay.h>
15
16 #include <drm/drmP.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_plane_helper.h>
19
20 #include "mgag200_drv.h"
21
22 #define MGAG200_LUT_SIZE 256
23
24 /*
25 * This file contains setup code for the CRTC.
26 */
27
28 static void mga_crtc_load_lut(struct drm_crtc *crtc)
29 {
30 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
31 struct drm_device *dev = crtc->dev;
32 struct mga_device *mdev = dev->dev_private;
33 struct drm_framebuffer *fb = crtc->primary->fb;
34 int i;
35
36 if (!crtc->enabled)
37 return;
38
39 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
40
41 if (fb && fb->format->cpp[0] * 8 == 16) {
42 int inc = (fb->format->depth == 15) ? 8 : 4;
43 u8 r, b;
44 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
45 if (fb->format->depth == 16) {
46 if (i > (MGAG200_LUT_SIZE >> 1)) {
47 r = b = 0;
48 } else {
49 r = mga_crtc->lut_r[i << 1];
50 b = mga_crtc->lut_b[i << 1];
51 }
52 } else {
53 r = mga_crtc->lut_r[i];
54 b = mga_crtc->lut_b[i];
55 }
56 /* VGA registers */
57 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
58 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
59 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
60 }
61 return;
62 }
63 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
64 /* VGA registers */
65 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
66 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
67 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
68 }
69 }
70
71 static inline void mga_wait_vsync(struct mga_device *mdev)
72 {
73 unsigned long timeout = jiffies + HZ/10;
74 unsigned int status = 0;
75
76 do {
77 status = RREG32(MGAREG_Status);
78 } while ((status & 0x08) && time_before(jiffies, timeout));
79 timeout = jiffies + HZ/10;
80 status = 0;
81 do {
82 status = RREG32(MGAREG_Status);
83 } while (!(status & 0x08) && time_before(jiffies, timeout));
84 }
85
86 static inline void mga_wait_busy(struct mga_device *mdev)
87 {
88 unsigned long timeout = jiffies + HZ;
89 unsigned int status = 0;
90 do {
91 status = RREG8(MGAREG_Status + 2);
92 } while ((status & 0x01) && time_before(jiffies, timeout));
93 }
94
95 #define P_ARRAY_SIZE 9
96
97 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
98 {
99 unsigned int vcomax, vcomin, pllreffreq;
100 unsigned int delta, tmpdelta, permitteddelta;
101 unsigned int testp, testm, testn;
102 unsigned int p, m, n;
103 unsigned int computed;
104 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
105 unsigned int fvv;
106 unsigned int i;
107
108 if (mdev->unique_rev_id <= 0x03) {
109
110 m = n = p = 0;
111 vcomax = 320000;
112 vcomin = 160000;
113 pllreffreq = 25000;
114
115 delta = 0xffffffff;
116 permitteddelta = clock * 5 / 1000;
117
118 for (testp = 8; testp > 0; testp /= 2) {
119 if (clock * testp > vcomax)
120 continue;
121 if (clock * testp < vcomin)
122 continue;
123
124 for (testn = 17; testn < 256; testn++) {
125 for (testm = 1; testm < 32; testm++) {
126 computed = (pllreffreq * testn) /
127 (testm * testp);
128 if (computed > clock)
129 tmpdelta = computed - clock;
130 else
131 tmpdelta = clock - computed;
132 if (tmpdelta < delta) {
133 delta = tmpdelta;
134 m = testm - 1;
135 n = testn - 1;
136 p = testp - 1;
137 }
138 }
139 }
140 }
141 } else {
142
143
144 m = n = p = 0;
145 vcomax = 1600000;
146 vcomin = 800000;
147 pllreffreq = 25000;
148
149 if (clock < 25000)
150 clock = 25000;
151
152 clock = clock * 2;
153
154 delta = 0xFFFFFFFF;
155 /* Permited delta is 0.5% as VESA Specification */
156 permitteddelta = clock * 5 / 1000;
157
158 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
159 testp = pvalues_e4[i];
160
161 if ((clock * testp) > vcomax)
162 continue;
163 if ((clock * testp) < vcomin)
164 continue;
165
166 for (testn = 50; testn <= 256; testn++) {
167 for (testm = 1; testm <= 32; testm++) {
168 computed = (pllreffreq * testn) /
169 (testm * testp);
170 if (computed > clock)
171 tmpdelta = computed - clock;
172 else
173 tmpdelta = clock - computed;
174
175 if (tmpdelta < delta) {
176 delta = tmpdelta;
177 m = testm - 1;
178 n = testn - 1;
179 p = testp - 1;
180 }
181 }
182 }
183 }
184
185 fvv = pllreffreq * (n + 1) / (m + 1);
186 fvv = (fvv - 800000) / 50000;
187
188 if (fvv > 15)
189 fvv = 15;
190
191 p |= (fvv << 4);
192 m |= 0x80;
193
194 clock = clock / 2;
195 }
196
197 if (delta > permitteddelta) {
198 pr_warn("PLL delta too large\n");
199 return 1;
200 }
201
202 WREG_DAC(MGA1064_PIX_PLLC_M, m);
203 WREG_DAC(MGA1064_PIX_PLLC_N, n);
204 WREG_DAC(MGA1064_PIX_PLLC_P, p);
205
206 if (mdev->unique_rev_id >= 0x04) {
207 WREG_DAC(0x1a, 0x09);
208 msleep(20);
209 WREG_DAC(0x1a, 0x01);
210
211 }
212
213 return 0;
214 }
215
216 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
217 {
218 unsigned int vcomax, vcomin, pllreffreq;
219 unsigned int delta, tmpdelta;
220 unsigned int testp, testm, testn, testp2;
221 unsigned int p, m, n;
222 unsigned int computed;
223 int i, j, tmpcount, vcount;
224 bool pll_locked = false;
225 u8 tmp;
226
227 m = n = p = 0;
228
229 delta = 0xffffffff;
230
231 if (mdev->type == G200_EW3) {
232
233 vcomax = 800000;
234 vcomin = 400000;
235 pllreffreq = 25000;
236
237 for (testp = 1; testp < 8; testp++) {
238 for (testp2 = 1; testp2 < 8; testp2++) {
239 if (testp < testp2)
240 continue;
241 if ((clock * testp * testp2) > vcomax)
242 continue;
243 if ((clock * testp * testp2) < vcomin)
244 continue;
245 for (testm = 1; testm < 26; testm++) {
246 for (testn = 32; testn < 2048 ; testn++) {
247 computed = (pllreffreq * testn) /
248 (testm * testp * testp2);
249 if (computed > clock)
250 tmpdelta = computed - clock;
251 else
252 tmpdelta = clock - computed;
253 if (tmpdelta < delta) {
254 delta = tmpdelta;
255 m = ((testn & 0x100) >> 1) |
256 (testm);
257 n = (testn & 0xFF);
258 p = ((testn & 0x600) >> 3) |
259 (testp2 << 3) |
260 (testp);
261 }
262 }
263 }
264 }
265 }
266 } else {
267
268 vcomax = 550000;
269 vcomin = 150000;
270 pllreffreq = 48000;
271
272 for (testp = 1; testp < 9; testp++) {
273 if (clock * testp > vcomax)
274 continue;
275 if (clock * testp < vcomin)
276 continue;
277
278 for (testm = 1; testm < 17; testm++) {
279 for (testn = 1; testn < 151; testn++) {
280 computed = (pllreffreq * testn) /
281 (testm * testp);
282 if (computed > clock)
283 tmpdelta = computed - clock;
284 else
285 tmpdelta = clock - computed;
286 if (tmpdelta < delta) {
287 delta = tmpdelta;
288 n = testn - 1;
289 m = (testm - 1) |
290 ((n >> 1) & 0x80);
291 p = testp - 1;
292 }
293 }
294 }
295 }
296 }
297
298 for (i = 0; i <= 32 && pll_locked == false; i++) {
299 if (i > 0) {
300 WREG8(MGAREG_CRTC_INDEX, 0x1e);
301 tmp = RREG8(MGAREG_CRTC_DATA);
302 if (tmp < 0xff)
303 WREG8(MGAREG_CRTC_DATA, tmp+1);
304 }
305
306 /* set pixclkdis to 1 */
307 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
308 tmp = RREG8(DAC_DATA);
309 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
310 WREG8(DAC_DATA, tmp);
311
312 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
313 tmp = RREG8(DAC_DATA);
314 tmp |= MGA1064_REMHEADCTL_CLKDIS;
315 WREG8(DAC_DATA, tmp);
316
317 /* select PLL Set C */
318 tmp = RREG8(MGAREG_MEM_MISC_READ);
319 tmp |= 0x3 << 2;
320 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
321
322 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
323 tmp = RREG8(DAC_DATA);
324 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
325 WREG8(DAC_DATA, tmp);
326
327 udelay(500);
328
329 /* reset the PLL */
330 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
331 tmp = RREG8(DAC_DATA);
332 tmp &= ~0x04;
333 WREG8(DAC_DATA, tmp);
334
335 udelay(50);
336
337 /* program pixel pll register */
338 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
339 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
340 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
341
342 udelay(50);
343
344 /* turn pll on */
345 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
346 tmp = RREG8(DAC_DATA);
347 tmp |= 0x04;
348 WREG_DAC(MGA1064_VREF_CTL, tmp);
349
350 udelay(500);
351
352 /* select the pixel pll */
353 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
354 tmp = RREG8(DAC_DATA);
355 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
356 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
357 WREG8(DAC_DATA, tmp);
358
359 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
360 tmp = RREG8(DAC_DATA);
361 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
362 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
363 WREG8(DAC_DATA, tmp);
364
365 /* reset dotclock rate bit */
366 WREG8(MGAREG_SEQ_INDEX, 1);
367 tmp = RREG8(MGAREG_SEQ_DATA);
368 tmp &= ~0x8;
369 WREG8(MGAREG_SEQ_DATA, tmp);
370
371 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
372 tmp = RREG8(DAC_DATA);
373 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
374 WREG8(DAC_DATA, tmp);
375
376 vcount = RREG8(MGAREG_VCOUNT);
377
378 for (j = 0; j < 30 && pll_locked == false; j++) {
379 tmpcount = RREG8(MGAREG_VCOUNT);
380 if (tmpcount < vcount)
381 vcount = 0;
382 if ((tmpcount - vcount) > 2)
383 pll_locked = true;
384 else
385 udelay(5);
386 }
387 }
388 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
389 tmp = RREG8(DAC_DATA);
390 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
391 WREG_DAC(MGA1064_REMHEADCTL, tmp);
392 return 0;
393 }
394
395 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
396 {
397 unsigned int vcomax, vcomin, pllreffreq;
398 unsigned int delta, tmpdelta;
399 unsigned int testp, testm, testn;
400 unsigned int p, m, n;
401 unsigned int computed;
402 u8 tmp;
403
404 m = n = p = 0;
405 vcomax = 550000;
406 vcomin = 150000;
407 pllreffreq = 50000;
408
409 delta = 0xffffffff;
410
411 for (testp = 16; testp > 0; testp--) {
412 if (clock * testp > vcomax)
413 continue;
414 if (clock * testp < vcomin)
415 continue;
416
417 for (testn = 1; testn < 257; testn++) {
418 for (testm = 1; testm < 17; testm++) {
419 computed = (pllreffreq * testn) /
420 (testm * testp);
421 if (computed > clock)
422 tmpdelta = computed - clock;
423 else
424 tmpdelta = clock - computed;
425 if (tmpdelta < delta) {
426 delta = tmpdelta;
427 n = testn - 1;
428 m = testm - 1;
429 p = testp - 1;
430 }
431 }
432 }
433 }
434
435 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
436 tmp = RREG8(DAC_DATA);
437 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
438 WREG8(DAC_DATA, tmp);
439
440 tmp = RREG8(MGAREG_MEM_MISC_READ);
441 tmp |= 0x3 << 2;
442 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
443
444 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
445 tmp = RREG8(DAC_DATA);
446 WREG8(DAC_DATA, tmp & ~0x40);
447
448 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
449 tmp = RREG8(DAC_DATA);
450 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
451 WREG8(DAC_DATA, tmp);
452
453 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
454 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
455 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
456
457 udelay(50);
458
459 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
460 tmp = RREG8(DAC_DATA);
461 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
462 WREG8(DAC_DATA, tmp);
463
464 udelay(500);
465
466 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
467 tmp = RREG8(DAC_DATA);
468 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
469 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
470 WREG8(DAC_DATA, tmp);
471
472 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
473 tmp = RREG8(DAC_DATA);
474 WREG8(DAC_DATA, tmp | 0x40);
475
476 tmp = RREG8(MGAREG_MEM_MISC_READ);
477 tmp |= (0x3 << 2);
478 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
479
480 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
481 tmp = RREG8(DAC_DATA);
482 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
483 WREG8(DAC_DATA, tmp);
484
485 return 0;
486 }
487
488 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
489 {
490 unsigned int vcomax, vcomin, pllreffreq;
491 unsigned int delta, tmpdelta;
492 unsigned int testp, testm, testn;
493 unsigned int p, m, n;
494 unsigned int computed;
495 int i, j, tmpcount, vcount;
496 u8 tmp;
497 bool pll_locked = false;
498
499 m = n = p = 0;
500
501 if (mdev->type == G200_EH3) {
502 vcomax = 3000000;
503 vcomin = 1500000;
504 pllreffreq = 25000;
505
506 delta = 0xffffffff;
507
508 testp = 0;
509
510 for (testm = 150; testm >= 6; testm--) {
511 if (clock * testm > vcomax)
512 continue;
513 if (clock * testm < vcomin)
514 continue;
515 for (testn = 120; testn >= 60; testn--) {
516 computed = (pllreffreq * testn) / testm;
517 if (computed > clock)
518 tmpdelta = computed - clock;
519 else
520 tmpdelta = clock - computed;
521 if (tmpdelta < delta) {
522 delta = tmpdelta;
523 n = testn;
524 m = testm;
525 p = testp;
526 }
527 if (delta == 0)
528 break;
529 }
530 if (delta == 0)
531 break;
532 }
533 } else {
534
535 vcomax = 800000;
536 vcomin = 400000;
537 pllreffreq = 33333;
538
539 delta = 0xffffffff;
540
541 for (testp = 16; testp > 0; testp >>= 1) {
542 if (clock * testp > vcomax)
543 continue;
544 if (clock * testp < vcomin)
545 continue;
546
547 for (testm = 1; testm < 33; testm++) {
548 for (testn = 17; testn < 257; testn++) {
549 computed = (pllreffreq * testn) /
550 (testm * testp);
551 if (computed > clock)
552 tmpdelta = computed - clock;
553 else
554 tmpdelta = clock - computed;
555 if (tmpdelta < delta) {
556 delta = tmpdelta;
557 n = testn - 1;
558 m = (testm - 1);
559 p = testp - 1;
560 }
561 if ((clock * testp) >= 600000)
562 p |= 0x80;
563 }
564 }
565 }
566 }
567 for (i = 0; i <= 32 && pll_locked == false; i++) {
568 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
569 tmp = RREG8(DAC_DATA);
570 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
571 WREG8(DAC_DATA, tmp);
572
573 tmp = RREG8(MGAREG_MEM_MISC_READ);
574 tmp |= 0x3 << 2;
575 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
576
577 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
578 tmp = RREG8(DAC_DATA);
579 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
580 WREG8(DAC_DATA, tmp);
581
582 udelay(500);
583
584 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
585 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
586 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
587
588 udelay(500);
589
590 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
591 tmp = RREG8(DAC_DATA);
592 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
593 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
594 WREG8(DAC_DATA, tmp);
595
596 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
597 tmp = RREG8(DAC_DATA);
598 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
599 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
600 WREG8(DAC_DATA, tmp);
601
602 vcount = RREG8(MGAREG_VCOUNT);
603
604 for (j = 0; j < 30 && pll_locked == false; j++) {
605 tmpcount = RREG8(MGAREG_VCOUNT);
606 if (tmpcount < vcount)
607 vcount = 0;
608 if ((tmpcount - vcount) > 2)
609 pll_locked = true;
610 else
611 udelay(5);
612 }
613 }
614
615 return 0;
616 }
617
618 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
619 {
620 unsigned int vcomax, vcomin, pllreffreq;
621 unsigned int delta, tmpdelta;
622 int testr, testn, testm, testo;
623 unsigned int p, m, n;
624 unsigned int computed, vco;
625 int tmp;
626 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
627
628 m = n = p = 0;
629 vcomax = 1488000;
630 vcomin = 1056000;
631 pllreffreq = 48000;
632
633 delta = 0xffffffff;
634
635 for (testr = 0; testr < 4; testr++) {
636 if (delta == 0)
637 break;
638 for (testn = 5; testn < 129; testn++) {
639 if (delta == 0)
640 break;
641 for (testm = 3; testm >= 0; testm--) {
642 if (delta == 0)
643 break;
644 for (testo = 5; testo < 33; testo++) {
645 vco = pllreffreq * (testn + 1) /
646 (testr + 1);
647 if (vco < vcomin)
648 continue;
649 if (vco > vcomax)
650 continue;
651 computed = vco / (m_div_val[testm] * (testo + 1));
652 if (computed > clock)
653 tmpdelta = computed - clock;
654 else
655 tmpdelta = clock - computed;
656 if (tmpdelta < delta) {
657 delta = tmpdelta;
658 m = testm | (testo << 3);
659 n = testn;
660 p = testr | (testr << 3);
661 }
662 }
663 }
664 }
665 }
666
667 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
668 tmp = RREG8(DAC_DATA);
669 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
670 WREG8(DAC_DATA, tmp);
671
672 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
673 tmp = RREG8(DAC_DATA);
674 tmp |= MGA1064_REMHEADCTL_CLKDIS;
675 WREG8(DAC_DATA, tmp);
676
677 tmp = RREG8(MGAREG_MEM_MISC_READ);
678 tmp |= (0x3<<2) | 0xc0;
679 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
680
681 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
682 tmp = RREG8(DAC_DATA);
683 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
684 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
685 WREG8(DAC_DATA, tmp);
686
687 udelay(500);
688
689 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
690 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
691 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
692
693 udelay(50);
694
695 return 0;
696 }
697
698 static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
699 {
700 switch(mdev->type) {
701 case G200_SE_A:
702 case G200_SE_B:
703 return mga_g200se_set_plls(mdev, clock);
704 break;
705 case G200_WB:
706 case G200_EW3:
707 return mga_g200wb_set_plls(mdev, clock);
708 break;
709 case G200_EV:
710 return mga_g200ev_set_plls(mdev, clock);
711 break;
712 case G200_EH:
713 case G200_EH3:
714 return mga_g200eh_set_plls(mdev, clock);
715 break;
716 case G200_ER:
717 return mga_g200er_set_plls(mdev, clock);
718 break;
719 }
720 return 0;
721 }
722
723 static void mga_g200wb_prepare(struct drm_crtc *crtc)
724 {
725 struct mga_device *mdev = crtc->dev->dev_private;
726 u8 tmp;
727 int iter_max;
728
729 /* 1- The first step is to warn the BMC of an upcoming mode change.
730 * We are putting the misc<0> to output.*/
731
732 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
733 tmp = RREG8(DAC_DATA);
734 tmp |= 0x10;
735 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
736
737 /* we are putting a 1 on the misc<0> line */
738 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
739 tmp = RREG8(DAC_DATA);
740 tmp |= 0x10;
741 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
742
743 /* 2- Second step to mask and further scan request
744 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
745 */
746 WREG8(DAC_INDEX, MGA1064_SPAREREG);
747 tmp = RREG8(DAC_DATA);
748 tmp |= 0x80;
749 WREG_DAC(MGA1064_SPAREREG, tmp);
750
751 /* 3a- the third step is to verifu if there is an active scan
752 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
753 */
754 iter_max = 300;
755 while (!(tmp & 0x1) && iter_max) {
756 WREG8(DAC_INDEX, MGA1064_SPAREREG);
757 tmp = RREG8(DAC_DATA);
758 udelay(1000);
759 iter_max--;
760 }
761
762 /* 3b- this step occurs only if the remove is actually scanning
763 * we are waiting for the end of the frame which is a 1 on
764 * remvsyncsts (XSPAREREG<1>)
765 */
766 if (iter_max) {
767 iter_max = 300;
768 while ((tmp & 0x2) && iter_max) {
769 WREG8(DAC_INDEX, MGA1064_SPAREREG);
770 tmp = RREG8(DAC_DATA);
771 udelay(1000);
772 iter_max--;
773 }
774 }
775 }
776
777 static void mga_g200wb_commit(struct drm_crtc *crtc)
778 {
779 u8 tmp;
780 struct mga_device *mdev = crtc->dev->dev_private;
781
782 /* 1- The first step is to ensure that the vrsten and hrsten are set */
783 WREG8(MGAREG_CRTCEXT_INDEX, 1);
784 tmp = RREG8(MGAREG_CRTCEXT_DATA);
785 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
786
787 /* 2- second step is to assert the rstlvl2 */
788 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
789 tmp = RREG8(DAC_DATA);
790 tmp |= 0x8;
791 WREG8(DAC_DATA, tmp);
792
793 /* wait 10 us */
794 udelay(10);
795
796 /* 3- deassert rstlvl2 */
797 tmp &= ~0x08;
798 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
799 WREG8(DAC_DATA, tmp);
800
801 /* 4- remove mask of scan request */
802 WREG8(DAC_INDEX, MGA1064_SPAREREG);
803 tmp = RREG8(DAC_DATA);
804 tmp &= ~0x80;
805 WREG8(DAC_DATA, tmp);
806
807 /* 5- put back a 0 on the misc<0> line */
808 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
809 tmp = RREG8(DAC_DATA);
810 tmp &= ~0x10;
811 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
812 }
813
814 /*
815 This is how the framebuffer base address is stored in g200 cards:
816 * Assume @offset is the gpu_addr variable of the framebuffer object
817 * Then addr is the number of _pixels_ (not bytes) from the start of
818 VRAM to the first pixel we want to display. (divided by 2 for 32bit
819 framebuffers)
820 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
821 addr<20> -> CRTCEXT0<6>
822 addr<19-16> -> CRTCEXT0<3-0>
823 addr<15-8> -> CRTCC<7-0>
824 addr<7-0> -> CRTCD<7-0>
825 CRTCEXT0 has to be programmed last to trigger an update and make the
826 new addr variable take effect.
827 */
828 static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
829 {
830 struct mga_device *mdev = crtc->dev->dev_private;
831 u32 addr;
832 int count;
833 u8 crtcext0;
834
835 while (RREG8(0x1fda) & 0x08);
836 while (!(RREG8(0x1fda) & 0x08));
837
838 count = RREG8(MGAREG_VCOUNT) + 2;
839 while (RREG8(MGAREG_VCOUNT) < count);
840
841 WREG8(MGAREG_CRTCEXT_INDEX, 0);
842 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
843 crtcext0 &= 0xB0;
844 addr = offset / 8;
845 /* Can't store addresses any higher than that...
846 but we also don't have more than 16MB of memory, so it should be fine. */
847 WARN_ON(addr > 0x1fffff);
848 crtcext0 |= (!!(addr & (1<<20)))<<6;
849 WREG_CRT(0x0d, (u8)(addr & 0xff));
850 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
851 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
852 }
853
854
855 /* ast is different - we will force move buffers out of VRAM */
856 static int mga_crtc_do_set_base(struct drm_crtc *crtc,
857 struct drm_framebuffer *fb,
858 int x, int y, int atomic)
859 {
860 struct mga_device *mdev = crtc->dev->dev_private;
861 struct drm_gem_object *obj;
862 struct mga_framebuffer *mga_fb;
863 struct mgag200_bo *bo;
864 int ret;
865 u64 gpu_addr;
866
867 /* push the previous fb to system ram */
868 if (!atomic && fb) {
869 mga_fb = to_mga_framebuffer(fb);
870 obj = mga_fb->obj;
871 bo = gem_to_mga_bo(obj);
872 ret = mgag200_bo_reserve(bo, false);
873 if (ret)
874 return ret;
875 mgag200_bo_push_sysram(bo);
876 mgag200_bo_unreserve(bo);
877 }
878
879 mga_fb = to_mga_framebuffer(crtc->primary->fb);
880 obj = mga_fb->obj;
881 bo = gem_to_mga_bo(obj);
882
883 ret = mgag200_bo_reserve(bo, false);
884 if (ret)
885 return ret;
886
887 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
888 if (ret) {
889 mgag200_bo_unreserve(bo);
890 return ret;
891 }
892
893 if (&mdev->mfbdev->mfb == mga_fb) {
894 /* if pushing console in kmap it */
895 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
896 if (ret)
897 DRM_ERROR("failed to kmap fbcon\n");
898
899 }
900 mgag200_bo_unreserve(bo);
901
902 mga_set_start_address(crtc, (u32)gpu_addr);
903
904 return 0;
905 }
906
907 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
908 struct drm_framebuffer *old_fb)
909 {
910 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
911 }
912
913 static int mga_crtc_mode_set(struct drm_crtc *crtc,
914 struct drm_display_mode *mode,
915 struct drm_display_mode *adjusted_mode,
916 int x, int y, struct drm_framebuffer *old_fb)
917 {
918 struct drm_device *dev = crtc->dev;
919 struct mga_device *mdev = dev->dev_private;
920 const struct drm_framebuffer *fb = crtc->primary->fb;
921 int hdisplay, hsyncstart, hsyncend, htotal;
922 int vdisplay, vsyncstart, vsyncend, vtotal;
923 int pitch;
924 int option = 0, option2 = 0;
925 int i;
926 unsigned char misc = 0;
927 unsigned char ext_vga[6];
928 u8 bppshift;
929
930 static unsigned char dacvalue[] = {
931 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
932 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
933 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
934 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
935 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
936 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
937 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
938 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
939 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
940 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
941 };
942
943 bppshift = mdev->bpp_shifts[fb->format->cpp[0] - 1];
944
945 switch (mdev->type) {
946 case G200_SE_A:
947 case G200_SE_B:
948 dacvalue[MGA1064_VREF_CTL] = 0x03;
949 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
950 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
951 MGA1064_MISC_CTL_VGA8 |
952 MGA1064_MISC_CTL_DAC_RAM_CS;
953 if (mdev->has_sdram)
954 option = 0x40049120;
955 else
956 option = 0x4004d120;
957 option2 = 0x00008000;
958 break;
959 case G200_WB:
960 case G200_EW3:
961 dacvalue[MGA1064_VREF_CTL] = 0x07;
962 option = 0x41049120;
963 option2 = 0x0000b000;
964 break;
965 case G200_EV:
966 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
967 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
968 MGA1064_MISC_CTL_DAC_RAM_CS;
969 option = 0x00000120;
970 option2 = 0x0000b000;
971 break;
972 case G200_EH:
973 case G200_EH3:
974 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
975 MGA1064_MISC_CTL_DAC_RAM_CS;
976 option = 0x00000120;
977 option2 = 0x0000b000;
978 break;
979 case G200_ER:
980 break;
981 }
982
983 switch (fb->format->cpp[0] * 8) {
984 case 8:
985 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
986 break;
987 case 16:
988 if (fb->format->depth == 15)
989 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
990 else
991 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
992 break;
993 case 24:
994 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
995 break;
996 case 32:
997 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
998 break;
999 }
1000
1001 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1002 misc |= 0x40;
1003 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1004 misc |= 0x80;
1005
1006
1007 for (i = 0; i < sizeof(dacvalue); i++) {
1008 if ((i <= 0x17) ||
1009 (i == 0x1b) ||
1010 (i == 0x1c) ||
1011 ((i >= 0x1f) && (i <= 0x29)) ||
1012 ((i >= 0x30) && (i <= 0x37)))
1013 continue;
1014 if (IS_G200_SE(mdev) &&
1015 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
1016 continue;
1017 if ((mdev->type == G200_EV ||
1018 mdev->type == G200_WB ||
1019 mdev->type == G200_EH ||
1020 mdev->type == G200_EW3 ||
1021 mdev->type == G200_EH3) &&
1022 (i >= 0x44) && (i <= 0x4e))
1023 continue;
1024
1025 WREG_DAC(i, dacvalue[i]);
1026 }
1027
1028 if (mdev->type == G200_ER)
1029 WREG_DAC(0x90, 0);
1030
1031 if (option)
1032 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
1033 if (option2)
1034 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
1035
1036 WREG_SEQ(2, 0xf);
1037 WREG_SEQ(3, 0);
1038 WREG_SEQ(4, 0xe);
1039
1040 pitch = fb->pitches[0] / fb->format->cpp[0];
1041 if (fb->format->cpp[0] * 8 == 24)
1042 pitch = (pitch * 3) >> (4 - bppshift);
1043 else
1044 pitch = pitch >> (4 - bppshift);
1045
1046 hdisplay = mode->hdisplay / 8 - 1;
1047 hsyncstart = mode->hsync_start / 8 - 1;
1048 hsyncend = mode->hsync_end / 8 - 1;
1049 htotal = mode->htotal / 8 - 1;
1050
1051 /* Work around hardware quirk */
1052 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1053 htotal++;
1054
1055 vdisplay = mode->vdisplay - 1;
1056 vsyncstart = mode->vsync_start - 1;
1057 vsyncend = mode->vsync_end - 1;
1058 vtotal = mode->vtotal - 2;
1059
1060 WREG_GFX(0, 0);
1061 WREG_GFX(1, 0);
1062 WREG_GFX(2, 0);
1063 WREG_GFX(3, 0);
1064 WREG_GFX(4, 0);
1065 WREG_GFX(5, 0x40);
1066 WREG_GFX(6, 0x5);
1067 WREG_GFX(7, 0xf);
1068 WREG_GFX(8, 0xf);
1069
1070 WREG_CRT(0, htotal - 4);
1071 WREG_CRT(1, hdisplay);
1072 WREG_CRT(2, hdisplay);
1073 WREG_CRT(3, (htotal & 0x1F) | 0x80);
1074 WREG_CRT(4, hsyncstart);
1075 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1076 WREG_CRT(6, vtotal & 0xFF);
1077 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1078 ((vdisplay & 0x100) >> 7) |
1079 ((vsyncstart & 0x100) >> 6) |
1080 ((vdisplay & 0x100) >> 5) |
1081 ((vdisplay & 0x100) >> 4) | /* linecomp */
1082 ((vtotal & 0x200) >> 4)|
1083 ((vdisplay & 0x200) >> 3) |
1084 ((vsyncstart & 0x200) >> 2));
1085 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1086 ((vdisplay & 0x200) >> 3));
1087 WREG_CRT(10, 0);
1088 WREG_CRT(11, 0);
1089 WREG_CRT(12, 0);
1090 WREG_CRT(13, 0);
1091 WREG_CRT(14, 0);
1092 WREG_CRT(15, 0);
1093 WREG_CRT(16, vsyncstart & 0xFF);
1094 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1095 WREG_CRT(18, vdisplay & 0xFF);
1096 WREG_CRT(19, pitch & 0xFF);
1097 WREG_CRT(20, 0);
1098 WREG_CRT(21, vdisplay & 0xFF);
1099 WREG_CRT(22, (vtotal + 1) & 0xFF);
1100 WREG_CRT(23, 0xc3);
1101 WREG_CRT(24, vdisplay & 0xFF);
1102
1103 ext_vga[0] = 0;
1104 ext_vga[5] = 0;
1105
1106 /* TODO interlace */
1107
1108 ext_vga[0] |= (pitch & 0x300) >> 4;
1109 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
1110 ((hdisplay & 0x100) >> 7) |
1111 ((hsyncstart & 0x100) >> 6) |
1112 (htotal & 0x40);
1113 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
1114 ((vdisplay & 0x400) >> 8) |
1115 ((vdisplay & 0xc00) >> 7) |
1116 ((vsyncstart & 0xc00) >> 5) |
1117 ((vdisplay & 0x400) >> 3);
1118 if (fb->format->cpp[0] * 8 == 24)
1119 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
1120 else
1121 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
1122 ext_vga[4] = 0;
1123 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1124 ext_vga[1] |= 0x88;
1125
1126 /* Set pixel clocks */
1127 misc = 0x2d;
1128 WREG8(MGA_MISC_OUT, misc);
1129
1130 mga_crtc_set_plls(mdev, mode->clock);
1131
1132 for (i = 0; i < 6; i++) {
1133 WREG_ECRT(i, ext_vga[i]);
1134 }
1135
1136 if (mdev->type == G200_ER)
1137 WREG_ECRT(0x24, 0x5);
1138
1139 if (mdev->type == G200_EW3)
1140 WREG_ECRT(0x34, 0x5);
1141
1142 if (mdev->type == G200_EV) {
1143 WREG_ECRT(6, 0);
1144 }
1145
1146 WREG_ECRT(0, ext_vga[0]);
1147 /* Enable mga pixel clock */
1148 misc = 0x2d;
1149
1150 WREG8(MGA_MISC_OUT, misc);
1151
1152 if (adjusted_mode)
1153 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
1154
1155 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
1156
1157 /* reset tagfifo */
1158 if (mdev->type == G200_ER) {
1159 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
1160 u8 seq1;
1161
1162 /* screen off */
1163 WREG8(MGAREG_SEQ_INDEX, 0x01);
1164 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
1165 WREG8(MGAREG_SEQ_DATA, seq1);
1166
1167 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
1168 udelay(1000);
1169 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1170
1171 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1172 }
1173
1174
1175 if (IS_G200_SE(mdev)) {
1176 if (mdev->unique_rev_id >= 0x02) {
1177 u8 hi_pri_lvl;
1178 u32 bpp;
1179 u32 mb;
1180
1181 if (fb->format->cpp[0] * 8 > 16)
1182 bpp = 32;
1183 else if (fb->format->cpp[0] * 8 > 8)
1184 bpp = 16;
1185 else
1186 bpp = 8;
1187
1188 mb = (mode->clock * bpp) / 1000;
1189 if (mb > 3100)
1190 hi_pri_lvl = 0;
1191 else if (mb > 2600)
1192 hi_pri_lvl = 1;
1193 else if (mb > 1900)
1194 hi_pri_lvl = 2;
1195 else if (mb > 1160)
1196 hi_pri_lvl = 3;
1197 else if (mb > 440)
1198 hi_pri_lvl = 4;
1199 else
1200 hi_pri_lvl = 5;
1201
1202 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1203 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
1204 } else {
1205 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1206 if (mdev->unique_rev_id >= 0x01)
1207 WREG8(MGAREG_CRTCEXT_DATA, 0x03);
1208 else
1209 WREG8(MGAREG_CRTCEXT_DATA, 0x04);
1210 }
1211 }
1212 return 0;
1213 }
1214
1215 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1216 static int mga_suspend(struct drm_crtc *crtc)
1217 {
1218 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1219 struct drm_device *dev = crtc->dev;
1220 struct mga_device *mdev = dev->dev_private;
1221 struct pci_dev *pdev = dev->pdev;
1222 int option;
1223
1224 if (mdev->suspended)
1225 return 0;
1226
1227 WREG_SEQ(1, 0x20);
1228 WREG_ECRT(1, 0x30);
1229 /* Disable the pixel clock */
1230 WREG_DAC(0x1a, 0x05);
1231 /* Power down the DAC */
1232 WREG_DAC(0x1e, 0x18);
1233 /* Power down the pixel PLL */
1234 WREG_DAC(0x1a, 0x0d);
1235
1236 /* Disable PLLs and clocks */
1237 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1238 option &= ~(0x1F8024);
1239 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1240 pci_set_power_state(pdev, PCI_D3hot);
1241 pci_disable_device(pdev);
1242
1243 mdev->suspended = true;
1244
1245 return 0;
1246 }
1247
1248 static int mga_resume(struct drm_crtc *crtc)
1249 {
1250 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1251 struct drm_device *dev = crtc->dev;
1252 struct mga_device *mdev = dev->dev_private;
1253 struct pci_dev *pdev = dev->pdev;
1254 int option;
1255
1256 if (!mdev->suspended)
1257 return 0;
1258
1259 pci_set_power_state(pdev, PCI_D0);
1260 pci_enable_device(pdev);
1261
1262 /* Disable sysclk */
1263 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1264 option &= ~(0x4);
1265 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1266
1267 mdev->suspended = false;
1268
1269 return 0;
1270 }
1271
1272 #endif
1273
1274 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1275 {
1276 struct drm_device *dev = crtc->dev;
1277 struct mga_device *mdev = dev->dev_private;
1278 u8 seq1 = 0, crtcext1 = 0;
1279
1280 switch (mode) {
1281 case DRM_MODE_DPMS_ON:
1282 seq1 = 0;
1283 crtcext1 = 0;
1284 mga_crtc_load_lut(crtc);
1285 break;
1286 case DRM_MODE_DPMS_STANDBY:
1287 seq1 = 0x20;
1288 crtcext1 = 0x10;
1289 break;
1290 case DRM_MODE_DPMS_SUSPEND:
1291 seq1 = 0x20;
1292 crtcext1 = 0x20;
1293 break;
1294 case DRM_MODE_DPMS_OFF:
1295 seq1 = 0x20;
1296 crtcext1 = 0x30;
1297 break;
1298 }
1299
1300 #if 0
1301 if (mode == DRM_MODE_DPMS_OFF) {
1302 mga_suspend(crtc);
1303 }
1304 #endif
1305 WREG8(MGAREG_SEQ_INDEX, 0x01);
1306 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1307 mga_wait_vsync(mdev);
1308 mga_wait_busy(mdev);
1309 WREG8(MGAREG_SEQ_DATA, seq1);
1310 msleep(20);
1311 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1312 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1313 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1314
1315 #if 0
1316 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1317 mga_resume(crtc);
1318 drm_helper_resume_force_mode(dev);
1319 }
1320 #endif
1321 }
1322
1323 /*
1324 * This is called before a mode is programmed. A typical use might be to
1325 * enable DPMS during the programming to avoid seeing intermediate stages,
1326 * but that's not relevant to us
1327 */
1328 static void mga_crtc_prepare(struct drm_crtc *crtc)
1329 {
1330 struct drm_device *dev = crtc->dev;
1331 struct mga_device *mdev = dev->dev_private;
1332 u8 tmp;
1333
1334 /* mga_resume(crtc);*/
1335
1336 WREG8(MGAREG_CRTC_INDEX, 0x11);
1337 tmp = RREG8(MGAREG_CRTC_DATA);
1338 WREG_CRT(0x11, tmp | 0x80);
1339
1340 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1341 WREG_SEQ(0, 1);
1342 msleep(50);
1343 WREG_SEQ(1, 0x20);
1344 msleep(20);
1345 } else {
1346 WREG8(MGAREG_SEQ_INDEX, 0x1);
1347 tmp = RREG8(MGAREG_SEQ_DATA);
1348
1349 /* start sync reset */
1350 WREG_SEQ(0, 1);
1351 WREG_SEQ(1, tmp | 0x20);
1352 }
1353
1354 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1355 mga_g200wb_prepare(crtc);
1356
1357 WREG_CRT(17, 0);
1358 }
1359
1360 /*
1361 * This is called after a mode is programmed. It should reverse anything done
1362 * by the prepare function
1363 */
1364 static void mga_crtc_commit(struct drm_crtc *crtc)
1365 {
1366 struct drm_device *dev = crtc->dev;
1367 struct mga_device *mdev = dev->dev_private;
1368 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1369 u8 tmp;
1370
1371 if (mdev->type == G200_WB || mdev->type == G200_EW3)
1372 mga_g200wb_commit(crtc);
1373
1374 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1375 msleep(50);
1376 WREG_SEQ(1, 0x0);
1377 msleep(20);
1378 WREG_SEQ(0, 0x3);
1379 } else {
1380 WREG8(MGAREG_SEQ_INDEX, 0x1);
1381 tmp = RREG8(MGAREG_SEQ_DATA);
1382
1383 tmp &= ~0x20;
1384 WREG_SEQ(0x1, tmp);
1385 WREG_SEQ(0, 3);
1386 }
1387 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1388 }
1389
1390 /*
1391 * The core can pass us a set of gamma values to program. We actually only
1392 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1393 * but it's a requirement that we provide the function
1394 */
1395 static int mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1396 u16 *blue, uint32_t size,
1397 struct drm_modeset_acquire_ctx *ctx)
1398 {
1399 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1400 int i;
1401
1402 for (i = 0; i < size; i++) {
1403 mga_crtc->lut_r[i] = red[i] >> 8;
1404 mga_crtc->lut_g[i] = green[i] >> 8;
1405 mga_crtc->lut_b[i] = blue[i] >> 8;
1406 }
1407 mga_crtc_load_lut(crtc);
1408
1409 return 0;
1410 }
1411
1412 /* Simple cleanup function */
1413 static void mga_crtc_destroy(struct drm_crtc *crtc)
1414 {
1415 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1416
1417 drm_crtc_cleanup(crtc);
1418 kfree(mga_crtc);
1419 }
1420
1421 static void mga_crtc_disable(struct drm_crtc *crtc)
1422 {
1423 int ret;
1424 DRM_DEBUG_KMS("\n");
1425 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1426 if (crtc->primary->fb) {
1427 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb);
1428 struct drm_gem_object *obj = mga_fb->obj;
1429 struct mgag200_bo *bo = gem_to_mga_bo(obj);
1430 ret = mgag200_bo_reserve(bo, false);
1431 if (ret)
1432 return;
1433 mgag200_bo_push_sysram(bo);
1434 mgag200_bo_unreserve(bo);
1435 }
1436 crtc->primary->fb = NULL;
1437 }
1438
1439 /* These provide the minimum set of functions required to handle a CRTC */
1440 static const struct drm_crtc_funcs mga_crtc_funcs = {
1441 .cursor_set = mga_crtc_cursor_set,
1442 .cursor_move = mga_crtc_cursor_move,
1443 .gamma_set = mga_crtc_gamma_set,
1444 .set_config = drm_crtc_helper_set_config,
1445 .destroy = mga_crtc_destroy,
1446 };
1447
1448 static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1449 .disable = mga_crtc_disable,
1450 .dpms = mga_crtc_dpms,
1451 .mode_set = mga_crtc_mode_set,
1452 .mode_set_base = mga_crtc_mode_set_base,
1453 .prepare = mga_crtc_prepare,
1454 .commit = mga_crtc_commit,
1455 .load_lut = mga_crtc_load_lut,
1456 };
1457
1458 /* CRTC setup */
1459 static void mga_crtc_init(struct mga_device *mdev)
1460 {
1461 struct mga_crtc *mga_crtc;
1462 int i;
1463
1464 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1465 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1466 GFP_KERNEL);
1467
1468 if (mga_crtc == NULL)
1469 return;
1470
1471 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
1472
1473 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1474 mdev->mode_info.crtc = mga_crtc;
1475
1476 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1477 mga_crtc->lut_r[i] = i;
1478 mga_crtc->lut_g[i] = i;
1479 mga_crtc->lut_b[i] = i;
1480 }
1481
1482 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1483 }
1484
1485 /** Sets the color ramps on behalf of fbcon */
1486 void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1487 u16 blue, int regno)
1488 {
1489 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1490
1491 mga_crtc->lut_r[regno] = red >> 8;
1492 mga_crtc->lut_g[regno] = green >> 8;
1493 mga_crtc->lut_b[regno] = blue >> 8;
1494 }
1495
1496 /** Gets the color ramps on behalf of fbcon */
1497 void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1498 u16 *blue, int regno)
1499 {
1500 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1501
1502 *red = (u16)mga_crtc->lut_r[regno] << 8;
1503 *green = (u16)mga_crtc->lut_g[regno] << 8;
1504 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1505 }
1506
1507 /*
1508 * The encoder comes after the CRTC in the output pipeline, but before
1509 * the connector. It's responsible for ensuring that the digital
1510 * stream is appropriately converted into the output format. Setup is
1511 * very simple in this case - all we have to do is inform qemu of the
1512 * colour depth in order to ensure that it displays appropriately
1513 */
1514
1515 /*
1516 * These functions are analagous to those in the CRTC code, but are intended
1517 * to handle any encoder-specific limitations
1518 */
1519 static void mga_encoder_mode_set(struct drm_encoder *encoder,
1520 struct drm_display_mode *mode,
1521 struct drm_display_mode *adjusted_mode)
1522 {
1523
1524 }
1525
1526 static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1527 {
1528 return;
1529 }
1530
1531 static void mga_encoder_prepare(struct drm_encoder *encoder)
1532 {
1533 }
1534
1535 static void mga_encoder_commit(struct drm_encoder *encoder)
1536 {
1537 }
1538
1539 static void mga_encoder_destroy(struct drm_encoder *encoder)
1540 {
1541 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1542 drm_encoder_cleanup(encoder);
1543 kfree(mga_encoder);
1544 }
1545
1546 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1547 .dpms = mga_encoder_dpms,
1548 .mode_set = mga_encoder_mode_set,
1549 .prepare = mga_encoder_prepare,
1550 .commit = mga_encoder_commit,
1551 };
1552
1553 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1554 .destroy = mga_encoder_destroy,
1555 };
1556
1557 static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1558 {
1559 struct drm_encoder *encoder;
1560 struct mga_encoder *mga_encoder;
1561
1562 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1563 if (!mga_encoder)
1564 return NULL;
1565
1566 encoder = &mga_encoder->base;
1567 encoder->possible_crtcs = 0x1;
1568
1569 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
1570 DRM_MODE_ENCODER_DAC, NULL);
1571 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1572
1573 return encoder;
1574 }
1575
1576
1577 static int mga_vga_get_modes(struct drm_connector *connector)
1578 {
1579 struct mga_connector *mga_connector = to_mga_connector(connector);
1580 struct edid *edid;
1581 int ret = 0;
1582
1583 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1584 if (edid) {
1585 drm_mode_connector_update_edid_property(connector, edid);
1586 ret = drm_add_edid_modes(connector, edid);
1587 kfree(edid);
1588 }
1589 return ret;
1590 }
1591
1592 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1593 int bits_per_pixel)
1594 {
1595 uint32_t total_area, divisor;
1596 uint64_t active_area, pixels_per_second, bandwidth;
1597 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1598
1599 divisor = 1024;
1600
1601 if (!mode->htotal || !mode->vtotal || !mode->clock)
1602 return 0;
1603
1604 active_area = mode->hdisplay * mode->vdisplay;
1605 total_area = mode->htotal * mode->vtotal;
1606
1607 pixels_per_second = active_area * mode->clock * 1000;
1608 do_div(pixels_per_second, total_area);
1609
1610 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1611 do_div(bandwidth, divisor);
1612
1613 return (uint32_t)(bandwidth);
1614 }
1615
1616 #define MODE_BANDWIDTH MODE_BAD
1617
1618 static int mga_vga_mode_valid(struct drm_connector *connector,
1619 struct drm_display_mode *mode)
1620 {
1621 struct drm_device *dev = connector->dev;
1622 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
1623 int bpp = 32;
1624
1625 if (IS_G200_SE(mdev)) {
1626 if (mdev->unique_rev_id == 0x01) {
1627 if (mode->hdisplay > 1600)
1628 return MODE_VIRTUAL_X;
1629 if (mode->vdisplay > 1200)
1630 return MODE_VIRTUAL_Y;
1631 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1632 > (24400 * 1024))
1633 return MODE_BANDWIDTH;
1634 } else if (mdev->unique_rev_id == 0x02) {
1635 if (mode->hdisplay > 1920)
1636 return MODE_VIRTUAL_X;
1637 if (mode->vdisplay > 1200)
1638 return MODE_VIRTUAL_Y;
1639 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1640 > (30100 * 1024))
1641 return MODE_BANDWIDTH;
1642 }
1643 } else if (mdev->type == G200_WB) {
1644 if (mode->hdisplay > 1280)
1645 return MODE_VIRTUAL_X;
1646 if (mode->vdisplay > 1024)
1647 return MODE_VIRTUAL_Y;
1648 if (mga_vga_calculate_mode_bandwidth(mode,
1649 bpp > (31877 * 1024)))
1650 return MODE_BANDWIDTH;
1651 } else if (mdev->type == G200_EV &&
1652 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1653 > (32700 * 1024))) {
1654 return MODE_BANDWIDTH;
1655 } else if (mdev->type == G200_EH &&
1656 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1657 > (37500 * 1024))) {
1658 return MODE_BANDWIDTH;
1659 } else if (mdev->type == G200_ER &&
1660 (mga_vga_calculate_mode_bandwidth(mode,
1661 bpp) > (55000 * 1024))) {
1662 return MODE_BANDWIDTH;
1663 }
1664
1665 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1666 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1667 return MODE_H_ILLEGAL;
1668 }
1669
1670 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1671 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1672 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1673 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1674 return MODE_BAD;
1675 }
1676
1677 /* Validate the mode input by the user */
1678 if (connector->cmdline_mode.specified) {
1679 if (connector->cmdline_mode.bpp_specified)
1680 bpp = connector->cmdline_mode.bpp;
1681 }
1682
1683 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
1684 if (connector->cmdline_mode.specified)
1685 connector->cmdline_mode.specified = false;
1686 return MODE_BAD;
1687 }
1688
1689 return MODE_OK;
1690 }
1691
1692 static struct drm_encoder *mga_connector_best_encoder(struct drm_connector
1693 *connector)
1694 {
1695 int enc_id = connector->encoder_ids[0];
1696 /* pick the encoder ids */
1697 if (enc_id)
1698 return drm_encoder_find(connector->dev, enc_id);
1699 return NULL;
1700 }
1701
1702 static void mga_connector_destroy(struct drm_connector *connector)
1703 {
1704 struct mga_connector *mga_connector = to_mga_connector(connector);
1705 mgag200_i2c_destroy(mga_connector->i2c);
1706 drm_connector_cleanup(connector);
1707 kfree(connector);
1708 }
1709
1710 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1711 .get_modes = mga_vga_get_modes,
1712 .mode_valid = mga_vga_mode_valid,
1713 .best_encoder = mga_connector_best_encoder,
1714 };
1715
1716 static const struct drm_connector_funcs mga_vga_connector_funcs = {
1717 .dpms = drm_helper_connector_dpms,
1718 .fill_modes = drm_helper_probe_single_connector_modes,
1719 .destroy = mga_connector_destroy,
1720 };
1721
1722 static struct drm_connector *mga_vga_init(struct drm_device *dev)
1723 {
1724 struct drm_connector *connector;
1725 struct mga_connector *mga_connector;
1726
1727 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1728 if (!mga_connector)
1729 return NULL;
1730
1731 connector = &mga_connector->base;
1732
1733 drm_connector_init(dev, connector,
1734 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1735
1736 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1737
1738 drm_connector_register(connector);
1739
1740 mga_connector->i2c = mgag200_i2c_create(dev);
1741 if (!mga_connector->i2c)
1742 DRM_ERROR("failed to add ddc bus\n");
1743
1744 return connector;
1745 }
1746
1747
1748 int mgag200_modeset_init(struct mga_device *mdev)
1749 {
1750 struct drm_encoder *encoder;
1751 struct drm_connector *connector;
1752 int ret;
1753
1754 mdev->mode_info.mode_config_initialized = true;
1755
1756 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1757 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1758
1759 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1760
1761 mga_crtc_init(mdev);
1762
1763 encoder = mga_encoder_init(mdev->dev);
1764 if (!encoder) {
1765 DRM_ERROR("mga_encoder_init failed\n");
1766 return -1;
1767 }
1768
1769 connector = mga_vga_init(mdev->dev);
1770 if (!connector) {
1771 DRM_ERROR("mga_vga_init failed\n");
1772 return -1;
1773 }
1774
1775 drm_mode_connector_attach_encoder(connector, encoder);
1776
1777 ret = mgag200_fbdev_init(mdev);
1778 if (ret) {
1779 DRM_ERROR("mga_fbdev_init failed\n");
1780 return ret;
1781 }
1782
1783 return 0;
1784 }
1785
1786 void mgag200_modeset_fini(struct mga_device *mdev)
1787 {
1788
1789 }
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