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Merge tag 'topic/drm-misc-2015-07-23' of git://anongit.freedesktop.org/drm-intel...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / mgag200 / mgag200_mode.c
1 /*
2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
4 *
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
8 *
9 * Authors: Matthew Garrett
10 * Matt Turner
11 * Dave Airlie
12 */
13
14 #include <linux/delay.h>
15
16 #include <drm/drmP.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_plane_helper.h>
19
20 #include "mgag200_drv.h"
21
22 #define MGAG200_LUT_SIZE 256
23
24 /*
25 * This file contains setup code for the CRTC.
26 */
27
28 static void mga_crtc_load_lut(struct drm_crtc *crtc)
29 {
30 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
31 struct drm_device *dev = crtc->dev;
32 struct mga_device *mdev = dev->dev_private;
33 struct drm_framebuffer *fb = crtc->primary->fb;
34 int i;
35
36 if (!crtc->enabled)
37 return;
38
39 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
40
41 if (fb && fb->bits_per_pixel == 16) {
42 int inc = (fb->depth == 15) ? 8 : 4;
43 u8 r, b;
44 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
45 if (fb->depth == 16) {
46 if (i > (MGAG200_LUT_SIZE >> 1)) {
47 r = b = 0;
48 } else {
49 r = mga_crtc->lut_r[i << 1];
50 b = mga_crtc->lut_b[i << 1];
51 }
52 } else {
53 r = mga_crtc->lut_r[i];
54 b = mga_crtc->lut_b[i];
55 }
56 /* VGA registers */
57 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
58 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
59 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
60 }
61 return;
62 }
63 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
64 /* VGA registers */
65 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
66 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
67 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
68 }
69 }
70
71 static inline void mga_wait_vsync(struct mga_device *mdev)
72 {
73 unsigned long timeout = jiffies + HZ/10;
74 unsigned int status = 0;
75
76 do {
77 status = RREG32(MGAREG_Status);
78 } while ((status & 0x08) && time_before(jiffies, timeout));
79 timeout = jiffies + HZ/10;
80 status = 0;
81 do {
82 status = RREG32(MGAREG_Status);
83 } while (!(status & 0x08) && time_before(jiffies, timeout));
84 }
85
86 static inline void mga_wait_busy(struct mga_device *mdev)
87 {
88 unsigned long timeout = jiffies + HZ;
89 unsigned int status = 0;
90 do {
91 status = RREG8(MGAREG_Status + 2);
92 } while ((status & 0x01) && time_before(jiffies, timeout));
93 }
94
95 /*
96 * The core passes the desired mode to the CRTC code to see whether any
97 * CRTC-specific modifications need to be made to it. We're in a position
98 * to just pass that straight through, so this does nothing
99 */
100 static bool mga_crtc_mode_fixup(struct drm_crtc *crtc,
101 const struct drm_display_mode *mode,
102 struct drm_display_mode *adjusted_mode)
103 {
104 return true;
105 }
106
107 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
108 {
109 unsigned int vcomax, vcomin, pllreffreq;
110 unsigned int delta, tmpdelta, permitteddelta;
111 unsigned int testp, testm, testn;
112 unsigned int p, m, n;
113 unsigned int computed;
114
115 m = n = p = 0;
116 vcomax = 320000;
117 vcomin = 160000;
118 pllreffreq = 25000;
119
120 delta = 0xffffffff;
121 permitteddelta = clock * 5 / 1000;
122
123 for (testp = 8; testp > 0; testp /= 2) {
124 if (clock * testp > vcomax)
125 continue;
126 if (clock * testp < vcomin)
127 continue;
128
129 for (testn = 17; testn < 256; testn++) {
130 for (testm = 1; testm < 32; testm++) {
131 computed = (pllreffreq * testn) /
132 (testm * testp);
133 if (computed > clock)
134 tmpdelta = computed - clock;
135 else
136 tmpdelta = clock - computed;
137 if (tmpdelta < delta) {
138 delta = tmpdelta;
139 m = testm - 1;
140 n = testn - 1;
141 p = testp - 1;
142 }
143 }
144 }
145 }
146
147 if (delta > permitteddelta) {
148 printk(KERN_WARNING "PLL delta too large\n");
149 return 1;
150 }
151
152 WREG_DAC(MGA1064_PIX_PLLC_M, m);
153 WREG_DAC(MGA1064_PIX_PLLC_N, n);
154 WREG_DAC(MGA1064_PIX_PLLC_P, p);
155 return 0;
156 }
157
158 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
159 {
160 unsigned int vcomax, vcomin, pllreffreq;
161 unsigned int delta, tmpdelta;
162 unsigned int testp, testm, testn;
163 unsigned int p, m, n;
164 unsigned int computed;
165 int i, j, tmpcount, vcount;
166 bool pll_locked = false;
167 u8 tmp;
168
169 m = n = p = 0;
170 vcomax = 550000;
171 vcomin = 150000;
172 pllreffreq = 48000;
173
174 delta = 0xffffffff;
175
176 for (testp = 1; testp < 9; testp++) {
177 if (clock * testp > vcomax)
178 continue;
179 if (clock * testp < vcomin)
180 continue;
181
182 for (testm = 1; testm < 17; testm++) {
183 for (testn = 1; testn < 151; testn++) {
184 computed = (pllreffreq * testn) /
185 (testm * testp);
186 if (computed > clock)
187 tmpdelta = computed - clock;
188 else
189 tmpdelta = clock - computed;
190 if (tmpdelta < delta) {
191 delta = tmpdelta;
192 n = testn - 1;
193 m = (testm - 1) | ((n >> 1) & 0x80);
194 p = testp - 1;
195 }
196 }
197 }
198 }
199
200 for (i = 0; i <= 32 && pll_locked == false; i++) {
201 if (i > 0) {
202 WREG8(MGAREG_CRTC_INDEX, 0x1e);
203 tmp = RREG8(MGAREG_CRTC_DATA);
204 if (tmp < 0xff)
205 WREG8(MGAREG_CRTC_DATA, tmp+1);
206 }
207
208 /* set pixclkdis to 1 */
209 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
210 tmp = RREG8(DAC_DATA);
211 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
212 WREG8(DAC_DATA, tmp);
213
214 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
215 tmp = RREG8(DAC_DATA);
216 tmp |= MGA1064_REMHEADCTL_CLKDIS;
217 WREG8(DAC_DATA, tmp);
218
219 /* select PLL Set C */
220 tmp = RREG8(MGAREG_MEM_MISC_READ);
221 tmp |= 0x3 << 2;
222 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
223
224 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
225 tmp = RREG8(DAC_DATA);
226 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
227 WREG8(DAC_DATA, tmp);
228
229 udelay(500);
230
231 /* reset the PLL */
232 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
233 tmp = RREG8(DAC_DATA);
234 tmp &= ~0x04;
235 WREG8(DAC_DATA, tmp);
236
237 udelay(50);
238
239 /* program pixel pll register */
240 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
241 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
242 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
243
244 udelay(50);
245
246 /* turn pll on */
247 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
248 tmp = RREG8(DAC_DATA);
249 tmp |= 0x04;
250 WREG_DAC(MGA1064_VREF_CTL, tmp);
251
252 udelay(500);
253
254 /* select the pixel pll */
255 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
256 tmp = RREG8(DAC_DATA);
257 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
258 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
259 WREG8(DAC_DATA, tmp);
260
261 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
262 tmp = RREG8(DAC_DATA);
263 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
264 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
265 WREG8(DAC_DATA, tmp);
266
267 /* reset dotclock rate bit */
268 WREG8(MGAREG_SEQ_INDEX, 1);
269 tmp = RREG8(MGAREG_SEQ_DATA);
270 tmp &= ~0x8;
271 WREG8(MGAREG_SEQ_DATA, tmp);
272
273 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
274 tmp = RREG8(DAC_DATA);
275 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
276 WREG8(DAC_DATA, tmp);
277
278 vcount = RREG8(MGAREG_VCOUNT);
279
280 for (j = 0; j < 30 && pll_locked == false; j++) {
281 tmpcount = RREG8(MGAREG_VCOUNT);
282 if (tmpcount < vcount)
283 vcount = 0;
284 if ((tmpcount - vcount) > 2)
285 pll_locked = true;
286 else
287 udelay(5);
288 }
289 }
290 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
291 tmp = RREG8(DAC_DATA);
292 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
293 WREG_DAC(MGA1064_REMHEADCTL, tmp);
294 return 0;
295 }
296
297 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
298 {
299 unsigned int vcomax, vcomin, pllreffreq;
300 unsigned int delta, tmpdelta;
301 unsigned int testp, testm, testn;
302 unsigned int p, m, n;
303 unsigned int computed;
304 u8 tmp;
305
306 m = n = p = 0;
307 vcomax = 550000;
308 vcomin = 150000;
309 pllreffreq = 50000;
310
311 delta = 0xffffffff;
312
313 for (testp = 16; testp > 0; testp--) {
314 if (clock * testp > vcomax)
315 continue;
316 if (clock * testp < vcomin)
317 continue;
318
319 for (testn = 1; testn < 257; testn++) {
320 for (testm = 1; testm < 17; testm++) {
321 computed = (pllreffreq * testn) /
322 (testm * testp);
323 if (computed > clock)
324 tmpdelta = computed - clock;
325 else
326 tmpdelta = clock - computed;
327 if (tmpdelta < delta) {
328 delta = tmpdelta;
329 n = testn - 1;
330 m = testm - 1;
331 p = testp - 1;
332 }
333 }
334 }
335 }
336
337 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
338 tmp = RREG8(DAC_DATA);
339 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
340 WREG8(DAC_DATA, tmp);
341
342 tmp = RREG8(MGAREG_MEM_MISC_READ);
343 tmp |= 0x3 << 2;
344 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
345
346 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
347 tmp = RREG8(DAC_DATA);
348 WREG8(DAC_DATA, tmp & ~0x40);
349
350 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
351 tmp = RREG8(DAC_DATA);
352 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
353 WREG8(DAC_DATA, tmp);
354
355 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
356 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
357 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
358
359 udelay(50);
360
361 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
362 tmp = RREG8(DAC_DATA);
363 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
364 WREG8(DAC_DATA, tmp);
365
366 udelay(500);
367
368 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
369 tmp = RREG8(DAC_DATA);
370 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
371 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
372 WREG8(DAC_DATA, tmp);
373
374 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
375 tmp = RREG8(DAC_DATA);
376 WREG8(DAC_DATA, tmp | 0x40);
377
378 tmp = RREG8(MGAREG_MEM_MISC_READ);
379 tmp |= (0x3 << 2);
380 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
381
382 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
383 tmp = RREG8(DAC_DATA);
384 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
385 WREG8(DAC_DATA, tmp);
386
387 return 0;
388 }
389
390 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
391 {
392 unsigned int vcomax, vcomin, pllreffreq;
393 unsigned int delta, tmpdelta;
394 unsigned int testp, testm, testn;
395 unsigned int p, m, n;
396 unsigned int computed;
397 int i, j, tmpcount, vcount;
398 u8 tmp;
399 bool pll_locked = false;
400
401 m = n = p = 0;
402 vcomax = 800000;
403 vcomin = 400000;
404 pllreffreq = 33333;
405
406 delta = 0xffffffff;
407
408 for (testp = 16; testp > 0; testp >>= 1) {
409 if (clock * testp > vcomax)
410 continue;
411 if (clock * testp < vcomin)
412 continue;
413
414 for (testm = 1; testm < 33; testm++) {
415 for (testn = 17; testn < 257; testn++) {
416 computed = (pllreffreq * testn) /
417 (testm * testp);
418 if (computed > clock)
419 tmpdelta = computed - clock;
420 else
421 tmpdelta = clock - computed;
422 if (tmpdelta < delta) {
423 delta = tmpdelta;
424 n = testn - 1;
425 m = (testm - 1);
426 p = testp - 1;
427 }
428 if ((clock * testp) >= 600000)
429 p |= 0x80;
430 }
431 }
432 }
433 for (i = 0; i <= 32 && pll_locked == false; i++) {
434 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
435 tmp = RREG8(DAC_DATA);
436 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
437 WREG8(DAC_DATA, tmp);
438
439 tmp = RREG8(MGAREG_MEM_MISC_READ);
440 tmp |= 0x3 << 2;
441 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
442
443 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
444 tmp = RREG8(DAC_DATA);
445 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
446 WREG8(DAC_DATA, tmp);
447
448 udelay(500);
449
450 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
451 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
452 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
453
454 udelay(500);
455
456 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
457 tmp = RREG8(DAC_DATA);
458 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
459 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
460 WREG8(DAC_DATA, tmp);
461
462 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
463 tmp = RREG8(DAC_DATA);
464 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
465 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
466 WREG8(DAC_DATA, tmp);
467
468 vcount = RREG8(MGAREG_VCOUNT);
469
470 for (j = 0; j < 30 && pll_locked == false; j++) {
471 tmpcount = RREG8(MGAREG_VCOUNT);
472 if (tmpcount < vcount)
473 vcount = 0;
474 if ((tmpcount - vcount) > 2)
475 pll_locked = true;
476 else
477 udelay(5);
478 }
479 }
480
481 return 0;
482 }
483
484 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
485 {
486 unsigned int vcomax, vcomin, pllreffreq;
487 unsigned int delta, tmpdelta;
488 int testr, testn, testm, testo;
489 unsigned int p, m, n;
490 unsigned int computed, vco;
491 int tmp;
492 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
493
494 m = n = p = 0;
495 vcomax = 1488000;
496 vcomin = 1056000;
497 pllreffreq = 48000;
498
499 delta = 0xffffffff;
500
501 for (testr = 0; testr < 4; testr++) {
502 if (delta == 0)
503 break;
504 for (testn = 5; testn < 129; testn++) {
505 if (delta == 0)
506 break;
507 for (testm = 3; testm >= 0; testm--) {
508 if (delta == 0)
509 break;
510 for (testo = 5; testo < 33; testo++) {
511 vco = pllreffreq * (testn + 1) /
512 (testr + 1);
513 if (vco < vcomin)
514 continue;
515 if (vco > vcomax)
516 continue;
517 computed = vco / (m_div_val[testm] * (testo + 1));
518 if (computed > clock)
519 tmpdelta = computed - clock;
520 else
521 tmpdelta = clock - computed;
522 if (tmpdelta < delta) {
523 delta = tmpdelta;
524 m = testm | (testo << 3);
525 n = testn;
526 p = testr | (testr << 3);
527 }
528 }
529 }
530 }
531 }
532
533 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
534 tmp = RREG8(DAC_DATA);
535 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
536 WREG8(DAC_DATA, tmp);
537
538 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
539 tmp = RREG8(DAC_DATA);
540 tmp |= MGA1064_REMHEADCTL_CLKDIS;
541 WREG8(DAC_DATA, tmp);
542
543 tmp = RREG8(MGAREG_MEM_MISC_READ);
544 tmp |= (0x3<<2) | 0xc0;
545 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
546
547 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
548 tmp = RREG8(DAC_DATA);
549 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
550 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
551 WREG8(DAC_DATA, tmp);
552
553 udelay(500);
554
555 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
556 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
557 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
558
559 udelay(50);
560
561 return 0;
562 }
563
564 static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
565 {
566 switch(mdev->type) {
567 case G200_SE_A:
568 case G200_SE_B:
569 return mga_g200se_set_plls(mdev, clock);
570 break;
571 case G200_WB:
572 return mga_g200wb_set_plls(mdev, clock);
573 break;
574 case G200_EV:
575 return mga_g200ev_set_plls(mdev, clock);
576 break;
577 case G200_EH:
578 return mga_g200eh_set_plls(mdev, clock);
579 break;
580 case G200_ER:
581 return mga_g200er_set_plls(mdev, clock);
582 break;
583 }
584 return 0;
585 }
586
587 static void mga_g200wb_prepare(struct drm_crtc *crtc)
588 {
589 struct mga_device *mdev = crtc->dev->dev_private;
590 u8 tmp;
591 int iter_max;
592
593 /* 1- The first step is to warn the BMC of an upcoming mode change.
594 * We are putting the misc<0> to output.*/
595
596 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
597 tmp = RREG8(DAC_DATA);
598 tmp |= 0x10;
599 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
600
601 /* we are putting a 1 on the misc<0> line */
602 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
603 tmp = RREG8(DAC_DATA);
604 tmp |= 0x10;
605 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
606
607 /* 2- Second step to mask and further scan request
608 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
609 */
610 WREG8(DAC_INDEX, MGA1064_SPAREREG);
611 tmp = RREG8(DAC_DATA);
612 tmp |= 0x80;
613 WREG_DAC(MGA1064_SPAREREG, tmp);
614
615 /* 3a- the third step is to verifu if there is an active scan
616 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
617 */
618 iter_max = 300;
619 while (!(tmp & 0x1) && iter_max) {
620 WREG8(DAC_INDEX, MGA1064_SPAREREG);
621 tmp = RREG8(DAC_DATA);
622 udelay(1000);
623 iter_max--;
624 }
625
626 /* 3b- this step occurs only if the remove is actually scanning
627 * we are waiting for the end of the frame which is a 1 on
628 * remvsyncsts (XSPAREREG<1>)
629 */
630 if (iter_max) {
631 iter_max = 300;
632 while ((tmp & 0x2) && iter_max) {
633 WREG8(DAC_INDEX, MGA1064_SPAREREG);
634 tmp = RREG8(DAC_DATA);
635 udelay(1000);
636 iter_max--;
637 }
638 }
639 }
640
641 static void mga_g200wb_commit(struct drm_crtc *crtc)
642 {
643 u8 tmp;
644 struct mga_device *mdev = crtc->dev->dev_private;
645
646 /* 1- The first step is to ensure that the vrsten and hrsten are set */
647 WREG8(MGAREG_CRTCEXT_INDEX, 1);
648 tmp = RREG8(MGAREG_CRTCEXT_DATA);
649 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
650
651 /* 2- second step is to assert the rstlvl2 */
652 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
653 tmp = RREG8(DAC_DATA);
654 tmp |= 0x8;
655 WREG8(DAC_DATA, tmp);
656
657 /* wait 10 us */
658 udelay(10);
659
660 /* 3- deassert rstlvl2 */
661 tmp &= ~0x08;
662 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
663 WREG8(DAC_DATA, tmp);
664
665 /* 4- remove mask of scan request */
666 WREG8(DAC_INDEX, MGA1064_SPAREREG);
667 tmp = RREG8(DAC_DATA);
668 tmp &= ~0x80;
669 WREG8(DAC_DATA, tmp);
670
671 /* 5- put back a 0 on the misc<0> line */
672 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
673 tmp = RREG8(DAC_DATA);
674 tmp &= ~0x10;
675 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
676 }
677
678 /*
679 This is how the framebuffer base address is stored in g200 cards:
680 * Assume @offset is the gpu_addr variable of the framebuffer object
681 * Then addr is the number of _pixels_ (not bytes) from the start of
682 VRAM to the first pixel we want to display. (divided by 2 for 32bit
683 framebuffers)
684 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
685 addr<20> -> CRTCEXT0<6>
686 addr<19-16> -> CRTCEXT0<3-0>
687 addr<15-8> -> CRTCC<7-0>
688 addr<7-0> -> CRTCD<7-0>
689 CRTCEXT0 has to be programmed last to trigger an update and make the
690 new addr variable take effect.
691 */
692 static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
693 {
694 struct mga_device *mdev = crtc->dev->dev_private;
695 u32 addr;
696 int count;
697 u8 crtcext0;
698
699 while (RREG8(0x1fda) & 0x08);
700 while (!(RREG8(0x1fda) & 0x08));
701
702 count = RREG8(MGAREG_VCOUNT) + 2;
703 while (RREG8(MGAREG_VCOUNT) < count);
704
705 WREG8(MGAREG_CRTCEXT_INDEX, 0);
706 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
707 crtcext0 &= 0xB0;
708 addr = offset / 8;
709 /* Can't store addresses any higher than that...
710 but we also don't have more than 16MB of memory, so it should be fine. */
711 WARN_ON(addr > 0x1fffff);
712 crtcext0 |= (!!(addr & (1<<20)))<<6;
713 WREG_CRT(0x0d, (u8)(addr & 0xff));
714 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
715 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
716 }
717
718
719 /* ast is different - we will force move buffers out of VRAM */
720 static int mga_crtc_do_set_base(struct drm_crtc *crtc,
721 struct drm_framebuffer *fb,
722 int x, int y, int atomic)
723 {
724 struct mga_device *mdev = crtc->dev->dev_private;
725 struct drm_gem_object *obj;
726 struct mga_framebuffer *mga_fb;
727 struct mgag200_bo *bo;
728 int ret;
729 u64 gpu_addr;
730
731 /* push the previous fb to system ram */
732 if (!atomic && fb) {
733 mga_fb = to_mga_framebuffer(fb);
734 obj = mga_fb->obj;
735 bo = gem_to_mga_bo(obj);
736 ret = mgag200_bo_reserve(bo, false);
737 if (ret)
738 return ret;
739 mgag200_bo_push_sysram(bo);
740 mgag200_bo_unreserve(bo);
741 }
742
743 mga_fb = to_mga_framebuffer(crtc->primary->fb);
744 obj = mga_fb->obj;
745 bo = gem_to_mga_bo(obj);
746
747 ret = mgag200_bo_reserve(bo, false);
748 if (ret)
749 return ret;
750
751 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
752 if (ret) {
753 mgag200_bo_unreserve(bo);
754 return ret;
755 }
756
757 if (&mdev->mfbdev->mfb == mga_fb) {
758 /* if pushing console in kmap it */
759 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
760 if (ret)
761 DRM_ERROR("failed to kmap fbcon\n");
762
763 }
764 mgag200_bo_unreserve(bo);
765
766 mga_set_start_address(crtc, (u32)gpu_addr);
767
768 return 0;
769 }
770
771 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
772 struct drm_framebuffer *old_fb)
773 {
774 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
775 }
776
777 static int mga_crtc_mode_set(struct drm_crtc *crtc,
778 struct drm_display_mode *mode,
779 struct drm_display_mode *adjusted_mode,
780 int x, int y, struct drm_framebuffer *old_fb)
781 {
782 struct drm_device *dev = crtc->dev;
783 struct mga_device *mdev = dev->dev_private;
784 int hdisplay, hsyncstart, hsyncend, htotal;
785 int vdisplay, vsyncstart, vsyncend, vtotal;
786 int pitch;
787 int option = 0, option2 = 0;
788 int i;
789 unsigned char misc = 0;
790 unsigned char ext_vga[6];
791 u8 bppshift;
792
793 static unsigned char dacvalue[] = {
794 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
795 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
796 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
797 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
798 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
799 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
800 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
801 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
802 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
803 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
804 };
805
806 bppshift = mdev->bpp_shifts[(crtc->primary->fb->bits_per_pixel >> 3) - 1];
807
808 switch (mdev->type) {
809 case G200_SE_A:
810 case G200_SE_B:
811 dacvalue[MGA1064_VREF_CTL] = 0x03;
812 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
813 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
814 MGA1064_MISC_CTL_VGA8 |
815 MGA1064_MISC_CTL_DAC_RAM_CS;
816 if (mdev->has_sdram)
817 option = 0x40049120;
818 else
819 option = 0x4004d120;
820 option2 = 0x00008000;
821 break;
822 case G200_WB:
823 dacvalue[MGA1064_VREF_CTL] = 0x07;
824 option = 0x41049120;
825 option2 = 0x0000b000;
826 break;
827 case G200_EV:
828 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
829 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
830 MGA1064_MISC_CTL_DAC_RAM_CS;
831 option = 0x00000120;
832 option2 = 0x0000b000;
833 break;
834 case G200_EH:
835 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
836 MGA1064_MISC_CTL_DAC_RAM_CS;
837 option = 0x00000120;
838 option2 = 0x0000b000;
839 break;
840 case G200_ER:
841 break;
842 }
843
844 switch (crtc->primary->fb->bits_per_pixel) {
845 case 8:
846 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
847 break;
848 case 16:
849 if (crtc->primary->fb->depth == 15)
850 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
851 else
852 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
853 break;
854 case 24:
855 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
856 break;
857 case 32:
858 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
859 break;
860 }
861
862 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
863 misc |= 0x40;
864 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
865 misc |= 0x80;
866
867
868 for (i = 0; i < sizeof(dacvalue); i++) {
869 if ((i <= 0x17) ||
870 (i == 0x1b) ||
871 (i == 0x1c) ||
872 ((i >= 0x1f) && (i <= 0x29)) ||
873 ((i >= 0x30) && (i <= 0x37)))
874 continue;
875 if (IS_G200_SE(mdev) &&
876 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
877 continue;
878 if ((mdev->type == G200_EV || mdev->type == G200_WB || mdev->type == G200_EH) &&
879 (i >= 0x44) && (i <= 0x4e))
880 continue;
881
882 WREG_DAC(i, dacvalue[i]);
883 }
884
885 if (mdev->type == G200_ER)
886 WREG_DAC(0x90, 0);
887
888 if (option)
889 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
890 if (option2)
891 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
892
893 WREG_SEQ(2, 0xf);
894 WREG_SEQ(3, 0);
895 WREG_SEQ(4, 0xe);
896
897 pitch = crtc->primary->fb->pitches[0] / (crtc->primary->fb->bits_per_pixel / 8);
898 if (crtc->primary->fb->bits_per_pixel == 24)
899 pitch = (pitch * 3) >> (4 - bppshift);
900 else
901 pitch = pitch >> (4 - bppshift);
902
903 hdisplay = mode->hdisplay / 8 - 1;
904 hsyncstart = mode->hsync_start / 8 - 1;
905 hsyncend = mode->hsync_end / 8 - 1;
906 htotal = mode->htotal / 8 - 1;
907
908 /* Work around hardware quirk */
909 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
910 htotal++;
911
912 vdisplay = mode->vdisplay - 1;
913 vsyncstart = mode->vsync_start - 1;
914 vsyncend = mode->vsync_end - 1;
915 vtotal = mode->vtotal - 2;
916
917 WREG_GFX(0, 0);
918 WREG_GFX(1, 0);
919 WREG_GFX(2, 0);
920 WREG_GFX(3, 0);
921 WREG_GFX(4, 0);
922 WREG_GFX(5, 0x40);
923 WREG_GFX(6, 0x5);
924 WREG_GFX(7, 0xf);
925 WREG_GFX(8, 0xf);
926
927 WREG_CRT(0, htotal - 4);
928 WREG_CRT(1, hdisplay);
929 WREG_CRT(2, hdisplay);
930 WREG_CRT(3, (htotal & 0x1F) | 0x80);
931 WREG_CRT(4, hsyncstart);
932 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
933 WREG_CRT(6, vtotal & 0xFF);
934 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
935 ((vdisplay & 0x100) >> 7) |
936 ((vsyncstart & 0x100) >> 6) |
937 ((vdisplay & 0x100) >> 5) |
938 ((vdisplay & 0x100) >> 4) | /* linecomp */
939 ((vtotal & 0x200) >> 4)|
940 ((vdisplay & 0x200) >> 3) |
941 ((vsyncstart & 0x200) >> 2));
942 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
943 ((vdisplay & 0x200) >> 3));
944 WREG_CRT(10, 0);
945 WREG_CRT(11, 0);
946 WREG_CRT(12, 0);
947 WREG_CRT(13, 0);
948 WREG_CRT(14, 0);
949 WREG_CRT(15, 0);
950 WREG_CRT(16, vsyncstart & 0xFF);
951 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
952 WREG_CRT(18, vdisplay & 0xFF);
953 WREG_CRT(19, pitch & 0xFF);
954 WREG_CRT(20, 0);
955 WREG_CRT(21, vdisplay & 0xFF);
956 WREG_CRT(22, (vtotal + 1) & 0xFF);
957 WREG_CRT(23, 0xc3);
958 WREG_CRT(24, vdisplay & 0xFF);
959
960 ext_vga[0] = 0;
961 ext_vga[5] = 0;
962
963 /* TODO interlace */
964
965 ext_vga[0] |= (pitch & 0x300) >> 4;
966 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
967 ((hdisplay & 0x100) >> 7) |
968 ((hsyncstart & 0x100) >> 6) |
969 (htotal & 0x40);
970 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
971 ((vdisplay & 0x400) >> 8) |
972 ((vdisplay & 0xc00) >> 7) |
973 ((vsyncstart & 0xc00) >> 5) |
974 ((vdisplay & 0x400) >> 3);
975 if (crtc->primary->fb->bits_per_pixel == 24)
976 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
977 else
978 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
979 ext_vga[4] = 0;
980 if (mdev->type == G200_WB)
981 ext_vga[1] |= 0x88;
982
983 /* Set pixel clocks */
984 misc = 0x2d;
985 WREG8(MGA_MISC_OUT, misc);
986
987 mga_crtc_set_plls(mdev, mode->clock);
988
989 for (i = 0; i < 6; i++) {
990 WREG_ECRT(i, ext_vga[i]);
991 }
992
993 if (mdev->type == G200_ER)
994 WREG_ECRT(0x24, 0x5);
995
996 if (mdev->type == G200_EV) {
997 WREG_ECRT(6, 0);
998 }
999
1000 WREG_ECRT(0, ext_vga[0]);
1001 /* Enable mga pixel clock */
1002 misc = 0x2d;
1003
1004 WREG8(MGA_MISC_OUT, misc);
1005
1006 if (adjusted_mode)
1007 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
1008
1009 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
1010
1011 /* reset tagfifo */
1012 if (mdev->type == G200_ER) {
1013 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
1014 u8 seq1;
1015
1016 /* screen off */
1017 WREG8(MGAREG_SEQ_INDEX, 0x01);
1018 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
1019 WREG8(MGAREG_SEQ_DATA, seq1);
1020
1021 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
1022 udelay(1000);
1023 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1024
1025 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1026 }
1027
1028
1029 if (IS_G200_SE(mdev)) {
1030 if (mdev->unique_rev_id >= 0x02) {
1031 u8 hi_pri_lvl;
1032 u32 bpp;
1033 u32 mb;
1034
1035 if (crtc->primary->fb->bits_per_pixel > 16)
1036 bpp = 32;
1037 else if (crtc->primary->fb->bits_per_pixel > 8)
1038 bpp = 16;
1039 else
1040 bpp = 8;
1041
1042 mb = (mode->clock * bpp) / 1000;
1043 if (mb > 3100)
1044 hi_pri_lvl = 0;
1045 else if (mb > 2600)
1046 hi_pri_lvl = 1;
1047 else if (mb > 1900)
1048 hi_pri_lvl = 2;
1049 else if (mb > 1160)
1050 hi_pri_lvl = 3;
1051 else if (mb > 440)
1052 hi_pri_lvl = 4;
1053 else
1054 hi_pri_lvl = 5;
1055
1056 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1057 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
1058 } else {
1059 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1060 if (mdev->unique_rev_id >= 0x01)
1061 WREG8(MGAREG_CRTCEXT_DATA, 0x03);
1062 else
1063 WREG8(MGAREG_CRTCEXT_DATA, 0x04);
1064 }
1065 }
1066 return 0;
1067 }
1068
1069 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1070 static int mga_suspend(struct drm_crtc *crtc)
1071 {
1072 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1073 struct drm_device *dev = crtc->dev;
1074 struct mga_device *mdev = dev->dev_private;
1075 struct pci_dev *pdev = dev->pdev;
1076 int option;
1077
1078 if (mdev->suspended)
1079 return 0;
1080
1081 WREG_SEQ(1, 0x20);
1082 WREG_ECRT(1, 0x30);
1083 /* Disable the pixel clock */
1084 WREG_DAC(0x1a, 0x05);
1085 /* Power down the DAC */
1086 WREG_DAC(0x1e, 0x18);
1087 /* Power down the pixel PLL */
1088 WREG_DAC(0x1a, 0x0d);
1089
1090 /* Disable PLLs and clocks */
1091 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1092 option &= ~(0x1F8024);
1093 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1094 pci_set_power_state(pdev, PCI_D3hot);
1095 pci_disable_device(pdev);
1096
1097 mdev->suspended = true;
1098
1099 return 0;
1100 }
1101
1102 static int mga_resume(struct drm_crtc *crtc)
1103 {
1104 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1105 struct drm_device *dev = crtc->dev;
1106 struct mga_device *mdev = dev->dev_private;
1107 struct pci_dev *pdev = dev->pdev;
1108 int option;
1109
1110 if (!mdev->suspended)
1111 return 0;
1112
1113 pci_set_power_state(pdev, PCI_D0);
1114 pci_enable_device(pdev);
1115
1116 /* Disable sysclk */
1117 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1118 option &= ~(0x4);
1119 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1120
1121 mdev->suspended = false;
1122
1123 return 0;
1124 }
1125
1126 #endif
1127
1128 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1129 {
1130 struct drm_device *dev = crtc->dev;
1131 struct mga_device *mdev = dev->dev_private;
1132 u8 seq1 = 0, crtcext1 = 0;
1133
1134 switch (mode) {
1135 case DRM_MODE_DPMS_ON:
1136 seq1 = 0;
1137 crtcext1 = 0;
1138 mga_crtc_load_lut(crtc);
1139 break;
1140 case DRM_MODE_DPMS_STANDBY:
1141 seq1 = 0x20;
1142 crtcext1 = 0x10;
1143 break;
1144 case DRM_MODE_DPMS_SUSPEND:
1145 seq1 = 0x20;
1146 crtcext1 = 0x20;
1147 break;
1148 case DRM_MODE_DPMS_OFF:
1149 seq1 = 0x20;
1150 crtcext1 = 0x30;
1151 break;
1152 }
1153
1154 #if 0
1155 if (mode == DRM_MODE_DPMS_OFF) {
1156 mga_suspend(crtc);
1157 }
1158 #endif
1159 WREG8(MGAREG_SEQ_INDEX, 0x01);
1160 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1161 mga_wait_vsync(mdev);
1162 mga_wait_busy(mdev);
1163 WREG8(MGAREG_SEQ_DATA, seq1);
1164 msleep(20);
1165 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1166 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1167 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1168
1169 #if 0
1170 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1171 mga_resume(crtc);
1172 drm_helper_resume_force_mode(dev);
1173 }
1174 #endif
1175 }
1176
1177 /*
1178 * This is called before a mode is programmed. A typical use might be to
1179 * enable DPMS during the programming to avoid seeing intermediate stages,
1180 * but that's not relevant to us
1181 */
1182 static void mga_crtc_prepare(struct drm_crtc *crtc)
1183 {
1184 struct drm_device *dev = crtc->dev;
1185 struct mga_device *mdev = dev->dev_private;
1186 u8 tmp;
1187
1188 /* mga_resume(crtc);*/
1189
1190 WREG8(MGAREG_CRTC_INDEX, 0x11);
1191 tmp = RREG8(MGAREG_CRTC_DATA);
1192 WREG_CRT(0x11, tmp | 0x80);
1193
1194 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1195 WREG_SEQ(0, 1);
1196 msleep(50);
1197 WREG_SEQ(1, 0x20);
1198 msleep(20);
1199 } else {
1200 WREG8(MGAREG_SEQ_INDEX, 0x1);
1201 tmp = RREG8(MGAREG_SEQ_DATA);
1202
1203 /* start sync reset */
1204 WREG_SEQ(0, 1);
1205 WREG_SEQ(1, tmp | 0x20);
1206 }
1207
1208 if (mdev->type == G200_WB)
1209 mga_g200wb_prepare(crtc);
1210
1211 WREG_CRT(17, 0);
1212 }
1213
1214 /*
1215 * This is called after a mode is programmed. It should reverse anything done
1216 * by the prepare function
1217 */
1218 static void mga_crtc_commit(struct drm_crtc *crtc)
1219 {
1220 struct drm_device *dev = crtc->dev;
1221 struct mga_device *mdev = dev->dev_private;
1222 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1223 u8 tmp;
1224
1225 if (mdev->type == G200_WB)
1226 mga_g200wb_commit(crtc);
1227
1228 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1229 msleep(50);
1230 WREG_SEQ(1, 0x0);
1231 msleep(20);
1232 WREG_SEQ(0, 0x3);
1233 } else {
1234 WREG8(MGAREG_SEQ_INDEX, 0x1);
1235 tmp = RREG8(MGAREG_SEQ_DATA);
1236
1237 tmp &= ~0x20;
1238 WREG_SEQ(0x1, tmp);
1239 WREG_SEQ(0, 3);
1240 }
1241 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1242 }
1243
1244 /*
1245 * The core can pass us a set of gamma values to program. We actually only
1246 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1247 * but it's a requirement that we provide the function
1248 */
1249 static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1250 u16 *blue, uint32_t start, uint32_t size)
1251 {
1252 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1253 int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size;
1254 int i;
1255
1256 for (i = start; i < end; i++) {
1257 mga_crtc->lut_r[i] = red[i] >> 8;
1258 mga_crtc->lut_g[i] = green[i] >> 8;
1259 mga_crtc->lut_b[i] = blue[i] >> 8;
1260 }
1261 mga_crtc_load_lut(crtc);
1262 }
1263
1264 /* Simple cleanup function */
1265 static void mga_crtc_destroy(struct drm_crtc *crtc)
1266 {
1267 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1268
1269 drm_crtc_cleanup(crtc);
1270 kfree(mga_crtc);
1271 }
1272
1273 static void mga_crtc_disable(struct drm_crtc *crtc)
1274 {
1275 int ret;
1276 DRM_DEBUG_KMS("\n");
1277 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1278 if (crtc->primary->fb) {
1279 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb);
1280 struct drm_gem_object *obj = mga_fb->obj;
1281 struct mgag200_bo *bo = gem_to_mga_bo(obj);
1282 ret = mgag200_bo_reserve(bo, false);
1283 if (ret)
1284 return;
1285 mgag200_bo_push_sysram(bo);
1286 mgag200_bo_unreserve(bo);
1287 }
1288 crtc->primary->fb = NULL;
1289 }
1290
1291 /* These provide the minimum set of functions required to handle a CRTC */
1292 static const struct drm_crtc_funcs mga_crtc_funcs = {
1293 .cursor_set = mga_crtc_cursor_set,
1294 .cursor_move = mga_crtc_cursor_move,
1295 .gamma_set = mga_crtc_gamma_set,
1296 .set_config = drm_crtc_helper_set_config,
1297 .destroy = mga_crtc_destroy,
1298 };
1299
1300 static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1301 .disable = mga_crtc_disable,
1302 .dpms = mga_crtc_dpms,
1303 .mode_fixup = mga_crtc_mode_fixup,
1304 .mode_set = mga_crtc_mode_set,
1305 .mode_set_base = mga_crtc_mode_set_base,
1306 .prepare = mga_crtc_prepare,
1307 .commit = mga_crtc_commit,
1308 .load_lut = mga_crtc_load_lut,
1309 };
1310
1311 /* CRTC setup */
1312 static void mga_crtc_init(struct mga_device *mdev)
1313 {
1314 struct mga_crtc *mga_crtc;
1315 int i;
1316
1317 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1318 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1319 GFP_KERNEL);
1320
1321 if (mga_crtc == NULL)
1322 return;
1323
1324 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
1325
1326 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1327 mdev->mode_info.crtc = mga_crtc;
1328
1329 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1330 mga_crtc->lut_r[i] = i;
1331 mga_crtc->lut_g[i] = i;
1332 mga_crtc->lut_b[i] = i;
1333 }
1334
1335 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1336 }
1337
1338 /** Sets the color ramps on behalf of fbcon */
1339 void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1340 u16 blue, int regno)
1341 {
1342 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1343
1344 mga_crtc->lut_r[regno] = red >> 8;
1345 mga_crtc->lut_g[regno] = green >> 8;
1346 mga_crtc->lut_b[regno] = blue >> 8;
1347 }
1348
1349 /** Gets the color ramps on behalf of fbcon */
1350 void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1351 u16 *blue, int regno)
1352 {
1353 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1354
1355 *red = (u16)mga_crtc->lut_r[regno] << 8;
1356 *green = (u16)mga_crtc->lut_g[regno] << 8;
1357 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1358 }
1359
1360 /*
1361 * The encoder comes after the CRTC in the output pipeline, but before
1362 * the connector. It's responsible for ensuring that the digital
1363 * stream is appropriately converted into the output format. Setup is
1364 * very simple in this case - all we have to do is inform qemu of the
1365 * colour depth in order to ensure that it displays appropriately
1366 */
1367
1368 /*
1369 * These functions are analagous to those in the CRTC code, but are intended
1370 * to handle any encoder-specific limitations
1371 */
1372 static bool mga_encoder_mode_fixup(struct drm_encoder *encoder,
1373 const struct drm_display_mode *mode,
1374 struct drm_display_mode *adjusted_mode)
1375 {
1376 return true;
1377 }
1378
1379 static void mga_encoder_mode_set(struct drm_encoder *encoder,
1380 struct drm_display_mode *mode,
1381 struct drm_display_mode *adjusted_mode)
1382 {
1383
1384 }
1385
1386 static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1387 {
1388 return;
1389 }
1390
1391 static void mga_encoder_prepare(struct drm_encoder *encoder)
1392 {
1393 }
1394
1395 static void mga_encoder_commit(struct drm_encoder *encoder)
1396 {
1397 }
1398
1399 static void mga_encoder_destroy(struct drm_encoder *encoder)
1400 {
1401 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1402 drm_encoder_cleanup(encoder);
1403 kfree(mga_encoder);
1404 }
1405
1406 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1407 .dpms = mga_encoder_dpms,
1408 .mode_fixup = mga_encoder_mode_fixup,
1409 .mode_set = mga_encoder_mode_set,
1410 .prepare = mga_encoder_prepare,
1411 .commit = mga_encoder_commit,
1412 };
1413
1414 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1415 .destroy = mga_encoder_destroy,
1416 };
1417
1418 static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1419 {
1420 struct drm_encoder *encoder;
1421 struct mga_encoder *mga_encoder;
1422
1423 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1424 if (!mga_encoder)
1425 return NULL;
1426
1427 encoder = &mga_encoder->base;
1428 encoder->possible_crtcs = 0x1;
1429
1430 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
1431 DRM_MODE_ENCODER_DAC);
1432 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1433
1434 return encoder;
1435 }
1436
1437
1438 static int mga_vga_get_modes(struct drm_connector *connector)
1439 {
1440 struct mga_connector *mga_connector = to_mga_connector(connector);
1441 struct edid *edid;
1442 int ret = 0;
1443
1444 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1445 if (edid) {
1446 drm_mode_connector_update_edid_property(connector, edid);
1447 ret = drm_add_edid_modes(connector, edid);
1448 kfree(edid);
1449 }
1450 return ret;
1451 }
1452
1453 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1454 int bits_per_pixel)
1455 {
1456 uint32_t total_area, divisor;
1457 int64_t active_area, pixels_per_second, bandwidth;
1458 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1459
1460 divisor = 1024;
1461
1462 if (!mode->htotal || !mode->vtotal || !mode->clock)
1463 return 0;
1464
1465 active_area = mode->hdisplay * mode->vdisplay;
1466 total_area = mode->htotal * mode->vtotal;
1467
1468 pixels_per_second = active_area * mode->clock * 1000;
1469 do_div(pixels_per_second, total_area);
1470
1471 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1472 do_div(bandwidth, divisor);
1473
1474 return (uint32_t)(bandwidth);
1475 }
1476
1477 #define MODE_BANDWIDTH MODE_BAD
1478
1479 static int mga_vga_mode_valid(struct drm_connector *connector,
1480 struct drm_display_mode *mode)
1481 {
1482 struct drm_device *dev = connector->dev;
1483 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
1484 int bpp = 32;
1485
1486 if (IS_G200_SE(mdev)) {
1487 if (mdev->unique_rev_id == 0x01) {
1488 if (mode->hdisplay > 1600)
1489 return MODE_VIRTUAL_X;
1490 if (mode->vdisplay > 1200)
1491 return MODE_VIRTUAL_Y;
1492 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1493 > (24400 * 1024))
1494 return MODE_BANDWIDTH;
1495 } else if (mdev->unique_rev_id >= 0x02) {
1496 if (mode->hdisplay > 1920)
1497 return MODE_VIRTUAL_X;
1498 if (mode->vdisplay > 1200)
1499 return MODE_VIRTUAL_Y;
1500 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1501 > (30100 * 1024))
1502 return MODE_BANDWIDTH;
1503 }
1504 } else if (mdev->type == G200_WB) {
1505 if (mode->hdisplay > 1280)
1506 return MODE_VIRTUAL_X;
1507 if (mode->vdisplay > 1024)
1508 return MODE_VIRTUAL_Y;
1509 if (mga_vga_calculate_mode_bandwidth(mode,
1510 bpp > (31877 * 1024)))
1511 return MODE_BANDWIDTH;
1512 } else if (mdev->type == G200_EV &&
1513 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1514 > (32700 * 1024))) {
1515 return MODE_BANDWIDTH;
1516 } else if (mdev->type == G200_EH &&
1517 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1518 > (37500 * 1024))) {
1519 return MODE_BANDWIDTH;
1520 } else if (mdev->type == G200_ER &&
1521 (mga_vga_calculate_mode_bandwidth(mode,
1522 bpp) > (55000 * 1024))) {
1523 return MODE_BANDWIDTH;
1524 }
1525
1526 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1527 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1528 return MODE_H_ILLEGAL;
1529 }
1530
1531 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1532 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1533 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1534 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1535 return MODE_BAD;
1536 }
1537
1538 /* Validate the mode input by the user */
1539 if (connector->cmdline_mode.specified) {
1540 if (connector->cmdline_mode.bpp_specified)
1541 bpp = connector->cmdline_mode.bpp;
1542 }
1543
1544 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
1545 if (connector->cmdline_mode.specified)
1546 connector->cmdline_mode.specified = false;
1547 return MODE_BAD;
1548 }
1549
1550 return MODE_OK;
1551 }
1552
1553 static struct drm_encoder *mga_connector_best_encoder(struct drm_connector
1554 *connector)
1555 {
1556 int enc_id = connector->encoder_ids[0];
1557 /* pick the encoder ids */
1558 if (enc_id)
1559 return drm_encoder_find(connector->dev, enc_id);
1560 return NULL;
1561 }
1562
1563 static enum drm_connector_status mga_vga_detect(struct drm_connector
1564 *connector, bool force)
1565 {
1566 return connector_status_connected;
1567 }
1568
1569 static void mga_connector_destroy(struct drm_connector *connector)
1570 {
1571 struct mga_connector *mga_connector = to_mga_connector(connector);
1572 mgag200_i2c_destroy(mga_connector->i2c);
1573 drm_connector_cleanup(connector);
1574 kfree(connector);
1575 }
1576
1577 struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1578 .get_modes = mga_vga_get_modes,
1579 .mode_valid = mga_vga_mode_valid,
1580 .best_encoder = mga_connector_best_encoder,
1581 };
1582
1583 struct drm_connector_funcs mga_vga_connector_funcs = {
1584 .dpms = drm_helper_connector_dpms,
1585 .detect = mga_vga_detect,
1586 .fill_modes = drm_helper_probe_single_connector_modes,
1587 .destroy = mga_connector_destroy,
1588 };
1589
1590 static struct drm_connector *mga_vga_init(struct drm_device *dev)
1591 {
1592 struct drm_connector *connector;
1593 struct mga_connector *mga_connector;
1594
1595 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1596 if (!mga_connector)
1597 return NULL;
1598
1599 connector = &mga_connector->base;
1600
1601 drm_connector_init(dev, connector,
1602 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1603
1604 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1605
1606 drm_connector_register(connector);
1607
1608 mga_connector->i2c = mgag200_i2c_create(dev);
1609 if (!mga_connector->i2c)
1610 DRM_ERROR("failed to add ddc bus\n");
1611
1612 return connector;
1613 }
1614
1615
1616 int mgag200_modeset_init(struct mga_device *mdev)
1617 {
1618 struct drm_encoder *encoder;
1619 struct drm_connector *connector;
1620 int ret;
1621
1622 mdev->mode_info.mode_config_initialized = true;
1623
1624 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1625 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1626
1627 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1628
1629 mga_crtc_init(mdev);
1630
1631 encoder = mga_encoder_init(mdev->dev);
1632 if (!encoder) {
1633 DRM_ERROR("mga_encoder_init failed\n");
1634 return -1;
1635 }
1636
1637 connector = mga_vga_init(mdev->dev);
1638 if (!connector) {
1639 DRM_ERROR("mga_vga_init failed\n");
1640 return -1;
1641 }
1642
1643 drm_mode_connector_attach_encoder(connector, encoder);
1644
1645 ret = mgag200_fbdev_init(mdev);
1646 if (ret) {
1647 DRM_ERROR("mga_fbdev_init failed\n");
1648 return ret;
1649 }
1650
1651 return 0;
1652 }
1653
1654 void mgag200_modeset_fini(struct mga_device *mdev)
1655 {
1656
1657 }
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