drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  */
   6
   7 #include <linux/delay.h>
   8
   9 #include <drm/drm_vblank.h>
  10
  11 #include "msm_drv.h"
  12 #include "msm_gem.h"
  13 #include "msm_mmu.h"
  14 #include "mdp4_kms.h"
  15
  16 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
  17
  18 static int mdp4_hw_init(struct msm_kms *kms)
  19 {
  20         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  21         struct drm_device *dev = mdp4_kms->dev;
  22         u32 major, minor, dmap_cfg, vg_cfg;
  23         unsigned long clk;
  24         int ret = 0;
  25
  26         pm_runtime_get_sync(dev->dev);
  27
  28         read_mdp_hw_revision(mdp4_kms, &major, &minor);
  29
  30         if (major != 4) {
  31                 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
  32                                 major, minor);
  33                 ret = -ENXIO;
  34                 goto out;
  35         }
  36
  37         mdp4_kms->rev = minor;
  38
  39         if (mdp4_kms->rev > 1) {
  40                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
  41                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
  42         }
  43
  44         mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
  45
  46         /* max read pending cmd config, 3 pending requests: */
  47         mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
  48
  49         clk = clk_get_rate(mdp4_kms->clk);
  50
  51         if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
  52                 dmap_cfg = 0x47;     /* 16 bytes-burst x 8 req */
  53                 vg_cfg = 0x47;       /* 16 bytes-burs x 8 req */
  54         } else {
  55                 dmap_cfg = 0x27;     /* 8 bytes-burst x 8 req */
  56                 vg_cfg = 0x43;       /* 16 bytes-burst x 4 req */
  57         }
  58
  59         DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
  60
  61         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
  62         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
  63
  64         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
  65         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
  66         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
  67         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
  68
  69         if (mdp4_kms->rev >= 2)
  70                 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
  71         mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
  72
  73         /* disable CSC matrix / YUV by default: */
  74         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
  75         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
  76         mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
  77         mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
  78         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
  79         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
  80
  81         if (mdp4_kms->rev > 1)
  82                 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
  83
  84 out:
  85         pm_runtime_put_sync(dev->dev);
  86
  87         return ret;
  88 }
  89
  90 static void mdp4_enable_commit(struct msm_kms *kms)
  91 {
  92         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  93         mdp4_enable(mdp4_kms);
  94 }
  95
  96 static void mdp4_disable_commit(struct msm_kms *kms)
  97 {
  98         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  99         mdp4_disable(mdp4_kms);
 100 }
 101
 102 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
 103 {
 104         int i;
 105         struct drm_crtc *crtc;
 106         struct drm_crtc_state *crtc_state;
 107
 108         /* see 119ecb7fd */
 109         for_each_new_crtc_in_state(state, crtc, crtc_state, i)
 110                 drm_crtc_vblank_get(crtc);
 111 }
 112
 113 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
 114 {
 115         /* TODO */
 116 }
 117
 118 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
 119 {
 120         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 121         struct drm_crtc *crtc;
 122
 123         for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
 124                 mdp4_crtc_wait_for_commit_done(crtc);
 125 }
 126
 127 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
 128 {
 129         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 130         struct drm_crtc *crtc;
 131
 132         /* see 119ecb7fd */
 133         for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
 134                 drm_crtc_vblank_put(crtc);
 135 }
 136
 137 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
 138                 struct drm_encoder *encoder)
 139 {
 140         /* if we had >1 encoder, we'd need something more clever: */
 141         switch (encoder->encoder_type) {
 142         case DRM_MODE_ENCODER_TMDS:
 143                 return mdp4_dtv_round_pixclk(encoder, rate);
 144         case DRM_MODE_ENCODER_LVDS:
 145         case DRM_MODE_ENCODER_DSI:
 146         default:
 147                 return rate;
 148         }
 149 }
 150
 151 static void mdp4_destroy(struct msm_kms *kms)
 152 {
 153         struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
 154         struct device *dev = mdp4_kms->dev->dev;
 155         struct msm_gem_address_space *aspace = kms->aspace;
 156
 157         if (mdp4_kms->blank_cursor_iova)
 158                 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
 159         drm_gem_object_put(mdp4_kms->blank_cursor_bo);
 160
 161         if (aspace) {
 162                 aspace->mmu->funcs->detach(aspace->mmu);
 163                 msm_gem_address_space_put(aspace);
 164         }
 165
 166         if (mdp4_kms->rpm_enabled)
 167                 pm_runtime_disable(dev);
 168
 169         mdp_kms_destroy(&mdp4_kms->base);
 170
 171         kfree(mdp4_kms);
 172 }
 173
 174 static const struct mdp_kms_funcs kms_funcs = {
 175         .base = {
 176                 .hw_init         = mdp4_hw_init,
 177                 .irq_preinstall  = mdp4_irq_preinstall,
 178                 .irq_postinstall = mdp4_irq_postinstall,
 179                 .irq_uninstall   = mdp4_irq_uninstall,
 180                 .irq             = mdp4_irq,
 181                 .enable_vblank   = mdp4_enable_vblank,
 182                 .disable_vblank  = mdp4_disable_vblank,
 183                 .enable_commit   = mdp4_enable_commit,
 184                 .disable_commit  = mdp4_disable_commit,
 185                 .prepare_commit  = mdp4_prepare_commit,
 186                 .flush_commit    = mdp4_flush_commit,
 187                 .wait_flush      = mdp4_wait_flush,
 188                 .complete_commit = mdp4_complete_commit,
 189                 .get_format      = mdp_get_format,
 190                 .round_pixclk    = mdp4_round_pixclk,
 191                 .destroy         = mdp4_destroy,
 192         },
 193         .set_irqmask         = mdp4_set_irqmask,
 194 };
 195
 196 int mdp4_disable(struct mdp4_kms *mdp4_kms)
 197 {
 198         DBG("");
 199
 200         clk_disable_unprepare(mdp4_kms->clk);
 201         if (mdp4_kms->pclk)
 202                 clk_disable_unprepare(mdp4_kms->pclk);
 203         if (mdp4_kms->lut_clk)
 204                 clk_disable_unprepare(mdp4_kms->lut_clk);
 205         if (mdp4_kms->axi_clk)
 206                 clk_disable_unprepare(mdp4_kms->axi_clk);
 207
 208         return 0;
 209 }
 210
 211 int mdp4_enable(struct mdp4_kms *mdp4_kms)
 212 {
 213         DBG("");
 214
 215         clk_prepare_enable(mdp4_kms->clk);
 216         if (mdp4_kms->pclk)
 217                 clk_prepare_enable(mdp4_kms->pclk);
 218         if (mdp4_kms->lut_clk)
 219                 clk_prepare_enable(mdp4_kms->lut_clk);
 220         if (mdp4_kms->axi_clk)
 221                 clk_prepare_enable(mdp4_kms->axi_clk);
 222
 223         return 0;
 224 }
 225
 226
 227 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
 228                                   int intf_type)
 229 {
 230         struct drm_device *dev = mdp4_kms->dev;
 231         struct msm_drm_private *priv = dev->dev_private;
 232         struct drm_encoder *encoder;
 233         struct drm_connector *connector;
 234         struct device_node *panel_node;
 235         int dsi_id;
 236         int ret;
 237
 238         switch (intf_type) {
 239         case DRM_MODE_ENCODER_LVDS:
 240                 /*
 241                  * bail out early if there is no panel node (no need to
 242                  * initialize LCDC encoder and LVDS connector)
 243                  */
 244                 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
 245                 if (!panel_node)
 246                         return 0;
 247
 248                 encoder = mdp4_lcdc_encoder_init(dev, panel_node);
 249                 if (IS_ERR(encoder)) {
 250                         DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
 251                         return PTR_ERR(encoder);
 252                 }
 253
 254                 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
 255                 encoder->possible_crtcs = 1 << DMA_P;
 256
 257                 connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
 258                 if (IS_ERR(connector)) {
 259                         DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
 260                         return PTR_ERR(connector);
 261                 }
 262
 263                 priv->encoders[priv->num_encoders++] = encoder;
 264                 priv->connectors[priv->num_connectors++] = connector;
 265
 266                 break;
 267         case DRM_MODE_ENCODER_TMDS:
 268                 encoder = mdp4_dtv_encoder_init(dev);
 269                 if (IS_ERR(encoder)) {
 270                         DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n");
 271                         return PTR_ERR(encoder);
 272                 }
 273
 274                 /* DTV can be hooked to DMA_E: */
 275                 encoder->possible_crtcs = 1 << 1;
 276
 277                 if (priv->hdmi) {
 278                         /* Construct bridge/connector for HDMI: */
 279                         ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
 280                         if (ret) {
 281                                 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret);
 282                                 return ret;
 283                         }
 284                 }
 285
 286                 priv->encoders[priv->num_encoders++] = encoder;
 287
 288                 break;
 289         case DRM_MODE_ENCODER_DSI:
 290                 /* only DSI1 supported for now */
 291                 dsi_id = 0;
 292
 293                 if (!priv->dsi[dsi_id])
 294                         break;
 295
 296                 encoder = mdp4_dsi_encoder_init(dev);
 297                 if (IS_ERR(encoder)) {
 298                         ret = PTR_ERR(encoder);
 299                         DRM_DEV_ERROR(dev->dev,
 300                                 "failed to construct DSI encoder: %d\n", ret);
 301                         return ret;
 302                 }
 303
 304                 /* TODO: Add DMA_S later? */
 305                 encoder->possible_crtcs = 1 << DMA_P;
 306                 priv->encoders[priv->num_encoders++] = encoder;
 307
 308                 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
 309                 if (ret) {
 310                         DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n",
 311                                 ret);
 312                         return ret;
 313                 }
 314
 315                 break;
 316         default:
 317                 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n");
 318                 return -EINVAL;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int modeset_init(struct mdp4_kms *mdp4_kms)
 325 {
 326         struct drm_device *dev = mdp4_kms->dev;
 327         struct msm_drm_private *priv = dev->dev_private;
 328         struct drm_plane *plane;
 329         struct drm_crtc *crtc;
 330         int i, ret;
 331         static const enum mdp4_pipe rgb_planes[] = {
 332                 RGB1, RGB2,
 333         };
 334         static const enum mdp4_pipe vg_planes[] = {
 335                 VG1, VG2,
 336         };
 337         static const enum mdp4_dma mdp4_crtcs[] = {
 338                 DMA_P, DMA_E,
 339         };
 340         static const char * const mdp4_crtc_names[] = {
 341                 "DMA_P", "DMA_E",
 342         };
 343         static const int mdp4_intfs[] = {
 344                 DRM_MODE_ENCODER_LVDS,
 345                 DRM_MODE_ENCODER_DSI,
 346                 DRM_MODE_ENCODER_TMDS,
 347         };
 348
 349         /* construct non-private planes: */
 350         for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
 351                 plane = mdp4_plane_init(dev, vg_planes[i], false);
 352                 if (IS_ERR(plane)) {
 353                         DRM_DEV_ERROR(dev->dev,
 354                                 "failed to construct plane for VG%d\n", i + 1);
 355                         ret = PTR_ERR(plane);
 356                         goto fail;
 357                 }
 358                 priv->planes[priv->num_planes++] = plane;
 359         }
 360
 361         for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
 362                 plane = mdp4_plane_init(dev, rgb_planes[i], true);
 363                 if (IS_ERR(plane)) {
 364                         DRM_DEV_ERROR(dev->dev,
 365                                 "failed to construct plane for RGB%d\n", i + 1);
 366                         ret = PTR_ERR(plane);
 367                         goto fail;
 368                 }
 369
 370                 crtc  = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
 371                                 mdp4_crtcs[i]);
 372                 if (IS_ERR(crtc)) {
 373                         DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n",
 374                                 mdp4_crtc_names[i]);
 375                         ret = PTR_ERR(crtc);
 376                         goto fail;
 377                 }
 378
 379                 priv->crtcs[priv->num_crtcs++] = crtc;
 380         }
 381
 382         /*
 383          * we currently set up two relatively fixed paths:
 384          *
 385          * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
 386          *                      or
 387          * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
 388          *
 389          * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
 390          */
 391
 392         for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
 393                 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
 394                 if (ret) {
 395                         DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n",
 396                                 i, ret);
 397                         goto fail;
 398                 }
 399         }
 400
 401         return 0;
 402
 403 fail:
 404         return ret;
 405 }
 406
 407 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,
 408                                  u32 *major, u32 *minor)
 409 {
 410         struct drm_device *dev = mdp4_kms->dev;
 411         u32 version;
 412
 413         mdp4_enable(mdp4_kms);
 414         version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
 415         mdp4_disable(mdp4_kms);
 416
 417         *major = FIELD(version, MDP4_VERSION_MAJOR);
 418         *minor = FIELD(version, MDP4_VERSION_MINOR);
 419
 420         DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor);
 421 }
 422
 423 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
 424 {
 425         struct platform_device *pdev = to_platform_device(dev->dev);
 426         struct mdp4_platform_config *config = mdp4_get_config(pdev);
 427         struct mdp4_kms *mdp4_kms;
 428         struct msm_kms *kms = NULL;
 429         struct msm_gem_address_space *aspace;
 430         int irq, ret;
 431
 432         mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
 433         if (!mdp4_kms) {
 434                 DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n");
 435                 ret = -ENOMEM;
 436                 goto fail;
 437         }
 438
 439         ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs);
 440         if (ret) {
 441                 DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
 442                 goto fail;
 443         }
 444
 445         kms = &mdp4_kms->base.base;
 446
 447         mdp4_kms->dev = dev;
 448
 449         mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
 450         if (IS_ERR(mdp4_kms->mmio)) {
 451                 ret = PTR_ERR(mdp4_kms->mmio);
 452                 goto fail;
 453         }
 454
 455         irq = platform_get_irq(pdev, 0);
 456         if (irq < 0) {
 457                 ret = irq;
 458                 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
 459                 goto fail;
 460         }
 461
 462         kms->irq = irq;
 463
 464         /* NOTE: driver for this regulator still missing upstream.. use
 465          * _get_exclusive() and ignore the error if it does not exist
 466          * (and hope that the bootloader left it on for us)
 467          */
 468         mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
 469         if (IS_ERR(mdp4_kms->vdd))
 470                 mdp4_kms->vdd = NULL;
 471
 472         if (mdp4_kms->vdd) {
 473                 ret = regulator_enable(mdp4_kms->vdd);
 474                 if (ret) {
 475                         DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret);
 476                         goto fail;
 477                 }
 478         }
 479
 480         mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
 481         if (IS_ERR(mdp4_kms->clk)) {
 482                 DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n");
 483                 ret = PTR_ERR(mdp4_kms->clk);
 484                 goto fail;
 485         }
 486
 487         mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
 488         if (IS_ERR(mdp4_kms->pclk))
 489                 mdp4_kms->pclk = NULL;
 490
 491         if (mdp4_kms->rev >= 2) {
 492                 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
 493                 if (IS_ERR(mdp4_kms->lut_clk)) {
 494                         DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
 495                         ret = PTR_ERR(mdp4_kms->lut_clk);
 496                         goto fail;
 497                 }
 498         }
 499
 500         mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
 501         if (IS_ERR(mdp4_kms->axi_clk)) {
 502                 DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n");
 503                 ret = PTR_ERR(mdp4_kms->axi_clk);
 504                 goto fail;
 505         }
 506
 507         clk_set_rate(mdp4_kms->clk, config->max_clk);
 508         if (mdp4_kms->lut_clk)
 509                 clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
 510
 511         pm_runtime_enable(dev->dev);
 512         mdp4_kms->rpm_enabled = true;
 513
 514         /* make sure things are off before attaching iommu (bootloader could
 515          * have left things on, in which case we'll start getting faults if
 516          * we don't disable):
 517          */
 518         mdp4_enable(mdp4_kms);
 519         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
 520         mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
 521         mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
 522         mdp4_disable(mdp4_kms);
 523         mdelay(16);
 524
 525         if (config->iommu) {
 526                 struct msm_mmu *mmu = msm_iommu_new(&pdev->dev,
 527                         config->iommu);
 528
 529                 aspace  = msm_gem_address_space_create(mmu,
 530                         "mdp4", 0x1000, 0x100000000 - 0x1000);
 531
 532                 if (IS_ERR(aspace)) {
 533                         if (!IS_ERR(mmu))
 534                                 mmu->funcs->destroy(mmu);
 535                         ret = PTR_ERR(aspace);
 536                         goto fail;
 537                 }
 538
 539                 kms->aspace = aspace;
 540         } else {
 541                 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
 542                                 "contig buffers for scanout\n");
 543                 aspace = NULL;
 544         }
 545
 546         ret = modeset_init(mdp4_kms);
 547         if (ret) {
 548                 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
 549                 goto fail;
 550         }
 551
 552         mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT);
 553         if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
 554                 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
 555                 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
 556                 mdp4_kms->blank_cursor_bo = NULL;
 557                 goto fail;
 558         }
 559
 560         ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
 561                         &mdp4_kms->blank_cursor_iova);
 562         if (ret) {
 563                 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
 564                 goto fail;
 565         }
 566
 567         dev->mode_config.min_width = 0;
 568         dev->mode_config.min_height = 0;
 569         dev->mode_config.max_width = 2048;
 570         dev->mode_config.max_height = 2048;
 571
 572         return kms;
 573
 574 fail:
 575         if (kms)
 576                 mdp4_destroy(kms);
 577         return ERR_PTR(ret);
 578 }
 579
 580 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
 581 {
 582         static struct mdp4_platform_config config = {};
 583
 584         /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
 585         config.max_clk = 266667000;
 586         config.iommu = iommu_domain_alloc(&platform_bus_type);
 587
 588         return &config;
 589 }