]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/msm/dsi/dsi_host.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / msm / dsi / dsi_host.c
1 /*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/of_graph.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
29 #include <video/mipi_display.h>
30
31 #include "dsi.h"
32 #include "dsi.xml.h"
33 #include "sfpb.xml.h"
34 #include "dsi_cfg.h"
35
36 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
37 {
38 u32 ver;
39
40 if (!major || !minor)
41 return -EINVAL;
42
43 /*
44 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
45 * makes all other registers 4-byte shifted down.
46 *
47 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
48 * older, we read the DSI_VERSION register without any shift(offset
49 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
50 * the case of DSI6G, this has to be zero (the offset points to a
51 * scratch register which we never touch)
52 */
53
54 ver = msm_readl(base + REG_DSI_VERSION);
55 if (ver) {
56 /* older dsi host, there is no register shift */
57 ver = FIELD(ver, DSI_VERSION_MAJOR);
58 if (ver <= MSM_DSI_VER_MAJOR_V2) {
59 /* old versions */
60 *major = ver;
61 *minor = 0;
62 return 0;
63 } else {
64 return -EINVAL;
65 }
66 } else {
67 /*
68 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
69 * registers are shifted down, read DSI_VERSION again with
70 * the shifted offset
71 */
72 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
73 ver = FIELD(ver, DSI_VERSION_MAJOR);
74 if (ver == MSM_DSI_VER_MAJOR_6G) {
75 /* 6G version */
76 *major = ver;
77 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
78 return 0;
79 } else {
80 return -EINVAL;
81 }
82 }
83 }
84
85 #define DSI_ERR_STATE_ACK 0x0000
86 #define DSI_ERR_STATE_TIMEOUT 0x0001
87 #define DSI_ERR_STATE_DLN0_PHY 0x0002
88 #define DSI_ERR_STATE_FIFO 0x0004
89 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
90 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
91 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
92
93 #define DSI_CLK_CTRL_ENABLE_CLKS \
94 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
95 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
96 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
97 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
98
99 struct msm_dsi_host {
100 struct mipi_dsi_host base;
101
102 struct platform_device *pdev;
103 struct drm_device *dev;
104
105 int id;
106
107 void __iomem *ctrl_base;
108 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
109
110 struct clk *bus_clks[DSI_BUS_CLK_MAX];
111
112 struct clk *byte_clk;
113 struct clk *esc_clk;
114 struct clk *pixel_clk;
115 struct clk *byte_clk_src;
116 struct clk *pixel_clk_src;
117
118 u32 byte_clk_rate;
119 u32 esc_clk_rate;
120
121 /* DSI v2 specific clocks */
122 struct clk *src_clk;
123 struct clk *esc_clk_src;
124 struct clk *dsi_clk_src;
125
126 u32 src_clk_rate;
127
128 struct gpio_desc *disp_en_gpio;
129 struct gpio_desc *te_gpio;
130
131 const struct msm_dsi_cfg_handler *cfg_hnd;
132
133 struct completion dma_comp;
134 struct completion video_comp;
135 struct mutex dev_mutex;
136 struct mutex cmd_mutex;
137 struct mutex clk_mutex;
138 spinlock_t intr_lock; /* Protect interrupt ctrl register */
139
140 u32 err_work_state;
141 struct work_struct err_work;
142 struct workqueue_struct *workqueue;
143
144 /* DSI 6G TX buffer*/
145 struct drm_gem_object *tx_gem_obj;
146
147 /* DSI v2 TX buffer */
148 void *tx_buf;
149 dma_addr_t tx_buf_paddr;
150
151 int tx_size;
152
153 u8 *rx_buf;
154
155 struct regmap *sfpb;
156
157 struct drm_display_mode *mode;
158
159 /* connected device info */
160 struct device_node *device_node;
161 unsigned int channel;
162 unsigned int lanes;
163 enum mipi_dsi_pixel_format format;
164 unsigned long mode_flags;
165
166 /* lane data parsed via DT */
167 int dlane_swap;
168 int num_data_lanes;
169
170 u32 dma_cmd_ctrl_restore;
171
172 bool registered;
173 bool power_on;
174 int irq;
175 };
176
177 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
178 {
179 switch (fmt) {
180 case MIPI_DSI_FMT_RGB565: return 16;
181 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
182 case MIPI_DSI_FMT_RGB666:
183 case MIPI_DSI_FMT_RGB888:
184 default: return 24;
185 }
186 }
187
188 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
189 {
190 return msm_readl(msm_host->ctrl_base + reg);
191 }
192 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
193 {
194 msm_writel(data, msm_host->ctrl_base + reg);
195 }
196
197 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
198 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
199
200 static const struct msm_dsi_cfg_handler *dsi_get_config(
201 struct msm_dsi_host *msm_host)
202 {
203 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
204 struct device *dev = &msm_host->pdev->dev;
205 struct regulator *gdsc_reg;
206 struct clk *ahb_clk;
207 int ret;
208 u32 major = 0, minor = 0;
209
210 gdsc_reg = regulator_get(dev, "gdsc");
211 if (IS_ERR(gdsc_reg)) {
212 pr_err("%s: cannot get gdsc\n", __func__);
213 goto exit;
214 }
215
216 ahb_clk = clk_get(dev, "iface_clk");
217 if (IS_ERR(ahb_clk)) {
218 pr_err("%s: cannot get interface clock\n", __func__);
219 goto put_gdsc;
220 }
221
222 ret = regulator_enable(gdsc_reg);
223 if (ret) {
224 pr_err("%s: unable to enable gdsc\n", __func__);
225 goto put_clk;
226 }
227
228 ret = clk_prepare_enable(ahb_clk);
229 if (ret) {
230 pr_err("%s: unable to enable ahb_clk\n", __func__);
231 goto disable_gdsc;
232 }
233
234 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
235 if (ret) {
236 pr_err("%s: Invalid version\n", __func__);
237 goto disable_clks;
238 }
239
240 cfg_hnd = msm_dsi_cfg_get(major, minor);
241
242 DBG("%s: Version %x:%x\n", __func__, major, minor);
243
244 disable_clks:
245 clk_disable_unprepare(ahb_clk);
246 disable_gdsc:
247 regulator_disable(gdsc_reg);
248 put_clk:
249 clk_put(ahb_clk);
250 put_gdsc:
251 regulator_put(gdsc_reg);
252 exit:
253 return cfg_hnd;
254 }
255
256 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
257 {
258 return container_of(host, struct msm_dsi_host, base);
259 }
260
261 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
262 {
263 struct regulator_bulk_data *s = msm_host->supplies;
264 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
265 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
266 int i;
267
268 DBG("");
269 for (i = num - 1; i >= 0; i--)
270 if (regs[i].disable_load >= 0)
271 regulator_set_load(s[i].consumer,
272 regs[i].disable_load);
273
274 regulator_bulk_disable(num, s);
275 }
276
277 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
278 {
279 struct regulator_bulk_data *s = msm_host->supplies;
280 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
281 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
282 int ret, i;
283
284 DBG("");
285 for (i = 0; i < num; i++) {
286 if (regs[i].enable_load >= 0) {
287 ret = regulator_set_load(s[i].consumer,
288 regs[i].enable_load);
289 if (ret < 0) {
290 pr_err("regulator %d set op mode failed, %d\n",
291 i, ret);
292 goto fail;
293 }
294 }
295 }
296
297 ret = regulator_bulk_enable(num, s);
298 if (ret < 0) {
299 pr_err("regulator enable failed, %d\n", ret);
300 goto fail;
301 }
302
303 return 0;
304
305 fail:
306 for (i--; i >= 0; i--)
307 regulator_set_load(s[i].consumer, regs[i].disable_load);
308 return ret;
309 }
310
311 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
312 {
313 struct regulator_bulk_data *s = msm_host->supplies;
314 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
315 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
316 int i, ret;
317
318 for (i = 0; i < num; i++)
319 s[i].supply = regs[i].name;
320
321 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
322 if (ret < 0) {
323 pr_err("%s: failed to init regulator, ret=%d\n",
324 __func__, ret);
325 return ret;
326 }
327
328 return 0;
329 }
330
331 static int dsi_clk_init(struct msm_dsi_host *msm_host)
332 {
333 struct device *dev = &msm_host->pdev->dev;
334 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
335 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
336 int i, ret = 0;
337
338 /* get bus clocks */
339 for (i = 0; i < cfg->num_bus_clks; i++) {
340 msm_host->bus_clks[i] = devm_clk_get(dev,
341 cfg->bus_clk_names[i]);
342 if (IS_ERR(msm_host->bus_clks[i])) {
343 ret = PTR_ERR(msm_host->bus_clks[i]);
344 pr_err("%s: Unable to get %s, ret = %d\n",
345 __func__, cfg->bus_clk_names[i], ret);
346 goto exit;
347 }
348 }
349
350 /* get link and source clocks */
351 msm_host->byte_clk = devm_clk_get(dev, "byte_clk");
352 if (IS_ERR(msm_host->byte_clk)) {
353 ret = PTR_ERR(msm_host->byte_clk);
354 pr_err("%s: can't find dsi_byte_clk. ret=%d\n",
355 __func__, ret);
356 msm_host->byte_clk = NULL;
357 goto exit;
358 }
359
360 msm_host->pixel_clk = devm_clk_get(dev, "pixel_clk");
361 if (IS_ERR(msm_host->pixel_clk)) {
362 ret = PTR_ERR(msm_host->pixel_clk);
363 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",
364 __func__, ret);
365 msm_host->pixel_clk = NULL;
366 goto exit;
367 }
368
369 msm_host->esc_clk = devm_clk_get(dev, "core_clk");
370 if (IS_ERR(msm_host->esc_clk)) {
371 ret = PTR_ERR(msm_host->esc_clk);
372 pr_err("%s: can't find dsi_esc_clk. ret=%d\n",
373 __func__, ret);
374 msm_host->esc_clk = NULL;
375 goto exit;
376 }
377
378 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
379 if (!msm_host->byte_clk_src) {
380 ret = -ENODEV;
381 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__, ret);
382 goto exit;
383 }
384
385 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
386 if (!msm_host->pixel_clk_src) {
387 ret = -ENODEV;
388 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__, ret);
389 goto exit;
390 }
391
392 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
393 msm_host->src_clk = devm_clk_get(dev, "src_clk");
394 if (IS_ERR(msm_host->src_clk)) {
395 ret = PTR_ERR(msm_host->src_clk);
396 pr_err("%s: can't find dsi_src_clk. ret=%d\n",
397 __func__, ret);
398 msm_host->src_clk = NULL;
399 goto exit;
400 }
401
402 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
403 if (!msm_host->esc_clk_src) {
404 ret = -ENODEV;
405 pr_err("%s: can't get esc_clk_src. ret=%d\n",
406 __func__, ret);
407 goto exit;
408 }
409
410 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
411 if (!msm_host->dsi_clk_src) {
412 ret = -ENODEV;
413 pr_err("%s: can't get dsi_clk_src. ret=%d\n",
414 __func__, ret);
415 }
416 }
417 exit:
418 return ret;
419 }
420
421 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
422 {
423 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
424 int i, ret;
425
426 DBG("id=%d", msm_host->id);
427
428 for (i = 0; i < cfg->num_bus_clks; i++) {
429 ret = clk_prepare_enable(msm_host->bus_clks[i]);
430 if (ret) {
431 pr_err("%s: failed to enable bus clock %d ret %d\n",
432 __func__, i, ret);
433 goto err;
434 }
435 }
436
437 return 0;
438 err:
439 for (; i > 0; i--)
440 clk_disable_unprepare(msm_host->bus_clks[i]);
441
442 return ret;
443 }
444
445 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
446 {
447 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
448 int i;
449
450 DBG("");
451
452 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
453 clk_disable_unprepare(msm_host->bus_clks[i]);
454 }
455
456 static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
457 {
458 int ret;
459
460 DBG("Set clk rates: pclk=%d, byteclk=%d",
461 msm_host->mode->clock, msm_host->byte_clk_rate);
462
463 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
464 if (ret) {
465 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
466 goto error;
467 }
468
469 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
470 if (ret) {
471 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
472 goto error;
473 }
474
475 ret = clk_prepare_enable(msm_host->esc_clk);
476 if (ret) {
477 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
478 goto error;
479 }
480
481 ret = clk_prepare_enable(msm_host->byte_clk);
482 if (ret) {
483 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
484 goto byte_clk_err;
485 }
486
487 ret = clk_prepare_enable(msm_host->pixel_clk);
488 if (ret) {
489 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
490 goto pixel_clk_err;
491 }
492
493 return 0;
494
495 pixel_clk_err:
496 clk_disable_unprepare(msm_host->byte_clk);
497 byte_clk_err:
498 clk_disable_unprepare(msm_host->esc_clk);
499 error:
500 return ret;
501 }
502
503 static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
504 {
505 int ret;
506
507 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
508 msm_host->mode->clock, msm_host->byte_clk_rate,
509 msm_host->esc_clk_rate, msm_host->src_clk_rate);
510
511 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
512 if (ret) {
513 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
514 goto error;
515 }
516
517 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
518 if (ret) {
519 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
520 goto error;
521 }
522
523 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
524 if (ret) {
525 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
526 goto error;
527 }
528
529 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
530 if (ret) {
531 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
532 goto error;
533 }
534
535 ret = clk_prepare_enable(msm_host->byte_clk);
536 if (ret) {
537 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
538 goto error;
539 }
540
541 ret = clk_prepare_enable(msm_host->esc_clk);
542 if (ret) {
543 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
544 goto esc_clk_err;
545 }
546
547 ret = clk_prepare_enable(msm_host->src_clk);
548 if (ret) {
549 pr_err("%s: Failed to enable dsi src clk\n", __func__);
550 goto src_clk_err;
551 }
552
553 ret = clk_prepare_enable(msm_host->pixel_clk);
554 if (ret) {
555 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
556 goto pixel_clk_err;
557 }
558
559 return 0;
560
561 pixel_clk_err:
562 clk_disable_unprepare(msm_host->src_clk);
563 src_clk_err:
564 clk_disable_unprepare(msm_host->esc_clk);
565 esc_clk_err:
566 clk_disable_unprepare(msm_host->byte_clk);
567 error:
568 return ret;
569 }
570
571 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
572 {
573 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
574
575 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
576 return dsi_link_clk_enable_6g(msm_host);
577 else
578 return dsi_link_clk_enable_v2(msm_host);
579 }
580
581 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
582 {
583 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
584
585 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
586 clk_disable_unprepare(msm_host->esc_clk);
587 clk_disable_unprepare(msm_host->pixel_clk);
588 clk_disable_unprepare(msm_host->byte_clk);
589 } else {
590 clk_disable_unprepare(msm_host->pixel_clk);
591 clk_disable_unprepare(msm_host->src_clk);
592 clk_disable_unprepare(msm_host->esc_clk);
593 clk_disable_unprepare(msm_host->byte_clk);
594 }
595 }
596
597 static int dsi_clk_ctrl(struct msm_dsi_host *msm_host, bool enable)
598 {
599 int ret = 0;
600
601 mutex_lock(&msm_host->clk_mutex);
602 if (enable) {
603 ret = dsi_bus_clk_enable(msm_host);
604 if (ret) {
605 pr_err("%s: Can not enable bus clk, %d\n",
606 __func__, ret);
607 goto unlock_ret;
608 }
609 ret = dsi_link_clk_enable(msm_host);
610 if (ret) {
611 pr_err("%s: Can not enable link clk, %d\n",
612 __func__, ret);
613 dsi_bus_clk_disable(msm_host);
614 goto unlock_ret;
615 }
616 } else {
617 dsi_link_clk_disable(msm_host);
618 dsi_bus_clk_disable(msm_host);
619 }
620
621 unlock_ret:
622 mutex_unlock(&msm_host->clk_mutex);
623 return ret;
624 }
625
626 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
627 {
628 struct drm_display_mode *mode = msm_host->mode;
629 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
630 u8 lanes = msm_host->lanes;
631 u32 bpp = dsi_get_bpp(msm_host->format);
632 u32 pclk_rate;
633
634 if (!mode) {
635 pr_err("%s: mode not set\n", __func__);
636 return -EINVAL;
637 }
638
639 pclk_rate = mode->clock * 1000;
640 if (lanes > 0) {
641 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
642 } else {
643 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
644 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
645 }
646
647 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
648
649 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
650
651 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
652 unsigned int esc_mhz, esc_div;
653 unsigned long byte_mhz;
654
655 msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
656
657 /*
658 * esc clock is byte clock followed by a 4 bit divider,
659 * we need to find an escape clock frequency within the
660 * mipi DSI spec range within the maximum divider limit
661 * We iterate here between an escape clock frequencey
662 * between 20 Mhz to 5 Mhz and pick up the first one
663 * that can be supported by our divider
664 */
665
666 byte_mhz = msm_host->byte_clk_rate / 1000000;
667
668 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
669 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
670
671 /*
672 * TODO: Ideally, we shouldn't know what sort of divider
673 * is available in mmss_cc, we're just assuming that
674 * it'll always be a 4 bit divider. Need to come up with
675 * a better way here.
676 */
677 if (esc_div >= 1 && esc_div <= 16)
678 break;
679 }
680
681 if (esc_mhz < 5)
682 return -EINVAL;
683
684 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
685
686 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
687 msm_host->src_clk_rate);
688 }
689
690 return 0;
691 }
692
693 static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host)
694 {
695 DBG("");
696 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
697 /* Make sure fully reset */
698 wmb();
699 udelay(1000);
700 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
701 udelay(100);
702 }
703
704 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
705 {
706 u32 intr;
707 unsigned long flags;
708
709 spin_lock_irqsave(&msm_host->intr_lock, flags);
710 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
711
712 if (enable)
713 intr |= mask;
714 else
715 intr &= ~mask;
716
717 DBG("intr=%x enable=%d", intr, enable);
718
719 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
720 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
721 }
722
723 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
724 {
725 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
726 return BURST_MODE;
727 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
728 return NON_BURST_SYNCH_PULSE;
729
730 return NON_BURST_SYNCH_EVENT;
731 }
732
733 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
734 const enum mipi_dsi_pixel_format mipi_fmt)
735 {
736 switch (mipi_fmt) {
737 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
738 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
739 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
740 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
741 default: return VID_DST_FORMAT_RGB888;
742 }
743 }
744
745 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
746 const enum mipi_dsi_pixel_format mipi_fmt)
747 {
748 switch (mipi_fmt) {
749 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
750 case MIPI_DSI_FMT_RGB666_PACKED:
751 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666;
752 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
753 default: return CMD_DST_FORMAT_RGB888;
754 }
755 }
756
757 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
758 u32 clk_pre, u32 clk_post)
759 {
760 u32 flags = msm_host->mode_flags;
761 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
762 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
763 u32 data = 0;
764
765 if (!enable) {
766 dsi_write(msm_host, REG_DSI_CTRL, 0);
767 return;
768 }
769
770 if (flags & MIPI_DSI_MODE_VIDEO) {
771 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
772 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
773 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
774 data |= DSI_VID_CFG0_HFP_POWER_STOP;
775 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
776 data |= DSI_VID_CFG0_HBP_POWER_STOP;
777 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
778 data |= DSI_VID_CFG0_HSA_POWER_STOP;
779 /* Always set low power stop mode for BLLP
780 * to let command engine send packets
781 */
782 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
783 DSI_VID_CFG0_BLLP_POWER_STOP;
784 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
785 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
786 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
787 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
788
789 /* Do not swap RGB colors */
790 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
791 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
792 } else {
793 /* Do not swap RGB colors */
794 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
795 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
796 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
797
798 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
799 DSI_CMD_CFG1_WR_MEM_CONTINUE(
800 MIPI_DCS_WRITE_MEMORY_CONTINUE);
801 /* Always insert DCS command */
802 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
803 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
804 }
805
806 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
807 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
808 DSI_CMD_DMA_CTRL_LOW_POWER);
809
810 data = 0;
811 /* Always assume dedicated TE pin */
812 data |= DSI_TRIG_CTRL_TE;
813 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
814 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
815 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
816 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
817 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
818 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
819 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
820
821 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) |
822 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre);
823 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
824
825 data = 0;
826 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
827 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
828 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
829
830 /* allow only ack-err-status to generate interrupt */
831 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
832
833 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
834
835 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
836
837 data = DSI_CTRL_CLK_EN;
838
839 DBG("lane number=%d", msm_host->lanes);
840 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
841
842 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
843 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
844
845 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
846 dsi_write(msm_host, REG_DSI_LANE_CTRL,
847 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
848
849 data |= DSI_CTRL_ENABLE;
850
851 dsi_write(msm_host, REG_DSI_CTRL, data);
852 }
853
854 static void dsi_timing_setup(struct msm_dsi_host *msm_host)
855 {
856 struct drm_display_mode *mode = msm_host->mode;
857 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
858 u32 h_total = mode->htotal;
859 u32 v_total = mode->vtotal;
860 u32 hs_end = mode->hsync_end - mode->hsync_start;
861 u32 vs_end = mode->vsync_end - mode->vsync_start;
862 u32 ha_start = h_total - mode->hsync_start;
863 u32 ha_end = ha_start + mode->hdisplay;
864 u32 va_start = v_total - mode->vsync_start;
865 u32 va_end = va_start + mode->vdisplay;
866 u32 wc;
867
868 DBG("");
869
870 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
871 dsi_write(msm_host, REG_DSI_ACTIVE_H,
872 DSI_ACTIVE_H_START(ha_start) |
873 DSI_ACTIVE_H_END(ha_end));
874 dsi_write(msm_host, REG_DSI_ACTIVE_V,
875 DSI_ACTIVE_V_START(va_start) |
876 DSI_ACTIVE_V_END(va_end));
877 dsi_write(msm_host, REG_DSI_TOTAL,
878 DSI_TOTAL_H_TOTAL(h_total - 1) |
879 DSI_TOTAL_V_TOTAL(v_total - 1));
880
881 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
882 DSI_ACTIVE_HSYNC_START(hs_start) |
883 DSI_ACTIVE_HSYNC_END(hs_end));
884 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
885 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
886 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
887 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
888 } else { /* command mode */
889 /* image data and 1 byte write_memory_start cmd */
890 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
891
892 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
893 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
894 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
895 msm_host->channel) |
896 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
897 MIPI_DSI_DCS_LONG_WRITE));
898
899 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
900 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
901 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
902 }
903 }
904
905 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
906 {
907 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
908 wmb(); /* clocks need to be enabled before reset */
909
910 dsi_write(msm_host, REG_DSI_RESET, 1);
911 wmb(); /* make sure reset happen */
912 dsi_write(msm_host, REG_DSI_RESET, 0);
913 }
914
915 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
916 bool video_mode, bool enable)
917 {
918 u32 dsi_ctrl;
919
920 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
921
922 if (!enable) {
923 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
924 DSI_CTRL_CMD_MODE_EN);
925 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
926 DSI_IRQ_MASK_VIDEO_DONE, 0);
927 } else {
928 if (video_mode) {
929 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
930 } else { /* command mode */
931 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
932 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
933 }
934 dsi_ctrl |= DSI_CTRL_ENABLE;
935 }
936
937 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
938 }
939
940 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
941 {
942 u32 data;
943
944 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
945
946 if (mode == 0)
947 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
948 else
949 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
950
951 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
952 }
953
954 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
955 {
956 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
957
958 reinit_completion(&msm_host->video_comp);
959
960 wait_for_completion_timeout(&msm_host->video_comp,
961 msecs_to_jiffies(70));
962
963 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
964 }
965
966 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
967 {
968 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
969 return;
970
971 if (msm_host->power_on) {
972 dsi_wait4video_done(msm_host);
973 /* delay 4 ms to skip BLLP */
974 usleep_range(2000, 4000);
975 }
976 }
977
978 /* dsi_cmd */
979 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
980 {
981 struct drm_device *dev = msm_host->dev;
982 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
983 int ret;
984 u32 iova;
985
986 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
987 mutex_lock(&dev->struct_mutex);
988 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
989 if (IS_ERR(msm_host->tx_gem_obj)) {
990 ret = PTR_ERR(msm_host->tx_gem_obj);
991 pr_err("%s: failed to allocate gem, %d\n",
992 __func__, ret);
993 msm_host->tx_gem_obj = NULL;
994 mutex_unlock(&dev->struct_mutex);
995 return ret;
996 }
997
998 ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova);
999 mutex_unlock(&dev->struct_mutex);
1000 if (ret) {
1001 pr_err("%s: failed to get iova, %d\n", __func__, ret);
1002 return ret;
1003 }
1004
1005 if (iova & 0x07) {
1006 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
1007 return -EINVAL;
1008 }
1009
1010 msm_host->tx_size = msm_host->tx_gem_obj->size;
1011 } else {
1012 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1013 &msm_host->tx_buf_paddr, GFP_KERNEL);
1014 if (!msm_host->tx_buf) {
1015 ret = -ENOMEM;
1016 pr_err("%s: failed to allocate tx buf, %d\n",
1017 __func__, ret);
1018 return ret;
1019 }
1020
1021 msm_host->tx_size = size;
1022 }
1023
1024 return 0;
1025 }
1026
1027 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1028 {
1029 struct drm_device *dev = msm_host->dev;
1030
1031 if (msm_host->tx_gem_obj) {
1032 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
1033 mutex_lock(&dev->struct_mutex);
1034 msm_gem_free_object(msm_host->tx_gem_obj);
1035 msm_host->tx_gem_obj = NULL;
1036 mutex_unlock(&dev->struct_mutex);
1037 }
1038
1039 if (msm_host->tx_buf)
1040 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1041 msm_host->tx_buf_paddr);
1042 }
1043
1044 /*
1045 * prepare cmd buffer to be txed
1046 */
1047 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1048 const struct mipi_dsi_msg *msg)
1049 {
1050 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1051 struct mipi_dsi_packet packet;
1052 int len;
1053 int ret;
1054 u8 *data;
1055
1056 ret = mipi_dsi_create_packet(&packet, msg);
1057 if (ret) {
1058 pr_err("%s: create packet failed, %d\n", __func__, ret);
1059 return ret;
1060 }
1061 len = (packet.size + 3) & (~0x3);
1062
1063 if (len > msm_host->tx_size) {
1064 pr_err("%s: packet size is too big\n", __func__);
1065 return -EINVAL;
1066 }
1067
1068 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1069 data = msm_gem_get_vaddr(msm_host->tx_gem_obj);
1070 if (IS_ERR(data)) {
1071 ret = PTR_ERR(data);
1072 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1073 return ret;
1074 }
1075 } else {
1076 data = msm_host->tx_buf;
1077 }
1078
1079 /* MSM specific command format in memory */
1080 data[0] = packet.header[1];
1081 data[1] = packet.header[2];
1082 data[2] = packet.header[0];
1083 data[3] = BIT(7); /* Last packet */
1084 if (mipi_dsi_packet_format_is_long(msg->type))
1085 data[3] |= BIT(6);
1086 if (msg->rx_buf && msg->rx_len)
1087 data[3] |= BIT(5);
1088
1089 /* Long packet */
1090 if (packet.payload && packet.payload_length)
1091 memcpy(data + 4, packet.payload, packet.payload_length);
1092
1093 /* Append 0xff to the end */
1094 if (packet.size < len)
1095 memset(data + packet.size, 0xff, len - packet.size);
1096
1097 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
1098 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1099
1100 return len;
1101 }
1102
1103 /*
1104 * dsi_short_read1_resp: 1 parameter
1105 */
1106 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1107 {
1108 u8 *data = msg->rx_buf;
1109 if (data && (msg->rx_len >= 1)) {
1110 *data = buf[1]; /* strip out dcs type */
1111 return 1;
1112 } else {
1113 pr_err("%s: read data does not match with rx_buf len %zu\n",
1114 __func__, msg->rx_len);
1115 return -EINVAL;
1116 }
1117 }
1118
1119 /*
1120 * dsi_short_read2_resp: 2 parameter
1121 */
1122 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1123 {
1124 u8 *data = msg->rx_buf;
1125 if (data && (msg->rx_len >= 2)) {
1126 data[0] = buf[1]; /* strip out dcs type */
1127 data[1] = buf[2];
1128 return 2;
1129 } else {
1130 pr_err("%s: read data does not match with rx_buf len %zu\n",
1131 __func__, msg->rx_len);
1132 return -EINVAL;
1133 }
1134 }
1135
1136 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1137 {
1138 /* strip out 4 byte dcs header */
1139 if (msg->rx_buf && msg->rx_len)
1140 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1141
1142 return msg->rx_len;
1143 }
1144
1145 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1146 {
1147 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1148 int ret;
1149 u32 dma_base;
1150 bool triggered;
1151
1152 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1153 ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &dma_base);
1154 if (ret) {
1155 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1156 return ret;
1157 }
1158 } else {
1159 dma_base = msm_host->tx_buf_paddr;
1160 }
1161
1162 reinit_completion(&msm_host->dma_comp);
1163
1164 dsi_wait4video_eng_busy(msm_host);
1165
1166 triggered = msm_dsi_manager_cmd_xfer_trigger(
1167 msm_host->id, dma_base, len);
1168 if (triggered) {
1169 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1170 msecs_to_jiffies(200));
1171 DBG("ret=%d", ret);
1172 if (ret == 0)
1173 ret = -ETIMEDOUT;
1174 else
1175 ret = len;
1176 } else
1177 ret = len;
1178
1179 return ret;
1180 }
1181
1182 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1183 u8 *buf, int rx_byte, int pkt_size)
1184 {
1185 u32 *lp, *temp, data;
1186 int i, j = 0, cnt;
1187 u32 read_cnt;
1188 u8 reg[16];
1189 int repeated_bytes = 0;
1190 int buf_offset = buf - msm_host->rx_buf;
1191
1192 lp = (u32 *)buf;
1193 temp = (u32 *)reg;
1194 cnt = (rx_byte + 3) >> 2;
1195 if (cnt > 4)
1196 cnt = 4; /* 4 x 32 bits registers only */
1197
1198 if (rx_byte == 4)
1199 read_cnt = 4;
1200 else
1201 read_cnt = pkt_size + 6;
1202
1203 /*
1204 * In case of multiple reads from the panel, after the first read, there
1205 * is possibility that there are some bytes in the payload repeating in
1206 * the RDBK_DATA registers. Since we read all the parameters from the
1207 * panel right from the first byte for every pass. We need to skip the
1208 * repeating bytes and then append the new parameters to the rx buffer.
1209 */
1210 if (read_cnt > 16) {
1211 int bytes_shifted;
1212 /* Any data more than 16 bytes will be shifted out.
1213 * The temp read buffer should already contain these bytes.
1214 * The remaining bytes in read buffer are the repeated bytes.
1215 */
1216 bytes_shifted = read_cnt - 16;
1217 repeated_bytes = buf_offset - bytes_shifted;
1218 }
1219
1220 for (i = cnt - 1; i >= 0; i--) {
1221 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1222 *temp++ = ntohl(data); /* to host byte order */
1223 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1224 }
1225
1226 for (i = repeated_bytes; i < 16; i++)
1227 buf[j++] = reg[i];
1228
1229 return j;
1230 }
1231
1232 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1233 const struct mipi_dsi_msg *msg)
1234 {
1235 int len, ret;
1236 int bllp_len = msm_host->mode->hdisplay *
1237 dsi_get_bpp(msm_host->format) / 8;
1238
1239 len = dsi_cmd_dma_add(msm_host, msg);
1240 if (!len) {
1241 pr_err("%s: failed to add cmd type = 0x%x\n",
1242 __func__, msg->type);
1243 return -EINVAL;
1244 }
1245
1246 /* for video mode, do not send cmds more than
1247 * one pixel line, since it only transmit it
1248 * during BLLP.
1249 */
1250 /* TODO: if the command is sent in LP mode, the bit rate is only
1251 * half of esc clk rate. In this case, if the video is already
1252 * actively streaming, we need to check more carefully if the
1253 * command can be fit into one BLLP.
1254 */
1255 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1256 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1257 __func__, len);
1258 return -EINVAL;
1259 }
1260
1261 ret = dsi_cmd_dma_tx(msm_host, len);
1262 if (ret < len) {
1263 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1264 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1265 return -ECOMM;
1266 }
1267
1268 return len;
1269 }
1270
1271 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1272 {
1273 u32 data0, data1;
1274
1275 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1276 data1 = data0;
1277 data1 &= ~DSI_CTRL_ENABLE;
1278 dsi_write(msm_host, REG_DSI_CTRL, data1);
1279 /*
1280 * dsi controller need to be disabled before
1281 * clocks turned on
1282 */
1283 wmb();
1284
1285 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1286 wmb(); /* make sure clocks enabled */
1287
1288 /* dsi controller can only be reset while clocks are running */
1289 dsi_write(msm_host, REG_DSI_RESET, 1);
1290 wmb(); /* make sure reset happen */
1291 dsi_write(msm_host, REG_DSI_RESET, 0);
1292 wmb(); /* controller out of reset */
1293 dsi_write(msm_host, REG_DSI_CTRL, data0);
1294 wmb(); /* make sure dsi controller enabled again */
1295 }
1296
1297 static void dsi_err_worker(struct work_struct *work)
1298 {
1299 struct msm_dsi_host *msm_host =
1300 container_of(work, struct msm_dsi_host, err_work);
1301 u32 status = msm_host->err_work_state;
1302
1303 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1304 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1305 dsi_sw_reset_restore(msm_host);
1306
1307 /* It is safe to clear here because error irq is disabled. */
1308 msm_host->err_work_state = 0;
1309
1310 /* enable dsi error interrupt */
1311 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1312 }
1313
1314 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1315 {
1316 u32 status;
1317
1318 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1319
1320 if (status) {
1321 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1322 /* Writing of an extra 0 needed to clear error bits */
1323 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1324 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1325 }
1326 }
1327
1328 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1329 {
1330 u32 status;
1331
1332 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1333
1334 if (status) {
1335 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1336 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1337 }
1338 }
1339
1340 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1341 {
1342 u32 status;
1343
1344 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1345
1346 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1347 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1348 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1349 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1350 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1351 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1352 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1353 }
1354 }
1355
1356 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1357 {
1358 u32 status;
1359
1360 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1361
1362 /* fifo underflow, overflow */
1363 if (status) {
1364 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1365 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1366 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1367 msm_host->err_work_state |=
1368 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1369 }
1370 }
1371
1372 static void dsi_status(struct msm_dsi_host *msm_host)
1373 {
1374 u32 status;
1375
1376 status = dsi_read(msm_host, REG_DSI_STATUS0);
1377
1378 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1379 dsi_write(msm_host, REG_DSI_STATUS0, status);
1380 msm_host->err_work_state |=
1381 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1382 }
1383 }
1384
1385 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1386 {
1387 u32 status;
1388
1389 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1390
1391 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1392 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1393 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1394 }
1395 }
1396
1397 static void dsi_error(struct msm_dsi_host *msm_host)
1398 {
1399 /* disable dsi error interrupt */
1400 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1401
1402 dsi_clk_status(msm_host);
1403 dsi_fifo_status(msm_host);
1404 dsi_ack_err_status(msm_host);
1405 dsi_timeout_status(msm_host);
1406 dsi_status(msm_host);
1407 dsi_dln0_phy_err(msm_host);
1408
1409 queue_work(msm_host->workqueue, &msm_host->err_work);
1410 }
1411
1412 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1413 {
1414 struct msm_dsi_host *msm_host = ptr;
1415 u32 isr;
1416 unsigned long flags;
1417
1418 if (!msm_host->ctrl_base)
1419 return IRQ_HANDLED;
1420
1421 spin_lock_irqsave(&msm_host->intr_lock, flags);
1422 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1423 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1424 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1425
1426 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1427
1428 if (isr & DSI_IRQ_ERROR)
1429 dsi_error(msm_host);
1430
1431 if (isr & DSI_IRQ_VIDEO_DONE)
1432 complete(&msm_host->video_comp);
1433
1434 if (isr & DSI_IRQ_CMD_DMA_DONE)
1435 complete(&msm_host->dma_comp);
1436
1437 return IRQ_HANDLED;
1438 }
1439
1440 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1441 struct device *panel_device)
1442 {
1443 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1444 "disp-enable",
1445 GPIOD_OUT_LOW);
1446 if (IS_ERR(msm_host->disp_en_gpio)) {
1447 DBG("cannot get disp-enable-gpios %ld",
1448 PTR_ERR(msm_host->disp_en_gpio));
1449 return PTR_ERR(msm_host->disp_en_gpio);
1450 }
1451
1452 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1453 GPIOD_IN);
1454 if (IS_ERR(msm_host->te_gpio)) {
1455 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1456 return PTR_ERR(msm_host->te_gpio);
1457 }
1458
1459 return 0;
1460 }
1461
1462 static int dsi_host_attach(struct mipi_dsi_host *host,
1463 struct mipi_dsi_device *dsi)
1464 {
1465 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1466 int ret;
1467
1468 if (dsi->lanes > msm_host->num_data_lanes)
1469 return -EINVAL;
1470
1471 msm_host->channel = dsi->channel;
1472 msm_host->lanes = dsi->lanes;
1473 msm_host->format = dsi->format;
1474 msm_host->mode_flags = dsi->mode_flags;
1475
1476 /* Some gpios defined in panel DT need to be controlled by host */
1477 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1478 if (ret)
1479 return ret;
1480
1481 DBG("id=%d", msm_host->id);
1482 if (msm_host->dev)
1483 drm_helper_hpd_irq_event(msm_host->dev);
1484
1485 return 0;
1486 }
1487
1488 static int dsi_host_detach(struct mipi_dsi_host *host,
1489 struct mipi_dsi_device *dsi)
1490 {
1491 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1492
1493 msm_host->device_node = NULL;
1494
1495 DBG("id=%d", msm_host->id);
1496 if (msm_host->dev)
1497 drm_helper_hpd_irq_event(msm_host->dev);
1498
1499 return 0;
1500 }
1501
1502 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1503 const struct mipi_dsi_msg *msg)
1504 {
1505 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1506 int ret;
1507
1508 if (!msg || !msm_host->power_on)
1509 return -EINVAL;
1510
1511 mutex_lock(&msm_host->cmd_mutex);
1512 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1513 mutex_unlock(&msm_host->cmd_mutex);
1514
1515 return ret;
1516 }
1517
1518 static struct mipi_dsi_host_ops dsi_host_ops = {
1519 .attach = dsi_host_attach,
1520 .detach = dsi_host_detach,
1521 .transfer = dsi_host_transfer,
1522 };
1523
1524 /*
1525 * List of supported physical to logical lane mappings.
1526 * For example, the 2nd entry represents the following mapping:
1527 *
1528 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1529 */
1530 static const int supported_data_lane_swaps[][4] = {
1531 { 0, 1, 2, 3 },
1532 { 3, 0, 1, 2 },
1533 { 2, 3, 0, 1 },
1534 { 1, 2, 3, 0 },
1535 { 0, 3, 2, 1 },
1536 { 1, 0, 3, 2 },
1537 { 2, 1, 0, 3 },
1538 { 3, 2, 1, 0 },
1539 };
1540
1541 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1542 struct device_node *ep)
1543 {
1544 struct device *dev = &msm_host->pdev->dev;
1545 struct property *prop;
1546 u32 lane_map[4];
1547 int ret, i, len, num_lanes;
1548
1549 prop = of_find_property(ep, "data-lanes", &len);
1550 if (!prop) {
1551 dev_dbg(dev, "failed to find data lane mapping\n");
1552 return -EINVAL;
1553 }
1554
1555 num_lanes = len / sizeof(u32);
1556
1557 if (num_lanes < 1 || num_lanes > 4) {
1558 dev_err(dev, "bad number of data lanes\n");
1559 return -EINVAL;
1560 }
1561
1562 msm_host->num_data_lanes = num_lanes;
1563
1564 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1565 num_lanes);
1566 if (ret) {
1567 dev_err(dev, "failed to read lane data\n");
1568 return ret;
1569 }
1570
1571 /*
1572 * compare DT specified physical-logical lane mappings with the ones
1573 * supported by hardware
1574 */
1575 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1576 const int *swap = supported_data_lane_swaps[i];
1577 int j;
1578
1579 /*
1580 * the data-lanes array we get from DT has a logical->physical
1581 * mapping. The "data lane swap" register field represents
1582 * supported configurations in a physical->logical mapping.
1583 * Translate the DT mapping to what we understand and find a
1584 * configuration that works.
1585 */
1586 for (j = 0; j < num_lanes; j++) {
1587 if (lane_map[j] < 0 || lane_map[j] > 3)
1588 dev_err(dev, "bad physical lane entry %u\n",
1589 lane_map[j]);
1590
1591 if (swap[lane_map[j]] != j)
1592 break;
1593 }
1594
1595 if (j == num_lanes) {
1596 msm_host->dlane_swap = i;
1597 return 0;
1598 }
1599 }
1600
1601 return -EINVAL;
1602 }
1603
1604 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1605 {
1606 struct device *dev = &msm_host->pdev->dev;
1607 struct device_node *np = dev->of_node;
1608 struct device_node *endpoint, *device_node;
1609 int ret;
1610
1611 /*
1612 * Get the endpoint of the output port of the DSI host. In our case,
1613 * this is mapped to port number with reg = 1. Don't return an error if
1614 * the remote endpoint isn't defined. It's possible that there is
1615 * nothing connected to the dsi output.
1616 */
1617 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1618 if (!endpoint) {
1619 dev_dbg(dev, "%s: no endpoint\n", __func__);
1620 return 0;
1621 }
1622
1623 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1624 if (ret) {
1625 dev_err(dev, "%s: invalid lane configuration %d\n",
1626 __func__, ret);
1627 goto err;
1628 }
1629
1630 /* Get panel node from the output port's endpoint data */
1631 device_node = of_graph_get_remote_port_parent(endpoint);
1632 if (!device_node) {
1633 dev_err(dev, "%s: no valid device\n", __func__);
1634 ret = -ENODEV;
1635 goto err;
1636 }
1637
1638 msm_host->device_node = device_node;
1639
1640 if (of_property_read_bool(np, "syscon-sfpb")) {
1641 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1642 "syscon-sfpb");
1643 if (IS_ERR(msm_host->sfpb)) {
1644 dev_err(dev, "%s: failed to get sfpb regmap\n",
1645 __func__);
1646 ret = PTR_ERR(msm_host->sfpb);
1647 }
1648 }
1649
1650 of_node_put(device_node);
1651
1652 err:
1653 of_node_put(endpoint);
1654
1655 return ret;
1656 }
1657
1658 static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1659 {
1660 struct platform_device *pdev = msm_host->pdev;
1661 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1662 struct resource *res;
1663 int i;
1664
1665 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1666 if (!res)
1667 return -EINVAL;
1668
1669 for (i = 0; i < cfg->num_dsi; i++) {
1670 if (cfg->io_start[i] == res->start)
1671 return i;
1672 }
1673
1674 return -EINVAL;
1675 }
1676
1677 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1678 {
1679 struct msm_dsi_host *msm_host = NULL;
1680 struct platform_device *pdev = msm_dsi->pdev;
1681 int ret;
1682
1683 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1684 if (!msm_host) {
1685 pr_err("%s: FAILED: cannot alloc dsi host\n",
1686 __func__);
1687 ret = -ENOMEM;
1688 goto fail;
1689 }
1690
1691 msm_host->pdev = pdev;
1692
1693 ret = dsi_host_parse_dt(msm_host);
1694 if (ret) {
1695 pr_err("%s: failed to parse dt\n", __func__);
1696 goto fail;
1697 }
1698
1699 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1700 if (IS_ERR(msm_host->ctrl_base)) {
1701 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1702 ret = PTR_ERR(msm_host->ctrl_base);
1703 goto fail;
1704 }
1705
1706 msm_host->cfg_hnd = dsi_get_config(msm_host);
1707 if (!msm_host->cfg_hnd) {
1708 ret = -EINVAL;
1709 pr_err("%s: get config failed\n", __func__);
1710 goto fail;
1711 }
1712
1713 msm_host->id = dsi_host_get_id(msm_host);
1714 if (msm_host->id < 0) {
1715 ret = msm_host->id;
1716 pr_err("%s: unable to identify DSI host index\n", __func__);
1717 goto fail;
1718 }
1719
1720 /* fixup base address by io offset */
1721 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1722
1723 ret = dsi_regulator_init(msm_host);
1724 if (ret) {
1725 pr_err("%s: regulator init failed\n", __func__);
1726 goto fail;
1727 }
1728
1729 ret = dsi_clk_init(msm_host);
1730 if (ret) {
1731 pr_err("%s: unable to initialize dsi clks\n", __func__);
1732 goto fail;
1733 }
1734
1735 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1736 if (!msm_host->rx_buf) {
1737 pr_err("%s: alloc rx temp buf failed\n", __func__);
1738 goto fail;
1739 }
1740
1741 init_completion(&msm_host->dma_comp);
1742 init_completion(&msm_host->video_comp);
1743 mutex_init(&msm_host->dev_mutex);
1744 mutex_init(&msm_host->cmd_mutex);
1745 mutex_init(&msm_host->clk_mutex);
1746 spin_lock_init(&msm_host->intr_lock);
1747
1748 /* setup workqueue */
1749 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1750 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1751
1752 msm_dsi->host = &msm_host->base;
1753 msm_dsi->id = msm_host->id;
1754
1755 DBG("Dsi Host %d initialized", msm_host->id);
1756 return 0;
1757
1758 fail:
1759 return ret;
1760 }
1761
1762 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1763 {
1764 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1765
1766 DBG("");
1767 dsi_tx_buf_free(msm_host);
1768 if (msm_host->workqueue) {
1769 flush_workqueue(msm_host->workqueue);
1770 destroy_workqueue(msm_host->workqueue);
1771 msm_host->workqueue = NULL;
1772 }
1773
1774 mutex_destroy(&msm_host->clk_mutex);
1775 mutex_destroy(&msm_host->cmd_mutex);
1776 mutex_destroy(&msm_host->dev_mutex);
1777 }
1778
1779 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1780 struct drm_device *dev)
1781 {
1782 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1783 struct platform_device *pdev = msm_host->pdev;
1784 int ret;
1785
1786 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1787 if (msm_host->irq < 0) {
1788 ret = msm_host->irq;
1789 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1790 return ret;
1791 }
1792
1793 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1794 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1795 "dsi_isr", msm_host);
1796 if (ret < 0) {
1797 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1798 msm_host->irq, ret);
1799 return ret;
1800 }
1801
1802 msm_host->dev = dev;
1803 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1804 if (ret) {
1805 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1806 return ret;
1807 }
1808
1809 return 0;
1810 }
1811
1812 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1813 {
1814 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1815 int ret;
1816
1817 /* Register mipi dsi host */
1818 if (!msm_host->registered) {
1819 host->dev = &msm_host->pdev->dev;
1820 host->ops = &dsi_host_ops;
1821 ret = mipi_dsi_host_register(host);
1822 if (ret)
1823 return ret;
1824
1825 msm_host->registered = true;
1826
1827 /* If the panel driver has not been probed after host register,
1828 * we should defer the host's probe.
1829 * It makes sure panel is connected when fbcon detects
1830 * connector status and gets the proper display mode to
1831 * create framebuffer.
1832 * Don't try to defer if there is nothing connected to the dsi
1833 * output
1834 */
1835 if (check_defer && msm_host->device_node) {
1836 if (!of_drm_find_panel(msm_host->device_node))
1837 if (!of_drm_find_bridge(msm_host->device_node))
1838 return -EPROBE_DEFER;
1839 }
1840 }
1841
1842 return 0;
1843 }
1844
1845 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1846 {
1847 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1848
1849 if (msm_host->registered) {
1850 mipi_dsi_host_unregister(host);
1851 host->dev = NULL;
1852 host->ops = NULL;
1853 msm_host->registered = false;
1854 }
1855 }
1856
1857 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1858 const struct mipi_dsi_msg *msg)
1859 {
1860 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1861
1862 /* TODO: make sure dsi_cmd_mdp is idle.
1863 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1864 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1865 * How to handle the old versions? Wait for mdp cmd done?
1866 */
1867
1868 /*
1869 * mdss interrupt is generated in mdp core clock domain
1870 * mdp clock need to be enabled to receive dsi interrupt
1871 */
1872 dsi_clk_ctrl(msm_host, 1);
1873
1874 /* TODO: vote for bus bandwidth */
1875
1876 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1877 dsi_set_tx_power_mode(0, msm_host);
1878
1879 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1880 dsi_write(msm_host, REG_DSI_CTRL,
1881 msm_host->dma_cmd_ctrl_restore |
1882 DSI_CTRL_CMD_MODE_EN |
1883 DSI_CTRL_ENABLE);
1884 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1885
1886 return 0;
1887 }
1888
1889 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1890 const struct mipi_dsi_msg *msg)
1891 {
1892 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1893
1894 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1895 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1896
1897 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1898 dsi_set_tx_power_mode(1, msm_host);
1899
1900 /* TODO: unvote for bus bandwidth */
1901
1902 dsi_clk_ctrl(msm_host, 0);
1903 }
1904
1905 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1906 const struct mipi_dsi_msg *msg)
1907 {
1908 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1909
1910 return dsi_cmds2buf_tx(msm_host, msg);
1911 }
1912
1913 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1914 const struct mipi_dsi_msg *msg)
1915 {
1916 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1917 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1918 int data_byte, rx_byte, dlen, end;
1919 int short_response, diff, pkt_size, ret = 0;
1920 char cmd;
1921 int rlen = msg->rx_len;
1922 u8 *buf;
1923
1924 if (rlen <= 2) {
1925 short_response = 1;
1926 pkt_size = rlen;
1927 rx_byte = 4;
1928 } else {
1929 short_response = 0;
1930 data_byte = 10; /* first read */
1931 if (rlen < data_byte)
1932 pkt_size = rlen;
1933 else
1934 pkt_size = data_byte;
1935 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1936 }
1937
1938 buf = msm_host->rx_buf;
1939 end = 0;
1940 while (!end) {
1941 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1942 struct mipi_dsi_msg max_pkt_size_msg = {
1943 .channel = msg->channel,
1944 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
1945 .tx_len = 2,
1946 .tx_buf = tx,
1947 };
1948
1949 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1950 rlen, pkt_size, rx_byte);
1951
1952 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
1953 if (ret < 2) {
1954 pr_err("%s: Set max pkt size failed, %d\n",
1955 __func__, ret);
1956 return -EINVAL;
1957 }
1958
1959 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
1960 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
1961 /* Clear the RDBK_DATA registers */
1962 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
1963 DSI_RDBK_DATA_CTRL_CLR);
1964 wmb(); /* make sure the RDBK registers are cleared */
1965 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
1966 wmb(); /* release cleared status before transfer */
1967 }
1968
1969 ret = dsi_cmds2buf_tx(msm_host, msg);
1970 if (ret < msg->tx_len) {
1971 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
1972 return ret;
1973 }
1974
1975 /*
1976 * once cmd_dma_done interrupt received,
1977 * return data from client is ready and stored
1978 * at RDBK_DATA register already
1979 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1980 * after that dcs header lost during shift into registers
1981 */
1982 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
1983
1984 if (dlen <= 0)
1985 return 0;
1986
1987 if (short_response)
1988 break;
1989
1990 if (rlen <= data_byte) {
1991 diff = data_byte - rlen;
1992 end = 1;
1993 } else {
1994 diff = 0;
1995 rlen -= data_byte;
1996 }
1997
1998 if (!end) {
1999 dlen -= 2; /* 2 crc */
2000 dlen -= diff;
2001 buf += dlen; /* next start position */
2002 data_byte = 14; /* NOT first read */
2003 if (rlen < data_byte)
2004 pkt_size += rlen;
2005 else
2006 pkt_size += data_byte;
2007 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2008 }
2009 }
2010
2011 /*
2012 * For single Long read, if the requested rlen < 10,
2013 * we need to shift the start position of rx
2014 * data buffer to skip the bytes which are not
2015 * updated.
2016 */
2017 if (pkt_size < 10 && !short_response)
2018 buf = msm_host->rx_buf + (10 - rlen);
2019 else
2020 buf = msm_host->rx_buf;
2021
2022 cmd = buf[0];
2023 switch (cmd) {
2024 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2025 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2026 ret = 0;
2027 break;
2028 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2029 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2030 ret = dsi_short_read1_resp(buf, msg);
2031 break;
2032 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2033 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2034 ret = dsi_short_read2_resp(buf, msg);
2035 break;
2036 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2037 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2038 ret = dsi_long_read_resp(buf, msg);
2039 break;
2040 default:
2041 pr_warn("%s:Invalid response cmd\n", __func__);
2042 ret = 0;
2043 }
2044
2045 return ret;
2046 }
2047
2048 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2049 u32 len)
2050 {
2051 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2052
2053 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2054 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2055 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2056
2057 /* Make sure trigger happens */
2058 wmb();
2059 }
2060
2061 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2062 struct msm_dsi_pll *src_pll)
2063 {
2064 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2065 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2066 struct clk *byte_clk_provider, *pixel_clk_provider;
2067 int ret;
2068
2069 ret = msm_dsi_pll_get_clk_provider(src_pll,
2070 &byte_clk_provider, &pixel_clk_provider);
2071 if (ret) {
2072 pr_info("%s: can't get provider from pll, don't set parent\n",
2073 __func__);
2074 return 0;
2075 }
2076
2077 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2078 if (ret) {
2079 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2080 __func__, ret);
2081 goto exit;
2082 }
2083
2084 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2085 if (ret) {
2086 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2087 __func__, ret);
2088 goto exit;
2089 }
2090
2091 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
2092 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2093 if (ret) {
2094 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2095 __func__, ret);
2096 goto exit;
2097 }
2098
2099 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2100 if (ret) {
2101 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2102 __func__, ret);
2103 goto exit;
2104 }
2105 }
2106
2107 exit:
2108 return ret;
2109 }
2110
2111 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2112 {
2113 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2114
2115 dsi_op_mode_config(msm_host,
2116 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2117
2118 /* TODO: clock should be turned off for command mode,
2119 * and only turned on before MDP START.
2120 * This part of code should be enabled once mdp driver support it.
2121 */
2122 /* if (msm_panel->mode == MSM_DSI_CMD_MODE)
2123 dsi_clk_ctrl(msm_host, 0); */
2124
2125 return 0;
2126 }
2127
2128 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2129 {
2130 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2131
2132 dsi_op_mode_config(msm_host,
2133 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2134
2135 /* Since we have disabled INTF, the video engine won't stop so that
2136 * the cmd engine will be blocked.
2137 * Reset to disable video engine so that we can send off cmd.
2138 */
2139 dsi_sw_reset(msm_host);
2140
2141 return 0;
2142 }
2143
2144 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2145 {
2146 enum sfpb_ahb_arb_master_port_en en;
2147
2148 if (!msm_host->sfpb)
2149 return;
2150
2151 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2152
2153 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2154 SFPB_GPREG_MASTER_PORT_EN__MASK,
2155 SFPB_GPREG_MASTER_PORT_EN(en));
2156 }
2157
2158 int msm_dsi_host_power_on(struct mipi_dsi_host *host)
2159 {
2160 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2161 u32 clk_pre = 0, clk_post = 0;
2162 int ret = 0;
2163
2164 mutex_lock(&msm_host->dev_mutex);
2165 if (msm_host->power_on) {
2166 DBG("dsi host already on");
2167 goto unlock_ret;
2168 }
2169
2170 msm_dsi_sfpb_config(msm_host, true);
2171
2172 ret = dsi_calc_clk_rate(msm_host);
2173 if (ret) {
2174 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2175 goto unlock_ret;
2176 }
2177
2178 ret = dsi_host_regulator_enable(msm_host);
2179 if (ret) {
2180 pr_err("%s:Failed to enable vregs.ret=%d\n",
2181 __func__, ret);
2182 goto unlock_ret;
2183 }
2184
2185 ret = dsi_bus_clk_enable(msm_host);
2186 if (ret) {
2187 pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret);
2188 goto fail_disable_reg;
2189 }
2190
2191 dsi_phy_sw_reset(msm_host);
2192 ret = msm_dsi_manager_phy_enable(msm_host->id,
2193 msm_host->byte_clk_rate * 8,
2194 msm_host->esc_clk_rate,
2195 &clk_pre, &clk_post);
2196 dsi_bus_clk_disable(msm_host);
2197 if (ret) {
2198 pr_err("%s: failed to enable phy, %d\n", __func__, ret);
2199 goto fail_disable_reg;
2200 }
2201
2202 ret = dsi_clk_ctrl(msm_host, 1);
2203 if (ret) {
2204 pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);
2205 goto fail_disable_reg;
2206 }
2207
2208 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2209 if (ret) {
2210 pr_err("%s: failed to set pinctrl default state, %d\n",
2211 __func__, ret);
2212 goto fail_disable_clk;
2213 }
2214
2215 dsi_timing_setup(msm_host);
2216 dsi_sw_reset(msm_host);
2217 dsi_ctrl_config(msm_host, true, clk_pre, clk_post);
2218
2219 if (msm_host->disp_en_gpio)
2220 gpiod_set_value(msm_host->disp_en_gpio, 1);
2221
2222 msm_host->power_on = true;
2223 mutex_unlock(&msm_host->dev_mutex);
2224
2225 return 0;
2226
2227 fail_disable_clk:
2228 dsi_clk_ctrl(msm_host, 0);
2229 fail_disable_reg:
2230 dsi_host_regulator_disable(msm_host);
2231 unlock_ret:
2232 mutex_unlock(&msm_host->dev_mutex);
2233 return ret;
2234 }
2235
2236 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2237 {
2238 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2239
2240 mutex_lock(&msm_host->dev_mutex);
2241 if (!msm_host->power_on) {
2242 DBG("dsi host already off");
2243 goto unlock_ret;
2244 }
2245
2246 dsi_ctrl_config(msm_host, false, 0, 0);
2247
2248 if (msm_host->disp_en_gpio)
2249 gpiod_set_value(msm_host->disp_en_gpio, 0);
2250
2251 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2252
2253 msm_dsi_manager_phy_disable(msm_host->id);
2254
2255 dsi_clk_ctrl(msm_host, 0);
2256
2257 dsi_host_regulator_disable(msm_host);
2258
2259 msm_dsi_sfpb_config(msm_host, false);
2260
2261 DBG("-");
2262
2263 msm_host->power_on = false;
2264
2265 unlock_ret:
2266 mutex_unlock(&msm_host->dev_mutex);
2267 return 0;
2268 }
2269
2270 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2271 struct drm_display_mode *mode)
2272 {
2273 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2274
2275 if (msm_host->mode) {
2276 drm_mode_destroy(msm_host->dev, msm_host->mode);
2277 msm_host->mode = NULL;
2278 }
2279
2280 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2281 if (!msm_host->mode) {
2282 pr_err("%s: cannot duplicate mode\n", __func__);
2283 return -ENOMEM;
2284 }
2285
2286 return 0;
2287 }
2288
2289 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
2290 unsigned long *panel_flags)
2291 {
2292 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2293 struct drm_panel *panel;
2294
2295 panel = of_drm_find_panel(msm_host->device_node);
2296 if (panel_flags)
2297 *panel_flags = msm_host->mode_flags;
2298
2299 return panel;
2300 }
2301
2302 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2303 {
2304 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2305
2306 return of_drm_find_bridge(msm_host->device_node);
2307 }
ubuntu-bionic-kernel mirror