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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / msm / dsi / dsi_host.c
1 /*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/of_graph.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
29 #include <video/mipi_display.h>
30
31 #include "dsi.h"
32 #include "dsi.xml.h"
33 #include "sfpb.xml.h"
34 #include "dsi_cfg.h"
35 #include "msm_kms.h"
36
37 #define DSI_RESET_TOGGLE_DELAY_MS 20
38
39 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
40 {
41 u32 ver;
42
43 if (!major || !minor)
44 return -EINVAL;
45
46 /*
47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
48 * makes all other registers 4-byte shifted down.
49 *
50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
51 * older, we read the DSI_VERSION register without any shift(offset
52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
53 * the case of DSI6G, this has to be zero (the offset points to a
54 * scratch register which we never touch)
55 */
56
57 ver = msm_readl(base + REG_DSI_VERSION);
58 if (ver) {
59 /* older dsi host, there is no register shift */
60 ver = FIELD(ver, DSI_VERSION_MAJOR);
61 if (ver <= MSM_DSI_VER_MAJOR_V2) {
62 /* old versions */
63 *major = ver;
64 *minor = 0;
65 return 0;
66 } else {
67 return -EINVAL;
68 }
69 } else {
70 /*
71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
72 * registers are shifted down, read DSI_VERSION again with
73 * the shifted offset
74 */
75 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
76 ver = FIELD(ver, DSI_VERSION_MAJOR);
77 if (ver == MSM_DSI_VER_MAJOR_6G) {
78 /* 6G version */
79 *major = ver;
80 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
81 return 0;
82 } else {
83 return -EINVAL;
84 }
85 }
86 }
87
88 #define DSI_ERR_STATE_ACK 0x0000
89 #define DSI_ERR_STATE_TIMEOUT 0x0001
90 #define DSI_ERR_STATE_DLN0_PHY 0x0002
91 #define DSI_ERR_STATE_FIFO 0x0004
92 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
93 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
94 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
95
96 #define DSI_CLK_CTRL_ENABLE_CLKS \
97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
101
102 struct msm_dsi_host {
103 struct mipi_dsi_host base;
104
105 struct platform_device *pdev;
106 struct drm_device *dev;
107
108 int id;
109
110 void __iomem *ctrl_base;
111 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
112
113 struct clk *bus_clks[DSI_BUS_CLK_MAX];
114
115 struct clk *byte_clk;
116 struct clk *esc_clk;
117 struct clk *pixel_clk;
118 struct clk *byte_clk_src;
119 struct clk *pixel_clk_src;
120
121 u32 byte_clk_rate;
122 u32 esc_clk_rate;
123
124 /* DSI v2 specific clocks */
125 struct clk *src_clk;
126 struct clk *esc_clk_src;
127 struct clk *dsi_clk_src;
128
129 u32 src_clk_rate;
130
131 struct gpio_desc *disp_en_gpio;
132 struct gpio_desc *te_gpio;
133
134 const struct msm_dsi_cfg_handler *cfg_hnd;
135
136 struct completion dma_comp;
137 struct completion video_comp;
138 struct mutex dev_mutex;
139 struct mutex cmd_mutex;
140 spinlock_t intr_lock; /* Protect interrupt ctrl register */
141
142 u32 err_work_state;
143 struct work_struct err_work;
144 struct work_struct hpd_work;
145 struct workqueue_struct *workqueue;
146
147 /* DSI 6G TX buffer*/
148 struct drm_gem_object *tx_gem_obj;
149
150 /* DSI v2 TX buffer */
151 void *tx_buf;
152 dma_addr_t tx_buf_paddr;
153
154 int tx_size;
155
156 u8 *rx_buf;
157
158 struct regmap *sfpb;
159
160 struct drm_display_mode *mode;
161
162 /* connected device info */
163 struct device_node *device_node;
164 unsigned int channel;
165 unsigned int lanes;
166 enum mipi_dsi_pixel_format format;
167 unsigned long mode_flags;
168
169 /* lane data parsed via DT */
170 int dlane_swap;
171 int num_data_lanes;
172
173 u32 dma_cmd_ctrl_restore;
174
175 bool registered;
176 bool power_on;
177 int irq;
178 };
179
180 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
181 {
182 switch (fmt) {
183 case MIPI_DSI_FMT_RGB565: return 16;
184 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
185 case MIPI_DSI_FMT_RGB666:
186 case MIPI_DSI_FMT_RGB888:
187 default: return 24;
188 }
189 }
190
191 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
192 {
193 return msm_readl(msm_host->ctrl_base + reg);
194 }
195 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
196 {
197 msm_writel(data, msm_host->ctrl_base + reg);
198 }
199
200 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host);
201 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host);
202
203 static const struct msm_dsi_cfg_handler *dsi_get_config(
204 struct msm_dsi_host *msm_host)
205 {
206 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
207 struct device *dev = &msm_host->pdev->dev;
208 struct regulator *gdsc_reg;
209 struct clk *ahb_clk;
210 int ret;
211 u32 major = 0, minor = 0;
212
213 gdsc_reg = regulator_get(dev, "gdsc");
214 if (IS_ERR(gdsc_reg)) {
215 pr_err("%s: cannot get gdsc\n", __func__);
216 goto exit;
217 }
218
219 ahb_clk = clk_get(dev, "iface_clk");
220 if (IS_ERR(ahb_clk)) {
221 pr_err("%s: cannot get interface clock\n", __func__);
222 goto put_gdsc;
223 }
224
225 pm_runtime_get_sync(dev);
226
227 ret = regulator_enable(gdsc_reg);
228 if (ret) {
229 pr_err("%s: unable to enable gdsc\n", __func__);
230 goto put_clk;
231 }
232
233 ret = clk_prepare_enable(ahb_clk);
234 if (ret) {
235 pr_err("%s: unable to enable ahb_clk\n", __func__);
236 goto disable_gdsc;
237 }
238
239 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
240 if (ret) {
241 pr_err("%s: Invalid version\n", __func__);
242 goto disable_clks;
243 }
244
245 cfg_hnd = msm_dsi_cfg_get(major, minor);
246
247 DBG("%s: Version %x:%x\n", __func__, major, minor);
248
249 disable_clks:
250 clk_disable_unprepare(ahb_clk);
251 disable_gdsc:
252 regulator_disable(gdsc_reg);
253 pm_runtime_put_sync(dev);
254 put_clk:
255 clk_put(ahb_clk);
256 put_gdsc:
257 regulator_put(gdsc_reg);
258 exit:
259 return cfg_hnd;
260 }
261
262 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
263 {
264 return container_of(host, struct msm_dsi_host, base);
265 }
266
267 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host)
268 {
269 struct regulator_bulk_data *s = msm_host->supplies;
270 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
271 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
272 int i;
273
274 DBG("");
275 for (i = num - 1; i >= 0; i--)
276 if (regs[i].disable_load >= 0)
277 regulator_set_load(s[i].consumer,
278 regs[i].disable_load);
279
280 regulator_bulk_disable(num, s);
281 }
282
283 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host)
284 {
285 struct regulator_bulk_data *s = msm_host->supplies;
286 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
287 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
288 int ret, i;
289
290 DBG("");
291 for (i = 0; i < num; i++) {
292 if (regs[i].enable_load >= 0) {
293 ret = regulator_set_load(s[i].consumer,
294 regs[i].enable_load);
295 if (ret < 0) {
296 pr_err("regulator %d set op mode failed, %d\n",
297 i, ret);
298 goto fail;
299 }
300 }
301 }
302
303 ret = regulator_bulk_enable(num, s);
304 if (ret < 0) {
305 pr_err("regulator enable failed, %d\n", ret);
306 goto fail;
307 }
308
309 return 0;
310
311 fail:
312 for (i--; i >= 0; i--)
313 regulator_set_load(s[i].consumer, regs[i].disable_load);
314 return ret;
315 }
316
317 static int dsi_regulator_init(struct msm_dsi_host *msm_host)
318 {
319 struct regulator_bulk_data *s = msm_host->supplies;
320 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs;
321 int num = msm_host->cfg_hnd->cfg->reg_cfg.num;
322 int i, ret;
323
324 for (i = 0; i < num; i++)
325 s[i].supply = regs[i].name;
326
327 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s);
328 if (ret < 0) {
329 pr_err("%s: failed to init regulator, ret=%d\n",
330 __func__, ret);
331 return ret;
332 }
333
334 return 0;
335 }
336
337 static int dsi_clk_init(struct msm_dsi_host *msm_host)
338 {
339 struct platform_device *pdev = msm_host->pdev;
340 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
341 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
342 int i, ret = 0;
343
344 /* get bus clocks */
345 for (i = 0; i < cfg->num_bus_clks; i++) {
346 msm_host->bus_clks[i] = msm_clk_get(pdev,
347 cfg->bus_clk_names[i]);
348 if (IS_ERR(msm_host->bus_clks[i])) {
349 ret = PTR_ERR(msm_host->bus_clks[i]);
350 pr_err("%s: Unable to get %s clock, ret = %d\n",
351 __func__, cfg->bus_clk_names[i], ret);
352 goto exit;
353 }
354 }
355
356 /* get link and source clocks */
357 msm_host->byte_clk = msm_clk_get(pdev, "byte");
358 if (IS_ERR(msm_host->byte_clk)) {
359 ret = PTR_ERR(msm_host->byte_clk);
360 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
361 __func__, ret);
362 msm_host->byte_clk = NULL;
363 goto exit;
364 }
365
366 msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
367 if (IS_ERR(msm_host->pixel_clk)) {
368 ret = PTR_ERR(msm_host->pixel_clk);
369 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
370 __func__, ret);
371 msm_host->pixel_clk = NULL;
372 goto exit;
373 }
374
375 msm_host->esc_clk = msm_clk_get(pdev, "core");
376 if (IS_ERR(msm_host->esc_clk)) {
377 ret = PTR_ERR(msm_host->esc_clk);
378 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
379 __func__, ret);
380 msm_host->esc_clk = NULL;
381 goto exit;
382 }
383
384 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk);
385 if (IS_ERR(msm_host->byte_clk_src)) {
386 ret = PTR_ERR(msm_host->byte_clk_src);
387 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret);
388 goto exit;
389 }
390
391 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk);
392 if (IS_ERR(msm_host->pixel_clk_src)) {
393 ret = PTR_ERR(msm_host->pixel_clk_src);
394 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret);
395 goto exit;
396 }
397
398 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
399 msm_host->src_clk = msm_clk_get(pdev, "src");
400 if (IS_ERR(msm_host->src_clk)) {
401 ret = PTR_ERR(msm_host->src_clk);
402 pr_err("%s: can't find src clock. ret=%d\n",
403 __func__, ret);
404 msm_host->src_clk = NULL;
405 goto exit;
406 }
407
408 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk);
409 if (!msm_host->esc_clk_src) {
410 ret = -ENODEV;
411 pr_err("%s: can't get esc clock parent. ret=%d\n",
412 __func__, ret);
413 goto exit;
414 }
415
416 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk);
417 if (!msm_host->dsi_clk_src) {
418 ret = -ENODEV;
419 pr_err("%s: can't get src clock parent. ret=%d\n",
420 __func__, ret);
421 }
422 }
423 exit:
424 return ret;
425 }
426
427 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host)
428 {
429 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
430 int i, ret;
431
432 DBG("id=%d", msm_host->id);
433
434 for (i = 0; i < cfg->num_bus_clks; i++) {
435 ret = clk_prepare_enable(msm_host->bus_clks[i]);
436 if (ret) {
437 pr_err("%s: failed to enable bus clock %d ret %d\n",
438 __func__, i, ret);
439 goto err;
440 }
441 }
442
443 return 0;
444 err:
445 for (; i > 0; i--)
446 clk_disable_unprepare(msm_host->bus_clks[i]);
447
448 return ret;
449 }
450
451 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host)
452 {
453 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
454 int i;
455
456 DBG("");
457
458 for (i = cfg->num_bus_clks - 1; i >= 0; i--)
459 clk_disable_unprepare(msm_host->bus_clks[i]);
460 }
461
462 int msm_dsi_runtime_suspend(struct device *dev)
463 {
464 struct platform_device *pdev = to_platform_device(dev);
465 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
466 struct mipi_dsi_host *host = msm_dsi->host;
467 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
468
469 if (!msm_host->cfg_hnd)
470 return 0;
471
472 dsi_bus_clk_disable(msm_host);
473
474 return 0;
475 }
476
477 int msm_dsi_runtime_resume(struct device *dev)
478 {
479 struct platform_device *pdev = to_platform_device(dev);
480 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
481 struct mipi_dsi_host *host = msm_dsi->host;
482 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
483
484 if (!msm_host->cfg_hnd)
485 return 0;
486
487 return dsi_bus_clk_enable(msm_host);
488 }
489
490 static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
491 {
492 int ret;
493
494 DBG("Set clk rates: pclk=%d, byteclk=%d",
495 msm_host->mode->clock, msm_host->byte_clk_rate);
496
497 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
498 if (ret) {
499 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
500 goto error;
501 }
502
503 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
504 if (ret) {
505 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
506 goto error;
507 }
508
509 ret = clk_prepare_enable(msm_host->esc_clk);
510 if (ret) {
511 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
512 goto error;
513 }
514
515 ret = clk_prepare_enable(msm_host->byte_clk);
516 if (ret) {
517 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
518 goto byte_clk_err;
519 }
520
521 ret = clk_prepare_enable(msm_host->pixel_clk);
522 if (ret) {
523 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
524 goto pixel_clk_err;
525 }
526
527 return 0;
528
529 pixel_clk_err:
530 clk_disable_unprepare(msm_host->byte_clk);
531 byte_clk_err:
532 clk_disable_unprepare(msm_host->esc_clk);
533 error:
534 return ret;
535 }
536
537 static int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
538 {
539 int ret;
540
541 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
542 msm_host->mode->clock, msm_host->byte_clk_rate,
543 msm_host->esc_clk_rate, msm_host->src_clk_rate);
544
545 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
546 if (ret) {
547 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
548 goto error;
549 }
550
551 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
552 if (ret) {
553 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
554 goto error;
555 }
556
557 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
558 if (ret) {
559 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
560 goto error;
561 }
562
563 ret = clk_set_rate(msm_host->pixel_clk, msm_host->mode->clock * 1000);
564 if (ret) {
565 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
566 goto error;
567 }
568
569 ret = clk_prepare_enable(msm_host->byte_clk);
570 if (ret) {
571 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
572 goto error;
573 }
574
575 ret = clk_prepare_enable(msm_host->esc_clk);
576 if (ret) {
577 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
578 goto esc_clk_err;
579 }
580
581 ret = clk_prepare_enable(msm_host->src_clk);
582 if (ret) {
583 pr_err("%s: Failed to enable dsi src clk\n", __func__);
584 goto src_clk_err;
585 }
586
587 ret = clk_prepare_enable(msm_host->pixel_clk);
588 if (ret) {
589 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
590 goto pixel_clk_err;
591 }
592
593 return 0;
594
595 pixel_clk_err:
596 clk_disable_unprepare(msm_host->src_clk);
597 src_clk_err:
598 clk_disable_unprepare(msm_host->esc_clk);
599 esc_clk_err:
600 clk_disable_unprepare(msm_host->byte_clk);
601 error:
602 return ret;
603 }
604
605 static int dsi_link_clk_enable(struct msm_dsi_host *msm_host)
606 {
607 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
608
609 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
610 return dsi_link_clk_enable_6g(msm_host);
611 else
612 return dsi_link_clk_enable_v2(msm_host);
613 }
614
615 static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)
616 {
617 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
618
619 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
620 clk_disable_unprepare(msm_host->esc_clk);
621 clk_disable_unprepare(msm_host->pixel_clk);
622 clk_disable_unprepare(msm_host->byte_clk);
623 } else {
624 clk_disable_unprepare(msm_host->pixel_clk);
625 clk_disable_unprepare(msm_host->src_clk);
626 clk_disable_unprepare(msm_host->esc_clk);
627 clk_disable_unprepare(msm_host->byte_clk);
628 }
629 }
630
631 static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
632 {
633 struct drm_display_mode *mode = msm_host->mode;
634 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
635 u8 lanes = msm_host->lanes;
636 u32 bpp = dsi_get_bpp(msm_host->format);
637 u32 pclk_rate;
638
639 if (!mode) {
640 pr_err("%s: mode not set\n", __func__);
641 return -EINVAL;
642 }
643
644 pclk_rate = mode->clock * 1000;
645 if (lanes > 0) {
646 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);
647 } else {
648 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
649 msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;
650 }
651
652 DBG("pclk=%d, bclk=%d", pclk_rate, msm_host->byte_clk_rate);
653
654 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
655
656 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
657 unsigned int esc_mhz, esc_div;
658 unsigned long byte_mhz;
659
660 msm_host->src_clk_rate = (pclk_rate * bpp) / 8;
661
662 /*
663 * esc clock is byte clock followed by a 4 bit divider,
664 * we need to find an escape clock frequency within the
665 * mipi DSI spec range within the maximum divider limit
666 * We iterate here between an escape clock frequencey
667 * between 20 Mhz to 5 Mhz and pick up the first one
668 * that can be supported by our divider
669 */
670
671 byte_mhz = msm_host->byte_clk_rate / 1000000;
672
673 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
674 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
675
676 /*
677 * TODO: Ideally, we shouldn't know what sort of divider
678 * is available in mmss_cc, we're just assuming that
679 * it'll always be a 4 bit divider. Need to come up with
680 * a better way here.
681 */
682 if (esc_div >= 1 && esc_div <= 16)
683 break;
684 }
685
686 if (esc_mhz < 5)
687 return -EINVAL;
688
689 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
690
691 DBG("esc=%d, src=%d", msm_host->esc_clk_rate,
692 msm_host->src_clk_rate);
693 }
694
695 return 0;
696 }
697
698 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
699 {
700 u32 intr;
701 unsigned long flags;
702
703 spin_lock_irqsave(&msm_host->intr_lock, flags);
704 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
705
706 if (enable)
707 intr |= mask;
708 else
709 intr &= ~mask;
710
711 DBG("intr=%x enable=%d", intr, enable);
712
713 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
714 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
715 }
716
717 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
718 {
719 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
720 return BURST_MODE;
721 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
722 return NON_BURST_SYNCH_PULSE;
723
724 return NON_BURST_SYNCH_EVENT;
725 }
726
727 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
728 const enum mipi_dsi_pixel_format mipi_fmt)
729 {
730 switch (mipi_fmt) {
731 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
732 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
733 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
734 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
735 default: return VID_DST_FORMAT_RGB888;
736 }
737 }
738
739 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
740 const enum mipi_dsi_pixel_format mipi_fmt)
741 {
742 switch (mipi_fmt) {
743 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
744 case MIPI_DSI_FMT_RGB666_PACKED:
745 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
746 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
747 default: return CMD_DST_FORMAT_RGB888;
748 }
749 }
750
751 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
752 struct msm_dsi_phy_shared_timings *phy_shared_timings)
753 {
754 u32 flags = msm_host->mode_flags;
755 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
756 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
757 u32 data = 0;
758
759 if (!enable) {
760 dsi_write(msm_host, REG_DSI_CTRL, 0);
761 return;
762 }
763
764 if (flags & MIPI_DSI_MODE_VIDEO) {
765 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
766 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
767 if (flags & MIPI_DSI_MODE_VIDEO_HFP)
768 data |= DSI_VID_CFG0_HFP_POWER_STOP;
769 if (flags & MIPI_DSI_MODE_VIDEO_HBP)
770 data |= DSI_VID_CFG0_HBP_POWER_STOP;
771 if (flags & MIPI_DSI_MODE_VIDEO_HSA)
772 data |= DSI_VID_CFG0_HSA_POWER_STOP;
773 /* Always set low power stop mode for BLLP
774 * to let command engine send packets
775 */
776 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
777 DSI_VID_CFG0_BLLP_POWER_STOP;
778 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
779 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
780 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
781 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
782
783 /* Do not swap RGB colors */
784 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
785 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
786 } else {
787 /* Do not swap RGB colors */
788 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
789 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
790 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
791
792 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
793 DSI_CMD_CFG1_WR_MEM_CONTINUE(
794 MIPI_DCS_WRITE_MEMORY_CONTINUE);
795 /* Always insert DCS command */
796 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
797 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
798 }
799
800 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
801 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
802 DSI_CMD_DMA_CTRL_LOW_POWER);
803
804 data = 0;
805 /* Always assume dedicated TE pin */
806 data |= DSI_TRIG_CTRL_TE;
807 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
808 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
809 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
810 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
811 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
812 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
813 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
814
815 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
816 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
817 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
818
819 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
820 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
821 phy_shared_timings->clk_pre_inc_by_2)
822 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
823 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
824
825 data = 0;
826 if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
827 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
828 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
829
830 /* allow only ack-err-status to generate interrupt */
831 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
832
833 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
834
835 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
836
837 data = DSI_CTRL_CLK_EN;
838
839 DBG("lane number=%d", msm_host->lanes);
840 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
841
842 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
843 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
844
845 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
846 dsi_write(msm_host, REG_DSI_LANE_CTRL,
847 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
848
849 data |= DSI_CTRL_ENABLE;
850
851 dsi_write(msm_host, REG_DSI_CTRL, data);
852 }
853
854 static void dsi_timing_setup(struct msm_dsi_host *msm_host)
855 {
856 struct drm_display_mode *mode = msm_host->mode;
857 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
858 u32 h_total = mode->htotal;
859 u32 v_total = mode->vtotal;
860 u32 hs_end = mode->hsync_end - mode->hsync_start;
861 u32 vs_end = mode->vsync_end - mode->vsync_start;
862 u32 ha_start = h_total - mode->hsync_start;
863 u32 ha_end = ha_start + mode->hdisplay;
864 u32 va_start = v_total - mode->vsync_start;
865 u32 va_end = va_start + mode->vdisplay;
866 u32 wc;
867
868 DBG("");
869
870 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
871 dsi_write(msm_host, REG_DSI_ACTIVE_H,
872 DSI_ACTIVE_H_START(ha_start) |
873 DSI_ACTIVE_H_END(ha_end));
874 dsi_write(msm_host, REG_DSI_ACTIVE_V,
875 DSI_ACTIVE_V_START(va_start) |
876 DSI_ACTIVE_V_END(va_end));
877 dsi_write(msm_host, REG_DSI_TOTAL,
878 DSI_TOTAL_H_TOTAL(h_total - 1) |
879 DSI_TOTAL_V_TOTAL(v_total - 1));
880
881 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
882 DSI_ACTIVE_HSYNC_START(hs_start) |
883 DSI_ACTIVE_HSYNC_END(hs_end));
884 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
885 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
886 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
887 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
888 } else { /* command mode */
889 /* image data and 1 byte write_memory_start cmd */
890 wc = mode->hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
891
892 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
893 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
894 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
895 msm_host->channel) |
896 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
897 MIPI_DSI_DCS_LONG_WRITE));
898
899 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
900 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode->hdisplay) |
901 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
902 }
903 }
904
905 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
906 {
907 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
908 wmb(); /* clocks need to be enabled before reset */
909
910 dsi_write(msm_host, REG_DSI_RESET, 1);
911 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
912 dsi_write(msm_host, REG_DSI_RESET, 0);
913 }
914
915 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
916 bool video_mode, bool enable)
917 {
918 u32 dsi_ctrl;
919
920 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
921
922 if (!enable) {
923 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
924 DSI_CTRL_CMD_MODE_EN);
925 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
926 DSI_IRQ_MASK_VIDEO_DONE, 0);
927 } else {
928 if (video_mode) {
929 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
930 } else { /* command mode */
931 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
932 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
933 }
934 dsi_ctrl |= DSI_CTRL_ENABLE;
935 }
936
937 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
938 }
939
940 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
941 {
942 u32 data;
943
944 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
945
946 if (mode == 0)
947 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
948 else
949 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
950
951 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
952 }
953
954 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
955 {
956 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
957
958 reinit_completion(&msm_host->video_comp);
959
960 wait_for_completion_timeout(&msm_host->video_comp,
961 msecs_to_jiffies(70));
962
963 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
964 }
965
966 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
967 {
968 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
969 return;
970
971 if (msm_host->power_on) {
972 dsi_wait4video_done(msm_host);
973 /* delay 4 ms to skip BLLP */
974 usleep_range(2000, 4000);
975 }
976 }
977
978 /* dsi_cmd */
979 static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
980 {
981 struct drm_device *dev = msm_host->dev;
982 struct msm_drm_private *priv = dev->dev_private;
983 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
984 int ret;
985 uint64_t iova;
986
987 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
988 msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
989 if (IS_ERR(msm_host->tx_gem_obj)) {
990 ret = PTR_ERR(msm_host->tx_gem_obj);
991 pr_err("%s: failed to allocate gem, %d\n",
992 __func__, ret);
993 msm_host->tx_gem_obj = NULL;
994 return ret;
995 }
996
997 ret = msm_gem_get_iova(msm_host->tx_gem_obj,
998 priv->kms->aspace, &iova);
999 mutex_unlock(&dev->struct_mutex);
1000 if (ret) {
1001 pr_err("%s: failed to get iova, %d\n", __func__, ret);
1002 return ret;
1003 }
1004
1005 if (iova & 0x07) {
1006 pr_err("%s: buf NOT 8 bytes aligned\n", __func__);
1007 return -EINVAL;
1008 }
1009
1010 msm_host->tx_size = msm_host->tx_gem_obj->size;
1011 } else {
1012 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1013 &msm_host->tx_buf_paddr, GFP_KERNEL);
1014 if (!msm_host->tx_buf) {
1015 ret = -ENOMEM;
1016 pr_err("%s: failed to allocate tx buf, %d\n",
1017 __func__, ret);
1018 return ret;
1019 }
1020
1021 msm_host->tx_size = size;
1022 }
1023
1024 return 0;
1025 }
1026
1027 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1028 {
1029 struct drm_device *dev = msm_host->dev;
1030
1031 if (msm_host->tx_gem_obj) {
1032 msm_gem_put_iova(msm_host->tx_gem_obj, 0);
1033 mutex_lock(&dev->struct_mutex);
1034 msm_gem_free_object(msm_host->tx_gem_obj);
1035 msm_host->tx_gem_obj = NULL;
1036 mutex_unlock(&dev->struct_mutex);
1037 }
1038
1039 if (msm_host->tx_buf)
1040 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1041 msm_host->tx_buf_paddr);
1042 }
1043
1044 /*
1045 * prepare cmd buffer to be txed
1046 */
1047 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1048 const struct mipi_dsi_msg *msg)
1049 {
1050 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1051 struct mipi_dsi_packet packet;
1052 int len;
1053 int ret;
1054 u8 *data;
1055
1056 ret = mipi_dsi_create_packet(&packet, msg);
1057 if (ret) {
1058 pr_err("%s: create packet failed, %d\n", __func__, ret);
1059 return ret;
1060 }
1061 len = (packet.size + 3) & (~0x3);
1062
1063 if (len > msm_host->tx_size) {
1064 pr_err("%s: packet size is too big\n", __func__);
1065 return -EINVAL;
1066 }
1067
1068 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1069 data = msm_gem_get_vaddr(msm_host->tx_gem_obj);
1070 if (IS_ERR(data)) {
1071 ret = PTR_ERR(data);
1072 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1073 return ret;
1074 }
1075 } else {
1076 data = msm_host->tx_buf;
1077 }
1078
1079 /* MSM specific command format in memory */
1080 data[0] = packet.header[1];
1081 data[1] = packet.header[2];
1082 data[2] = packet.header[0];
1083 data[3] = BIT(7); /* Last packet */
1084 if (mipi_dsi_packet_format_is_long(msg->type))
1085 data[3] |= BIT(6);
1086 if (msg->rx_buf && msg->rx_len)
1087 data[3] |= BIT(5);
1088
1089 /* Long packet */
1090 if (packet.payload && packet.payload_length)
1091 memcpy(data + 4, packet.payload, packet.payload_length);
1092
1093 /* Append 0xff to the end */
1094 if (packet.size < len)
1095 memset(data + packet.size, 0xff, len - packet.size);
1096
1097 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G)
1098 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1099
1100 return len;
1101 }
1102
1103 /*
1104 * dsi_short_read1_resp: 1 parameter
1105 */
1106 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1107 {
1108 u8 *data = msg->rx_buf;
1109 if (data && (msg->rx_len >= 1)) {
1110 *data = buf[1]; /* strip out dcs type */
1111 return 1;
1112 } else {
1113 pr_err("%s: read data does not match with rx_buf len %zu\n",
1114 __func__, msg->rx_len);
1115 return -EINVAL;
1116 }
1117 }
1118
1119 /*
1120 * dsi_short_read2_resp: 2 parameter
1121 */
1122 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1123 {
1124 u8 *data = msg->rx_buf;
1125 if (data && (msg->rx_len >= 2)) {
1126 data[0] = buf[1]; /* strip out dcs type */
1127 data[1] = buf[2];
1128 return 2;
1129 } else {
1130 pr_err("%s: read data does not match with rx_buf len %zu\n",
1131 __func__, msg->rx_len);
1132 return -EINVAL;
1133 }
1134 }
1135
1136 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1137 {
1138 /* strip out 4 byte dcs header */
1139 if (msg->rx_buf && msg->rx_len)
1140 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1141
1142 return msg->rx_len;
1143 }
1144
1145 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1146 {
1147 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1148 struct drm_device *dev = msm_host->dev;
1149 struct msm_drm_private *priv = dev->dev_private;
1150 int ret;
1151 uint64_t dma_base;
1152 bool triggered;
1153
1154 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
1155 ret = msm_gem_get_iova(msm_host->tx_gem_obj,
1156 priv->kms->aspace, &dma_base);
1157 if (ret) {
1158 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1159 return ret;
1160 }
1161 } else {
1162 dma_base = msm_host->tx_buf_paddr;
1163 }
1164
1165 reinit_completion(&msm_host->dma_comp);
1166
1167 dsi_wait4video_eng_busy(msm_host);
1168
1169 triggered = msm_dsi_manager_cmd_xfer_trigger(
1170 msm_host->id, dma_base, len);
1171 if (triggered) {
1172 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1173 msecs_to_jiffies(200));
1174 DBG("ret=%d", ret);
1175 if (ret == 0)
1176 ret = -ETIMEDOUT;
1177 else
1178 ret = len;
1179 } else
1180 ret = len;
1181
1182 return ret;
1183 }
1184
1185 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1186 u8 *buf, int rx_byte, int pkt_size)
1187 {
1188 u32 *lp, *temp, data;
1189 int i, j = 0, cnt;
1190 u32 read_cnt;
1191 u8 reg[16];
1192 int repeated_bytes = 0;
1193 int buf_offset = buf - msm_host->rx_buf;
1194
1195 lp = (u32 *)buf;
1196 temp = (u32 *)reg;
1197 cnt = (rx_byte + 3) >> 2;
1198 if (cnt > 4)
1199 cnt = 4; /* 4 x 32 bits registers only */
1200
1201 if (rx_byte == 4)
1202 read_cnt = 4;
1203 else
1204 read_cnt = pkt_size + 6;
1205
1206 /*
1207 * In case of multiple reads from the panel, after the first read, there
1208 * is possibility that there are some bytes in the payload repeating in
1209 * the RDBK_DATA registers. Since we read all the parameters from the
1210 * panel right from the first byte for every pass. We need to skip the
1211 * repeating bytes and then append the new parameters to the rx buffer.
1212 */
1213 if (read_cnt > 16) {
1214 int bytes_shifted;
1215 /* Any data more than 16 bytes will be shifted out.
1216 * The temp read buffer should already contain these bytes.
1217 * The remaining bytes in read buffer are the repeated bytes.
1218 */
1219 bytes_shifted = read_cnt - 16;
1220 repeated_bytes = buf_offset - bytes_shifted;
1221 }
1222
1223 for (i = cnt - 1; i >= 0; i--) {
1224 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1225 *temp++ = ntohl(data); /* to host byte order */
1226 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1227 }
1228
1229 for (i = repeated_bytes; i < 16; i++)
1230 buf[j++] = reg[i];
1231
1232 return j;
1233 }
1234
1235 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1236 const struct mipi_dsi_msg *msg)
1237 {
1238 int len, ret;
1239 int bllp_len = msm_host->mode->hdisplay *
1240 dsi_get_bpp(msm_host->format) / 8;
1241
1242 len = dsi_cmd_dma_add(msm_host, msg);
1243 if (!len) {
1244 pr_err("%s: failed to add cmd type = 0x%x\n",
1245 __func__, msg->type);
1246 return -EINVAL;
1247 }
1248
1249 /* for video mode, do not send cmds more than
1250 * one pixel line, since it only transmit it
1251 * during BLLP.
1252 */
1253 /* TODO: if the command is sent in LP mode, the bit rate is only
1254 * half of esc clk rate. In this case, if the video is already
1255 * actively streaming, we need to check more carefully if the
1256 * command can be fit into one BLLP.
1257 */
1258 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1259 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1260 __func__, len);
1261 return -EINVAL;
1262 }
1263
1264 ret = dsi_cmd_dma_tx(msm_host, len);
1265 if (ret < len) {
1266 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1267 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len);
1268 return -ECOMM;
1269 }
1270
1271 return len;
1272 }
1273
1274 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host)
1275 {
1276 u32 data0, data1;
1277
1278 data0 = dsi_read(msm_host, REG_DSI_CTRL);
1279 data1 = data0;
1280 data1 &= ~DSI_CTRL_ENABLE;
1281 dsi_write(msm_host, REG_DSI_CTRL, data1);
1282 /*
1283 * dsi controller need to be disabled before
1284 * clocks turned on
1285 */
1286 wmb();
1287
1288 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1289 wmb(); /* make sure clocks enabled */
1290
1291 /* dsi controller can only be reset while clocks are running */
1292 dsi_write(msm_host, REG_DSI_RESET, 1);
1293 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1294 dsi_write(msm_host, REG_DSI_RESET, 0);
1295 wmb(); /* controller out of reset */
1296 dsi_write(msm_host, REG_DSI_CTRL, data0);
1297 wmb(); /* make sure dsi controller enabled again */
1298 }
1299
1300 static void dsi_hpd_worker(struct work_struct *work)
1301 {
1302 struct msm_dsi_host *msm_host =
1303 container_of(work, struct msm_dsi_host, hpd_work);
1304
1305 drm_helper_hpd_irq_event(msm_host->dev);
1306 }
1307
1308 static void dsi_err_worker(struct work_struct *work)
1309 {
1310 struct msm_dsi_host *msm_host =
1311 container_of(work, struct msm_dsi_host, err_work);
1312 u32 status = msm_host->err_work_state;
1313
1314 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1315 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1316 dsi_sw_reset_restore(msm_host);
1317
1318 /* It is safe to clear here because error irq is disabled. */
1319 msm_host->err_work_state = 0;
1320
1321 /* enable dsi error interrupt */
1322 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1323 }
1324
1325 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1326 {
1327 u32 status;
1328
1329 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1330
1331 if (status) {
1332 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1333 /* Writing of an extra 0 needed to clear error bits */
1334 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1335 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1336 }
1337 }
1338
1339 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1340 {
1341 u32 status;
1342
1343 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1344
1345 if (status) {
1346 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1347 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1348 }
1349 }
1350
1351 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1352 {
1353 u32 status;
1354
1355 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1356
1357 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1358 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1359 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1360 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1361 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1362 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1363 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1364 }
1365 }
1366
1367 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1368 {
1369 u32 status;
1370
1371 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1372
1373 /* fifo underflow, overflow */
1374 if (status) {
1375 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1376 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1377 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1378 msm_host->err_work_state |=
1379 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1380 }
1381 }
1382
1383 static void dsi_status(struct msm_dsi_host *msm_host)
1384 {
1385 u32 status;
1386
1387 status = dsi_read(msm_host, REG_DSI_STATUS0);
1388
1389 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1390 dsi_write(msm_host, REG_DSI_STATUS0, status);
1391 msm_host->err_work_state |=
1392 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1393 }
1394 }
1395
1396 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1397 {
1398 u32 status;
1399
1400 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1401
1402 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1403 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1404 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1405 }
1406 }
1407
1408 static void dsi_error(struct msm_dsi_host *msm_host)
1409 {
1410 /* disable dsi error interrupt */
1411 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1412
1413 dsi_clk_status(msm_host);
1414 dsi_fifo_status(msm_host);
1415 dsi_ack_err_status(msm_host);
1416 dsi_timeout_status(msm_host);
1417 dsi_status(msm_host);
1418 dsi_dln0_phy_err(msm_host);
1419
1420 queue_work(msm_host->workqueue, &msm_host->err_work);
1421 }
1422
1423 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1424 {
1425 struct msm_dsi_host *msm_host = ptr;
1426 u32 isr;
1427 unsigned long flags;
1428
1429 if (!msm_host->ctrl_base)
1430 return IRQ_HANDLED;
1431
1432 spin_lock_irqsave(&msm_host->intr_lock, flags);
1433 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1434 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1435 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1436
1437 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1438
1439 if (isr & DSI_IRQ_ERROR)
1440 dsi_error(msm_host);
1441
1442 if (isr & DSI_IRQ_VIDEO_DONE)
1443 complete(&msm_host->video_comp);
1444
1445 if (isr & DSI_IRQ_CMD_DMA_DONE)
1446 complete(&msm_host->dma_comp);
1447
1448 return IRQ_HANDLED;
1449 }
1450
1451 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1452 struct device *panel_device)
1453 {
1454 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1455 "disp-enable",
1456 GPIOD_OUT_LOW);
1457 if (IS_ERR(msm_host->disp_en_gpio)) {
1458 DBG("cannot get disp-enable-gpios %ld",
1459 PTR_ERR(msm_host->disp_en_gpio));
1460 return PTR_ERR(msm_host->disp_en_gpio);
1461 }
1462
1463 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1464 GPIOD_IN);
1465 if (IS_ERR(msm_host->te_gpio)) {
1466 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1467 return PTR_ERR(msm_host->te_gpio);
1468 }
1469
1470 return 0;
1471 }
1472
1473 static int dsi_host_attach(struct mipi_dsi_host *host,
1474 struct mipi_dsi_device *dsi)
1475 {
1476 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1477 int ret;
1478
1479 if (dsi->lanes > msm_host->num_data_lanes)
1480 return -EINVAL;
1481
1482 msm_host->channel = dsi->channel;
1483 msm_host->lanes = dsi->lanes;
1484 msm_host->format = dsi->format;
1485 msm_host->mode_flags = dsi->mode_flags;
1486
1487 msm_dsi_manager_attach_dsi_device(msm_host->id, dsi->mode_flags);
1488
1489 /* Some gpios defined in panel DT need to be controlled by host */
1490 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1491 if (ret)
1492 return ret;
1493
1494 DBG("id=%d", msm_host->id);
1495 if (msm_host->dev)
1496 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1497
1498 return 0;
1499 }
1500
1501 static int dsi_host_detach(struct mipi_dsi_host *host,
1502 struct mipi_dsi_device *dsi)
1503 {
1504 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1505
1506 msm_host->device_node = NULL;
1507
1508 DBG("id=%d", msm_host->id);
1509 if (msm_host->dev)
1510 queue_work(msm_host->workqueue, &msm_host->hpd_work);
1511
1512 return 0;
1513 }
1514
1515 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1516 const struct mipi_dsi_msg *msg)
1517 {
1518 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1519 int ret;
1520
1521 if (!msg || !msm_host->power_on)
1522 return -EINVAL;
1523
1524 mutex_lock(&msm_host->cmd_mutex);
1525 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1526 mutex_unlock(&msm_host->cmd_mutex);
1527
1528 return ret;
1529 }
1530
1531 static struct mipi_dsi_host_ops dsi_host_ops = {
1532 .attach = dsi_host_attach,
1533 .detach = dsi_host_detach,
1534 .transfer = dsi_host_transfer,
1535 };
1536
1537 /*
1538 * List of supported physical to logical lane mappings.
1539 * For example, the 2nd entry represents the following mapping:
1540 *
1541 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1542 */
1543 static const int supported_data_lane_swaps[][4] = {
1544 { 0, 1, 2, 3 },
1545 { 3, 0, 1, 2 },
1546 { 2, 3, 0, 1 },
1547 { 1, 2, 3, 0 },
1548 { 0, 3, 2, 1 },
1549 { 1, 0, 3, 2 },
1550 { 2, 1, 0, 3 },
1551 { 3, 2, 1, 0 },
1552 };
1553
1554 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1555 struct device_node *ep)
1556 {
1557 struct device *dev = &msm_host->pdev->dev;
1558 struct property *prop;
1559 u32 lane_map[4];
1560 int ret, i, len, num_lanes;
1561
1562 prop = of_find_property(ep, "data-lanes", &len);
1563 if (!prop) {
1564 dev_dbg(dev,
1565 "failed to find data lane mapping, using default\n");
1566 return 0;
1567 }
1568
1569 num_lanes = len / sizeof(u32);
1570
1571 if (num_lanes < 1 || num_lanes > 4) {
1572 dev_err(dev, "bad number of data lanes\n");
1573 return -EINVAL;
1574 }
1575
1576 msm_host->num_data_lanes = num_lanes;
1577
1578 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1579 num_lanes);
1580 if (ret) {
1581 dev_err(dev, "failed to read lane data\n");
1582 return ret;
1583 }
1584
1585 /*
1586 * compare DT specified physical-logical lane mappings with the ones
1587 * supported by hardware
1588 */
1589 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1590 const int *swap = supported_data_lane_swaps[i];
1591 int j;
1592
1593 /*
1594 * the data-lanes array we get from DT has a logical->physical
1595 * mapping. The "data lane swap" register field represents
1596 * supported configurations in a physical->logical mapping.
1597 * Translate the DT mapping to what we understand and find a
1598 * configuration that works.
1599 */
1600 for (j = 0; j < num_lanes; j++) {
1601 if (lane_map[j] < 0 || lane_map[j] > 3)
1602 dev_err(dev, "bad physical lane entry %u\n",
1603 lane_map[j]);
1604
1605 if (swap[lane_map[j]] != j)
1606 break;
1607 }
1608
1609 if (j == num_lanes) {
1610 msm_host->dlane_swap = i;
1611 return 0;
1612 }
1613 }
1614
1615 return -EINVAL;
1616 }
1617
1618 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1619 {
1620 struct device *dev = &msm_host->pdev->dev;
1621 struct device_node *np = dev->of_node;
1622 struct device_node *endpoint, *device_node;
1623 int ret = 0;
1624
1625 /*
1626 * Get the endpoint of the output port of the DSI host. In our case,
1627 * this is mapped to port number with reg = 1. Don't return an error if
1628 * the remote endpoint isn't defined. It's possible that there is
1629 * nothing connected to the dsi output.
1630 */
1631 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1632 if (!endpoint) {
1633 dev_dbg(dev, "%s: no endpoint\n", __func__);
1634 return 0;
1635 }
1636
1637 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1638 if (ret) {
1639 dev_err(dev, "%s: invalid lane configuration %d\n",
1640 __func__, ret);
1641 goto err;
1642 }
1643
1644 /* Get panel node from the output port's endpoint data */
1645 device_node = of_graph_get_remote_node(np, 1, 0);
1646 if (!device_node) {
1647 dev_dbg(dev, "%s: no valid device\n", __func__);
1648 goto err;
1649 }
1650
1651 msm_host->device_node = device_node;
1652
1653 if (of_property_read_bool(np, "syscon-sfpb")) {
1654 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1655 "syscon-sfpb");
1656 if (IS_ERR(msm_host->sfpb)) {
1657 dev_err(dev, "%s: failed to get sfpb regmap\n",
1658 __func__);
1659 ret = PTR_ERR(msm_host->sfpb);
1660 }
1661 }
1662
1663 of_node_put(device_node);
1664
1665 err:
1666 of_node_put(endpoint);
1667
1668 return ret;
1669 }
1670
1671 static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1672 {
1673 struct platform_device *pdev = msm_host->pdev;
1674 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1675 struct resource *res;
1676 int i;
1677
1678 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1679 if (!res)
1680 return -EINVAL;
1681
1682 for (i = 0; i < cfg->num_dsi; i++) {
1683 if (cfg->io_start[i] == res->start)
1684 return i;
1685 }
1686
1687 return -EINVAL;
1688 }
1689
1690 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1691 {
1692 struct msm_dsi_host *msm_host = NULL;
1693 struct platform_device *pdev = msm_dsi->pdev;
1694 int ret;
1695
1696 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1697 if (!msm_host) {
1698 pr_err("%s: FAILED: cannot alloc dsi host\n",
1699 __func__);
1700 ret = -ENOMEM;
1701 goto fail;
1702 }
1703
1704 msm_host->pdev = pdev;
1705 msm_dsi->host = &msm_host->base;
1706
1707 ret = dsi_host_parse_dt(msm_host);
1708 if (ret) {
1709 pr_err("%s: failed to parse dt\n", __func__);
1710 goto fail;
1711 }
1712
1713 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL");
1714 if (IS_ERR(msm_host->ctrl_base)) {
1715 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1716 ret = PTR_ERR(msm_host->ctrl_base);
1717 goto fail;
1718 }
1719
1720 pm_runtime_enable(&pdev->dev);
1721
1722 msm_host->cfg_hnd = dsi_get_config(msm_host);
1723 if (!msm_host->cfg_hnd) {
1724 ret = -EINVAL;
1725 pr_err("%s: get config failed\n", __func__);
1726 goto fail;
1727 }
1728
1729 msm_host->id = dsi_host_get_id(msm_host);
1730 if (msm_host->id < 0) {
1731 ret = msm_host->id;
1732 pr_err("%s: unable to identify DSI host index\n", __func__);
1733 goto fail;
1734 }
1735
1736 /* fixup base address by io offset */
1737 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset;
1738
1739 ret = dsi_regulator_init(msm_host);
1740 if (ret) {
1741 pr_err("%s: regulator init failed\n", __func__);
1742 goto fail;
1743 }
1744
1745 ret = dsi_clk_init(msm_host);
1746 if (ret) {
1747 pr_err("%s: unable to initialize dsi clks\n", __func__);
1748 goto fail;
1749 }
1750
1751 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1752 if (!msm_host->rx_buf) {
1753 ret = -ENOMEM;
1754 pr_err("%s: alloc rx temp buf failed\n", __func__);
1755 goto fail;
1756 }
1757
1758 init_completion(&msm_host->dma_comp);
1759 init_completion(&msm_host->video_comp);
1760 mutex_init(&msm_host->dev_mutex);
1761 mutex_init(&msm_host->cmd_mutex);
1762 spin_lock_init(&msm_host->intr_lock);
1763
1764 /* setup workqueue */
1765 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1766 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1767 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker);
1768
1769 msm_dsi->id = msm_host->id;
1770
1771 DBG("Dsi Host %d initialized", msm_host->id);
1772 return 0;
1773
1774 fail:
1775 return ret;
1776 }
1777
1778 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1779 {
1780 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1781
1782 DBG("");
1783 dsi_tx_buf_free(msm_host);
1784 if (msm_host->workqueue) {
1785 flush_workqueue(msm_host->workqueue);
1786 destroy_workqueue(msm_host->workqueue);
1787 msm_host->workqueue = NULL;
1788 }
1789
1790 mutex_destroy(&msm_host->cmd_mutex);
1791 mutex_destroy(&msm_host->dev_mutex);
1792
1793 pm_runtime_disable(&msm_host->pdev->dev);
1794 }
1795
1796 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1797 struct drm_device *dev)
1798 {
1799 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1800 struct platform_device *pdev = msm_host->pdev;
1801 int ret;
1802
1803 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1804 if (msm_host->irq < 0) {
1805 ret = msm_host->irq;
1806 dev_err(dev->dev, "failed to get irq: %d\n", ret);
1807 return ret;
1808 }
1809
1810 ret = devm_request_irq(&pdev->dev, msm_host->irq,
1811 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1812 "dsi_isr", msm_host);
1813 if (ret < 0) {
1814 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1815 msm_host->irq, ret);
1816 return ret;
1817 }
1818
1819 msm_host->dev = dev;
1820 ret = dsi_tx_buf_alloc(msm_host, SZ_4K);
1821 if (ret) {
1822 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1823 return ret;
1824 }
1825
1826 return 0;
1827 }
1828
1829 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer)
1830 {
1831 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1832 int ret;
1833
1834 /* Register mipi dsi host */
1835 if (!msm_host->registered) {
1836 host->dev = &msm_host->pdev->dev;
1837 host->ops = &dsi_host_ops;
1838 ret = mipi_dsi_host_register(host);
1839 if (ret)
1840 return ret;
1841
1842 msm_host->registered = true;
1843
1844 /* If the panel driver has not been probed after host register,
1845 * we should defer the host's probe.
1846 * It makes sure panel is connected when fbcon detects
1847 * connector status and gets the proper display mode to
1848 * create framebuffer.
1849 * Don't try to defer if there is nothing connected to the dsi
1850 * output
1851 */
1852 if (check_defer && msm_host->device_node) {
1853 if (!of_drm_find_panel(msm_host->device_node))
1854 if (!of_drm_find_bridge(msm_host->device_node))
1855 return -EPROBE_DEFER;
1856 }
1857 }
1858
1859 return 0;
1860 }
1861
1862 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1863 {
1864 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1865
1866 if (msm_host->registered) {
1867 mipi_dsi_host_unregister(host);
1868 host->dev = NULL;
1869 host->ops = NULL;
1870 msm_host->registered = false;
1871 }
1872 }
1873
1874 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1875 const struct mipi_dsi_msg *msg)
1876 {
1877 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1878
1879 /* TODO: make sure dsi_cmd_mdp is idle.
1880 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1881 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1882 * How to handle the old versions? Wait for mdp cmd done?
1883 */
1884
1885 /*
1886 * mdss interrupt is generated in mdp core clock domain
1887 * mdp clock need to be enabled to receive dsi interrupt
1888 */
1889 pm_runtime_get_sync(&msm_host->pdev->dev);
1890 dsi_link_clk_enable(msm_host);
1891
1892 /* TODO: vote for bus bandwidth */
1893
1894 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1895 dsi_set_tx_power_mode(0, msm_host);
1896
1897 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
1898 dsi_write(msm_host, REG_DSI_CTRL,
1899 msm_host->dma_cmd_ctrl_restore |
1900 DSI_CTRL_CMD_MODE_EN |
1901 DSI_CTRL_ENABLE);
1902 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
1903
1904 return 0;
1905 }
1906
1907 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
1908 const struct mipi_dsi_msg *msg)
1909 {
1910 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1911
1912 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
1913 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
1914
1915 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
1916 dsi_set_tx_power_mode(1, msm_host);
1917
1918 /* TODO: unvote for bus bandwidth */
1919
1920 dsi_link_clk_disable(msm_host);
1921 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
1922 }
1923
1924 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
1925 const struct mipi_dsi_msg *msg)
1926 {
1927 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1928
1929 return dsi_cmds2buf_tx(msm_host, msg);
1930 }
1931
1932 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
1933 const struct mipi_dsi_msg *msg)
1934 {
1935 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1936 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1937 int data_byte, rx_byte, dlen, end;
1938 int short_response, diff, pkt_size, ret = 0;
1939 char cmd;
1940 int rlen = msg->rx_len;
1941 u8 *buf;
1942
1943 if (rlen <= 2) {
1944 short_response = 1;
1945 pkt_size = rlen;
1946 rx_byte = 4;
1947 } else {
1948 short_response = 0;
1949 data_byte = 10; /* first read */
1950 if (rlen < data_byte)
1951 pkt_size = rlen;
1952 else
1953 pkt_size = data_byte;
1954 rx_byte = data_byte + 6; /* 4 header + 2 crc */
1955 }
1956
1957 buf = msm_host->rx_buf;
1958 end = 0;
1959 while (!end) {
1960 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
1961 struct mipi_dsi_msg max_pkt_size_msg = {
1962 .channel = msg->channel,
1963 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
1964 .tx_len = 2,
1965 .tx_buf = tx,
1966 };
1967
1968 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1969 rlen, pkt_size, rx_byte);
1970
1971 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
1972 if (ret < 2) {
1973 pr_err("%s: Set max pkt size failed, %d\n",
1974 __func__, ret);
1975 return -EINVAL;
1976 }
1977
1978 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
1979 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
1980 /* Clear the RDBK_DATA registers */
1981 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
1982 DSI_RDBK_DATA_CTRL_CLR);
1983 wmb(); /* make sure the RDBK registers are cleared */
1984 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
1985 wmb(); /* release cleared status before transfer */
1986 }
1987
1988 ret = dsi_cmds2buf_tx(msm_host, msg);
1989 if (ret < msg->tx_len) {
1990 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
1991 return ret;
1992 }
1993
1994 /*
1995 * once cmd_dma_done interrupt received,
1996 * return data from client is ready and stored
1997 * at RDBK_DATA register already
1998 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1999 * after that dcs header lost during shift into registers
2000 */
2001 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2002
2003 if (dlen <= 0)
2004 return 0;
2005
2006 if (short_response)
2007 break;
2008
2009 if (rlen <= data_byte) {
2010 diff = data_byte - rlen;
2011 end = 1;
2012 } else {
2013 diff = 0;
2014 rlen -= data_byte;
2015 }
2016
2017 if (!end) {
2018 dlen -= 2; /* 2 crc */
2019 dlen -= diff;
2020 buf += dlen; /* next start position */
2021 data_byte = 14; /* NOT first read */
2022 if (rlen < data_byte)
2023 pkt_size += rlen;
2024 else
2025 pkt_size += data_byte;
2026 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2027 }
2028 }
2029
2030 /*
2031 * For single Long read, if the requested rlen < 10,
2032 * we need to shift the start position of rx
2033 * data buffer to skip the bytes which are not
2034 * updated.
2035 */
2036 if (pkt_size < 10 && !short_response)
2037 buf = msm_host->rx_buf + (10 - rlen);
2038 else
2039 buf = msm_host->rx_buf;
2040
2041 cmd = buf[0];
2042 switch (cmd) {
2043 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2044 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2045 ret = 0;
2046 break;
2047 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2048 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2049 ret = dsi_short_read1_resp(buf, msg);
2050 break;
2051 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2052 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2053 ret = dsi_short_read2_resp(buf, msg);
2054 break;
2055 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2056 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2057 ret = dsi_long_read_resp(buf, msg);
2058 break;
2059 default:
2060 pr_warn("%s:Invalid response cmd\n", __func__);
2061 ret = 0;
2062 }
2063
2064 return ret;
2065 }
2066
2067 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2068 u32 len)
2069 {
2070 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2071
2072 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2073 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2074 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2075
2076 /* Make sure trigger happens */
2077 wmb();
2078 }
2079
2080 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
2081 struct msm_dsi_pll *src_pll)
2082 {
2083 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2084 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2085 struct clk *byte_clk_provider, *pixel_clk_provider;
2086 int ret;
2087
2088 ret = msm_dsi_pll_get_clk_provider(src_pll,
2089 &byte_clk_provider, &pixel_clk_provider);
2090 if (ret) {
2091 pr_info("%s: can't get provider from pll, don't set parent\n",
2092 __func__);
2093 return 0;
2094 }
2095
2096 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider);
2097 if (ret) {
2098 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2099 __func__, ret);
2100 goto exit;
2101 }
2102
2103 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider);
2104 if (ret) {
2105 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2106 __func__, ret);
2107 goto exit;
2108 }
2109
2110 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_V2) {
2111 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider);
2112 if (ret) {
2113 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2114 __func__, ret);
2115 goto exit;
2116 }
2117
2118 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider);
2119 if (ret) {
2120 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2121 __func__, ret);
2122 goto exit;
2123 }
2124 }
2125
2126 exit:
2127 return ret;
2128 }
2129
2130 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2131 {
2132 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2133
2134 DBG("");
2135 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2136 /* Make sure fully reset */
2137 wmb();
2138 udelay(1000);
2139 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2140 udelay(100);
2141 }
2142
2143 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2144 struct msm_dsi_phy_clk_request *clk_req)
2145 {
2146 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2147 int ret;
2148
2149 ret = dsi_calc_clk_rate(msm_host);
2150 if (ret) {
2151 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2152 return;
2153 }
2154
2155 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2156 clk_req->escclk_rate = msm_host->esc_clk_rate;
2157 }
2158
2159 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2160 {
2161 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2162
2163 dsi_op_mode_config(msm_host,
2164 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2165
2166 /* TODO: clock should be turned off for command mode,
2167 * and only turned on before MDP START.
2168 * This part of code should be enabled once mdp driver support it.
2169 */
2170 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2171 * dsi_link_clk_disable(msm_host);
2172 * pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2173 * }
2174 */
2175
2176 return 0;
2177 }
2178
2179 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2180 {
2181 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2182
2183 dsi_op_mode_config(msm_host,
2184 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2185
2186 /* Since we have disabled INTF, the video engine won't stop so that
2187 * the cmd engine will be blocked.
2188 * Reset to disable video engine so that we can send off cmd.
2189 */
2190 dsi_sw_reset(msm_host);
2191
2192 return 0;
2193 }
2194
2195 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2196 {
2197 enum sfpb_ahb_arb_master_port_en en;
2198
2199 if (!msm_host->sfpb)
2200 return;
2201
2202 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2203
2204 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2205 SFPB_GPREG_MASTER_PORT_EN__MASK,
2206 SFPB_GPREG_MASTER_PORT_EN(en));
2207 }
2208
2209 int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2210 struct msm_dsi_phy_shared_timings *phy_shared_timings)
2211 {
2212 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2213 int ret = 0;
2214
2215 mutex_lock(&msm_host->dev_mutex);
2216 if (msm_host->power_on) {
2217 DBG("dsi host already on");
2218 goto unlock_ret;
2219 }
2220
2221 msm_dsi_sfpb_config(msm_host, true);
2222
2223 ret = dsi_host_regulator_enable(msm_host);
2224 if (ret) {
2225 pr_err("%s:Failed to enable vregs.ret=%d\n",
2226 __func__, ret);
2227 goto unlock_ret;
2228 }
2229
2230 pm_runtime_get_sync(&msm_host->pdev->dev);
2231 ret = dsi_link_clk_enable(msm_host);
2232 if (ret) {
2233 pr_err("%s: failed to enable link clocks. ret=%d\n",
2234 __func__, ret);
2235 goto fail_disable_reg;
2236 }
2237
2238 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2239 if (ret) {
2240 pr_err("%s: failed to set pinctrl default state, %d\n",
2241 __func__, ret);
2242 goto fail_disable_clk;
2243 }
2244
2245 dsi_timing_setup(msm_host);
2246 dsi_sw_reset(msm_host);
2247 dsi_ctrl_config(msm_host, true, phy_shared_timings);
2248
2249 if (msm_host->disp_en_gpio)
2250 gpiod_set_value(msm_host->disp_en_gpio, 1);
2251
2252 msm_host->power_on = true;
2253 mutex_unlock(&msm_host->dev_mutex);
2254
2255 return 0;
2256
2257 fail_disable_clk:
2258 dsi_link_clk_disable(msm_host);
2259 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2260 fail_disable_reg:
2261 dsi_host_regulator_disable(msm_host);
2262 unlock_ret:
2263 mutex_unlock(&msm_host->dev_mutex);
2264 return ret;
2265 }
2266
2267 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2268 {
2269 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2270
2271 mutex_lock(&msm_host->dev_mutex);
2272 if (!msm_host->power_on) {
2273 DBG("dsi host already off");
2274 goto unlock_ret;
2275 }
2276
2277 dsi_ctrl_config(msm_host, false, NULL);
2278
2279 if (msm_host->disp_en_gpio)
2280 gpiod_set_value(msm_host->disp_en_gpio, 0);
2281
2282 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2283
2284 dsi_link_clk_disable(msm_host);
2285 pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2286
2287 dsi_host_regulator_disable(msm_host);
2288
2289 msm_dsi_sfpb_config(msm_host, false);
2290
2291 DBG("-");
2292
2293 msm_host->power_on = false;
2294
2295 unlock_ret:
2296 mutex_unlock(&msm_host->dev_mutex);
2297 return 0;
2298 }
2299
2300 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2301 struct drm_display_mode *mode)
2302 {
2303 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2304
2305 if (msm_host->mode) {
2306 drm_mode_destroy(msm_host->dev, msm_host->mode);
2307 msm_host->mode = NULL;
2308 }
2309
2310 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2311 if (!msm_host->mode) {
2312 pr_err("%s: cannot duplicate mode\n", __func__);
2313 return -ENOMEM;
2314 }
2315
2316 return 0;
2317 }
2318
2319 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host,
2320 unsigned long *panel_flags)
2321 {
2322 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2323 struct drm_panel *panel;
2324
2325 panel = of_drm_find_panel(msm_host->device_node);
2326 if (panel_flags)
2327 *panel_flags = msm_host->mode_flags;
2328
2329 return panel;
2330 }
2331
2332 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host)
2333 {
2334 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2335
2336 return of_drm_find_bridge(msm_host->device_node);
2337 }
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