2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/interrupt.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/of_graph.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/spinlock.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/regmap.h>
29 #include <video/mipi_display.h>
37 static int dsi_get_version(const void __iomem
*base
, u32
*major
, u32
*minor
)
45 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
46 * makes all other registers 4-byte shifted down.
48 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
49 * older, we read the DSI_VERSION register without any shift(offset
50 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
51 * the case of DSI6G, this has to be zero (the offset points to a
52 * scratch register which we never touch)
55 ver
= msm_readl(base
+ REG_DSI_VERSION
);
57 /* older dsi host, there is no register shift */
58 ver
= FIELD(ver
, DSI_VERSION_MAJOR
);
59 if (ver
<= MSM_DSI_VER_MAJOR_V2
) {
69 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
70 * registers are shifted down, read DSI_VERSION again with
73 ver
= msm_readl(base
+ DSI_6G_REG_SHIFT
+ REG_DSI_VERSION
);
74 ver
= FIELD(ver
, DSI_VERSION_MAJOR
);
75 if (ver
== MSM_DSI_VER_MAJOR_6G
) {
78 *minor
= msm_readl(base
+ REG_DSI_6G_HW_VERSION
);
86 #define DSI_ERR_STATE_ACK 0x0000
87 #define DSI_ERR_STATE_TIMEOUT 0x0001
88 #define DSI_ERR_STATE_DLN0_PHY 0x0002
89 #define DSI_ERR_STATE_FIFO 0x0004
90 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
91 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
92 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
94 #define DSI_CLK_CTRL_ENABLE_CLKS \
95 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
96 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
97 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
98 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
100 struct msm_dsi_host
{
101 struct mipi_dsi_host base
;
103 struct platform_device
*pdev
;
104 struct drm_device
*dev
;
108 void __iomem
*ctrl_base
;
109 struct regulator_bulk_data supplies
[DSI_DEV_REGULATOR_MAX
];
111 struct clk
*bus_clks
[DSI_BUS_CLK_MAX
];
113 struct clk
*byte_clk
;
115 struct clk
*pixel_clk
;
116 struct clk
*byte_clk_src
;
117 struct clk
*pixel_clk_src
;
122 /* DSI v2 specific clocks */
124 struct clk
*esc_clk_src
;
125 struct clk
*dsi_clk_src
;
129 struct gpio_desc
*disp_en_gpio
;
130 struct gpio_desc
*te_gpio
;
132 const struct msm_dsi_cfg_handler
*cfg_hnd
;
134 struct completion dma_comp
;
135 struct completion video_comp
;
136 struct mutex dev_mutex
;
137 struct mutex cmd_mutex
;
138 spinlock_t intr_lock
; /* Protect interrupt ctrl register */
141 struct work_struct err_work
;
142 struct work_struct hpd_work
;
143 struct workqueue_struct
*workqueue
;
145 /* DSI 6G TX buffer*/
146 struct drm_gem_object
*tx_gem_obj
;
148 /* DSI v2 TX buffer */
150 dma_addr_t tx_buf_paddr
;
158 struct drm_display_mode
*mode
;
160 /* connected device info */
161 struct device_node
*device_node
;
162 unsigned int channel
;
164 enum mipi_dsi_pixel_format format
;
165 unsigned long mode_flags
;
167 /* lane data parsed via DT */
171 u32 dma_cmd_ctrl_restore
;
178 static u32
dsi_get_bpp(const enum mipi_dsi_pixel_format fmt
)
181 case MIPI_DSI_FMT_RGB565
: return 16;
182 case MIPI_DSI_FMT_RGB666_PACKED
: return 18;
183 case MIPI_DSI_FMT_RGB666
:
184 case MIPI_DSI_FMT_RGB888
:
189 static inline u32
dsi_read(struct msm_dsi_host
*msm_host
, u32 reg
)
191 return msm_readl(msm_host
->ctrl_base
+ reg
);
193 static inline void dsi_write(struct msm_dsi_host
*msm_host
, u32 reg
, u32 data
)
195 msm_writel(data
, msm_host
->ctrl_base
+ reg
);
198 static int dsi_host_regulator_enable(struct msm_dsi_host
*msm_host
);
199 static void dsi_host_regulator_disable(struct msm_dsi_host
*msm_host
);
201 static const struct msm_dsi_cfg_handler
*dsi_get_config(
202 struct msm_dsi_host
*msm_host
)
204 const struct msm_dsi_cfg_handler
*cfg_hnd
= NULL
;
205 struct device
*dev
= &msm_host
->pdev
->dev
;
206 struct regulator
*gdsc_reg
;
209 u32 major
= 0, minor
= 0;
211 gdsc_reg
= regulator_get(dev
, "gdsc");
212 if (IS_ERR(gdsc_reg
)) {
213 pr_err("%s: cannot get gdsc\n", __func__
);
217 ahb_clk
= clk_get(dev
, "iface_clk");
218 if (IS_ERR(ahb_clk
)) {
219 pr_err("%s: cannot get interface clock\n", __func__
);
223 pm_runtime_get_sync(dev
);
225 ret
= regulator_enable(gdsc_reg
);
227 pr_err("%s: unable to enable gdsc\n", __func__
);
231 ret
= clk_prepare_enable(ahb_clk
);
233 pr_err("%s: unable to enable ahb_clk\n", __func__
);
237 ret
= dsi_get_version(msm_host
->ctrl_base
, &major
, &minor
);
239 pr_err("%s: Invalid version\n", __func__
);
243 cfg_hnd
= msm_dsi_cfg_get(major
, minor
);
245 DBG("%s: Version %x:%x\n", __func__
, major
, minor
);
248 clk_disable_unprepare(ahb_clk
);
250 regulator_disable(gdsc_reg
);
251 pm_runtime_put_autosuspend(dev
);
255 regulator_put(gdsc_reg
);
260 static inline struct msm_dsi_host
*to_msm_dsi_host(struct mipi_dsi_host
*host
)
262 return container_of(host
, struct msm_dsi_host
, base
);
265 static void dsi_host_regulator_disable(struct msm_dsi_host
*msm_host
)
267 struct regulator_bulk_data
*s
= msm_host
->supplies
;
268 const struct dsi_reg_entry
*regs
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.regs
;
269 int num
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.num
;
273 for (i
= num
- 1; i
>= 0; i
--)
274 if (regs
[i
].disable_load
>= 0)
275 regulator_set_load(s
[i
].consumer
,
276 regs
[i
].disable_load
);
278 regulator_bulk_disable(num
, s
);
281 static int dsi_host_regulator_enable(struct msm_dsi_host
*msm_host
)
283 struct regulator_bulk_data
*s
= msm_host
->supplies
;
284 const struct dsi_reg_entry
*regs
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.regs
;
285 int num
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.num
;
289 for (i
= 0; i
< num
; i
++) {
290 if (regs
[i
].enable_load
>= 0) {
291 ret
= regulator_set_load(s
[i
].consumer
,
292 regs
[i
].enable_load
);
294 pr_err("regulator %d set op mode failed, %d\n",
301 ret
= regulator_bulk_enable(num
, s
);
303 pr_err("regulator enable failed, %d\n", ret
);
310 for (i
--; i
>= 0; i
--)
311 regulator_set_load(s
[i
].consumer
, regs
[i
].disable_load
);
315 static int dsi_regulator_init(struct msm_dsi_host
*msm_host
)
317 struct regulator_bulk_data
*s
= msm_host
->supplies
;
318 const struct dsi_reg_entry
*regs
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.regs
;
319 int num
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.num
;
322 for (i
= 0; i
< num
; i
++)
323 s
[i
].supply
= regs
[i
].name
;
325 ret
= devm_regulator_bulk_get(&msm_host
->pdev
->dev
, num
, s
);
327 pr_err("%s: failed to init regulator, ret=%d\n",
335 static int dsi_clk_init(struct msm_dsi_host
*msm_host
)
337 struct device
*dev
= &msm_host
->pdev
->dev
;
338 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
339 const struct msm_dsi_config
*cfg
= cfg_hnd
->cfg
;
343 for (i
= 0; i
< cfg
->num_bus_clks
; i
++) {
344 msm_host
->bus_clks
[i
] = devm_clk_get(dev
,
345 cfg
->bus_clk_names
[i
]);
346 if (IS_ERR(msm_host
->bus_clks
[i
])) {
347 ret
= PTR_ERR(msm_host
->bus_clks
[i
]);
348 pr_err("%s: Unable to get %s, ret = %d\n",
349 __func__
, cfg
->bus_clk_names
[i
], ret
);
354 /* get link and source clocks */
355 msm_host
->byte_clk
= devm_clk_get(dev
, "byte_clk");
356 if (IS_ERR(msm_host
->byte_clk
)) {
357 ret
= PTR_ERR(msm_host
->byte_clk
);
358 pr_err("%s: can't find dsi_byte_clk. ret=%d\n",
360 msm_host
->byte_clk
= NULL
;
364 msm_host
->pixel_clk
= devm_clk_get(dev
, "pixel_clk");
365 if (IS_ERR(msm_host
->pixel_clk
)) {
366 ret
= PTR_ERR(msm_host
->pixel_clk
);
367 pr_err("%s: can't find dsi_pixel_clk. ret=%d\n",
369 msm_host
->pixel_clk
= NULL
;
373 msm_host
->esc_clk
= devm_clk_get(dev
, "core_clk");
374 if (IS_ERR(msm_host
->esc_clk
)) {
375 ret
= PTR_ERR(msm_host
->esc_clk
);
376 pr_err("%s: can't find dsi_esc_clk. ret=%d\n",
378 msm_host
->esc_clk
= NULL
;
382 msm_host
->byte_clk_src
= clk_get_parent(msm_host
->byte_clk
);
383 if (!msm_host
->byte_clk_src
) {
385 pr_err("%s: can't find byte_clk_src. ret=%d\n", __func__
, ret
);
389 msm_host
->pixel_clk_src
= clk_get_parent(msm_host
->pixel_clk
);
390 if (!msm_host
->pixel_clk_src
) {
392 pr_err("%s: can't find pixel_clk_src. ret=%d\n", __func__
, ret
);
396 if (cfg_hnd
->major
== MSM_DSI_VER_MAJOR_V2
) {
397 msm_host
->src_clk
= devm_clk_get(dev
, "src_clk");
398 if (IS_ERR(msm_host
->src_clk
)) {
399 ret
= PTR_ERR(msm_host
->src_clk
);
400 pr_err("%s: can't find dsi_src_clk. ret=%d\n",
402 msm_host
->src_clk
= NULL
;
406 msm_host
->esc_clk_src
= clk_get_parent(msm_host
->esc_clk
);
407 if (!msm_host
->esc_clk_src
) {
409 pr_err("%s: can't get esc_clk_src. ret=%d\n",
414 msm_host
->dsi_clk_src
= clk_get_parent(msm_host
->src_clk
);
415 if (!msm_host
->dsi_clk_src
) {
417 pr_err("%s: can't get dsi_clk_src. ret=%d\n",
425 static int dsi_bus_clk_enable(struct msm_dsi_host
*msm_host
)
427 const struct msm_dsi_config
*cfg
= msm_host
->cfg_hnd
->cfg
;
430 DBG("id=%d", msm_host
->id
);
432 for (i
= 0; i
< cfg
->num_bus_clks
; i
++) {
433 ret
= clk_prepare_enable(msm_host
->bus_clks
[i
]);
435 pr_err("%s: failed to enable bus clock %d ret %d\n",
444 clk_disable_unprepare(msm_host
->bus_clks
[i
]);
449 static void dsi_bus_clk_disable(struct msm_dsi_host
*msm_host
)
451 const struct msm_dsi_config
*cfg
= msm_host
->cfg_hnd
->cfg
;
456 for (i
= cfg
->num_bus_clks
- 1; i
>= 0; i
--)
457 clk_disable_unprepare(msm_host
->bus_clks
[i
]);
460 int msm_dsi_runtime_suspend(struct device
*dev
)
462 struct platform_device
*pdev
= to_platform_device(dev
);
463 struct msm_dsi
*msm_dsi
= platform_get_drvdata(pdev
);
464 struct mipi_dsi_host
*host
= msm_dsi
->host
;
465 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
467 if (!msm_host
->cfg_hnd
)
470 dsi_bus_clk_disable(msm_host
);
475 int msm_dsi_runtime_resume(struct device
*dev
)
477 struct platform_device
*pdev
= to_platform_device(dev
);
478 struct msm_dsi
*msm_dsi
= platform_get_drvdata(pdev
);
479 struct mipi_dsi_host
*host
= msm_dsi
->host
;
480 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
482 if (!msm_host
->cfg_hnd
)
485 return dsi_bus_clk_enable(msm_host
);
488 static int dsi_link_clk_enable_6g(struct msm_dsi_host
*msm_host
)
492 DBG("Set clk rates: pclk=%d, byteclk=%d",
493 msm_host
->mode
->clock
, msm_host
->byte_clk_rate
);
495 ret
= clk_set_rate(msm_host
->byte_clk
, msm_host
->byte_clk_rate
);
497 pr_err("%s: Failed to set rate byte clk, %d\n", __func__
, ret
);
501 ret
= clk_set_rate(msm_host
->pixel_clk
, msm_host
->mode
->clock
* 1000);
503 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__
, ret
);
507 ret
= clk_prepare_enable(msm_host
->esc_clk
);
509 pr_err("%s: Failed to enable dsi esc clk\n", __func__
);
513 ret
= clk_prepare_enable(msm_host
->byte_clk
);
515 pr_err("%s: Failed to enable dsi byte clk\n", __func__
);
519 ret
= clk_prepare_enable(msm_host
->pixel_clk
);
521 pr_err("%s: Failed to enable dsi pixel clk\n", __func__
);
528 clk_disable_unprepare(msm_host
->byte_clk
);
530 clk_disable_unprepare(msm_host
->esc_clk
);
535 static int dsi_link_clk_enable_v2(struct msm_dsi_host
*msm_host
)
539 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
540 msm_host
->mode
->clock
, msm_host
->byte_clk_rate
,
541 msm_host
->esc_clk_rate
, msm_host
->src_clk_rate
);
543 ret
= clk_set_rate(msm_host
->byte_clk
, msm_host
->byte_clk_rate
);
545 pr_err("%s: Failed to set rate byte clk, %d\n", __func__
, ret
);
549 ret
= clk_set_rate(msm_host
->esc_clk
, msm_host
->esc_clk_rate
);
551 pr_err("%s: Failed to set rate esc clk, %d\n", __func__
, ret
);
555 ret
= clk_set_rate(msm_host
->src_clk
, msm_host
->src_clk_rate
);
557 pr_err("%s: Failed to set rate src clk, %d\n", __func__
, ret
);
561 ret
= clk_set_rate(msm_host
->pixel_clk
, msm_host
->mode
->clock
* 1000);
563 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__
, ret
);
567 ret
= clk_prepare_enable(msm_host
->byte_clk
);
569 pr_err("%s: Failed to enable dsi byte clk\n", __func__
);
573 ret
= clk_prepare_enable(msm_host
->esc_clk
);
575 pr_err("%s: Failed to enable dsi esc clk\n", __func__
);
579 ret
= clk_prepare_enable(msm_host
->src_clk
);
581 pr_err("%s: Failed to enable dsi src clk\n", __func__
);
585 ret
= clk_prepare_enable(msm_host
->pixel_clk
);
587 pr_err("%s: Failed to enable dsi pixel clk\n", __func__
);
594 clk_disable_unprepare(msm_host
->src_clk
);
596 clk_disable_unprepare(msm_host
->esc_clk
);
598 clk_disable_unprepare(msm_host
->byte_clk
);
603 static int dsi_link_clk_enable(struct msm_dsi_host
*msm_host
)
605 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
607 if (cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
)
608 return dsi_link_clk_enable_6g(msm_host
);
610 return dsi_link_clk_enable_v2(msm_host
);
613 static void dsi_link_clk_disable(struct msm_dsi_host
*msm_host
)
615 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
617 if (cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
) {
618 clk_disable_unprepare(msm_host
->esc_clk
);
619 clk_disable_unprepare(msm_host
->pixel_clk
);
620 clk_disable_unprepare(msm_host
->byte_clk
);
622 clk_disable_unprepare(msm_host
->pixel_clk
);
623 clk_disable_unprepare(msm_host
->src_clk
);
624 clk_disable_unprepare(msm_host
->esc_clk
);
625 clk_disable_unprepare(msm_host
->byte_clk
);
629 static int dsi_calc_clk_rate(struct msm_dsi_host
*msm_host
)
631 struct drm_display_mode
*mode
= msm_host
->mode
;
632 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
633 u8 lanes
= msm_host
->lanes
;
634 u32 bpp
= dsi_get_bpp(msm_host
->format
);
638 pr_err("%s: mode not set\n", __func__
);
642 pclk_rate
= mode
->clock
* 1000;
644 msm_host
->byte_clk_rate
= (pclk_rate
* bpp
) / (8 * lanes
);
646 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__
);
647 msm_host
->byte_clk_rate
= (pclk_rate
* bpp
) / 8;
650 DBG("pclk=%d, bclk=%d", pclk_rate
, msm_host
->byte_clk_rate
);
652 msm_host
->esc_clk_rate
= clk_get_rate(msm_host
->esc_clk
);
654 if (cfg_hnd
->major
== MSM_DSI_VER_MAJOR_V2
) {
655 unsigned int esc_mhz
, esc_div
;
656 unsigned long byte_mhz
;
658 msm_host
->src_clk_rate
= (pclk_rate
* bpp
) / 8;
661 * esc clock is byte clock followed by a 4 bit divider,
662 * we need to find an escape clock frequency within the
663 * mipi DSI spec range within the maximum divider limit
664 * We iterate here between an escape clock frequencey
665 * between 20 Mhz to 5 Mhz and pick up the first one
666 * that can be supported by our divider
669 byte_mhz
= msm_host
->byte_clk_rate
/ 1000000;
671 for (esc_mhz
= 20; esc_mhz
>= 5; esc_mhz
--) {
672 esc_div
= DIV_ROUND_UP(byte_mhz
, esc_mhz
);
675 * TODO: Ideally, we shouldn't know what sort of divider
676 * is available in mmss_cc, we're just assuming that
677 * it'll always be a 4 bit divider. Need to come up with
680 if (esc_div
>= 1 && esc_div
<= 16)
687 msm_host
->esc_clk_rate
= msm_host
->byte_clk_rate
/ esc_div
;
689 DBG("esc=%d, src=%d", msm_host
->esc_clk_rate
,
690 msm_host
->src_clk_rate
);
696 static void dsi_intr_ctrl(struct msm_dsi_host
*msm_host
, u32 mask
, int enable
)
701 spin_lock_irqsave(&msm_host
->intr_lock
, flags
);
702 intr
= dsi_read(msm_host
, REG_DSI_INTR_CTRL
);
709 DBG("intr=%x enable=%d", intr
, enable
);
711 dsi_write(msm_host
, REG_DSI_INTR_CTRL
, intr
);
712 spin_unlock_irqrestore(&msm_host
->intr_lock
, flags
);
715 static inline enum dsi_traffic_mode
dsi_get_traffic_mode(const u32 mode_flags
)
717 if (mode_flags
& MIPI_DSI_MODE_VIDEO_BURST
)
719 else if (mode_flags
& MIPI_DSI_MODE_VIDEO_SYNC_PULSE
)
720 return NON_BURST_SYNCH_PULSE
;
722 return NON_BURST_SYNCH_EVENT
;
725 static inline enum dsi_vid_dst_format
dsi_get_vid_fmt(
726 const enum mipi_dsi_pixel_format mipi_fmt
)
729 case MIPI_DSI_FMT_RGB888
: return VID_DST_FORMAT_RGB888
;
730 case MIPI_DSI_FMT_RGB666
: return VID_DST_FORMAT_RGB666_LOOSE
;
731 case MIPI_DSI_FMT_RGB666_PACKED
: return VID_DST_FORMAT_RGB666
;
732 case MIPI_DSI_FMT_RGB565
: return VID_DST_FORMAT_RGB565
;
733 default: return VID_DST_FORMAT_RGB888
;
737 static inline enum dsi_cmd_dst_format
dsi_get_cmd_fmt(
738 const enum mipi_dsi_pixel_format mipi_fmt
)
741 case MIPI_DSI_FMT_RGB888
: return CMD_DST_FORMAT_RGB888
;
742 case MIPI_DSI_FMT_RGB666_PACKED
:
743 case MIPI_DSI_FMT_RGB666
: return VID_DST_FORMAT_RGB666
;
744 case MIPI_DSI_FMT_RGB565
: return CMD_DST_FORMAT_RGB565
;
745 default: return CMD_DST_FORMAT_RGB888
;
749 static void dsi_ctrl_config(struct msm_dsi_host
*msm_host
, bool enable
,
750 struct msm_dsi_phy_shared_timings
*phy_shared_timings
)
752 u32 flags
= msm_host
->mode_flags
;
753 enum mipi_dsi_pixel_format mipi_fmt
= msm_host
->format
;
754 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
758 dsi_write(msm_host
, REG_DSI_CTRL
, 0);
762 if (flags
& MIPI_DSI_MODE_VIDEO
) {
763 if (flags
& MIPI_DSI_MODE_VIDEO_HSE
)
764 data
|= DSI_VID_CFG0_PULSE_MODE_HSA_HE
;
765 if (flags
& MIPI_DSI_MODE_VIDEO_HFP
)
766 data
|= DSI_VID_CFG0_HFP_POWER_STOP
;
767 if (flags
& MIPI_DSI_MODE_VIDEO_HBP
)
768 data
|= DSI_VID_CFG0_HBP_POWER_STOP
;
769 if (flags
& MIPI_DSI_MODE_VIDEO_HSA
)
770 data
|= DSI_VID_CFG0_HSA_POWER_STOP
;
771 /* Always set low power stop mode for BLLP
772 * to let command engine send packets
774 data
|= DSI_VID_CFG0_EOF_BLLP_POWER_STOP
|
775 DSI_VID_CFG0_BLLP_POWER_STOP
;
776 data
|= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags
));
777 data
|= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt
));
778 data
|= DSI_VID_CFG0_VIRT_CHANNEL(msm_host
->channel
);
779 dsi_write(msm_host
, REG_DSI_VID_CFG0
, data
);
781 /* Do not swap RGB colors */
782 data
= DSI_VID_CFG1_RGB_SWAP(SWAP_RGB
);
783 dsi_write(msm_host
, REG_DSI_VID_CFG1
, 0);
785 /* Do not swap RGB colors */
786 data
= DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB
);
787 data
|= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt
));
788 dsi_write(msm_host
, REG_DSI_CMD_CFG0
, data
);
790 data
= DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START
) |
791 DSI_CMD_CFG1_WR_MEM_CONTINUE(
792 MIPI_DCS_WRITE_MEMORY_CONTINUE
);
793 /* Always insert DCS command */
794 data
|= DSI_CMD_CFG1_INSERT_DCS_COMMAND
;
795 dsi_write(msm_host
, REG_DSI_CMD_CFG1
, data
);
798 dsi_write(msm_host
, REG_DSI_CMD_DMA_CTRL
,
799 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER
|
800 DSI_CMD_DMA_CTRL_LOW_POWER
);
803 /* Always assume dedicated TE pin */
804 data
|= DSI_TRIG_CTRL_TE
;
805 data
|= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE
);
806 data
|= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW
);
807 data
|= DSI_TRIG_CTRL_STREAM(msm_host
->channel
);
808 if ((cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
) &&
809 (cfg_hnd
->minor
>= MSM_DSI_6G_VER_MINOR_V1_2
))
810 data
|= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME
;
811 dsi_write(msm_host
, REG_DSI_TRIG_CTRL
, data
);
813 data
= DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings
->clk_post
) |
814 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings
->clk_pre
);
815 dsi_write(msm_host
, REG_DSI_CLKOUT_TIMING_CTRL
, data
);
817 if ((cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
) &&
818 (cfg_hnd
->minor
> MSM_DSI_6G_VER_MINOR_V1_0
) &&
819 phy_shared_timings
->clk_pre_inc_by_2
)
820 dsi_write(msm_host
, REG_DSI_T_CLK_PRE_EXTEND
,
821 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK
);
824 if (!(flags
& MIPI_DSI_MODE_EOT_PACKET
))
825 data
|= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND
;
826 dsi_write(msm_host
, REG_DSI_EOT_PACKET_CTRL
, data
);
828 /* allow only ack-err-status to generate interrupt */
829 dsi_write(msm_host
, REG_DSI_ERR_INT_MASK0
, 0x13ff3fe0);
831 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_ERROR
, 1);
833 dsi_write(msm_host
, REG_DSI_CLK_CTRL
, DSI_CLK_CTRL_ENABLE_CLKS
);
835 data
= DSI_CTRL_CLK_EN
;
837 DBG("lane number=%d", msm_host
->lanes
);
838 data
|= ((DSI_CTRL_LANE0
<< msm_host
->lanes
) - DSI_CTRL_LANE0
);
840 dsi_write(msm_host
, REG_DSI_LANE_SWAP_CTRL
,
841 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host
->dlane_swap
));
843 if (!(flags
& MIPI_DSI_CLOCK_NON_CONTINUOUS
))
844 dsi_write(msm_host
, REG_DSI_LANE_CTRL
,
845 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST
);
847 data
|= DSI_CTRL_ENABLE
;
849 dsi_write(msm_host
, REG_DSI_CTRL
, data
);
852 static void dsi_timing_setup(struct msm_dsi_host
*msm_host
)
854 struct drm_display_mode
*mode
= msm_host
->mode
;
855 u32 hs_start
= 0, vs_start
= 0; /* take sync start as 0 */
856 u32 h_total
= mode
->htotal
;
857 u32 v_total
= mode
->vtotal
;
858 u32 hs_end
= mode
->hsync_end
- mode
->hsync_start
;
859 u32 vs_end
= mode
->vsync_end
- mode
->vsync_start
;
860 u32 ha_start
= h_total
- mode
->hsync_start
;
861 u32 ha_end
= ha_start
+ mode
->hdisplay
;
862 u32 va_start
= v_total
- mode
->vsync_start
;
863 u32 va_end
= va_start
+ mode
->vdisplay
;
868 if (msm_host
->mode_flags
& MIPI_DSI_MODE_VIDEO
) {
869 dsi_write(msm_host
, REG_DSI_ACTIVE_H
,
870 DSI_ACTIVE_H_START(ha_start
) |
871 DSI_ACTIVE_H_END(ha_end
));
872 dsi_write(msm_host
, REG_DSI_ACTIVE_V
,
873 DSI_ACTIVE_V_START(va_start
) |
874 DSI_ACTIVE_V_END(va_end
));
875 dsi_write(msm_host
, REG_DSI_TOTAL
,
876 DSI_TOTAL_H_TOTAL(h_total
- 1) |
877 DSI_TOTAL_V_TOTAL(v_total
- 1));
879 dsi_write(msm_host
, REG_DSI_ACTIVE_HSYNC
,
880 DSI_ACTIVE_HSYNC_START(hs_start
) |
881 DSI_ACTIVE_HSYNC_END(hs_end
));
882 dsi_write(msm_host
, REG_DSI_ACTIVE_VSYNC_HPOS
, 0);
883 dsi_write(msm_host
, REG_DSI_ACTIVE_VSYNC_VPOS
,
884 DSI_ACTIVE_VSYNC_VPOS_START(vs_start
) |
885 DSI_ACTIVE_VSYNC_VPOS_END(vs_end
));
886 } else { /* command mode */
887 /* image data and 1 byte write_memory_start cmd */
888 wc
= mode
->hdisplay
* dsi_get_bpp(msm_host
->format
) / 8 + 1;
890 dsi_write(msm_host
, REG_DSI_CMD_MDP_STREAM_CTRL
,
891 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc
) |
892 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
894 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
895 MIPI_DSI_DCS_LONG_WRITE
));
897 dsi_write(msm_host
, REG_DSI_CMD_MDP_STREAM_TOTAL
,
898 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(mode
->hdisplay
) |
899 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode
->vdisplay
));
903 static void dsi_sw_reset(struct msm_dsi_host
*msm_host
)
905 dsi_write(msm_host
, REG_DSI_CLK_CTRL
, DSI_CLK_CTRL_ENABLE_CLKS
);
906 wmb(); /* clocks need to be enabled before reset */
908 dsi_write(msm_host
, REG_DSI_RESET
, 1);
909 wmb(); /* make sure reset happen */
910 dsi_write(msm_host
, REG_DSI_RESET
, 0);
913 static void dsi_op_mode_config(struct msm_dsi_host
*msm_host
,
914 bool video_mode
, bool enable
)
918 dsi_ctrl
= dsi_read(msm_host
, REG_DSI_CTRL
);
921 dsi_ctrl
&= ~(DSI_CTRL_ENABLE
| DSI_CTRL_VID_MODE_EN
|
922 DSI_CTRL_CMD_MODE_EN
);
923 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_CMD_MDP_DONE
|
924 DSI_IRQ_MASK_VIDEO_DONE
, 0);
927 dsi_ctrl
|= DSI_CTRL_VID_MODE_EN
;
928 } else { /* command mode */
929 dsi_ctrl
|= DSI_CTRL_CMD_MODE_EN
;
930 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_CMD_MDP_DONE
, 1);
932 dsi_ctrl
|= DSI_CTRL_ENABLE
;
935 dsi_write(msm_host
, REG_DSI_CTRL
, dsi_ctrl
);
938 static void dsi_set_tx_power_mode(int mode
, struct msm_dsi_host
*msm_host
)
942 data
= dsi_read(msm_host
, REG_DSI_CMD_DMA_CTRL
);
945 data
&= ~DSI_CMD_DMA_CTRL_LOW_POWER
;
947 data
|= DSI_CMD_DMA_CTRL_LOW_POWER
;
949 dsi_write(msm_host
, REG_DSI_CMD_DMA_CTRL
, data
);
952 static void dsi_wait4video_done(struct msm_dsi_host
*msm_host
)
954 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_VIDEO_DONE
, 1);
956 reinit_completion(&msm_host
->video_comp
);
958 wait_for_completion_timeout(&msm_host
->video_comp
,
959 msecs_to_jiffies(70));
961 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_VIDEO_DONE
, 0);
964 static void dsi_wait4video_eng_busy(struct msm_dsi_host
*msm_host
)
966 if (!(msm_host
->mode_flags
& MIPI_DSI_MODE_VIDEO
))
969 if (msm_host
->power_on
) {
970 dsi_wait4video_done(msm_host
);
971 /* delay 4 ms to skip BLLP */
972 usleep_range(2000, 4000);
977 static int dsi_tx_buf_alloc(struct msm_dsi_host
*msm_host
, int size
)
979 struct drm_device
*dev
= msm_host
->dev
;
980 struct msm_drm_private
*priv
= dev
->dev_private
;
981 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
985 if (cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
) {
986 msm_host
->tx_gem_obj
= msm_gem_new(dev
, size
, MSM_BO_UNCACHED
);
987 if (IS_ERR(msm_host
->tx_gem_obj
)) {
988 ret
= PTR_ERR(msm_host
->tx_gem_obj
);
989 pr_err("%s: failed to allocate gem, %d\n",
991 msm_host
->tx_gem_obj
= NULL
;
995 ret
= msm_gem_get_iova(msm_host
->tx_gem_obj
,
996 priv
->kms
->aspace
, &iova
);
997 mutex_unlock(&dev
->struct_mutex
);
999 pr_err("%s: failed to get iova, %d\n", __func__
, ret
);
1004 pr_err("%s: buf NOT 8 bytes aligned\n", __func__
);
1008 msm_host
->tx_size
= msm_host
->tx_gem_obj
->size
;
1010 msm_host
->tx_buf
= dma_alloc_coherent(dev
->dev
, size
,
1011 &msm_host
->tx_buf_paddr
, GFP_KERNEL
);
1012 if (!msm_host
->tx_buf
) {
1014 pr_err("%s: failed to allocate tx buf, %d\n",
1019 msm_host
->tx_size
= size
;
1025 static void dsi_tx_buf_free(struct msm_dsi_host
*msm_host
)
1027 struct drm_device
*dev
= msm_host
->dev
;
1029 if (msm_host
->tx_gem_obj
) {
1030 msm_gem_put_iova(msm_host
->tx_gem_obj
, 0);
1031 mutex_lock(&dev
->struct_mutex
);
1032 msm_gem_free_object(msm_host
->tx_gem_obj
);
1033 msm_host
->tx_gem_obj
= NULL
;
1034 mutex_unlock(&dev
->struct_mutex
);
1037 if (msm_host
->tx_buf
)
1038 dma_free_coherent(dev
->dev
, msm_host
->tx_size
, msm_host
->tx_buf
,
1039 msm_host
->tx_buf_paddr
);
1043 * prepare cmd buffer to be txed
1045 static int dsi_cmd_dma_add(struct msm_dsi_host
*msm_host
,
1046 const struct mipi_dsi_msg
*msg
)
1048 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
1049 struct mipi_dsi_packet packet
;
1054 ret
= mipi_dsi_create_packet(&packet
, msg
);
1056 pr_err("%s: create packet failed, %d\n", __func__
, ret
);
1059 len
= (packet
.size
+ 3) & (~0x3);
1061 if (len
> msm_host
->tx_size
) {
1062 pr_err("%s: packet size is too big\n", __func__
);
1066 if (cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
) {
1067 data
= msm_gem_get_vaddr(msm_host
->tx_gem_obj
);
1069 ret
= PTR_ERR(data
);
1070 pr_err("%s: get vaddr failed, %d\n", __func__
, ret
);
1074 data
= msm_host
->tx_buf
;
1077 /* MSM specific command format in memory */
1078 data
[0] = packet
.header
[1];
1079 data
[1] = packet
.header
[2];
1080 data
[2] = packet
.header
[0];
1081 data
[3] = BIT(7); /* Last packet */
1082 if (mipi_dsi_packet_format_is_long(msg
->type
))
1084 if (msg
->rx_buf
&& msg
->rx_len
)
1088 if (packet
.payload
&& packet
.payload_length
)
1089 memcpy(data
+ 4, packet
.payload
, packet
.payload_length
);
1091 /* Append 0xff to the end */
1092 if (packet
.size
< len
)
1093 memset(data
+ packet
.size
, 0xff, len
- packet
.size
);
1095 if (cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
)
1096 msm_gem_put_vaddr(msm_host
->tx_gem_obj
);
1102 * dsi_short_read1_resp: 1 parameter
1104 static int dsi_short_read1_resp(u8
*buf
, const struct mipi_dsi_msg
*msg
)
1106 u8
*data
= msg
->rx_buf
;
1107 if (data
&& (msg
->rx_len
>= 1)) {
1108 *data
= buf
[1]; /* strip out dcs type */
1111 pr_err("%s: read data does not match with rx_buf len %zu\n",
1112 __func__
, msg
->rx_len
);
1118 * dsi_short_read2_resp: 2 parameter
1120 static int dsi_short_read2_resp(u8
*buf
, const struct mipi_dsi_msg
*msg
)
1122 u8
*data
= msg
->rx_buf
;
1123 if (data
&& (msg
->rx_len
>= 2)) {
1124 data
[0] = buf
[1]; /* strip out dcs type */
1128 pr_err("%s: read data does not match with rx_buf len %zu\n",
1129 __func__
, msg
->rx_len
);
1134 static int dsi_long_read_resp(u8
*buf
, const struct mipi_dsi_msg
*msg
)
1136 /* strip out 4 byte dcs header */
1137 if (msg
->rx_buf
&& msg
->rx_len
)
1138 memcpy(msg
->rx_buf
, buf
+ 4, msg
->rx_len
);
1143 static int dsi_cmd_dma_tx(struct msm_dsi_host
*msm_host
, int len
)
1145 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
1146 struct drm_device
*dev
= msm_host
->dev
;
1147 struct msm_drm_private
*priv
= dev
->dev_private
;
1152 if (cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
) {
1153 ret
= msm_gem_get_iova(msm_host
->tx_gem_obj
,
1154 priv
->kms
->aspace
, &dma_base
);
1156 pr_err("%s: failed to get iova: %d\n", __func__
, ret
);
1160 dma_base
= msm_host
->tx_buf_paddr
;
1163 reinit_completion(&msm_host
->dma_comp
);
1165 dsi_wait4video_eng_busy(msm_host
);
1167 triggered
= msm_dsi_manager_cmd_xfer_trigger(
1168 msm_host
->id
, dma_base
, len
);
1170 ret
= wait_for_completion_timeout(&msm_host
->dma_comp
,
1171 msecs_to_jiffies(200));
1183 static int dsi_cmd_dma_rx(struct msm_dsi_host
*msm_host
,
1184 u8
*buf
, int rx_byte
, int pkt_size
)
1186 u32
*lp
, *temp
, data
;
1190 int repeated_bytes
= 0;
1191 int buf_offset
= buf
- msm_host
->rx_buf
;
1195 cnt
= (rx_byte
+ 3) >> 2;
1197 cnt
= 4; /* 4 x 32 bits registers only */
1202 read_cnt
= pkt_size
+ 6;
1205 * In case of multiple reads from the panel, after the first read, there
1206 * is possibility that there are some bytes in the payload repeating in
1207 * the RDBK_DATA registers. Since we read all the parameters from the
1208 * panel right from the first byte for every pass. We need to skip the
1209 * repeating bytes and then append the new parameters to the rx buffer.
1211 if (read_cnt
> 16) {
1213 /* Any data more than 16 bytes will be shifted out.
1214 * The temp read buffer should already contain these bytes.
1215 * The remaining bytes in read buffer are the repeated bytes.
1217 bytes_shifted
= read_cnt
- 16;
1218 repeated_bytes
= buf_offset
- bytes_shifted
;
1221 for (i
= cnt
- 1; i
>= 0; i
--) {
1222 data
= dsi_read(msm_host
, REG_DSI_RDBK_DATA(i
));
1223 *temp
++ = ntohl(data
); /* to host byte order */
1224 DBG("data = 0x%x and ntohl(data) = 0x%x", data
, ntohl(data
));
1227 for (i
= repeated_bytes
; i
< 16; i
++)
1233 static int dsi_cmds2buf_tx(struct msm_dsi_host
*msm_host
,
1234 const struct mipi_dsi_msg
*msg
)
1237 int bllp_len
= msm_host
->mode
->hdisplay
*
1238 dsi_get_bpp(msm_host
->format
) / 8;
1240 len
= dsi_cmd_dma_add(msm_host
, msg
);
1242 pr_err("%s: failed to add cmd type = 0x%x\n",
1243 __func__
, msg
->type
);
1247 /* for video mode, do not send cmds more than
1248 * one pixel line, since it only transmit it
1251 /* TODO: if the command is sent in LP mode, the bit rate is only
1252 * half of esc clk rate. In this case, if the video is already
1253 * actively streaming, we need to check more carefully if the
1254 * command can be fit into one BLLP.
1256 if ((msm_host
->mode_flags
& MIPI_DSI_MODE_VIDEO
) && (len
> bllp_len
)) {
1257 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1262 ret
= dsi_cmd_dma_tx(msm_host
, len
);
1264 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1265 __func__
, msg
->type
, (*(u8
*)(msg
->tx_buf
)), len
);
1272 static void dsi_sw_reset_restore(struct msm_dsi_host
*msm_host
)
1276 data0
= dsi_read(msm_host
, REG_DSI_CTRL
);
1278 data1
&= ~DSI_CTRL_ENABLE
;
1279 dsi_write(msm_host
, REG_DSI_CTRL
, data1
);
1281 * dsi controller need to be disabled before
1286 dsi_write(msm_host
, REG_DSI_CLK_CTRL
, DSI_CLK_CTRL_ENABLE_CLKS
);
1287 wmb(); /* make sure clocks enabled */
1289 /* dsi controller can only be reset while clocks are running */
1290 dsi_write(msm_host
, REG_DSI_RESET
, 1);
1291 wmb(); /* make sure reset happen */
1292 dsi_write(msm_host
, REG_DSI_RESET
, 0);
1293 wmb(); /* controller out of reset */
1294 dsi_write(msm_host
, REG_DSI_CTRL
, data0
);
1295 wmb(); /* make sure dsi controller enabled again */
1298 static void dsi_hpd_worker(struct work_struct
*work
)
1300 struct msm_dsi_host
*msm_host
=
1301 container_of(work
, struct msm_dsi_host
, hpd_work
);
1303 drm_helper_hpd_irq_event(msm_host
->dev
);
1306 static void dsi_err_worker(struct work_struct
*work
)
1308 struct msm_dsi_host
*msm_host
=
1309 container_of(work
, struct msm_dsi_host
, err_work
);
1310 u32 status
= msm_host
->err_work_state
;
1312 pr_err_ratelimited("%s: status=%x\n", __func__
, status
);
1313 if (status
& DSI_ERR_STATE_MDP_FIFO_UNDERFLOW
)
1314 dsi_sw_reset_restore(msm_host
);
1316 /* It is safe to clear here because error irq is disabled. */
1317 msm_host
->err_work_state
= 0;
1319 /* enable dsi error interrupt */
1320 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_ERROR
, 1);
1323 static void dsi_ack_err_status(struct msm_dsi_host
*msm_host
)
1327 status
= dsi_read(msm_host
, REG_DSI_ACK_ERR_STATUS
);
1330 dsi_write(msm_host
, REG_DSI_ACK_ERR_STATUS
, status
);
1331 /* Writing of an extra 0 needed to clear error bits */
1332 dsi_write(msm_host
, REG_DSI_ACK_ERR_STATUS
, 0);
1333 msm_host
->err_work_state
|= DSI_ERR_STATE_ACK
;
1337 static void dsi_timeout_status(struct msm_dsi_host
*msm_host
)
1341 status
= dsi_read(msm_host
, REG_DSI_TIMEOUT_STATUS
);
1344 dsi_write(msm_host
, REG_DSI_TIMEOUT_STATUS
, status
);
1345 msm_host
->err_work_state
|= DSI_ERR_STATE_TIMEOUT
;
1349 static void dsi_dln0_phy_err(struct msm_dsi_host
*msm_host
)
1353 status
= dsi_read(msm_host
, REG_DSI_DLN0_PHY_ERR
);
1355 if (status
& (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC
|
1356 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC
|
1357 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL
|
1358 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0
|
1359 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1
)) {
1360 dsi_write(msm_host
, REG_DSI_DLN0_PHY_ERR
, status
);
1361 msm_host
->err_work_state
|= DSI_ERR_STATE_DLN0_PHY
;
1365 static void dsi_fifo_status(struct msm_dsi_host
*msm_host
)
1369 status
= dsi_read(msm_host
, REG_DSI_FIFO_STATUS
);
1371 /* fifo underflow, overflow */
1373 dsi_write(msm_host
, REG_DSI_FIFO_STATUS
, status
);
1374 msm_host
->err_work_state
|= DSI_ERR_STATE_FIFO
;
1375 if (status
& DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW
)
1376 msm_host
->err_work_state
|=
1377 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW
;
1381 static void dsi_status(struct msm_dsi_host
*msm_host
)
1385 status
= dsi_read(msm_host
, REG_DSI_STATUS0
);
1387 if (status
& DSI_STATUS0_INTERLEAVE_OP_CONTENTION
) {
1388 dsi_write(msm_host
, REG_DSI_STATUS0
, status
);
1389 msm_host
->err_work_state
|=
1390 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION
;
1394 static void dsi_clk_status(struct msm_dsi_host
*msm_host
)
1398 status
= dsi_read(msm_host
, REG_DSI_CLK_STATUS
);
1400 if (status
& DSI_CLK_STATUS_PLL_UNLOCKED
) {
1401 dsi_write(msm_host
, REG_DSI_CLK_STATUS
, status
);
1402 msm_host
->err_work_state
|= DSI_ERR_STATE_PLL_UNLOCKED
;
1406 static void dsi_error(struct msm_dsi_host
*msm_host
)
1408 /* disable dsi error interrupt */
1409 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_ERROR
, 0);
1411 dsi_clk_status(msm_host
);
1412 dsi_fifo_status(msm_host
);
1413 dsi_ack_err_status(msm_host
);
1414 dsi_timeout_status(msm_host
);
1415 dsi_status(msm_host
);
1416 dsi_dln0_phy_err(msm_host
);
1418 queue_work(msm_host
->workqueue
, &msm_host
->err_work
);
1421 static irqreturn_t
dsi_host_irq(int irq
, void *ptr
)
1423 struct msm_dsi_host
*msm_host
= ptr
;
1425 unsigned long flags
;
1427 if (!msm_host
->ctrl_base
)
1430 spin_lock_irqsave(&msm_host
->intr_lock
, flags
);
1431 isr
= dsi_read(msm_host
, REG_DSI_INTR_CTRL
);
1432 dsi_write(msm_host
, REG_DSI_INTR_CTRL
, isr
);
1433 spin_unlock_irqrestore(&msm_host
->intr_lock
, flags
);
1435 DBG("isr=0x%x, id=%d", isr
, msm_host
->id
);
1437 if (isr
& DSI_IRQ_ERROR
)
1438 dsi_error(msm_host
);
1440 if (isr
& DSI_IRQ_VIDEO_DONE
)
1441 complete(&msm_host
->video_comp
);
1443 if (isr
& DSI_IRQ_CMD_DMA_DONE
)
1444 complete(&msm_host
->dma_comp
);
1449 static int dsi_host_init_panel_gpios(struct msm_dsi_host
*msm_host
,
1450 struct device
*panel_device
)
1452 msm_host
->disp_en_gpio
= devm_gpiod_get_optional(panel_device
,
1455 if (IS_ERR(msm_host
->disp_en_gpio
)) {
1456 DBG("cannot get disp-enable-gpios %ld",
1457 PTR_ERR(msm_host
->disp_en_gpio
));
1458 return PTR_ERR(msm_host
->disp_en_gpio
);
1461 msm_host
->te_gpio
= devm_gpiod_get_optional(panel_device
, "disp-te",
1463 if (IS_ERR(msm_host
->te_gpio
)) {
1464 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host
->te_gpio
));
1465 return PTR_ERR(msm_host
->te_gpio
);
1471 static int dsi_host_attach(struct mipi_dsi_host
*host
,
1472 struct mipi_dsi_device
*dsi
)
1474 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1477 if (dsi
->lanes
> msm_host
->num_data_lanes
)
1480 msm_host
->channel
= dsi
->channel
;
1481 msm_host
->lanes
= dsi
->lanes
;
1482 msm_host
->format
= dsi
->format
;
1483 msm_host
->mode_flags
= dsi
->mode_flags
;
1485 msm_dsi_manager_attach_dsi_device(msm_host
->id
, dsi
->mode_flags
);
1487 /* Some gpios defined in panel DT need to be controlled by host */
1488 ret
= dsi_host_init_panel_gpios(msm_host
, &dsi
->dev
);
1492 DBG("id=%d", msm_host
->id
);
1494 queue_work(msm_host
->workqueue
, &msm_host
->hpd_work
);
1499 static int dsi_host_detach(struct mipi_dsi_host
*host
,
1500 struct mipi_dsi_device
*dsi
)
1502 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1504 msm_host
->device_node
= NULL
;
1506 DBG("id=%d", msm_host
->id
);
1508 queue_work(msm_host
->workqueue
, &msm_host
->hpd_work
);
1513 static ssize_t
dsi_host_transfer(struct mipi_dsi_host
*host
,
1514 const struct mipi_dsi_msg
*msg
)
1516 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1519 if (!msg
|| !msm_host
->power_on
)
1522 mutex_lock(&msm_host
->cmd_mutex
);
1523 ret
= msm_dsi_manager_cmd_xfer(msm_host
->id
, msg
);
1524 mutex_unlock(&msm_host
->cmd_mutex
);
1529 static struct mipi_dsi_host_ops dsi_host_ops
= {
1530 .attach
= dsi_host_attach
,
1531 .detach
= dsi_host_detach
,
1532 .transfer
= dsi_host_transfer
,
1536 * List of supported physical to logical lane mappings.
1537 * For example, the 2nd entry represents the following mapping:
1539 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1541 static const int supported_data_lane_swaps
[][4] = {
1552 static int dsi_host_parse_lane_data(struct msm_dsi_host
*msm_host
,
1553 struct device_node
*ep
)
1555 struct device
*dev
= &msm_host
->pdev
->dev
;
1556 struct property
*prop
;
1558 int ret
, i
, len
, num_lanes
;
1560 prop
= of_find_property(ep
, "data-lanes", &len
);
1563 "failed to find data lane mapping, using default\n");
1567 num_lanes
= len
/ sizeof(u32
);
1569 if (num_lanes
< 1 || num_lanes
> 4) {
1570 dev_err(dev
, "bad number of data lanes\n");
1574 msm_host
->num_data_lanes
= num_lanes
;
1576 ret
= of_property_read_u32_array(ep
, "data-lanes", lane_map
,
1579 dev_err(dev
, "failed to read lane data\n");
1584 * compare DT specified physical-logical lane mappings with the ones
1585 * supported by hardware
1587 for (i
= 0; i
< ARRAY_SIZE(supported_data_lane_swaps
); i
++) {
1588 const int *swap
= supported_data_lane_swaps
[i
];
1592 * the data-lanes array we get from DT has a logical->physical
1593 * mapping. The "data lane swap" register field represents
1594 * supported configurations in a physical->logical mapping.
1595 * Translate the DT mapping to what we understand and find a
1596 * configuration that works.
1598 for (j
= 0; j
< num_lanes
; j
++) {
1599 if (lane_map
[j
] < 0 || lane_map
[j
] > 3)
1600 dev_err(dev
, "bad physical lane entry %u\n",
1603 if (swap
[lane_map
[j
]] != j
)
1607 if (j
== num_lanes
) {
1608 msm_host
->dlane_swap
= i
;
1616 static int dsi_host_parse_dt(struct msm_dsi_host
*msm_host
)
1618 struct device
*dev
= &msm_host
->pdev
->dev
;
1619 struct device_node
*np
= dev
->of_node
;
1620 struct device_node
*endpoint
, *device_node
;
1624 * Get the endpoint of the output port of the DSI host. In our case,
1625 * this is mapped to port number with reg = 1. Don't return an error if
1626 * the remote endpoint isn't defined. It's possible that there is
1627 * nothing connected to the dsi output.
1629 endpoint
= of_graph_get_endpoint_by_regs(np
, 1, -1);
1631 dev_dbg(dev
, "%s: no endpoint\n", __func__
);
1635 ret
= dsi_host_parse_lane_data(msm_host
, endpoint
);
1637 dev_err(dev
, "%s: invalid lane configuration %d\n",
1642 /* Get panel node from the output port's endpoint data */
1643 device_node
= of_graph_get_remote_node(np
, 1, 0);
1645 dev_dbg(dev
, "%s: no valid device\n", __func__
);
1649 msm_host
->device_node
= device_node
;
1651 if (of_property_read_bool(np
, "syscon-sfpb")) {
1652 msm_host
->sfpb
= syscon_regmap_lookup_by_phandle(np
,
1654 if (IS_ERR(msm_host
->sfpb
)) {
1655 dev_err(dev
, "%s: failed to get sfpb regmap\n",
1657 ret
= PTR_ERR(msm_host
->sfpb
);
1661 of_node_put(device_node
);
1664 of_node_put(endpoint
);
1669 static int dsi_host_get_id(struct msm_dsi_host
*msm_host
)
1671 struct platform_device
*pdev
= msm_host
->pdev
;
1672 const struct msm_dsi_config
*cfg
= msm_host
->cfg_hnd
->cfg
;
1673 struct resource
*res
;
1676 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dsi_ctrl");
1680 for (i
= 0; i
< cfg
->num_dsi
; i
++) {
1681 if (cfg
->io_start
[i
] == res
->start
)
1688 int msm_dsi_host_init(struct msm_dsi
*msm_dsi
)
1690 struct msm_dsi_host
*msm_host
= NULL
;
1691 struct platform_device
*pdev
= msm_dsi
->pdev
;
1694 msm_host
= devm_kzalloc(&pdev
->dev
, sizeof(*msm_host
), GFP_KERNEL
);
1696 pr_err("%s: FAILED: cannot alloc dsi host\n",
1702 msm_host
->pdev
= pdev
;
1703 msm_dsi
->host
= &msm_host
->base
;
1705 ret
= dsi_host_parse_dt(msm_host
);
1707 pr_err("%s: failed to parse dt\n", __func__
);
1711 msm_host
->ctrl_base
= msm_ioremap(pdev
, "dsi_ctrl", "DSI CTRL");
1712 if (IS_ERR(msm_host
->ctrl_base
)) {
1713 pr_err("%s: unable to map Dsi ctrl base\n", __func__
);
1714 ret
= PTR_ERR(msm_host
->ctrl_base
);
1718 pm_runtime_enable(&pdev
->dev
);
1720 msm_host
->cfg_hnd
= dsi_get_config(msm_host
);
1721 if (!msm_host
->cfg_hnd
) {
1723 pr_err("%s: get config failed\n", __func__
);
1727 msm_host
->id
= dsi_host_get_id(msm_host
);
1728 if (msm_host
->id
< 0) {
1730 pr_err("%s: unable to identify DSI host index\n", __func__
);
1734 /* fixup base address by io offset */
1735 msm_host
->ctrl_base
+= msm_host
->cfg_hnd
->cfg
->io_offset
;
1737 ret
= dsi_regulator_init(msm_host
);
1739 pr_err("%s: regulator init failed\n", __func__
);
1743 ret
= dsi_clk_init(msm_host
);
1745 pr_err("%s: unable to initialize dsi clks\n", __func__
);
1749 msm_host
->rx_buf
= devm_kzalloc(&pdev
->dev
, SZ_4K
, GFP_KERNEL
);
1750 if (!msm_host
->rx_buf
) {
1752 pr_err("%s: alloc rx temp buf failed\n", __func__
);
1756 init_completion(&msm_host
->dma_comp
);
1757 init_completion(&msm_host
->video_comp
);
1758 mutex_init(&msm_host
->dev_mutex
);
1759 mutex_init(&msm_host
->cmd_mutex
);
1760 spin_lock_init(&msm_host
->intr_lock
);
1762 /* setup workqueue */
1763 msm_host
->workqueue
= alloc_ordered_workqueue("dsi_drm_work", 0);
1764 INIT_WORK(&msm_host
->err_work
, dsi_err_worker
);
1765 INIT_WORK(&msm_host
->hpd_work
, dsi_hpd_worker
);
1767 msm_dsi
->id
= msm_host
->id
;
1769 DBG("Dsi Host %d initialized", msm_host
->id
);
1776 void msm_dsi_host_destroy(struct mipi_dsi_host
*host
)
1778 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1781 dsi_tx_buf_free(msm_host
);
1782 if (msm_host
->workqueue
) {
1783 flush_workqueue(msm_host
->workqueue
);
1784 destroy_workqueue(msm_host
->workqueue
);
1785 msm_host
->workqueue
= NULL
;
1788 mutex_destroy(&msm_host
->cmd_mutex
);
1789 mutex_destroy(&msm_host
->dev_mutex
);
1791 pm_runtime_disable(&msm_host
->pdev
->dev
);
1794 int msm_dsi_host_modeset_init(struct mipi_dsi_host
*host
,
1795 struct drm_device
*dev
)
1797 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1798 struct platform_device
*pdev
= msm_host
->pdev
;
1801 msm_host
->irq
= irq_of_parse_and_map(pdev
->dev
.of_node
, 0);
1802 if (msm_host
->irq
< 0) {
1803 ret
= msm_host
->irq
;
1804 dev_err(dev
->dev
, "failed to get irq: %d\n", ret
);
1808 ret
= devm_request_irq(&pdev
->dev
, msm_host
->irq
,
1809 dsi_host_irq
, IRQF_TRIGGER_HIGH
| IRQF_ONESHOT
,
1810 "dsi_isr", msm_host
);
1812 dev_err(&pdev
->dev
, "failed to request IRQ%u: %d\n",
1813 msm_host
->irq
, ret
);
1817 msm_host
->dev
= dev
;
1818 ret
= dsi_tx_buf_alloc(msm_host
, SZ_4K
);
1820 pr_err("%s: alloc tx gem obj failed, %d\n", __func__
, ret
);
1827 int msm_dsi_host_register(struct mipi_dsi_host
*host
, bool check_defer
)
1829 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1832 /* Register mipi dsi host */
1833 if (!msm_host
->registered
) {
1834 host
->dev
= &msm_host
->pdev
->dev
;
1835 host
->ops
= &dsi_host_ops
;
1836 ret
= mipi_dsi_host_register(host
);
1840 msm_host
->registered
= true;
1842 /* If the panel driver has not been probed after host register,
1843 * we should defer the host's probe.
1844 * It makes sure panel is connected when fbcon detects
1845 * connector status and gets the proper display mode to
1846 * create framebuffer.
1847 * Don't try to defer if there is nothing connected to the dsi
1850 if (check_defer
&& msm_host
->device_node
) {
1851 if (!of_drm_find_panel(msm_host
->device_node
))
1852 if (!of_drm_find_bridge(msm_host
->device_node
))
1853 return -EPROBE_DEFER
;
1860 void msm_dsi_host_unregister(struct mipi_dsi_host
*host
)
1862 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1864 if (msm_host
->registered
) {
1865 mipi_dsi_host_unregister(host
);
1868 msm_host
->registered
= false;
1872 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host
*host
,
1873 const struct mipi_dsi_msg
*msg
)
1875 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1877 /* TODO: make sure dsi_cmd_mdp is idle.
1878 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1879 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1880 * How to handle the old versions? Wait for mdp cmd done?
1884 * mdss interrupt is generated in mdp core clock domain
1885 * mdp clock need to be enabled to receive dsi interrupt
1887 pm_runtime_get_sync(&msm_host
->pdev
->dev
);
1888 dsi_link_clk_enable(msm_host
);
1890 /* TODO: vote for bus bandwidth */
1892 if (!(msg
->flags
& MIPI_DSI_MSG_USE_LPM
))
1893 dsi_set_tx_power_mode(0, msm_host
);
1895 msm_host
->dma_cmd_ctrl_restore
= dsi_read(msm_host
, REG_DSI_CTRL
);
1896 dsi_write(msm_host
, REG_DSI_CTRL
,
1897 msm_host
->dma_cmd_ctrl_restore
|
1898 DSI_CTRL_CMD_MODE_EN
|
1900 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_CMD_DMA_DONE
, 1);
1905 void msm_dsi_host_xfer_restore(struct mipi_dsi_host
*host
,
1906 const struct mipi_dsi_msg
*msg
)
1908 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1910 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_CMD_DMA_DONE
, 0);
1911 dsi_write(msm_host
, REG_DSI_CTRL
, msm_host
->dma_cmd_ctrl_restore
);
1913 if (!(msg
->flags
& MIPI_DSI_MSG_USE_LPM
))
1914 dsi_set_tx_power_mode(1, msm_host
);
1916 /* TODO: unvote for bus bandwidth */
1918 dsi_link_clk_disable(msm_host
);
1919 pm_runtime_put_autosuspend(&msm_host
->pdev
->dev
);
1922 int msm_dsi_host_cmd_tx(struct mipi_dsi_host
*host
,
1923 const struct mipi_dsi_msg
*msg
)
1925 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1927 return dsi_cmds2buf_tx(msm_host
, msg
);
1930 int msm_dsi_host_cmd_rx(struct mipi_dsi_host
*host
,
1931 const struct mipi_dsi_msg
*msg
)
1933 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1934 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
1935 int data_byte
, rx_byte
, dlen
, end
;
1936 int short_response
, diff
, pkt_size
, ret
= 0;
1938 int rlen
= msg
->rx_len
;
1947 data_byte
= 10; /* first read */
1948 if (rlen
< data_byte
)
1951 pkt_size
= data_byte
;
1952 rx_byte
= data_byte
+ 6; /* 4 header + 2 crc */
1955 buf
= msm_host
->rx_buf
;
1958 u8 tx
[2] = {pkt_size
& 0xff, pkt_size
>> 8};
1959 struct mipi_dsi_msg max_pkt_size_msg
= {
1960 .channel
= msg
->channel
,
1961 .type
= MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
,
1966 DBG("rlen=%d pkt_size=%d rx_byte=%d",
1967 rlen
, pkt_size
, rx_byte
);
1969 ret
= dsi_cmds2buf_tx(msm_host
, &max_pkt_size_msg
);
1971 pr_err("%s: Set max pkt size failed, %d\n",
1976 if ((cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
) &&
1977 (cfg_hnd
->minor
>= MSM_DSI_6G_VER_MINOR_V1_1
)) {
1978 /* Clear the RDBK_DATA registers */
1979 dsi_write(msm_host
, REG_DSI_RDBK_DATA_CTRL
,
1980 DSI_RDBK_DATA_CTRL_CLR
);
1981 wmb(); /* make sure the RDBK registers are cleared */
1982 dsi_write(msm_host
, REG_DSI_RDBK_DATA_CTRL
, 0);
1983 wmb(); /* release cleared status before transfer */
1986 ret
= dsi_cmds2buf_tx(msm_host
, msg
);
1987 if (ret
< msg
->tx_len
) {
1988 pr_err("%s: Read cmd Tx failed, %d\n", __func__
, ret
);
1993 * once cmd_dma_done interrupt received,
1994 * return data from client is ready and stored
1995 * at RDBK_DATA register already
1996 * since rx fifo is 16 bytes, dcs header is kept at first loop,
1997 * after that dcs header lost during shift into registers
1999 dlen
= dsi_cmd_dma_rx(msm_host
, buf
, rx_byte
, pkt_size
);
2007 if (rlen
<= data_byte
) {
2008 diff
= data_byte
- rlen
;
2016 dlen
-= 2; /* 2 crc */
2018 buf
+= dlen
; /* next start position */
2019 data_byte
= 14; /* NOT first read */
2020 if (rlen
< data_byte
)
2023 pkt_size
+= data_byte
;
2024 DBG("buf=%p dlen=%d diff=%d", buf
, dlen
, diff
);
2029 * For single Long read, if the requested rlen < 10,
2030 * we need to shift the start position of rx
2031 * data buffer to skip the bytes which are not
2034 if (pkt_size
< 10 && !short_response
)
2035 buf
= msm_host
->rx_buf
+ (10 - rlen
);
2037 buf
= msm_host
->rx_buf
;
2041 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
:
2042 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__
);
2045 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE
:
2046 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
:
2047 ret
= dsi_short_read1_resp(buf
, msg
);
2049 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE
:
2050 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
:
2051 ret
= dsi_short_read2_resp(buf
, msg
);
2053 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE
:
2054 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
:
2055 ret
= dsi_long_read_resp(buf
, msg
);
2058 pr_warn("%s:Invalid response cmd\n", __func__
);
2065 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host
*host
, u32 dma_base
,
2068 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2070 dsi_write(msm_host
, REG_DSI_DMA_BASE
, dma_base
);
2071 dsi_write(msm_host
, REG_DSI_DMA_LEN
, len
);
2072 dsi_write(msm_host
, REG_DSI_TRIG_DMA
, 1);
2074 /* Make sure trigger happens */
2078 int msm_dsi_host_set_src_pll(struct mipi_dsi_host
*host
,
2079 struct msm_dsi_pll
*src_pll
)
2081 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2082 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
2083 struct clk
*byte_clk_provider
, *pixel_clk_provider
;
2086 ret
= msm_dsi_pll_get_clk_provider(src_pll
,
2087 &byte_clk_provider
, &pixel_clk_provider
);
2089 pr_info("%s: can't get provider from pll, don't set parent\n",
2094 ret
= clk_set_parent(msm_host
->byte_clk_src
, byte_clk_provider
);
2096 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2101 ret
= clk_set_parent(msm_host
->pixel_clk_src
, pixel_clk_provider
);
2103 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2108 if (cfg_hnd
->major
== MSM_DSI_VER_MAJOR_V2
) {
2109 ret
= clk_set_parent(msm_host
->dsi_clk_src
, pixel_clk_provider
);
2111 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2116 ret
= clk_set_parent(msm_host
->esc_clk_src
, byte_clk_provider
);
2118 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2128 void msm_dsi_host_reset_phy(struct mipi_dsi_host
*host
)
2130 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2133 dsi_write(msm_host
, REG_DSI_PHY_RESET
, DSI_PHY_RESET_RESET
);
2134 /* Make sure fully reset */
2137 dsi_write(msm_host
, REG_DSI_PHY_RESET
, 0);
2141 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host
*host
,
2142 struct msm_dsi_phy_clk_request
*clk_req
)
2144 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2147 ret
= dsi_calc_clk_rate(msm_host
);
2149 pr_err("%s: unable to calc clk rate, %d\n", __func__
, ret
);
2153 clk_req
->bitclk_rate
= msm_host
->byte_clk_rate
* 8;
2154 clk_req
->escclk_rate
= msm_host
->esc_clk_rate
;
2157 int msm_dsi_host_enable(struct mipi_dsi_host
*host
)
2159 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2161 dsi_op_mode_config(msm_host
,
2162 !!(msm_host
->mode_flags
& MIPI_DSI_MODE_VIDEO
), true);
2164 /* TODO: clock should be turned off for command mode,
2165 * and only turned on before MDP START.
2166 * This part of code should be enabled once mdp driver support it.
2168 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2169 * dsi_link_clk_disable(msm_host);
2170 * pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2177 int msm_dsi_host_disable(struct mipi_dsi_host
*host
)
2179 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2181 dsi_op_mode_config(msm_host
,
2182 !!(msm_host
->mode_flags
& MIPI_DSI_MODE_VIDEO
), false);
2184 /* Since we have disabled INTF, the video engine won't stop so that
2185 * the cmd engine will be blocked.
2186 * Reset to disable video engine so that we can send off cmd.
2188 dsi_sw_reset(msm_host
);
2193 static void msm_dsi_sfpb_config(struct msm_dsi_host
*msm_host
, bool enable
)
2195 enum sfpb_ahb_arb_master_port_en en
;
2197 if (!msm_host
->sfpb
)
2200 en
= enable
? SFPB_MASTER_PORT_ENABLE
: SFPB_MASTER_PORT_DISABLE
;
2202 regmap_update_bits(msm_host
->sfpb
, REG_SFPB_GPREG
,
2203 SFPB_GPREG_MASTER_PORT_EN__MASK
,
2204 SFPB_GPREG_MASTER_PORT_EN(en
));
2207 int msm_dsi_host_power_on(struct mipi_dsi_host
*host
,
2208 struct msm_dsi_phy_shared_timings
*phy_shared_timings
)
2210 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2213 mutex_lock(&msm_host
->dev_mutex
);
2214 if (msm_host
->power_on
) {
2215 DBG("dsi host already on");
2219 msm_dsi_sfpb_config(msm_host
, true);
2221 ret
= dsi_host_regulator_enable(msm_host
);
2223 pr_err("%s:Failed to enable vregs.ret=%d\n",
2228 pm_runtime_get_sync(&msm_host
->pdev
->dev
);
2229 ret
= dsi_link_clk_enable(msm_host
);
2231 pr_err("%s: failed to enable link clocks. ret=%d\n",
2233 goto fail_disable_reg
;
2236 ret
= pinctrl_pm_select_default_state(&msm_host
->pdev
->dev
);
2238 pr_err("%s: failed to set pinctrl default state, %d\n",
2240 goto fail_disable_clk
;
2243 dsi_timing_setup(msm_host
);
2244 dsi_sw_reset(msm_host
);
2245 dsi_ctrl_config(msm_host
, true, phy_shared_timings
);
2247 if (msm_host
->disp_en_gpio
)
2248 gpiod_set_value(msm_host
->disp_en_gpio
, 1);
2250 msm_host
->power_on
= true;
2251 mutex_unlock(&msm_host
->dev_mutex
);
2256 dsi_link_clk_disable(msm_host
);
2257 pm_runtime_put_autosuspend(&msm_host
->pdev
->dev
);
2259 dsi_host_regulator_disable(msm_host
);
2261 mutex_unlock(&msm_host
->dev_mutex
);
2265 int msm_dsi_host_power_off(struct mipi_dsi_host
*host
)
2267 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2269 mutex_lock(&msm_host
->dev_mutex
);
2270 if (!msm_host
->power_on
) {
2271 DBG("dsi host already off");
2275 dsi_ctrl_config(msm_host
, false, NULL
);
2277 if (msm_host
->disp_en_gpio
)
2278 gpiod_set_value(msm_host
->disp_en_gpio
, 0);
2280 pinctrl_pm_select_sleep_state(&msm_host
->pdev
->dev
);
2282 dsi_link_clk_disable(msm_host
);
2283 pm_runtime_put_autosuspend(&msm_host
->pdev
->dev
);
2285 dsi_host_regulator_disable(msm_host
);
2287 msm_dsi_sfpb_config(msm_host
, false);
2291 msm_host
->power_on
= false;
2294 mutex_unlock(&msm_host
->dev_mutex
);
2298 int msm_dsi_host_set_display_mode(struct mipi_dsi_host
*host
,
2299 struct drm_display_mode
*mode
)
2301 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2303 if (msm_host
->mode
) {
2304 drm_mode_destroy(msm_host
->dev
, msm_host
->mode
);
2305 msm_host
->mode
= NULL
;
2308 msm_host
->mode
= drm_mode_duplicate(msm_host
->dev
, mode
);
2309 if (!msm_host
->mode
) {
2310 pr_err("%s: cannot duplicate mode\n", __func__
);
2317 struct drm_panel
*msm_dsi_host_get_panel(struct mipi_dsi_host
*host
,
2318 unsigned long *panel_flags
)
2320 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2321 struct drm_panel
*panel
;
2323 panel
= of_drm_find_panel(msm_host
->device_node
);
2325 *panel_flags
= msm_host
->mode_flags
;
2330 struct drm_bridge
*msm_dsi_host_get_bridge(struct mipi_dsi_host
*host
)
2332 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2334 return of_drm_find_bridge(msm_host
->device_node
);