1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
9 #include <linux/gpio.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interrupt.h>
12 #include <linux/of_device.h>
13 #include <linux/of_gpio.h>
14 #include <linux/of_irq.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/of_graph.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/spinlock.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/regmap.h>
21 #include <video/mipi_display.h>
29 static int dsi_get_version(const void __iomem
*base
, u32
*major
, u32
*minor
)
37 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
38 * makes all other registers 4-byte shifted down.
40 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
41 * older, we read the DSI_VERSION register without any shift(offset
42 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
43 * the case of DSI6G, this has to be zero (the offset points to a
44 * scratch register which we never touch)
47 ver
= msm_readl(base
+ REG_DSI_VERSION
);
49 /* older dsi host, there is no register shift */
50 ver
= FIELD(ver
, DSI_VERSION_MAJOR
);
51 if (ver
<= MSM_DSI_VER_MAJOR_V2
) {
61 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
62 * registers are shifted down, read DSI_VERSION again with
65 ver
= msm_readl(base
+ DSI_6G_REG_SHIFT
+ REG_DSI_VERSION
);
66 ver
= FIELD(ver
, DSI_VERSION_MAJOR
);
67 if (ver
== MSM_DSI_VER_MAJOR_6G
) {
70 *minor
= msm_readl(base
+ REG_DSI_6G_HW_VERSION
);
78 #define DSI_ERR_STATE_ACK 0x0000
79 #define DSI_ERR_STATE_TIMEOUT 0x0001
80 #define DSI_ERR_STATE_DLN0_PHY 0x0002
81 #define DSI_ERR_STATE_FIFO 0x0004
82 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
83 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
84 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
86 #define DSI_CLK_CTRL_ENABLE_CLKS \
87 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
88 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
89 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
90 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
93 struct mipi_dsi_host base
;
95 struct platform_device
*pdev
;
96 struct drm_device
*dev
;
100 void __iomem
*ctrl_base
;
101 struct regulator_bulk_data supplies
[DSI_DEV_REGULATOR_MAX
];
103 struct clk
*bus_clks
[DSI_BUS_CLK_MAX
];
105 struct clk
*byte_clk
;
107 struct clk
*pixel_clk
;
108 struct clk
*byte_clk_src
;
109 struct clk
*pixel_clk_src
;
110 struct clk
*byte_intf_clk
;
116 /* DSI v2 specific clocks */
118 struct clk
*esc_clk_src
;
119 struct clk
*dsi_clk_src
;
123 struct gpio_desc
*disp_en_gpio
;
124 struct gpio_desc
*te_gpio
;
126 const struct msm_dsi_cfg_handler
*cfg_hnd
;
128 struct completion dma_comp
;
129 struct completion video_comp
;
130 struct mutex dev_mutex
;
131 struct mutex cmd_mutex
;
132 spinlock_t intr_lock
; /* Protect interrupt ctrl register */
135 struct work_struct err_work
;
136 struct work_struct hpd_work
;
137 struct workqueue_struct
*workqueue
;
139 /* DSI 6G TX buffer*/
140 struct drm_gem_object
*tx_gem_obj
;
142 /* DSI v2 TX buffer */
144 dma_addr_t tx_buf_paddr
;
152 struct drm_display_mode
*mode
;
154 /* connected device info */
155 struct device_node
*device_node
;
156 unsigned int channel
;
158 enum mipi_dsi_pixel_format format
;
159 unsigned long mode_flags
;
161 /* lane data parsed via DT */
165 u32 dma_cmd_ctrl_restore
;
173 static u32
dsi_get_bpp(const enum mipi_dsi_pixel_format fmt
)
176 case MIPI_DSI_FMT_RGB565
: return 16;
177 case MIPI_DSI_FMT_RGB666_PACKED
: return 18;
178 case MIPI_DSI_FMT_RGB666
:
179 case MIPI_DSI_FMT_RGB888
:
184 static inline u32
dsi_read(struct msm_dsi_host
*msm_host
, u32 reg
)
186 return msm_readl(msm_host
->ctrl_base
+ reg
);
188 static inline void dsi_write(struct msm_dsi_host
*msm_host
, u32 reg
, u32 data
)
190 msm_writel(data
, msm_host
->ctrl_base
+ reg
);
193 static int dsi_host_regulator_enable(struct msm_dsi_host
*msm_host
);
194 static void dsi_host_regulator_disable(struct msm_dsi_host
*msm_host
);
196 static const struct msm_dsi_cfg_handler
*dsi_get_config(
197 struct msm_dsi_host
*msm_host
)
199 const struct msm_dsi_cfg_handler
*cfg_hnd
= NULL
;
200 struct device
*dev
= &msm_host
->pdev
->dev
;
201 struct regulator
*gdsc_reg
;
204 u32 major
= 0, minor
= 0;
206 gdsc_reg
= regulator_get(dev
, "gdsc");
207 if (IS_ERR(gdsc_reg
)) {
208 pr_err("%s: cannot get gdsc\n", __func__
);
212 ahb_clk
= msm_clk_get(msm_host
->pdev
, "iface");
213 if (IS_ERR(ahb_clk
)) {
214 pr_err("%s: cannot get interface clock\n", __func__
);
218 pm_runtime_get_sync(dev
);
220 ret
= regulator_enable(gdsc_reg
);
222 pr_err("%s: unable to enable gdsc\n", __func__
);
226 ret
= clk_prepare_enable(ahb_clk
);
228 pr_err("%s: unable to enable ahb_clk\n", __func__
);
232 ret
= dsi_get_version(msm_host
->ctrl_base
, &major
, &minor
);
234 pr_err("%s: Invalid version\n", __func__
);
238 cfg_hnd
= msm_dsi_cfg_get(major
, minor
);
240 DBG("%s: Version %x:%x\n", __func__
, major
, minor
);
243 clk_disable_unprepare(ahb_clk
);
245 regulator_disable(gdsc_reg
);
246 pm_runtime_put_sync(dev
);
248 regulator_put(gdsc_reg
);
253 static inline struct msm_dsi_host
*to_msm_dsi_host(struct mipi_dsi_host
*host
)
255 return container_of(host
, struct msm_dsi_host
, base
);
258 static void dsi_host_regulator_disable(struct msm_dsi_host
*msm_host
)
260 struct regulator_bulk_data
*s
= msm_host
->supplies
;
261 const struct dsi_reg_entry
*regs
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.regs
;
262 int num
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.num
;
266 for (i
= num
- 1; i
>= 0; i
--)
267 if (regs
[i
].disable_load
>= 0)
268 regulator_set_load(s
[i
].consumer
,
269 regs
[i
].disable_load
);
271 regulator_bulk_disable(num
, s
);
274 static int dsi_host_regulator_enable(struct msm_dsi_host
*msm_host
)
276 struct regulator_bulk_data
*s
= msm_host
->supplies
;
277 const struct dsi_reg_entry
*regs
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.regs
;
278 int num
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.num
;
282 for (i
= 0; i
< num
; i
++) {
283 if (regs
[i
].enable_load
>= 0) {
284 ret
= regulator_set_load(s
[i
].consumer
,
285 regs
[i
].enable_load
);
287 pr_err("regulator %d set op mode failed, %d\n",
294 ret
= regulator_bulk_enable(num
, s
);
296 pr_err("regulator enable failed, %d\n", ret
);
303 for (i
--; i
>= 0; i
--)
304 regulator_set_load(s
[i
].consumer
, regs
[i
].disable_load
);
308 static int dsi_regulator_init(struct msm_dsi_host
*msm_host
)
310 struct regulator_bulk_data
*s
= msm_host
->supplies
;
311 const struct dsi_reg_entry
*regs
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.regs
;
312 int num
= msm_host
->cfg_hnd
->cfg
->reg_cfg
.num
;
315 for (i
= 0; i
< num
; i
++)
316 s
[i
].supply
= regs
[i
].name
;
318 ret
= devm_regulator_bulk_get(&msm_host
->pdev
->dev
, num
, s
);
320 pr_err("%s: failed to init regulator, ret=%d\n",
328 int dsi_clk_init_v2(struct msm_dsi_host
*msm_host
)
330 struct platform_device
*pdev
= msm_host
->pdev
;
333 msm_host
->src_clk
= msm_clk_get(pdev
, "src");
335 if (IS_ERR(msm_host
->src_clk
)) {
336 ret
= PTR_ERR(msm_host
->src_clk
);
337 pr_err("%s: can't find src clock. ret=%d\n",
339 msm_host
->src_clk
= NULL
;
343 msm_host
->esc_clk_src
= clk_get_parent(msm_host
->esc_clk
);
344 if (!msm_host
->esc_clk_src
) {
346 pr_err("%s: can't get esc clock parent. ret=%d\n",
351 msm_host
->dsi_clk_src
= clk_get_parent(msm_host
->src_clk
);
352 if (!msm_host
->dsi_clk_src
) {
354 pr_err("%s: can't get src clock parent. ret=%d\n",
361 int dsi_clk_init_6g_v2(struct msm_dsi_host
*msm_host
)
363 struct platform_device
*pdev
= msm_host
->pdev
;
366 msm_host
->byte_intf_clk
= msm_clk_get(pdev
, "byte_intf");
367 if (IS_ERR(msm_host
->byte_intf_clk
)) {
368 ret
= PTR_ERR(msm_host
->byte_intf_clk
);
369 pr_err("%s: can't find byte_intf clock. ret=%d\n",
376 static int dsi_clk_init(struct msm_dsi_host
*msm_host
)
378 struct platform_device
*pdev
= msm_host
->pdev
;
379 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
380 const struct msm_dsi_config
*cfg
= cfg_hnd
->cfg
;
384 for (i
= 0; i
< cfg
->num_bus_clks
; i
++) {
385 msm_host
->bus_clks
[i
] = msm_clk_get(pdev
,
386 cfg
->bus_clk_names
[i
]);
387 if (IS_ERR(msm_host
->bus_clks
[i
])) {
388 ret
= PTR_ERR(msm_host
->bus_clks
[i
]);
389 pr_err("%s: Unable to get %s clock, ret = %d\n",
390 __func__
, cfg
->bus_clk_names
[i
], ret
);
395 /* get link and source clocks */
396 msm_host
->byte_clk
= msm_clk_get(pdev
, "byte");
397 if (IS_ERR(msm_host
->byte_clk
)) {
398 ret
= PTR_ERR(msm_host
->byte_clk
);
399 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
401 msm_host
->byte_clk
= NULL
;
405 msm_host
->pixel_clk
= msm_clk_get(pdev
, "pixel");
406 if (IS_ERR(msm_host
->pixel_clk
)) {
407 ret
= PTR_ERR(msm_host
->pixel_clk
);
408 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
410 msm_host
->pixel_clk
= NULL
;
414 msm_host
->esc_clk
= msm_clk_get(pdev
, "core");
415 if (IS_ERR(msm_host
->esc_clk
)) {
416 ret
= PTR_ERR(msm_host
->esc_clk
);
417 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
419 msm_host
->esc_clk
= NULL
;
423 msm_host
->byte_clk_src
= clk_get_parent(msm_host
->byte_clk
);
424 if (!msm_host
->byte_clk_src
) {
426 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__
, ret
);
430 msm_host
->pixel_clk_src
= clk_get_parent(msm_host
->pixel_clk
);
431 if (!msm_host
->pixel_clk_src
) {
433 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__
, ret
);
437 if (cfg_hnd
->ops
->clk_init_ver
)
438 ret
= cfg_hnd
->ops
->clk_init_ver(msm_host
);
443 static int dsi_bus_clk_enable(struct msm_dsi_host
*msm_host
)
445 const struct msm_dsi_config
*cfg
= msm_host
->cfg_hnd
->cfg
;
448 DBG("id=%d", msm_host
->id
);
450 for (i
= 0; i
< cfg
->num_bus_clks
; i
++) {
451 ret
= clk_prepare_enable(msm_host
->bus_clks
[i
]);
453 pr_err("%s: failed to enable bus clock %d ret %d\n",
462 clk_disable_unprepare(msm_host
->bus_clks
[i
]);
467 static void dsi_bus_clk_disable(struct msm_dsi_host
*msm_host
)
469 const struct msm_dsi_config
*cfg
= msm_host
->cfg_hnd
->cfg
;
474 for (i
= cfg
->num_bus_clks
- 1; i
>= 0; i
--)
475 clk_disable_unprepare(msm_host
->bus_clks
[i
]);
478 int msm_dsi_runtime_suspend(struct device
*dev
)
480 struct platform_device
*pdev
= to_platform_device(dev
);
481 struct msm_dsi
*msm_dsi
= platform_get_drvdata(pdev
);
482 struct mipi_dsi_host
*host
= msm_dsi
->host
;
483 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
485 if (!msm_host
->cfg_hnd
)
488 dsi_bus_clk_disable(msm_host
);
493 int msm_dsi_runtime_resume(struct device
*dev
)
495 struct platform_device
*pdev
= to_platform_device(dev
);
496 struct msm_dsi
*msm_dsi
= platform_get_drvdata(pdev
);
497 struct mipi_dsi_host
*host
= msm_dsi
->host
;
498 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
500 if (!msm_host
->cfg_hnd
)
503 return dsi_bus_clk_enable(msm_host
);
506 int dsi_link_clk_enable_6g(struct msm_dsi_host
*msm_host
)
510 DBG("Set clk rates: pclk=%d, byteclk=%d",
511 msm_host
->mode
->clock
, msm_host
->byte_clk_rate
);
513 ret
= clk_set_rate(msm_host
->byte_clk
, msm_host
->byte_clk_rate
);
515 pr_err("%s: Failed to set rate byte clk, %d\n", __func__
, ret
);
519 ret
= clk_set_rate(msm_host
->pixel_clk
, msm_host
->pixel_clk_rate
);
521 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__
, ret
);
525 if (msm_host
->byte_intf_clk
) {
526 ret
= clk_set_rate(msm_host
->byte_intf_clk
,
527 msm_host
->byte_clk_rate
/ 2);
529 pr_err("%s: Failed to set rate byte intf clk, %d\n",
535 ret
= clk_prepare_enable(msm_host
->esc_clk
);
537 pr_err("%s: Failed to enable dsi esc clk\n", __func__
);
541 ret
= clk_prepare_enable(msm_host
->byte_clk
);
543 pr_err("%s: Failed to enable dsi byte clk\n", __func__
);
547 ret
= clk_prepare_enable(msm_host
->pixel_clk
);
549 pr_err("%s: Failed to enable dsi pixel clk\n", __func__
);
553 if (msm_host
->byte_intf_clk
) {
554 ret
= clk_prepare_enable(msm_host
->byte_intf_clk
);
556 pr_err("%s: Failed to enable byte intf clk\n",
558 goto byte_intf_clk_err
;
565 clk_disable_unprepare(msm_host
->pixel_clk
);
567 clk_disable_unprepare(msm_host
->byte_clk
);
569 clk_disable_unprepare(msm_host
->esc_clk
);
574 int dsi_link_clk_enable_v2(struct msm_dsi_host
*msm_host
)
578 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d",
579 msm_host
->mode
->clock
, msm_host
->byte_clk_rate
,
580 msm_host
->esc_clk_rate
, msm_host
->src_clk_rate
);
582 ret
= clk_set_rate(msm_host
->byte_clk
, msm_host
->byte_clk_rate
);
584 pr_err("%s: Failed to set rate byte clk, %d\n", __func__
, ret
);
588 ret
= clk_set_rate(msm_host
->esc_clk
, msm_host
->esc_clk_rate
);
590 pr_err("%s: Failed to set rate esc clk, %d\n", __func__
, ret
);
594 ret
= clk_set_rate(msm_host
->src_clk
, msm_host
->src_clk_rate
);
596 pr_err("%s: Failed to set rate src clk, %d\n", __func__
, ret
);
600 ret
= clk_set_rate(msm_host
->pixel_clk
, msm_host
->pixel_clk_rate
);
602 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__
, ret
);
606 ret
= clk_prepare_enable(msm_host
->byte_clk
);
608 pr_err("%s: Failed to enable dsi byte clk\n", __func__
);
612 ret
= clk_prepare_enable(msm_host
->esc_clk
);
614 pr_err("%s: Failed to enable dsi esc clk\n", __func__
);
618 ret
= clk_prepare_enable(msm_host
->src_clk
);
620 pr_err("%s: Failed to enable dsi src clk\n", __func__
);
624 ret
= clk_prepare_enable(msm_host
->pixel_clk
);
626 pr_err("%s: Failed to enable dsi pixel clk\n", __func__
);
633 clk_disable_unprepare(msm_host
->src_clk
);
635 clk_disable_unprepare(msm_host
->esc_clk
);
637 clk_disable_unprepare(msm_host
->byte_clk
);
642 void dsi_link_clk_disable_6g(struct msm_dsi_host
*msm_host
)
644 clk_disable_unprepare(msm_host
->esc_clk
);
645 clk_disable_unprepare(msm_host
->pixel_clk
);
646 if (msm_host
->byte_intf_clk
)
647 clk_disable_unprepare(msm_host
->byte_intf_clk
);
648 clk_disable_unprepare(msm_host
->byte_clk
);
651 void dsi_link_clk_disable_v2(struct msm_dsi_host
*msm_host
)
653 clk_disable_unprepare(msm_host
->pixel_clk
);
654 clk_disable_unprepare(msm_host
->src_clk
);
655 clk_disable_unprepare(msm_host
->esc_clk
);
656 clk_disable_unprepare(msm_host
->byte_clk
);
659 static u32
dsi_get_pclk_rate(struct msm_dsi_host
*msm_host
, bool is_dual_dsi
)
661 struct drm_display_mode
*mode
= msm_host
->mode
;
664 pclk_rate
= mode
->clock
* 1000;
667 * For dual DSI mode, the current DRM mode has the complete width of the
668 * panel. Since, the complete panel is driven by two DSI controllers,
669 * the clock rates have to be split between the two dsi controllers.
670 * Adjust the byte and pixel clock rates for each dsi host accordingly.
678 static void dsi_calc_pclk(struct msm_dsi_host
*msm_host
, bool is_dual_dsi
)
680 u8 lanes
= msm_host
->lanes
;
681 u32 bpp
= dsi_get_bpp(msm_host
->format
);
682 u32 pclk_rate
= dsi_get_pclk_rate(msm_host
, is_dual_dsi
);
683 u64 pclk_bpp
= (u64
)pclk_rate
* bpp
;
686 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__
);
690 do_div(pclk_bpp
, (8 * lanes
));
692 msm_host
->pixel_clk_rate
= pclk_rate
;
693 msm_host
->byte_clk_rate
= pclk_bpp
;
695 DBG("pclk=%d, bclk=%d", msm_host
->pixel_clk_rate
,
696 msm_host
->byte_clk_rate
);
700 int dsi_calc_clk_rate_6g(struct msm_dsi_host
*msm_host
, bool is_dual_dsi
)
702 if (!msm_host
->mode
) {
703 pr_err("%s: mode not set\n", __func__
);
707 dsi_calc_pclk(msm_host
, is_dual_dsi
);
708 msm_host
->esc_clk_rate
= clk_get_rate(msm_host
->esc_clk
);
712 int dsi_calc_clk_rate_v2(struct msm_dsi_host
*msm_host
, bool is_dual_dsi
)
714 u32 bpp
= dsi_get_bpp(msm_host
->format
);
716 unsigned int esc_mhz
, esc_div
;
717 unsigned long byte_mhz
;
719 dsi_calc_pclk(msm_host
, is_dual_dsi
);
721 pclk_bpp
= (u64
)dsi_get_pclk_rate(msm_host
, is_dual_dsi
) * bpp
;
723 msm_host
->src_clk_rate
= pclk_bpp
;
726 * esc clock is byte clock followed by a 4 bit divider,
727 * we need to find an escape clock frequency within the
728 * mipi DSI spec range within the maximum divider limit
729 * We iterate here between an escape clock frequencey
730 * between 20 Mhz to 5 Mhz and pick up the first one
731 * that can be supported by our divider
734 byte_mhz
= msm_host
->byte_clk_rate
/ 1000000;
736 for (esc_mhz
= 20; esc_mhz
>= 5; esc_mhz
--) {
737 esc_div
= DIV_ROUND_UP(byte_mhz
, esc_mhz
);
740 * TODO: Ideally, we shouldn't know what sort of divider
741 * is available in mmss_cc, we're just assuming that
742 * it'll always be a 4 bit divider. Need to come up with
745 if (esc_div
>= 1 && esc_div
<= 16)
752 msm_host
->esc_clk_rate
= msm_host
->byte_clk_rate
/ esc_div
;
754 DBG("esc=%d, src=%d", msm_host
->esc_clk_rate
,
755 msm_host
->src_clk_rate
);
760 static void dsi_intr_ctrl(struct msm_dsi_host
*msm_host
, u32 mask
, int enable
)
765 spin_lock_irqsave(&msm_host
->intr_lock
, flags
);
766 intr
= dsi_read(msm_host
, REG_DSI_INTR_CTRL
);
773 DBG("intr=%x enable=%d", intr
, enable
);
775 dsi_write(msm_host
, REG_DSI_INTR_CTRL
, intr
);
776 spin_unlock_irqrestore(&msm_host
->intr_lock
, flags
);
779 static inline enum dsi_traffic_mode
dsi_get_traffic_mode(const u32 mode_flags
)
781 if (mode_flags
& MIPI_DSI_MODE_VIDEO_BURST
)
783 else if (mode_flags
& MIPI_DSI_MODE_VIDEO_SYNC_PULSE
)
784 return NON_BURST_SYNCH_PULSE
;
786 return NON_BURST_SYNCH_EVENT
;
789 static inline enum dsi_vid_dst_format
dsi_get_vid_fmt(
790 const enum mipi_dsi_pixel_format mipi_fmt
)
793 case MIPI_DSI_FMT_RGB888
: return VID_DST_FORMAT_RGB888
;
794 case MIPI_DSI_FMT_RGB666
: return VID_DST_FORMAT_RGB666_LOOSE
;
795 case MIPI_DSI_FMT_RGB666_PACKED
: return VID_DST_FORMAT_RGB666
;
796 case MIPI_DSI_FMT_RGB565
: return VID_DST_FORMAT_RGB565
;
797 default: return VID_DST_FORMAT_RGB888
;
801 static inline enum dsi_cmd_dst_format
dsi_get_cmd_fmt(
802 const enum mipi_dsi_pixel_format mipi_fmt
)
805 case MIPI_DSI_FMT_RGB888
: return CMD_DST_FORMAT_RGB888
;
806 case MIPI_DSI_FMT_RGB666_PACKED
:
807 case MIPI_DSI_FMT_RGB666
: return CMD_DST_FORMAT_RGB666
;
808 case MIPI_DSI_FMT_RGB565
: return CMD_DST_FORMAT_RGB565
;
809 default: return CMD_DST_FORMAT_RGB888
;
813 static void dsi_ctrl_config(struct msm_dsi_host
*msm_host
, bool enable
,
814 struct msm_dsi_phy_shared_timings
*phy_shared_timings
)
816 u32 flags
= msm_host
->mode_flags
;
817 enum mipi_dsi_pixel_format mipi_fmt
= msm_host
->format
;
818 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
822 dsi_write(msm_host
, REG_DSI_CTRL
, 0);
826 if (flags
& MIPI_DSI_MODE_VIDEO
) {
827 if (flags
& MIPI_DSI_MODE_VIDEO_HSE
)
828 data
|= DSI_VID_CFG0_PULSE_MODE_HSA_HE
;
829 if (flags
& MIPI_DSI_MODE_VIDEO_HFP
)
830 data
|= DSI_VID_CFG0_HFP_POWER_STOP
;
831 if (flags
& MIPI_DSI_MODE_VIDEO_HBP
)
832 data
|= DSI_VID_CFG0_HBP_POWER_STOP
;
833 if (flags
& MIPI_DSI_MODE_VIDEO_HSA
)
834 data
|= DSI_VID_CFG0_HSA_POWER_STOP
;
835 /* Always set low power stop mode for BLLP
836 * to let command engine send packets
838 data
|= DSI_VID_CFG0_EOF_BLLP_POWER_STOP
|
839 DSI_VID_CFG0_BLLP_POWER_STOP
;
840 data
|= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags
));
841 data
|= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt
));
842 data
|= DSI_VID_CFG0_VIRT_CHANNEL(msm_host
->channel
);
843 dsi_write(msm_host
, REG_DSI_VID_CFG0
, data
);
845 /* Do not swap RGB colors */
846 data
= DSI_VID_CFG1_RGB_SWAP(SWAP_RGB
);
847 dsi_write(msm_host
, REG_DSI_VID_CFG1
, 0);
849 /* Do not swap RGB colors */
850 data
= DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB
);
851 data
|= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt
));
852 dsi_write(msm_host
, REG_DSI_CMD_CFG0
, data
);
854 data
= DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START
) |
855 DSI_CMD_CFG1_WR_MEM_CONTINUE(
856 MIPI_DCS_WRITE_MEMORY_CONTINUE
);
857 /* Always insert DCS command */
858 data
|= DSI_CMD_CFG1_INSERT_DCS_COMMAND
;
859 dsi_write(msm_host
, REG_DSI_CMD_CFG1
, data
);
862 dsi_write(msm_host
, REG_DSI_CMD_DMA_CTRL
,
863 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER
|
864 DSI_CMD_DMA_CTRL_LOW_POWER
);
867 /* Always assume dedicated TE pin */
868 data
|= DSI_TRIG_CTRL_TE
;
869 data
|= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE
);
870 data
|= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW
);
871 data
|= DSI_TRIG_CTRL_STREAM(msm_host
->channel
);
872 if ((cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
) &&
873 (cfg_hnd
->minor
>= MSM_DSI_6G_VER_MINOR_V1_2
))
874 data
|= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME
;
875 dsi_write(msm_host
, REG_DSI_TRIG_CTRL
, data
);
877 data
= DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings
->clk_post
) |
878 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings
->clk_pre
);
879 dsi_write(msm_host
, REG_DSI_CLKOUT_TIMING_CTRL
, data
);
881 if ((cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
) &&
882 (cfg_hnd
->minor
> MSM_DSI_6G_VER_MINOR_V1_0
) &&
883 phy_shared_timings
->clk_pre_inc_by_2
)
884 dsi_write(msm_host
, REG_DSI_T_CLK_PRE_EXTEND
,
885 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK
);
888 if (!(flags
& MIPI_DSI_MODE_EOT_PACKET
))
889 data
|= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND
;
890 dsi_write(msm_host
, REG_DSI_EOT_PACKET_CTRL
, data
);
892 /* allow only ack-err-status to generate interrupt */
893 dsi_write(msm_host
, REG_DSI_ERR_INT_MASK0
, 0x13ff3fe0);
895 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_ERROR
, 1);
897 dsi_write(msm_host
, REG_DSI_CLK_CTRL
, DSI_CLK_CTRL_ENABLE_CLKS
);
899 data
= DSI_CTRL_CLK_EN
;
901 DBG("lane number=%d", msm_host
->lanes
);
902 data
|= ((DSI_CTRL_LANE0
<< msm_host
->lanes
) - DSI_CTRL_LANE0
);
904 dsi_write(msm_host
, REG_DSI_LANE_SWAP_CTRL
,
905 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host
->dlane_swap
));
907 if (!(flags
& MIPI_DSI_CLOCK_NON_CONTINUOUS
))
908 dsi_write(msm_host
, REG_DSI_LANE_CTRL
,
909 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST
);
911 data
|= DSI_CTRL_ENABLE
;
913 dsi_write(msm_host
, REG_DSI_CTRL
, data
);
916 static void dsi_timing_setup(struct msm_dsi_host
*msm_host
, bool is_dual_dsi
)
918 struct drm_display_mode
*mode
= msm_host
->mode
;
919 u32 hs_start
= 0, vs_start
= 0; /* take sync start as 0 */
920 u32 h_total
= mode
->htotal
;
921 u32 v_total
= mode
->vtotal
;
922 u32 hs_end
= mode
->hsync_end
- mode
->hsync_start
;
923 u32 vs_end
= mode
->vsync_end
- mode
->vsync_start
;
924 u32 ha_start
= h_total
- mode
->hsync_start
;
925 u32 ha_end
= ha_start
+ mode
->hdisplay
;
926 u32 va_start
= v_total
- mode
->vsync_start
;
927 u32 va_end
= va_start
+ mode
->vdisplay
;
928 u32 hdisplay
= mode
->hdisplay
;
934 * For dual DSI mode, the current DRM mode has
935 * the complete width of the panel. Since, the complete
936 * panel is driven by two DSI controllers, the horizontal
937 * timings have to be split between the two dsi controllers.
938 * Adjust the DSI host timing values accordingly.
948 if (msm_host
->mode_flags
& MIPI_DSI_MODE_VIDEO
) {
949 dsi_write(msm_host
, REG_DSI_ACTIVE_H
,
950 DSI_ACTIVE_H_START(ha_start
) |
951 DSI_ACTIVE_H_END(ha_end
));
952 dsi_write(msm_host
, REG_DSI_ACTIVE_V
,
953 DSI_ACTIVE_V_START(va_start
) |
954 DSI_ACTIVE_V_END(va_end
));
955 dsi_write(msm_host
, REG_DSI_TOTAL
,
956 DSI_TOTAL_H_TOTAL(h_total
- 1) |
957 DSI_TOTAL_V_TOTAL(v_total
- 1));
959 dsi_write(msm_host
, REG_DSI_ACTIVE_HSYNC
,
960 DSI_ACTIVE_HSYNC_START(hs_start
) |
961 DSI_ACTIVE_HSYNC_END(hs_end
));
962 dsi_write(msm_host
, REG_DSI_ACTIVE_VSYNC_HPOS
, 0);
963 dsi_write(msm_host
, REG_DSI_ACTIVE_VSYNC_VPOS
,
964 DSI_ACTIVE_VSYNC_VPOS_START(vs_start
) |
965 DSI_ACTIVE_VSYNC_VPOS_END(vs_end
));
966 } else { /* command mode */
967 /* image data and 1 byte write_memory_start cmd */
968 wc
= hdisplay
* dsi_get_bpp(msm_host
->format
) / 8 + 1;
970 dsi_write(msm_host
, REG_DSI_CMD_MDP_STREAM_CTRL
,
971 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc
) |
972 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
974 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
975 MIPI_DSI_DCS_LONG_WRITE
));
977 dsi_write(msm_host
, REG_DSI_CMD_MDP_STREAM_TOTAL
,
978 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay
) |
979 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode
->vdisplay
));
983 static void dsi_sw_reset(struct msm_dsi_host
*msm_host
)
985 dsi_write(msm_host
, REG_DSI_CLK_CTRL
, DSI_CLK_CTRL_ENABLE_CLKS
);
986 wmb(); /* clocks need to be enabled before reset */
988 dsi_write(msm_host
, REG_DSI_RESET
, 1);
989 wmb(); /* make sure reset happen */
990 dsi_write(msm_host
, REG_DSI_RESET
, 0);
993 static void dsi_op_mode_config(struct msm_dsi_host
*msm_host
,
994 bool video_mode
, bool enable
)
998 dsi_ctrl
= dsi_read(msm_host
, REG_DSI_CTRL
);
1001 dsi_ctrl
&= ~(DSI_CTRL_ENABLE
| DSI_CTRL_VID_MODE_EN
|
1002 DSI_CTRL_CMD_MODE_EN
);
1003 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_CMD_MDP_DONE
|
1004 DSI_IRQ_MASK_VIDEO_DONE
, 0);
1007 dsi_ctrl
|= DSI_CTRL_VID_MODE_EN
;
1008 } else { /* command mode */
1009 dsi_ctrl
|= DSI_CTRL_CMD_MODE_EN
;
1010 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_CMD_MDP_DONE
, 1);
1012 dsi_ctrl
|= DSI_CTRL_ENABLE
;
1015 dsi_write(msm_host
, REG_DSI_CTRL
, dsi_ctrl
);
1018 static void dsi_set_tx_power_mode(int mode
, struct msm_dsi_host
*msm_host
)
1022 data
= dsi_read(msm_host
, REG_DSI_CMD_DMA_CTRL
);
1025 data
&= ~DSI_CMD_DMA_CTRL_LOW_POWER
;
1027 data
|= DSI_CMD_DMA_CTRL_LOW_POWER
;
1029 dsi_write(msm_host
, REG_DSI_CMD_DMA_CTRL
, data
);
1032 static void dsi_wait4video_done(struct msm_dsi_host
*msm_host
)
1035 struct device
*dev
= &msm_host
->pdev
->dev
;
1037 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_VIDEO_DONE
, 1);
1039 reinit_completion(&msm_host
->video_comp
);
1041 ret
= wait_for_completion_timeout(&msm_host
->video_comp
,
1042 msecs_to_jiffies(70));
1045 DRM_DEV_ERROR(dev
, "wait for video done timed out\n");
1047 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_VIDEO_DONE
, 0);
1050 static void dsi_wait4video_eng_busy(struct msm_dsi_host
*msm_host
)
1052 if (!(msm_host
->mode_flags
& MIPI_DSI_MODE_VIDEO
))
1055 if (msm_host
->power_on
&& msm_host
->enabled
) {
1056 dsi_wait4video_done(msm_host
);
1057 /* delay 4 ms to skip BLLP */
1058 usleep_range(2000, 4000);
1062 int dsi_tx_buf_alloc_6g(struct msm_dsi_host
*msm_host
, int size
)
1064 struct drm_device
*dev
= msm_host
->dev
;
1065 struct msm_drm_private
*priv
= dev
->dev_private
;
1069 data
= msm_gem_kernel_new(dev
, size
, MSM_BO_UNCACHED
,
1071 &msm_host
->tx_gem_obj
, &iova
);
1074 msm_host
->tx_gem_obj
= NULL
;
1075 return PTR_ERR(data
);
1078 msm_gem_object_set_name(msm_host
->tx_gem_obj
, "tx_gem");
1080 msm_host
->tx_size
= msm_host
->tx_gem_obj
->size
;
1085 int dsi_tx_buf_alloc_v2(struct msm_dsi_host
*msm_host
, int size
)
1087 struct drm_device
*dev
= msm_host
->dev
;
1089 msm_host
->tx_buf
= dma_alloc_coherent(dev
->dev
, size
,
1090 &msm_host
->tx_buf_paddr
, GFP_KERNEL
);
1091 if (!msm_host
->tx_buf
)
1094 msm_host
->tx_size
= size
;
1099 static void dsi_tx_buf_free(struct msm_dsi_host
*msm_host
)
1101 struct drm_device
*dev
= msm_host
->dev
;
1102 struct msm_drm_private
*priv
;
1105 * This is possible if we're tearing down before we've had a chance to
1106 * fully initialize. A very real possibility if our probe is deferred,
1107 * in which case we'll hit msm_dsi_host_destroy() without having run
1108 * through the dsi_tx_buf_alloc().
1113 priv
= dev
->dev_private
;
1114 if (msm_host
->tx_gem_obj
) {
1115 msm_gem_unpin_iova(msm_host
->tx_gem_obj
, priv
->kms
->aspace
);
1116 drm_gem_object_put_unlocked(msm_host
->tx_gem_obj
);
1117 msm_host
->tx_gem_obj
= NULL
;
1120 if (msm_host
->tx_buf
)
1121 dma_free_coherent(dev
->dev
, msm_host
->tx_size
, msm_host
->tx_buf
,
1122 msm_host
->tx_buf_paddr
);
1125 void *dsi_tx_buf_get_6g(struct msm_dsi_host
*msm_host
)
1127 return msm_gem_get_vaddr(msm_host
->tx_gem_obj
);
1130 void *dsi_tx_buf_get_v2(struct msm_dsi_host
*msm_host
)
1132 return msm_host
->tx_buf
;
1135 void dsi_tx_buf_put_6g(struct msm_dsi_host
*msm_host
)
1137 msm_gem_put_vaddr(msm_host
->tx_gem_obj
);
1141 * prepare cmd buffer to be txed
1143 static int dsi_cmd_dma_add(struct msm_dsi_host
*msm_host
,
1144 const struct mipi_dsi_msg
*msg
)
1146 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
1147 struct mipi_dsi_packet packet
;
1152 ret
= mipi_dsi_create_packet(&packet
, msg
);
1154 pr_err("%s: create packet failed, %d\n", __func__
, ret
);
1157 len
= (packet
.size
+ 3) & (~0x3);
1159 if (len
> msm_host
->tx_size
) {
1160 pr_err("%s: packet size is too big\n", __func__
);
1164 data
= cfg_hnd
->ops
->tx_buf_get(msm_host
);
1166 ret
= PTR_ERR(data
);
1167 pr_err("%s: get vaddr failed, %d\n", __func__
, ret
);
1171 /* MSM specific command format in memory */
1172 data
[0] = packet
.header
[1];
1173 data
[1] = packet
.header
[2];
1174 data
[2] = packet
.header
[0];
1175 data
[3] = BIT(7); /* Last packet */
1176 if (mipi_dsi_packet_format_is_long(msg
->type
))
1178 if (msg
->rx_buf
&& msg
->rx_len
)
1182 if (packet
.payload
&& packet
.payload_length
)
1183 memcpy(data
+ 4, packet
.payload
, packet
.payload_length
);
1185 /* Append 0xff to the end */
1186 if (packet
.size
< len
)
1187 memset(data
+ packet
.size
, 0xff, len
- packet
.size
);
1189 if (cfg_hnd
->ops
->tx_buf_put
)
1190 cfg_hnd
->ops
->tx_buf_put(msm_host
);
1196 * dsi_short_read1_resp: 1 parameter
1198 static int dsi_short_read1_resp(u8
*buf
, const struct mipi_dsi_msg
*msg
)
1200 u8
*data
= msg
->rx_buf
;
1201 if (data
&& (msg
->rx_len
>= 1)) {
1202 *data
= buf
[1]; /* strip out dcs type */
1205 pr_err("%s: read data does not match with rx_buf len %zu\n",
1206 __func__
, msg
->rx_len
);
1212 * dsi_short_read2_resp: 2 parameter
1214 static int dsi_short_read2_resp(u8
*buf
, const struct mipi_dsi_msg
*msg
)
1216 u8
*data
= msg
->rx_buf
;
1217 if (data
&& (msg
->rx_len
>= 2)) {
1218 data
[0] = buf
[1]; /* strip out dcs type */
1222 pr_err("%s: read data does not match with rx_buf len %zu\n",
1223 __func__
, msg
->rx_len
);
1228 static int dsi_long_read_resp(u8
*buf
, const struct mipi_dsi_msg
*msg
)
1230 /* strip out 4 byte dcs header */
1231 if (msg
->rx_buf
&& msg
->rx_len
)
1232 memcpy(msg
->rx_buf
, buf
+ 4, msg
->rx_len
);
1237 int dsi_dma_base_get_6g(struct msm_dsi_host
*msm_host
, uint64_t *dma_base
)
1239 struct drm_device
*dev
= msm_host
->dev
;
1240 struct msm_drm_private
*priv
= dev
->dev_private
;
1245 return msm_gem_get_and_pin_iova(msm_host
->tx_gem_obj
,
1246 priv
->kms
->aspace
, dma_base
);
1249 int dsi_dma_base_get_v2(struct msm_dsi_host
*msm_host
, uint64_t *dma_base
)
1254 *dma_base
= msm_host
->tx_buf_paddr
;
1258 static int dsi_cmd_dma_tx(struct msm_dsi_host
*msm_host
, int len
)
1260 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
1265 ret
= cfg_hnd
->ops
->dma_base_get(msm_host
, &dma_base
);
1267 pr_err("%s: failed to get iova: %d\n", __func__
, ret
);
1271 reinit_completion(&msm_host
->dma_comp
);
1273 dsi_wait4video_eng_busy(msm_host
);
1275 triggered
= msm_dsi_manager_cmd_xfer_trigger(
1276 msm_host
->id
, dma_base
, len
);
1278 ret
= wait_for_completion_timeout(&msm_host
->dma_comp
,
1279 msecs_to_jiffies(200));
1291 static int dsi_cmd_dma_rx(struct msm_dsi_host
*msm_host
,
1292 u8
*buf
, int rx_byte
, int pkt_size
)
1294 u32
*lp
, *temp
, data
;
1298 int repeated_bytes
= 0;
1299 int buf_offset
= buf
- msm_host
->rx_buf
;
1303 cnt
= (rx_byte
+ 3) >> 2;
1305 cnt
= 4; /* 4 x 32 bits registers only */
1310 read_cnt
= pkt_size
+ 6;
1313 * In case of multiple reads from the panel, after the first read, there
1314 * is possibility that there are some bytes in the payload repeating in
1315 * the RDBK_DATA registers. Since we read all the parameters from the
1316 * panel right from the first byte for every pass. We need to skip the
1317 * repeating bytes and then append the new parameters to the rx buffer.
1319 if (read_cnt
> 16) {
1321 /* Any data more than 16 bytes will be shifted out.
1322 * The temp read buffer should already contain these bytes.
1323 * The remaining bytes in read buffer are the repeated bytes.
1325 bytes_shifted
= read_cnt
- 16;
1326 repeated_bytes
= buf_offset
- bytes_shifted
;
1329 for (i
= cnt
- 1; i
>= 0; i
--) {
1330 data
= dsi_read(msm_host
, REG_DSI_RDBK_DATA(i
));
1331 *temp
++ = ntohl(data
); /* to host byte order */
1332 DBG("data = 0x%x and ntohl(data) = 0x%x", data
, ntohl(data
));
1335 for (i
= repeated_bytes
; i
< 16; i
++)
1341 static int dsi_cmds2buf_tx(struct msm_dsi_host
*msm_host
,
1342 const struct mipi_dsi_msg
*msg
)
1345 int bllp_len
= msm_host
->mode
->hdisplay
*
1346 dsi_get_bpp(msm_host
->format
) / 8;
1348 len
= dsi_cmd_dma_add(msm_host
, msg
);
1350 pr_err("%s: failed to add cmd type = 0x%x\n",
1351 __func__
, msg
->type
);
1355 /* for video mode, do not send cmds more than
1356 * one pixel line, since it only transmit it
1359 /* TODO: if the command is sent in LP mode, the bit rate is only
1360 * half of esc clk rate. In this case, if the video is already
1361 * actively streaming, we need to check more carefully if the
1362 * command can be fit into one BLLP.
1364 if ((msm_host
->mode_flags
& MIPI_DSI_MODE_VIDEO
) && (len
> bllp_len
)) {
1365 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1370 ret
= dsi_cmd_dma_tx(msm_host
, len
);
1372 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n",
1373 __func__
, msg
->type
, (*(u8
*)(msg
->tx_buf
)), len
);
1380 static void dsi_sw_reset_restore(struct msm_dsi_host
*msm_host
)
1384 data0
= dsi_read(msm_host
, REG_DSI_CTRL
);
1386 data1
&= ~DSI_CTRL_ENABLE
;
1387 dsi_write(msm_host
, REG_DSI_CTRL
, data1
);
1389 * dsi controller need to be disabled before
1394 dsi_write(msm_host
, REG_DSI_CLK_CTRL
, DSI_CLK_CTRL_ENABLE_CLKS
);
1395 wmb(); /* make sure clocks enabled */
1397 /* dsi controller can only be reset while clocks are running */
1398 dsi_write(msm_host
, REG_DSI_RESET
, 1);
1399 wmb(); /* make sure reset happen */
1400 dsi_write(msm_host
, REG_DSI_RESET
, 0);
1401 wmb(); /* controller out of reset */
1402 dsi_write(msm_host
, REG_DSI_CTRL
, data0
);
1403 wmb(); /* make sure dsi controller enabled again */
1406 static void dsi_hpd_worker(struct work_struct
*work
)
1408 struct msm_dsi_host
*msm_host
=
1409 container_of(work
, struct msm_dsi_host
, hpd_work
);
1411 drm_helper_hpd_irq_event(msm_host
->dev
);
1414 static void dsi_err_worker(struct work_struct
*work
)
1416 struct msm_dsi_host
*msm_host
=
1417 container_of(work
, struct msm_dsi_host
, err_work
);
1418 u32 status
= msm_host
->err_work_state
;
1420 pr_err_ratelimited("%s: status=%x\n", __func__
, status
);
1421 if (status
& DSI_ERR_STATE_MDP_FIFO_UNDERFLOW
)
1422 dsi_sw_reset_restore(msm_host
);
1424 /* It is safe to clear here because error irq is disabled. */
1425 msm_host
->err_work_state
= 0;
1427 /* enable dsi error interrupt */
1428 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_ERROR
, 1);
1431 static void dsi_ack_err_status(struct msm_dsi_host
*msm_host
)
1435 status
= dsi_read(msm_host
, REG_DSI_ACK_ERR_STATUS
);
1438 dsi_write(msm_host
, REG_DSI_ACK_ERR_STATUS
, status
);
1439 /* Writing of an extra 0 needed to clear error bits */
1440 dsi_write(msm_host
, REG_DSI_ACK_ERR_STATUS
, 0);
1441 msm_host
->err_work_state
|= DSI_ERR_STATE_ACK
;
1445 static void dsi_timeout_status(struct msm_dsi_host
*msm_host
)
1449 status
= dsi_read(msm_host
, REG_DSI_TIMEOUT_STATUS
);
1452 dsi_write(msm_host
, REG_DSI_TIMEOUT_STATUS
, status
);
1453 msm_host
->err_work_state
|= DSI_ERR_STATE_TIMEOUT
;
1457 static void dsi_dln0_phy_err(struct msm_dsi_host
*msm_host
)
1461 status
= dsi_read(msm_host
, REG_DSI_DLN0_PHY_ERR
);
1463 if (status
& (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC
|
1464 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC
|
1465 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL
|
1466 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0
|
1467 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1
)) {
1468 dsi_write(msm_host
, REG_DSI_DLN0_PHY_ERR
, status
);
1469 msm_host
->err_work_state
|= DSI_ERR_STATE_DLN0_PHY
;
1473 static void dsi_fifo_status(struct msm_dsi_host
*msm_host
)
1477 status
= dsi_read(msm_host
, REG_DSI_FIFO_STATUS
);
1479 /* fifo underflow, overflow */
1481 dsi_write(msm_host
, REG_DSI_FIFO_STATUS
, status
);
1482 msm_host
->err_work_state
|= DSI_ERR_STATE_FIFO
;
1483 if (status
& DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW
)
1484 msm_host
->err_work_state
|=
1485 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW
;
1489 static void dsi_status(struct msm_dsi_host
*msm_host
)
1493 status
= dsi_read(msm_host
, REG_DSI_STATUS0
);
1495 if (status
& DSI_STATUS0_INTERLEAVE_OP_CONTENTION
) {
1496 dsi_write(msm_host
, REG_DSI_STATUS0
, status
);
1497 msm_host
->err_work_state
|=
1498 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION
;
1502 static void dsi_clk_status(struct msm_dsi_host
*msm_host
)
1506 status
= dsi_read(msm_host
, REG_DSI_CLK_STATUS
);
1508 if (status
& DSI_CLK_STATUS_PLL_UNLOCKED
) {
1509 dsi_write(msm_host
, REG_DSI_CLK_STATUS
, status
);
1510 msm_host
->err_work_state
|= DSI_ERR_STATE_PLL_UNLOCKED
;
1514 static void dsi_error(struct msm_dsi_host
*msm_host
)
1516 /* disable dsi error interrupt */
1517 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_ERROR
, 0);
1519 dsi_clk_status(msm_host
);
1520 dsi_fifo_status(msm_host
);
1521 dsi_ack_err_status(msm_host
);
1522 dsi_timeout_status(msm_host
);
1523 dsi_status(msm_host
);
1524 dsi_dln0_phy_err(msm_host
);
1526 queue_work(msm_host
->workqueue
, &msm_host
->err_work
);
1529 static irqreturn_t
dsi_host_irq(int irq
, void *ptr
)
1531 struct msm_dsi_host
*msm_host
= ptr
;
1533 unsigned long flags
;
1535 if (!msm_host
->ctrl_base
)
1538 spin_lock_irqsave(&msm_host
->intr_lock
, flags
);
1539 isr
= dsi_read(msm_host
, REG_DSI_INTR_CTRL
);
1540 dsi_write(msm_host
, REG_DSI_INTR_CTRL
, isr
);
1541 spin_unlock_irqrestore(&msm_host
->intr_lock
, flags
);
1543 DBG("isr=0x%x, id=%d", isr
, msm_host
->id
);
1545 if (isr
& DSI_IRQ_ERROR
)
1546 dsi_error(msm_host
);
1548 if (isr
& DSI_IRQ_VIDEO_DONE
)
1549 complete(&msm_host
->video_comp
);
1551 if (isr
& DSI_IRQ_CMD_DMA_DONE
)
1552 complete(&msm_host
->dma_comp
);
1557 static int dsi_host_init_panel_gpios(struct msm_dsi_host
*msm_host
,
1558 struct device
*panel_device
)
1560 msm_host
->disp_en_gpio
= devm_gpiod_get_optional(panel_device
,
1563 if (IS_ERR(msm_host
->disp_en_gpio
)) {
1564 DBG("cannot get disp-enable-gpios %ld",
1565 PTR_ERR(msm_host
->disp_en_gpio
));
1566 return PTR_ERR(msm_host
->disp_en_gpio
);
1569 msm_host
->te_gpio
= devm_gpiod_get_optional(panel_device
, "disp-te",
1571 if (IS_ERR(msm_host
->te_gpio
)) {
1572 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host
->te_gpio
));
1573 return PTR_ERR(msm_host
->te_gpio
);
1579 static int dsi_host_attach(struct mipi_dsi_host
*host
,
1580 struct mipi_dsi_device
*dsi
)
1582 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1585 if (dsi
->lanes
> msm_host
->num_data_lanes
)
1588 msm_host
->channel
= dsi
->channel
;
1589 msm_host
->lanes
= dsi
->lanes
;
1590 msm_host
->format
= dsi
->format
;
1591 msm_host
->mode_flags
= dsi
->mode_flags
;
1593 msm_dsi_manager_attach_dsi_device(msm_host
->id
, dsi
->mode_flags
);
1595 /* Some gpios defined in panel DT need to be controlled by host */
1596 ret
= dsi_host_init_panel_gpios(msm_host
, &dsi
->dev
);
1600 DBG("id=%d", msm_host
->id
);
1602 queue_work(msm_host
->workqueue
, &msm_host
->hpd_work
);
1607 static int dsi_host_detach(struct mipi_dsi_host
*host
,
1608 struct mipi_dsi_device
*dsi
)
1610 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1612 msm_host
->device_node
= NULL
;
1614 DBG("id=%d", msm_host
->id
);
1616 queue_work(msm_host
->workqueue
, &msm_host
->hpd_work
);
1621 static ssize_t
dsi_host_transfer(struct mipi_dsi_host
*host
,
1622 const struct mipi_dsi_msg
*msg
)
1624 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1627 if (!msg
|| !msm_host
->power_on
)
1630 mutex_lock(&msm_host
->cmd_mutex
);
1631 ret
= msm_dsi_manager_cmd_xfer(msm_host
->id
, msg
);
1632 mutex_unlock(&msm_host
->cmd_mutex
);
1637 static struct mipi_dsi_host_ops dsi_host_ops
= {
1638 .attach
= dsi_host_attach
,
1639 .detach
= dsi_host_detach
,
1640 .transfer
= dsi_host_transfer
,
1644 * List of supported physical to logical lane mappings.
1645 * For example, the 2nd entry represents the following mapping:
1647 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1649 static const int supported_data_lane_swaps
[][4] = {
1660 static int dsi_host_parse_lane_data(struct msm_dsi_host
*msm_host
,
1661 struct device_node
*ep
)
1663 struct device
*dev
= &msm_host
->pdev
->dev
;
1664 struct property
*prop
;
1666 int ret
, i
, len
, num_lanes
;
1668 prop
= of_find_property(ep
, "data-lanes", &len
);
1671 "failed to find data lane mapping, using default\n");
1675 num_lanes
= len
/ sizeof(u32
);
1677 if (num_lanes
< 1 || num_lanes
> 4) {
1678 DRM_DEV_ERROR(dev
, "bad number of data lanes\n");
1682 msm_host
->num_data_lanes
= num_lanes
;
1684 ret
= of_property_read_u32_array(ep
, "data-lanes", lane_map
,
1687 DRM_DEV_ERROR(dev
, "failed to read lane data\n");
1692 * compare DT specified physical-logical lane mappings with the ones
1693 * supported by hardware
1695 for (i
= 0; i
< ARRAY_SIZE(supported_data_lane_swaps
); i
++) {
1696 const int *swap
= supported_data_lane_swaps
[i
];
1700 * the data-lanes array we get from DT has a logical->physical
1701 * mapping. The "data lane swap" register field represents
1702 * supported configurations in a physical->logical mapping.
1703 * Translate the DT mapping to what we understand and find a
1704 * configuration that works.
1706 for (j
= 0; j
< num_lanes
; j
++) {
1707 if (lane_map
[j
] < 0 || lane_map
[j
] > 3)
1708 DRM_DEV_ERROR(dev
, "bad physical lane entry %u\n",
1711 if (swap
[lane_map
[j
]] != j
)
1715 if (j
== num_lanes
) {
1716 msm_host
->dlane_swap
= i
;
1724 static int dsi_host_parse_dt(struct msm_dsi_host
*msm_host
)
1726 struct device
*dev
= &msm_host
->pdev
->dev
;
1727 struct device_node
*np
= dev
->of_node
;
1728 struct device_node
*endpoint
, *device_node
;
1732 * Get the endpoint of the output port of the DSI host. In our case,
1733 * this is mapped to port number with reg = 1. Don't return an error if
1734 * the remote endpoint isn't defined. It's possible that there is
1735 * nothing connected to the dsi output.
1737 endpoint
= of_graph_get_endpoint_by_regs(np
, 1, -1);
1739 DRM_DEV_DEBUG(dev
, "%s: no endpoint\n", __func__
);
1743 ret
= dsi_host_parse_lane_data(msm_host
, endpoint
);
1745 DRM_DEV_ERROR(dev
, "%s: invalid lane configuration %d\n",
1751 /* Get panel node from the output port's endpoint data */
1752 device_node
= of_graph_get_remote_node(np
, 1, 0);
1754 DRM_DEV_DEBUG(dev
, "%s: no valid device\n", __func__
);
1759 msm_host
->device_node
= device_node
;
1761 if (of_property_read_bool(np
, "syscon-sfpb")) {
1762 msm_host
->sfpb
= syscon_regmap_lookup_by_phandle(np
,
1764 if (IS_ERR(msm_host
->sfpb
)) {
1765 DRM_DEV_ERROR(dev
, "%s: failed to get sfpb regmap\n",
1767 ret
= PTR_ERR(msm_host
->sfpb
);
1771 of_node_put(device_node
);
1774 of_node_put(endpoint
);
1779 static int dsi_host_get_id(struct msm_dsi_host
*msm_host
)
1781 struct platform_device
*pdev
= msm_host
->pdev
;
1782 const struct msm_dsi_config
*cfg
= msm_host
->cfg_hnd
->cfg
;
1783 struct resource
*res
;
1786 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dsi_ctrl");
1790 for (i
= 0; i
< cfg
->num_dsi
; i
++) {
1791 if (cfg
->io_start
[i
] == res
->start
)
1798 int msm_dsi_host_init(struct msm_dsi
*msm_dsi
)
1800 struct msm_dsi_host
*msm_host
= NULL
;
1801 struct platform_device
*pdev
= msm_dsi
->pdev
;
1804 msm_host
= devm_kzalloc(&pdev
->dev
, sizeof(*msm_host
), GFP_KERNEL
);
1806 pr_err("%s: FAILED: cannot alloc dsi host\n",
1812 msm_host
->pdev
= pdev
;
1813 msm_dsi
->host
= &msm_host
->base
;
1815 ret
= dsi_host_parse_dt(msm_host
);
1817 pr_err("%s: failed to parse dt\n", __func__
);
1821 msm_host
->ctrl_base
= msm_ioremap(pdev
, "dsi_ctrl", "DSI CTRL");
1822 if (IS_ERR(msm_host
->ctrl_base
)) {
1823 pr_err("%s: unable to map Dsi ctrl base\n", __func__
);
1824 ret
= PTR_ERR(msm_host
->ctrl_base
);
1828 pm_runtime_enable(&pdev
->dev
);
1830 msm_host
->cfg_hnd
= dsi_get_config(msm_host
);
1831 if (!msm_host
->cfg_hnd
) {
1833 pr_err("%s: get config failed\n", __func__
);
1837 msm_host
->id
= dsi_host_get_id(msm_host
);
1838 if (msm_host
->id
< 0) {
1840 pr_err("%s: unable to identify DSI host index\n", __func__
);
1844 /* fixup base address by io offset */
1845 msm_host
->ctrl_base
+= msm_host
->cfg_hnd
->cfg
->io_offset
;
1847 ret
= dsi_regulator_init(msm_host
);
1849 pr_err("%s: regulator init failed\n", __func__
);
1853 ret
= dsi_clk_init(msm_host
);
1855 pr_err("%s: unable to initialize dsi clks\n", __func__
);
1859 msm_host
->rx_buf
= devm_kzalloc(&pdev
->dev
, SZ_4K
, GFP_KERNEL
);
1860 if (!msm_host
->rx_buf
) {
1862 pr_err("%s: alloc rx temp buf failed\n", __func__
);
1866 init_completion(&msm_host
->dma_comp
);
1867 init_completion(&msm_host
->video_comp
);
1868 mutex_init(&msm_host
->dev_mutex
);
1869 mutex_init(&msm_host
->cmd_mutex
);
1870 spin_lock_init(&msm_host
->intr_lock
);
1872 /* setup workqueue */
1873 msm_host
->workqueue
= alloc_ordered_workqueue("dsi_drm_work", 0);
1874 INIT_WORK(&msm_host
->err_work
, dsi_err_worker
);
1875 INIT_WORK(&msm_host
->hpd_work
, dsi_hpd_worker
);
1877 msm_dsi
->id
= msm_host
->id
;
1879 DBG("Dsi Host %d initialized", msm_host
->id
);
1886 void msm_dsi_host_destroy(struct mipi_dsi_host
*host
)
1888 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1891 dsi_tx_buf_free(msm_host
);
1892 if (msm_host
->workqueue
) {
1893 flush_workqueue(msm_host
->workqueue
);
1894 destroy_workqueue(msm_host
->workqueue
);
1895 msm_host
->workqueue
= NULL
;
1898 mutex_destroy(&msm_host
->cmd_mutex
);
1899 mutex_destroy(&msm_host
->dev_mutex
);
1901 pm_runtime_disable(&msm_host
->pdev
->dev
);
1904 int msm_dsi_host_modeset_init(struct mipi_dsi_host
*host
,
1905 struct drm_device
*dev
)
1907 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1908 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
1909 struct platform_device
*pdev
= msm_host
->pdev
;
1912 msm_host
->irq
= irq_of_parse_and_map(pdev
->dev
.of_node
, 0);
1913 if (msm_host
->irq
< 0) {
1914 ret
= msm_host
->irq
;
1915 DRM_DEV_ERROR(dev
->dev
, "failed to get irq: %d\n", ret
);
1919 ret
= devm_request_irq(&pdev
->dev
, msm_host
->irq
,
1920 dsi_host_irq
, IRQF_TRIGGER_HIGH
| IRQF_ONESHOT
,
1921 "dsi_isr", msm_host
);
1923 DRM_DEV_ERROR(&pdev
->dev
, "failed to request IRQ%u: %d\n",
1924 msm_host
->irq
, ret
);
1928 msm_host
->dev
= dev
;
1929 ret
= cfg_hnd
->ops
->tx_buf_alloc(msm_host
, SZ_4K
);
1931 pr_err("%s: alloc tx gem obj failed, %d\n", __func__
, ret
);
1938 int msm_dsi_host_register(struct mipi_dsi_host
*host
, bool check_defer
)
1940 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1943 /* Register mipi dsi host */
1944 if (!msm_host
->registered
) {
1945 host
->dev
= &msm_host
->pdev
->dev
;
1946 host
->ops
= &dsi_host_ops
;
1947 ret
= mipi_dsi_host_register(host
);
1951 msm_host
->registered
= true;
1953 /* If the panel driver has not been probed after host register,
1954 * we should defer the host's probe.
1955 * It makes sure panel is connected when fbcon detects
1956 * connector status and gets the proper display mode to
1957 * create framebuffer.
1958 * Don't try to defer if there is nothing connected to the dsi
1961 if (check_defer
&& msm_host
->device_node
) {
1962 if (IS_ERR(of_drm_find_panel(msm_host
->device_node
)))
1963 if (!of_drm_find_bridge(msm_host
->device_node
))
1964 return -EPROBE_DEFER
;
1971 void msm_dsi_host_unregister(struct mipi_dsi_host
*host
)
1973 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1975 if (msm_host
->registered
) {
1976 mipi_dsi_host_unregister(host
);
1979 msm_host
->registered
= false;
1983 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host
*host
,
1984 const struct mipi_dsi_msg
*msg
)
1986 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
1987 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
1989 /* TODO: make sure dsi_cmd_mdp is idle.
1990 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1991 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
1992 * How to handle the old versions? Wait for mdp cmd done?
1996 * mdss interrupt is generated in mdp core clock domain
1997 * mdp clock need to be enabled to receive dsi interrupt
1999 pm_runtime_get_sync(&msm_host
->pdev
->dev
);
2000 cfg_hnd
->ops
->link_clk_enable(msm_host
);
2002 /* TODO: vote for bus bandwidth */
2004 if (!(msg
->flags
& MIPI_DSI_MSG_USE_LPM
))
2005 dsi_set_tx_power_mode(0, msm_host
);
2007 msm_host
->dma_cmd_ctrl_restore
= dsi_read(msm_host
, REG_DSI_CTRL
);
2008 dsi_write(msm_host
, REG_DSI_CTRL
,
2009 msm_host
->dma_cmd_ctrl_restore
|
2010 DSI_CTRL_CMD_MODE_EN
|
2012 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_CMD_DMA_DONE
, 1);
2017 void msm_dsi_host_xfer_restore(struct mipi_dsi_host
*host
,
2018 const struct mipi_dsi_msg
*msg
)
2020 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2021 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
2023 dsi_intr_ctrl(msm_host
, DSI_IRQ_MASK_CMD_DMA_DONE
, 0);
2024 dsi_write(msm_host
, REG_DSI_CTRL
, msm_host
->dma_cmd_ctrl_restore
);
2026 if (!(msg
->flags
& MIPI_DSI_MSG_USE_LPM
))
2027 dsi_set_tx_power_mode(1, msm_host
);
2029 /* TODO: unvote for bus bandwidth */
2031 cfg_hnd
->ops
->link_clk_disable(msm_host
);
2032 pm_runtime_put_autosuspend(&msm_host
->pdev
->dev
);
2035 int msm_dsi_host_cmd_tx(struct mipi_dsi_host
*host
,
2036 const struct mipi_dsi_msg
*msg
)
2038 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2040 return dsi_cmds2buf_tx(msm_host
, msg
);
2043 int msm_dsi_host_cmd_rx(struct mipi_dsi_host
*host
,
2044 const struct mipi_dsi_msg
*msg
)
2046 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2047 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
2048 int data_byte
, rx_byte
, dlen
, end
;
2049 int short_response
, diff
, pkt_size
, ret
= 0;
2051 int rlen
= msg
->rx_len
;
2060 data_byte
= 10; /* first read */
2061 if (rlen
< data_byte
)
2064 pkt_size
= data_byte
;
2065 rx_byte
= data_byte
+ 6; /* 4 header + 2 crc */
2068 buf
= msm_host
->rx_buf
;
2071 u8 tx
[2] = {pkt_size
& 0xff, pkt_size
>> 8};
2072 struct mipi_dsi_msg max_pkt_size_msg
= {
2073 .channel
= msg
->channel
,
2074 .type
= MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
,
2079 DBG("rlen=%d pkt_size=%d rx_byte=%d",
2080 rlen
, pkt_size
, rx_byte
);
2082 ret
= dsi_cmds2buf_tx(msm_host
, &max_pkt_size_msg
);
2084 pr_err("%s: Set max pkt size failed, %d\n",
2089 if ((cfg_hnd
->major
== MSM_DSI_VER_MAJOR_6G
) &&
2090 (cfg_hnd
->minor
>= MSM_DSI_6G_VER_MINOR_V1_1
)) {
2091 /* Clear the RDBK_DATA registers */
2092 dsi_write(msm_host
, REG_DSI_RDBK_DATA_CTRL
,
2093 DSI_RDBK_DATA_CTRL_CLR
);
2094 wmb(); /* make sure the RDBK registers are cleared */
2095 dsi_write(msm_host
, REG_DSI_RDBK_DATA_CTRL
, 0);
2096 wmb(); /* release cleared status before transfer */
2099 ret
= dsi_cmds2buf_tx(msm_host
, msg
);
2100 if (ret
< msg
->tx_len
) {
2101 pr_err("%s: Read cmd Tx failed, %d\n", __func__
, ret
);
2106 * once cmd_dma_done interrupt received,
2107 * return data from client is ready and stored
2108 * at RDBK_DATA register already
2109 * since rx fifo is 16 bytes, dcs header is kept at first loop,
2110 * after that dcs header lost during shift into registers
2112 dlen
= dsi_cmd_dma_rx(msm_host
, buf
, rx_byte
, pkt_size
);
2120 if (rlen
<= data_byte
) {
2121 diff
= data_byte
- rlen
;
2129 dlen
-= 2; /* 2 crc */
2131 buf
+= dlen
; /* next start position */
2132 data_byte
= 14; /* NOT first read */
2133 if (rlen
< data_byte
)
2136 pkt_size
+= data_byte
;
2137 DBG("buf=%p dlen=%d diff=%d", buf
, dlen
, diff
);
2142 * For single Long read, if the requested rlen < 10,
2143 * we need to shift the start position of rx
2144 * data buffer to skip the bytes which are not
2147 if (pkt_size
< 10 && !short_response
)
2148 buf
= msm_host
->rx_buf
+ (10 - rlen
);
2150 buf
= msm_host
->rx_buf
;
2154 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
:
2155 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__
);
2158 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE
:
2159 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
:
2160 ret
= dsi_short_read1_resp(buf
, msg
);
2162 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE
:
2163 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
:
2164 ret
= dsi_short_read2_resp(buf
, msg
);
2166 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE
:
2167 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
:
2168 ret
= dsi_long_read_resp(buf
, msg
);
2171 pr_warn("%s:Invalid response cmd\n", __func__
);
2178 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host
*host
, u32 dma_base
,
2181 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2183 dsi_write(msm_host
, REG_DSI_DMA_BASE
, dma_base
);
2184 dsi_write(msm_host
, REG_DSI_DMA_LEN
, len
);
2185 dsi_write(msm_host
, REG_DSI_TRIG_DMA
, 1);
2187 /* Make sure trigger happens */
2191 int msm_dsi_host_set_src_pll(struct mipi_dsi_host
*host
,
2192 struct msm_dsi_pll
*src_pll
)
2194 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2195 struct clk
*byte_clk_provider
, *pixel_clk_provider
;
2198 ret
= msm_dsi_pll_get_clk_provider(src_pll
,
2199 &byte_clk_provider
, &pixel_clk_provider
);
2201 pr_info("%s: can't get provider from pll, don't set parent\n",
2206 ret
= clk_set_parent(msm_host
->byte_clk_src
, byte_clk_provider
);
2208 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n",
2213 ret
= clk_set_parent(msm_host
->pixel_clk_src
, pixel_clk_provider
);
2215 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n",
2220 if (msm_host
->dsi_clk_src
) {
2221 ret
= clk_set_parent(msm_host
->dsi_clk_src
, pixel_clk_provider
);
2223 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n",
2229 if (msm_host
->esc_clk_src
) {
2230 ret
= clk_set_parent(msm_host
->esc_clk_src
, byte_clk_provider
);
2232 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n",
2242 void msm_dsi_host_reset_phy(struct mipi_dsi_host
*host
)
2244 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2247 dsi_write(msm_host
, REG_DSI_PHY_RESET
, DSI_PHY_RESET_RESET
);
2248 /* Make sure fully reset */
2251 dsi_write(msm_host
, REG_DSI_PHY_RESET
, 0);
2255 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host
*host
,
2256 struct msm_dsi_phy_clk_request
*clk_req
,
2259 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2260 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
2263 ret
= cfg_hnd
->ops
->calc_clk_rate(msm_host
, is_dual_dsi
);
2265 pr_err("%s: unable to calc clk rate, %d\n", __func__
, ret
);
2269 clk_req
->bitclk_rate
= msm_host
->byte_clk_rate
* 8;
2270 clk_req
->escclk_rate
= msm_host
->esc_clk_rate
;
2273 int msm_dsi_host_enable(struct mipi_dsi_host
*host
)
2275 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2277 dsi_op_mode_config(msm_host
,
2278 !!(msm_host
->mode_flags
& MIPI_DSI_MODE_VIDEO
), true);
2280 /* TODO: clock should be turned off for command mode,
2281 * and only turned on before MDP START.
2282 * This part of code should be enabled once mdp driver support it.
2284 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2285 * dsi_link_clk_disable(msm_host);
2286 * pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2289 msm_host
->enabled
= true;
2293 int msm_dsi_host_disable(struct mipi_dsi_host
*host
)
2295 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2297 msm_host
->enabled
= false;
2298 dsi_op_mode_config(msm_host
,
2299 !!(msm_host
->mode_flags
& MIPI_DSI_MODE_VIDEO
), false);
2301 /* Since we have disabled INTF, the video engine won't stop so that
2302 * the cmd engine will be blocked.
2303 * Reset to disable video engine so that we can send off cmd.
2305 dsi_sw_reset(msm_host
);
2310 static void msm_dsi_sfpb_config(struct msm_dsi_host
*msm_host
, bool enable
)
2312 enum sfpb_ahb_arb_master_port_en en
;
2314 if (!msm_host
->sfpb
)
2317 en
= enable
? SFPB_MASTER_PORT_ENABLE
: SFPB_MASTER_PORT_DISABLE
;
2319 regmap_update_bits(msm_host
->sfpb
, REG_SFPB_GPREG
,
2320 SFPB_GPREG_MASTER_PORT_EN__MASK
,
2321 SFPB_GPREG_MASTER_PORT_EN(en
));
2324 int msm_dsi_host_power_on(struct mipi_dsi_host
*host
,
2325 struct msm_dsi_phy_shared_timings
*phy_shared_timings
,
2328 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2329 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
2332 mutex_lock(&msm_host
->dev_mutex
);
2333 if (msm_host
->power_on
) {
2334 DBG("dsi host already on");
2338 msm_dsi_sfpb_config(msm_host
, true);
2340 ret
= dsi_host_regulator_enable(msm_host
);
2342 pr_err("%s:Failed to enable vregs.ret=%d\n",
2347 pm_runtime_get_sync(&msm_host
->pdev
->dev
);
2348 ret
= cfg_hnd
->ops
->link_clk_enable(msm_host
);
2350 pr_err("%s: failed to enable link clocks. ret=%d\n",
2352 goto fail_disable_reg
;
2355 ret
= pinctrl_pm_select_default_state(&msm_host
->pdev
->dev
);
2357 pr_err("%s: failed to set pinctrl default state, %d\n",
2359 goto fail_disable_clk
;
2362 dsi_timing_setup(msm_host
, is_dual_dsi
);
2363 dsi_sw_reset(msm_host
);
2364 dsi_ctrl_config(msm_host
, true, phy_shared_timings
);
2366 if (msm_host
->disp_en_gpio
)
2367 gpiod_set_value(msm_host
->disp_en_gpio
, 1);
2369 msm_host
->power_on
= true;
2370 mutex_unlock(&msm_host
->dev_mutex
);
2375 cfg_hnd
->ops
->link_clk_disable(msm_host
);
2376 pm_runtime_put_autosuspend(&msm_host
->pdev
->dev
);
2378 dsi_host_regulator_disable(msm_host
);
2380 mutex_unlock(&msm_host
->dev_mutex
);
2384 int msm_dsi_host_power_off(struct mipi_dsi_host
*host
)
2386 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2387 const struct msm_dsi_cfg_handler
*cfg_hnd
= msm_host
->cfg_hnd
;
2389 mutex_lock(&msm_host
->dev_mutex
);
2390 if (!msm_host
->power_on
) {
2391 DBG("dsi host already off");
2395 dsi_ctrl_config(msm_host
, false, NULL
);
2397 if (msm_host
->disp_en_gpio
)
2398 gpiod_set_value(msm_host
->disp_en_gpio
, 0);
2400 pinctrl_pm_select_sleep_state(&msm_host
->pdev
->dev
);
2402 cfg_hnd
->ops
->link_clk_disable(msm_host
);
2403 pm_runtime_put_autosuspend(&msm_host
->pdev
->dev
);
2405 dsi_host_regulator_disable(msm_host
);
2407 msm_dsi_sfpb_config(msm_host
, false);
2411 msm_host
->power_on
= false;
2414 mutex_unlock(&msm_host
->dev_mutex
);
2418 int msm_dsi_host_set_display_mode(struct mipi_dsi_host
*host
,
2419 const struct drm_display_mode
*mode
)
2421 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2423 if (msm_host
->mode
) {
2424 drm_mode_destroy(msm_host
->dev
, msm_host
->mode
);
2425 msm_host
->mode
= NULL
;
2428 msm_host
->mode
= drm_mode_duplicate(msm_host
->dev
, mode
);
2429 if (!msm_host
->mode
) {
2430 pr_err("%s: cannot duplicate mode\n", __func__
);
2437 struct drm_panel
*msm_dsi_host_get_panel(struct mipi_dsi_host
*host
,
2438 unsigned long *panel_flags
)
2440 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2441 struct drm_panel
*panel
;
2443 panel
= of_drm_find_panel(msm_host
->device_node
);
2445 *panel_flags
= msm_host
->mode_flags
;
2450 struct drm_bridge
*msm_dsi_host_get_bridge(struct mipi_dsi_host
*host
)
2452 struct msm_dsi_host
*msm_host
= to_msm_dsi_host(host
);
2454 return of_drm_find_bridge(msm_host
->device_node
);