1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 #include <linux/platform_device.h>
10 #define S_DIV_ROUND_UP(n, d) \
11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
13 static inline s32
linear_inter(s32 tmax
, s32 tmin
, s32 percent
,
14 s32 min_result
, bool even
)
18 v
= (tmax
- tmin
) * percent
;
19 v
= S_DIV_ROUND_UP(v
, 100) + tmin
;
20 if (even
&& (v
& 0x1))
21 return max_t(s32
, min_result
, v
- 1);
23 return max_t(s32
, min_result
, v
);
26 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing
*timing
,
27 s32 ui
, s32 coeff
, s32 pcnt
)
29 s32 tmax
, tmin
, clk_z
;
33 temp
= 300 * coeff
- ((timing
->clk_prepare
>> 1) + 1) * 2 * ui
;
34 tmin
= S_DIV_ROUND_UP(temp
, ui
) - 2;
37 clk_z
= linear_inter(2 * tmin
, tmin
, pcnt
, 0, true);
40 clk_z
= linear_inter(tmax
, tmin
, pcnt
, 0, true);
44 temp
= (timing
->hs_rqst
+ timing
->clk_prepare
+ clk_z
) & 0x7;
45 timing
->clk_zero
= clk_z
+ 8 - temp
;
48 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing
*timing
,
49 struct msm_dsi_phy_clk_request
*clk_req
)
51 const unsigned long bit_rate
= clk_req
->bitclk_rate
;
52 const unsigned long esc_rate
= clk_req
->escclk_rate
;
56 s32 pcnt1
= (bit_rate
> 1200000000) ? 15 : 10;
58 s32 pcnt3
= (bit_rate
> 180000000) ? 10 : 40;
59 s32 coeff
= 1000; /* Precision, should avoid overflow */
62 if (!bit_rate
|| !esc_rate
)
65 ui
= mult_frac(NSEC_PER_MSEC
, coeff
, bit_rate
/ 1000);
66 lpx
= mult_frac(NSEC_PER_MSEC
, coeff
, esc_rate
/ 1000);
68 tmax
= S_DIV_ROUND_UP(95 * coeff
, ui
) - 2;
69 tmin
= S_DIV_ROUND_UP(38 * coeff
, ui
) - 2;
70 timing
->clk_prepare
= linear_inter(tmax
, tmin
, pcnt0
, 0, true);
74 timing
->hs_rqst
= temp
;
76 timing
->hs_rqst
= max_t(s32
, 0, temp
- 2);
78 /* Calculate clk_zero after clk_prepare and hs_rqst */
79 dsi_dphy_timing_calc_clk_zero(timing
, ui
, coeff
, pcnt2
);
81 temp
= 105 * coeff
+ 12 * ui
- 20 * coeff
;
82 tmax
= S_DIV_ROUND_UP(temp
, ui
) - 2;
83 tmin
= S_DIV_ROUND_UP(60 * coeff
, ui
) - 2;
84 timing
->clk_trail
= linear_inter(tmax
, tmin
, pcnt3
, 0, true);
86 temp
= 85 * coeff
+ 6 * ui
;
87 tmax
= S_DIV_ROUND_UP(temp
, ui
) - 2;
88 temp
= 40 * coeff
+ 4 * ui
;
89 tmin
= S_DIV_ROUND_UP(temp
, ui
) - 2;
90 timing
->hs_prepare
= linear_inter(tmax
, tmin
, pcnt1
, 0, true);
93 temp
= ((timing
->hs_prepare
>> 1) + 1) * 2 * ui
+ 2 * ui
;
94 temp
= 145 * coeff
+ 10 * ui
- temp
;
95 tmin
= S_DIV_ROUND_UP(temp
, ui
) - 2;
96 timing
->hs_zero
= linear_inter(tmax
, tmin
, pcnt2
, 24, true);
98 temp
= 105 * coeff
+ 12 * ui
- 20 * coeff
;
99 tmax
= S_DIV_ROUND_UP(temp
, ui
) - 2;
100 temp
= 60 * coeff
+ 4 * ui
;
101 tmin
= DIV_ROUND_UP(temp
, ui
) - 2;
102 timing
->hs_trail
= linear_inter(tmax
, tmin
, pcnt3
, 0, true);
105 tmin
= S_DIV_ROUND_UP(100 * coeff
, ui
) - 2;
106 timing
->hs_exit
= linear_inter(tmax
, tmin
, pcnt2
, 0, true);
109 temp
= ((timing
->hs_exit
>> 1) + 1) * 2 * ui
;
110 temp
= 60 * coeff
+ 52 * ui
- 24 * ui
- temp
;
111 tmin
= S_DIV_ROUND_UP(temp
, 8 * ui
) - 1;
112 timing
->shared_timings
.clk_post
= linear_inter(tmax
, tmin
, pcnt2
, 0,
115 temp
= ((timing
->clk_prepare
>> 1) + 1) * 2 * ui
;
116 temp
+= ((timing
->clk_zero
>> 1) + 1) * 2 * ui
;
117 temp
+= 8 * ui
+ lpx
;
118 tmin
= S_DIV_ROUND_UP(temp
, 8 * ui
) - 1;
120 temp
= linear_inter(2 * tmax
, tmin
, pcnt2
, 0, false);
121 timing
->shared_timings
.clk_pre
= temp
>> 1;
122 timing
->shared_timings
.clk_pre_inc_by_2
= true;
124 timing
->shared_timings
.clk_pre
=
125 linear_inter(tmax
, tmin
, pcnt2
, 0, false);
126 timing
->shared_timings
.clk_pre_inc_by_2
= false;
133 DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
134 timing
->shared_timings
.clk_pre
, timing
->shared_timings
.clk_post
,
135 timing
->shared_timings
.clk_pre_inc_by_2
, timing
->clk_zero
,
136 timing
->clk_trail
, timing
->clk_prepare
, timing
->hs_exit
,
137 timing
->hs_zero
, timing
->hs_prepare
, timing
->hs_trail
,
143 int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing
*timing
,
144 struct msm_dsi_phy_clk_request
*clk_req
)
146 const unsigned long bit_rate
= clk_req
->bitclk_rate
;
147 const unsigned long esc_rate
= clk_req
->escclk_rate
;
156 s32 coeff
= 1000; /* Precision, should avoid overflow */
157 s32 hb_en
, hb_en_ckln
, pd_ckln
, pd
;
161 if (!bit_rate
|| !esc_rate
)
164 timing
->hs_halfbyte_en
= 0;
166 timing
->hs_halfbyte_en_ckln
= 0;
168 timing
->hs_prep_dly_ckln
= (bit_rate
> 100000000) ? 0 : 3;
169 pd_ckln
= timing
->hs_prep_dly_ckln
;
170 timing
->hs_prep_dly
= (bit_rate
> 120000000) ? 0 : 1;
171 pd
= timing
->hs_prep_dly
;
173 val
= (hb_en
<< 2) + (pd
<< 1);
174 val_ckln
= (hb_en_ckln
<< 2) + (pd_ckln
<< 1);
176 ui
= mult_frac(NSEC_PER_MSEC
, coeff
, bit_rate
/ 1000);
178 lpx
= mult_frac(NSEC_PER_MSEC
, coeff
, esc_rate
/ 1000);
180 temp
= S_DIV_ROUND_UP(38 * coeff
- val_ckln
* ui
, ui_x8
);
181 tmin
= max_t(s32
, temp
, 0);
182 temp
= (95 * coeff
- val_ckln
* ui
) / ui_x8
;
183 tmax
= max_t(s32
, temp
, 0);
184 timing
->clk_prepare
= linear_inter(tmax
, tmin
, pcnt0
, 0, false);
186 temp
= 300 * coeff
- ((timing
->clk_prepare
<< 3) + val_ckln
) * ui
;
187 tmin
= S_DIV_ROUND_UP(temp
- 11 * ui
, ui_x8
) - 3;
188 tmax
= (tmin
> 255) ? 511 : 255;
189 timing
->clk_zero
= linear_inter(tmax
, tmin
, pcnt5
, 0, false);
191 tmin
= DIV_ROUND_UP(60 * coeff
+ 3 * ui
, ui_x8
);
192 temp
= 105 * coeff
+ 12 * ui
- 20 * coeff
;
193 tmax
= (temp
+ 3 * ui
) / ui_x8
;
194 timing
->clk_trail
= linear_inter(tmax
, tmin
, pcnt3
, 0, false);
196 temp
= S_DIV_ROUND_UP(40 * coeff
+ 4 * ui
- val
* ui
, ui_x8
);
197 tmin
= max_t(s32
, temp
, 0);
198 temp
= (85 * coeff
+ 6 * ui
- val
* ui
) / ui_x8
;
199 tmax
= max_t(s32
, temp
, 0);
200 timing
->hs_prepare
= linear_inter(tmax
, tmin
, pcnt1
, 0, false);
202 temp
= 145 * coeff
+ 10 * ui
- ((timing
->hs_prepare
<< 3) + val
) * ui
;
203 tmin
= S_DIV_ROUND_UP(temp
- 11 * ui
, ui_x8
) - 3;
205 timing
->hs_zero
= linear_inter(tmax
, tmin
, pcnt4
, 0, false);
207 tmin
= DIV_ROUND_UP(60 * coeff
+ 4 * ui
+ 3 * ui
, ui_x8
);
208 temp
= 105 * coeff
+ 12 * ui
- 20 * coeff
;
209 tmax
= (temp
+ 3 * ui
) / ui_x8
;
210 timing
->hs_trail
= linear_inter(tmax
, tmin
, pcnt3
, 0, false);
212 temp
= 50 * coeff
+ ((hb_en
<< 2) - 8) * ui
;
213 timing
->hs_rqst
= S_DIV_ROUND_UP(temp
, ui_x8
);
215 tmin
= DIV_ROUND_UP(100 * coeff
, ui_x8
) - 1;
217 timing
->hs_exit
= linear_inter(tmax
, tmin
, pcnt2
, 0, false);
219 temp
= 50 * coeff
+ ((hb_en_ckln
<< 2) - 8) * ui
;
220 timing
->hs_rqst_ckln
= S_DIV_ROUND_UP(temp
, ui_x8
);
222 temp
= 60 * coeff
+ 52 * ui
- 43 * ui
;
223 tmin
= DIV_ROUND_UP(temp
, ui_x8
) - 1;
225 timing
->shared_timings
.clk_post
=
226 linear_inter(tmax
, tmin
, pcnt2
, 0, false);
228 temp
= 8 * ui
+ ((timing
->clk_prepare
<< 3) + val_ckln
) * ui
;
229 temp
+= (((timing
->clk_zero
+ 3) << 3) + 11 - (pd_ckln
<< 1)) * ui
;
230 temp
+= hb_en_ckln
? (((timing
->hs_rqst_ckln
<< 3) + 4) * ui
) :
231 (((timing
->hs_rqst_ckln
<< 3) + 8) * ui
);
232 tmin
= S_DIV_ROUND_UP(temp
, ui_x8
) - 1;
235 temp
= linear_inter(tmax
<< 1, tmin
, pcnt2
, 0, false);
236 timing
->shared_timings
.clk_pre
= temp
>> 1;
237 timing
->shared_timings
.clk_pre_inc_by_2
= 1;
239 timing
->shared_timings
.clk_pre
=
240 linear_inter(tmax
, tmin
, pcnt2
, 0, false);
241 timing
->shared_timings
.clk_pre_inc_by_2
= 0;
248 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
249 timing
->shared_timings
.clk_pre
, timing
->shared_timings
.clk_post
,
250 timing
->shared_timings
.clk_pre_inc_by_2
, timing
->clk_zero
,
251 timing
->clk_trail
, timing
->clk_prepare
, timing
->hs_exit
,
252 timing
->hs_zero
, timing
->hs_prepare
, timing
->hs_trail
,
253 timing
->hs_rqst
, timing
->hs_rqst_ckln
, timing
->hs_halfbyte_en
,
254 timing
->hs_halfbyte_en_ckln
, timing
->hs_prep_dly
,
255 timing
->hs_prep_dly_ckln
);
260 int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing
*timing
,
261 struct msm_dsi_phy_clk_request
*clk_req
)
263 const unsigned long bit_rate
= clk_req
->bitclk_rate
;
264 const unsigned long esc_rate
= clk_req
->escclk_rate
;
273 s32 coeff
= 1000; /* Precision, should avoid overflow */
274 s32 hb_en
, hb_en_ckln
;
277 if (!bit_rate
|| !esc_rate
)
280 timing
->hs_halfbyte_en
= 0;
282 timing
->hs_halfbyte_en_ckln
= 0;
285 ui
= mult_frac(NSEC_PER_MSEC
, coeff
, bit_rate
/ 1000);
287 lpx
= mult_frac(NSEC_PER_MSEC
, coeff
, esc_rate
/ 1000);
289 temp
= S_DIV_ROUND_UP(38 * coeff
, ui_x8
);
290 tmin
= max_t(s32
, temp
, 0);
291 temp
= (95 * coeff
) / ui_x8
;
292 tmax
= max_t(s32
, temp
, 0);
293 timing
->clk_prepare
= linear_inter(tmax
, tmin
, pcnt0
, 0, false);
295 temp
= 300 * coeff
- (timing
->clk_prepare
<< 3) * ui
;
296 tmin
= S_DIV_ROUND_UP(temp
, ui_x8
) - 1;
297 tmax
= (tmin
> 255) ? 511 : 255;
298 timing
->clk_zero
= linear_inter(tmax
, tmin
, pcnt5
, 0, false);
300 tmin
= DIV_ROUND_UP(60 * coeff
+ 3 * ui
, ui_x8
);
301 temp
= 105 * coeff
+ 12 * ui
- 20 * coeff
;
302 tmax
= (temp
+ 3 * ui
) / ui_x8
;
303 timing
->clk_trail
= linear_inter(tmax
, tmin
, pcnt3
, 0, false);
305 temp
= S_DIV_ROUND_UP(40 * coeff
+ 4 * ui
, ui_x8
);
306 tmin
= max_t(s32
, temp
, 0);
307 temp
= (85 * coeff
+ 6 * ui
) / ui_x8
;
308 tmax
= max_t(s32
, temp
, 0);
309 timing
->hs_prepare
= linear_inter(tmax
, tmin
, pcnt1
, 0, false);
311 temp
= 145 * coeff
+ 10 * ui
- (timing
->hs_prepare
<< 3) * ui
;
312 tmin
= S_DIV_ROUND_UP(temp
, ui_x8
) - 1;
314 timing
->hs_zero
= linear_inter(tmax
, tmin
, pcnt4
, 0, false);
316 tmin
= DIV_ROUND_UP(60 * coeff
+ 4 * ui
, ui_x8
) - 1;
317 temp
= 105 * coeff
+ 12 * ui
- 20 * coeff
;
318 tmax
= (temp
/ ui_x8
) - 1;
319 timing
->hs_trail
= linear_inter(tmax
, tmin
, pcnt3
, 0, false);
321 temp
= 50 * coeff
+ ((hb_en
<< 2) - 8) * ui
;
322 timing
->hs_rqst
= S_DIV_ROUND_UP(temp
, ui_x8
);
324 tmin
= DIV_ROUND_UP(100 * coeff
, ui_x8
) - 1;
326 timing
->hs_exit
= linear_inter(tmax
, tmin
, pcnt2
, 0, false);
328 temp
= 50 * coeff
+ ((hb_en_ckln
<< 2) - 8) * ui
;
329 timing
->hs_rqst_ckln
= S_DIV_ROUND_UP(temp
, ui_x8
);
331 temp
= 60 * coeff
+ 52 * ui
- 43 * ui
;
332 tmin
= DIV_ROUND_UP(temp
, ui_x8
) - 1;
334 timing
->shared_timings
.clk_post
=
335 linear_inter(tmax
, tmin
, pcnt2
, 0, false);
337 temp
= 8 * ui
+ (timing
->clk_prepare
<< 3) * ui
;
338 temp
+= (((timing
->clk_zero
+ 3) << 3) + 11) * ui
;
339 temp
+= hb_en_ckln
? (((timing
->hs_rqst_ckln
<< 3) + 4) * ui
) :
340 (((timing
->hs_rqst_ckln
<< 3) + 8) * ui
);
341 tmin
= S_DIV_ROUND_UP(temp
, ui_x8
) - 1;
344 temp
= linear_inter(tmax
<< 1, tmin
, pcnt2
, 0, false);
345 timing
->shared_timings
.clk_pre
= temp
>> 1;
346 timing
->shared_timings
.clk_pre_inc_by_2
= 1;
348 timing
->shared_timings
.clk_pre
=
349 linear_inter(tmax
, tmin
, pcnt2
, 0, false);
350 timing
->shared_timings
.clk_pre_inc_by_2
= 0;
357 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
358 timing
->shared_timings
.clk_pre
, timing
->shared_timings
.clk_post
,
359 timing
->shared_timings
.clk_pre_inc_by_2
, timing
->clk_zero
,
360 timing
->clk_trail
, timing
->clk_prepare
, timing
->hs_exit
,
361 timing
->hs_zero
, timing
->hs_prepare
, timing
->hs_trail
,
362 timing
->hs_rqst
, timing
->hs_rqst_ckln
, timing
->hs_halfbyte_en
,
363 timing
->hs_halfbyte_en_ckln
, timing
->hs_prep_dly
,
364 timing
->hs_prep_dly_ckln
);
369 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy
*phy
, int pll_id
, u32 reg
,
372 int phy_id
= phy
->id
;
375 if ((phy_id
>= DSI_MAX
) || (pll_id
>= DSI_MAX
))
378 val
= dsi_phy_read(phy
->base
+ reg
);
380 if (phy
->cfg
->src_pll_truthtable
[phy_id
][pll_id
])
381 dsi_phy_write(phy
->base
+ reg
, val
| bit_mask
);
383 dsi_phy_write(phy
->base
+ reg
, val
& (~bit_mask
));
386 static int dsi_phy_regulator_init(struct msm_dsi_phy
*phy
)
388 struct regulator_bulk_data
*s
= phy
->supplies
;
389 const struct dsi_reg_entry
*regs
= phy
->cfg
->reg_cfg
.regs
;
390 struct device
*dev
= &phy
->pdev
->dev
;
391 int num
= phy
->cfg
->reg_cfg
.num
;
394 for (i
= 0; i
< num
; i
++)
395 s
[i
].supply
= regs
[i
].name
;
397 ret
= devm_regulator_bulk_get(dev
, num
, s
);
399 if (ret
!= -EPROBE_DEFER
) {
401 "%s: failed to init regulator, ret=%d\n",
411 static void dsi_phy_regulator_disable(struct msm_dsi_phy
*phy
)
413 struct regulator_bulk_data
*s
= phy
->supplies
;
414 const struct dsi_reg_entry
*regs
= phy
->cfg
->reg_cfg
.regs
;
415 int num
= phy
->cfg
->reg_cfg
.num
;
419 for (i
= num
- 1; i
>= 0; i
--)
420 if (regs
[i
].disable_load
>= 0)
421 regulator_set_load(s
[i
].consumer
, regs
[i
].disable_load
);
423 regulator_bulk_disable(num
, s
);
426 static int dsi_phy_regulator_enable(struct msm_dsi_phy
*phy
)
428 struct regulator_bulk_data
*s
= phy
->supplies
;
429 const struct dsi_reg_entry
*regs
= phy
->cfg
->reg_cfg
.regs
;
430 struct device
*dev
= &phy
->pdev
->dev
;
431 int num
= phy
->cfg
->reg_cfg
.num
;
435 for (i
= 0; i
< num
; i
++) {
436 if (regs
[i
].enable_load
>= 0) {
437 ret
= regulator_set_load(s
[i
].consumer
,
438 regs
[i
].enable_load
);
441 "regulator %d set op mode failed, %d\n",
448 ret
= regulator_bulk_enable(num
, s
);
450 DRM_DEV_ERROR(dev
, "regulator enable failed, %d\n", ret
);
457 for (i
--; i
>= 0; i
--)
458 regulator_set_load(s
[i
].consumer
, regs
[i
].disable_load
);
462 static int dsi_phy_enable_resource(struct msm_dsi_phy
*phy
)
464 struct device
*dev
= &phy
->pdev
->dev
;
467 pm_runtime_get_sync(dev
);
469 ret
= clk_prepare_enable(phy
->ahb_clk
);
471 DRM_DEV_ERROR(dev
, "%s: can't enable ahb clk, %d\n", __func__
, ret
);
472 pm_runtime_put_sync(dev
);
478 static void dsi_phy_disable_resource(struct msm_dsi_phy
*phy
)
480 clk_disable_unprepare(phy
->ahb_clk
);
481 pm_runtime_put_autosuspend(&phy
->pdev
->dev
);
484 static const struct of_device_id dsi_phy_dt_match
[] = {
485 #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
486 { .compatible
= "qcom,dsi-phy-28nm-hpm",
487 .data
= &dsi_phy_28nm_hpm_cfgs
},
488 { .compatible
= "qcom,dsi-phy-28nm-lp",
489 .data
= &dsi_phy_28nm_lp_cfgs
},
491 #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
492 { .compatible
= "qcom,dsi-phy-20nm",
493 .data
= &dsi_phy_20nm_cfgs
},
495 #ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
496 { .compatible
= "qcom,dsi-phy-28nm-8960",
497 .data
= &dsi_phy_28nm_8960_cfgs
},
499 #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
500 { .compatible
= "qcom,dsi-phy-14nm",
501 .data
= &dsi_phy_14nm_cfgs
},
503 #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
504 { .compatible
= "qcom,dsi-phy-10nm",
505 .data
= &dsi_phy_10nm_cfgs
},
506 { .compatible
= "qcom,dsi-phy-10nm-8998",
507 .data
= &dsi_phy_10nm_8998_cfgs
},
513 * Currently, we only support one SoC for each PHY type. When we have multiple
514 * SoCs for the same PHY, we can try to make the index searching a bit more
517 static int dsi_phy_get_id(struct msm_dsi_phy
*phy
)
519 struct platform_device
*pdev
= phy
->pdev
;
520 const struct msm_dsi_phy_cfg
*cfg
= phy
->cfg
;
521 struct resource
*res
;
524 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dsi_phy");
528 for (i
= 0; i
< cfg
->num_dsi_phy
; i
++) {
529 if (cfg
->io_start
[i
] == res
->start
)
536 int msm_dsi_phy_init_common(struct msm_dsi_phy
*phy
)
538 struct platform_device
*pdev
= phy
->pdev
;
541 phy
->reg_base
= msm_ioremap(pdev
, "dsi_phy_regulator",
543 if (IS_ERR(phy
->reg_base
)) {
544 DRM_DEV_ERROR(&pdev
->dev
, "%s: failed to map phy regulator base\n",
554 static int dsi_phy_driver_probe(struct platform_device
*pdev
)
556 struct msm_dsi_phy
*phy
;
557 struct device
*dev
= &pdev
->dev
;
558 const struct of_device_id
*match
;
561 phy
= devm_kzalloc(dev
, sizeof(*phy
), GFP_KERNEL
);
565 match
= of_match_node(dsi_phy_dt_match
, dev
->of_node
);
569 phy
->cfg
= match
->data
;
572 phy
->id
= dsi_phy_get_id(phy
);
575 DRM_DEV_ERROR(dev
, "%s: couldn't identify PHY index, %d\n",
580 phy
->regulator_ldo_mode
= of_property_read_bool(dev
->of_node
,
581 "qcom,dsi-phy-regulator-ldo-mode");
583 phy
->base
= msm_ioremap(pdev
, "dsi_phy", "DSI_PHY");
584 if (IS_ERR(phy
->base
)) {
585 DRM_DEV_ERROR(dev
, "%s: failed to map phy base\n", __func__
);
590 ret
= dsi_phy_regulator_init(phy
);
594 phy
->ahb_clk
= msm_clk_get(pdev
, "iface");
595 if (IS_ERR(phy
->ahb_clk
)) {
596 DRM_DEV_ERROR(dev
, "%s: Unable to get ahb clk\n", __func__
);
597 ret
= PTR_ERR(phy
->ahb_clk
);
601 if (phy
->cfg
->ops
.init
) {
602 ret
= phy
->cfg
->ops
.init(phy
);
607 /* PLL init will call into clk_register which requires
608 * register access, so we need to enable power and ahb clock.
610 ret
= dsi_phy_enable_resource(phy
);
614 phy
->pll
= msm_dsi_pll_init(pdev
, phy
->cfg
->type
, phy
->id
);
615 if (IS_ERR_OR_NULL(phy
->pll
)) {
617 "%s: pll init failed: %ld, need separate pll clk driver\n",
618 __func__
, PTR_ERR(phy
->pll
));
622 dsi_phy_disable_resource(phy
);
624 platform_set_drvdata(pdev
, phy
);
632 static int dsi_phy_driver_remove(struct platform_device
*pdev
)
634 struct msm_dsi_phy
*phy
= platform_get_drvdata(pdev
);
636 if (phy
&& phy
->pll
) {
637 msm_dsi_pll_destroy(phy
->pll
);
641 platform_set_drvdata(pdev
, NULL
);
646 static struct platform_driver dsi_phy_platform_driver
= {
647 .probe
= dsi_phy_driver_probe
,
648 .remove
= dsi_phy_driver_remove
,
650 .name
= "msm_dsi_phy",
651 .of_match_table
= dsi_phy_dt_match
,
655 void __init
msm_dsi_phy_driver_register(void)
657 platform_driver_register(&dsi_phy_platform_driver
);
660 void __exit
msm_dsi_phy_driver_unregister(void)
662 platform_driver_unregister(&dsi_phy_platform_driver
);
665 int msm_dsi_phy_enable(struct msm_dsi_phy
*phy
, int src_pll_id
,
666 struct msm_dsi_phy_clk_request
*clk_req
)
671 if (!phy
|| !phy
->cfg
->ops
.enable
)
674 dev
= &phy
->pdev
->dev
;
676 ret
= dsi_phy_enable_resource(phy
);
678 DRM_DEV_ERROR(dev
, "%s: resource enable failed, %d\n",
683 ret
= dsi_phy_regulator_enable(phy
);
685 DRM_DEV_ERROR(dev
, "%s: regulator enable failed, %d\n",
690 ret
= phy
->cfg
->ops
.enable(phy
, src_pll_id
, clk_req
);
692 DRM_DEV_ERROR(dev
, "%s: phy enable failed, %d\n", __func__
, ret
);
697 * Resetting DSI PHY silently changes its PLL registers to reset status,
698 * which will confuse clock driver and result in wrong output rate of
699 * link clocks. Restore PLL status if its PLL is being used as clock
702 if (phy
->usecase
!= MSM_DSI_PHY_SLAVE
) {
703 ret
= msm_dsi_pll_restore_state(phy
->pll
);
705 DRM_DEV_ERROR(dev
, "%s: failed to restore pll state, %d\n",
707 goto pll_restor_fail
;
714 if (phy
->cfg
->ops
.disable
)
715 phy
->cfg
->ops
.disable(phy
);
717 dsi_phy_regulator_disable(phy
);
719 dsi_phy_disable_resource(phy
);
724 void msm_dsi_phy_disable(struct msm_dsi_phy
*phy
)
726 if (!phy
|| !phy
->cfg
->ops
.disable
)
729 phy
->cfg
->ops
.disable(phy
);
731 dsi_phy_regulator_disable(phy
);
732 dsi_phy_disable_resource(phy
);
735 void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy
*phy
,
736 struct msm_dsi_phy_shared_timings
*shared_timings
)
738 memcpy(shared_timings
, &phy
->timing
.shared_timings
,
739 sizeof(*shared_timings
));
742 struct msm_dsi_pll
*msm_dsi_phy_get_pll(struct msm_dsi_phy
*phy
)
750 void msm_dsi_phy_set_usecase(struct msm_dsi_phy
*phy
,
751 enum msm_dsi_phy_usecase uc
)