4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
23 Copyright (C) 2013-2017 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
49 enum hdmi_hdcp_key_state
{
50 HDCP_KEYS_STATE_NO_KEYS
= 0,
51 HDCP_KEYS_STATE_NOT_CHECKED
= 1,
52 HDCP_KEYS_STATE_CHECKING
= 2,
53 HDCP_KEYS_STATE_VALID
= 3,
54 HDCP_KEYS_STATE_AKSV_NOT_VALID
= 4,
55 HDCP_KEYS_STATE_CHKSUM_MISMATCH
= 5,
56 HDCP_KEYS_STATE_PROD_AKSV
= 6,
57 HDCP_KEYS_STATE_RESERVED
= 7,
60 enum hdmi_ddc_read_write
{
72 #define REG_HDMI_CTRL 0x00000000
73 #define HDMI_CTRL_ENABLE 0x00000001
74 #define HDMI_CTRL_HDMI 0x00000002
75 #define HDMI_CTRL_ENCRYPTED 0x00000004
77 #define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
78 #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
80 #define REG_HDMI_ACR_PKT_CTRL 0x00000024
81 #define HDMI_ACR_PKT_CTRL_CONT 0x00000001
82 #define HDMI_ACR_PKT_CTRL_SEND 0x00000002
83 #define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030
84 #define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4
85 static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val
)
87 return ((val
) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT
) & HDMI_ACR_PKT_CTRL_SELECT__MASK
;
89 #define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100
90 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000
91 #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16
92 static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val
)
94 return ((val
) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT
) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK
;
96 #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000
98 #define REG_HDMI_VBI_PKT_CTRL 0x00000028
99 #define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010
100 #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020
101 #define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100
102 #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200
103 #define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000
104 #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000
106 #define REG_HDMI_INFOFRAME_CTRL0 0x0000002c
107 #define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001
108 #define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002
109 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010
110 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020
111 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040
112 #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080
114 #define REG_HDMI_INFOFRAME_CTRL1 0x00000030
115 #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f
116 #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0
117 static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val
)
119 return ((val
) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT
) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK
;
121 #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00
122 #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT 8
123 static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val
)
125 return ((val
) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT
) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK
;
127 #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000
128 #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT 16
129 static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val
)
131 return ((val
) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT
) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK
;
133 #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000
134 #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT 24
135 static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val
)
137 return ((val
) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT
) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK
;
140 #define REG_HDMI_GEN_PKT_CTRL 0x00000034
141 #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001
142 #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002
143 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c
144 #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2
145 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val
)
147 return ((val
) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT
) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK
;
149 #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010
150 #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020
151 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000
152 #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16
153 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val
)
155 return ((val
) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT
) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK
;
157 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000
158 #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24
159 static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val
)
161 return ((val
) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT
) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK
;
164 #define REG_HDMI_GC 0x00000040
165 #define HDMI_GC_MUTE 0x00000001
167 #define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044
168 #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001
169 #define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002
171 static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0
) { return 0x0000006c + 0x4*i0
; }
173 #define REG_HDMI_GENERIC0_HDR 0x00000084
175 static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0
) { return 0x00000088 + 0x4*i0
; }
177 #define REG_HDMI_GENERIC1_HDR 0x000000a4
179 static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0
) { return 0x000000a8 + 0x4*i0
; }
181 static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0
) { return 0x000000c4 + 0x8*i0
; }
183 static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0
) { return 0x000000c4 + 0x8*i0
; }
184 #define HDMI_ACR_0_CTS__MASK 0xfffff000
185 #define HDMI_ACR_0_CTS__SHIFT 12
186 static inline uint32_t HDMI_ACR_0_CTS(uint32_t val
)
188 return ((val
) << HDMI_ACR_0_CTS__SHIFT
) & HDMI_ACR_0_CTS__MASK
;
191 static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0
) { return 0x000000c8 + 0x8*i0
; }
192 #define HDMI_ACR_1_N__MASK 0xffffffff
193 #define HDMI_ACR_1_N__SHIFT 0
194 static inline uint32_t HDMI_ACR_1_N(uint32_t val
)
196 return ((val
) << HDMI_ACR_1_N__SHIFT
) & HDMI_ACR_1_N__MASK
;
199 #define REG_HDMI_AUDIO_INFO0 0x000000e4
200 #define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff
201 #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0
202 static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val
)
204 return ((val
) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT
) & HDMI_AUDIO_INFO0_CHECKSUM__MASK
;
206 #define HDMI_AUDIO_INFO0_CC__MASK 0x00000700
207 #define HDMI_AUDIO_INFO0_CC__SHIFT 8
208 static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val
)
210 return ((val
) << HDMI_AUDIO_INFO0_CC__SHIFT
) & HDMI_AUDIO_INFO0_CC__MASK
;
213 #define REG_HDMI_AUDIO_INFO1 0x000000e8
214 #define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff
215 #define HDMI_AUDIO_INFO1_CA__SHIFT 0
216 static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val
)
218 return ((val
) << HDMI_AUDIO_INFO1_CA__SHIFT
) & HDMI_AUDIO_INFO1_CA__MASK
;
220 #define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800
221 #define HDMI_AUDIO_INFO1_LSV__SHIFT 11
222 static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val
)
224 return ((val
) << HDMI_AUDIO_INFO1_LSV__SHIFT
) & HDMI_AUDIO_INFO1_LSV__MASK
;
226 #define HDMI_AUDIO_INFO1_DM_INH 0x00008000
228 #define REG_HDMI_HDCP_CTRL 0x00000110
229 #define HDMI_HDCP_CTRL_ENABLE 0x00000001
230 #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100
232 #define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114
233 #define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004
235 #define REG_HDMI_HDCP_INT_CTRL 0x00000118
236 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001
237 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002
238 #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004
239 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010
240 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020
241 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040
242 #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080
243 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100
244 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200
245 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400
246 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000
247 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000
248 #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000
250 #define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c
251 #define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100
252 #define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200
253 #define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000
254 #define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000
255 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000
256 #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28
257 static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val
)
259 return ((val
) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT
) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK
;
262 #define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120
263 #define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001
265 #define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124
266 #define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001
268 #define REG_HDMI_HDCP_DDC_STATUS 0x00000128
269 #define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010
270 #define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400
271 #define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000
272 #define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000
273 #define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000
274 #define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000
275 #define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000
277 #define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c
279 #define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c
281 #define REG_HDMI_HDCP_RESET 0x00000130
282 #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001
284 #define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134
286 #define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138
288 #define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c
290 #define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140
292 #define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144
294 #define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148
296 #define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c
298 #define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150
300 #define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154
302 #define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158
304 #define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c
306 #define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160
308 #define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164
310 #define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168
312 #define REG_HDMI_VENSPEC_INFO0 0x0000016c
314 #define REG_HDMI_VENSPEC_INFO1 0x00000170
316 #define REG_HDMI_VENSPEC_INFO2 0x00000174
318 #define REG_HDMI_VENSPEC_INFO3 0x00000178
320 #define REG_HDMI_VENSPEC_INFO4 0x0000017c
322 #define REG_HDMI_VENSPEC_INFO5 0x00000180
324 #define REG_HDMI_VENSPEC_INFO6 0x00000184
326 #define REG_HDMI_AUDIO_CFG 0x000001d0
327 #define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001
328 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0
329 #define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4
330 static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val
)
332 return ((val
) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT
) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK
;
335 #define REG_HDMI_USEC_REFTIMER 0x00000208
337 #define REG_HDMI_DDC_CTRL 0x0000020c
338 #define HDMI_DDC_CTRL_GO 0x00000001
339 #define HDMI_DDC_CTRL_SOFT_RESET 0x00000002
340 #define HDMI_DDC_CTRL_SEND_RESET 0x00000004
341 #define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008
342 #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000
343 #define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20
344 static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val
)
346 return ((val
) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT
) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK
;
349 #define REG_HDMI_DDC_ARBITRATION 0x00000210
350 #define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010
352 #define REG_HDMI_DDC_INT_CTRL 0x00000214
353 #define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001
354 #define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002
355 #define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004
357 #define REG_HDMI_DDC_SW_STATUS 0x00000218
358 #define HDMI_DDC_SW_STATUS_NACK0 0x00001000
359 #define HDMI_DDC_SW_STATUS_NACK1 0x00002000
360 #define HDMI_DDC_SW_STATUS_NACK2 0x00004000
361 #define HDMI_DDC_SW_STATUS_NACK3 0x00008000
363 #define REG_HDMI_DDC_HW_STATUS 0x0000021c
364 #define HDMI_DDC_HW_STATUS_DONE 0x00000008
366 #define REG_HDMI_DDC_SPEED 0x00000220
367 #define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003
368 #define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0
369 static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val
)
371 return ((val
) << HDMI_DDC_SPEED_THRESHOLD__SHIFT
) & HDMI_DDC_SPEED_THRESHOLD__MASK
;
373 #define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000
374 #define HDMI_DDC_SPEED_PRESCALE__SHIFT 16
375 static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val
)
377 return ((val
) << HDMI_DDC_SPEED_PRESCALE__SHIFT
) & HDMI_DDC_SPEED_PRESCALE__MASK
;
380 #define REG_HDMI_DDC_SETUP 0x00000224
381 #define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000
382 #define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24
383 static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val
)
385 return ((val
) << HDMI_DDC_SETUP_TIMEOUT__SHIFT
) & HDMI_DDC_SETUP_TIMEOUT__MASK
;
388 static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0
) { return 0x00000228 + 0x4*i0
; }
390 static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0
) { return 0x00000228 + 0x4*i0
; }
391 #define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001
392 #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0
393 static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val
)
395 return ((val
) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT
) & HDMI_I2C_TRANSACTION_REG_RW__MASK
;
397 #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100
398 #define HDMI_I2C_TRANSACTION_REG_START 0x00001000
399 #define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000
400 #define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000
401 #define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16
402 static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val
)
404 return ((val
) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT
) & HDMI_I2C_TRANSACTION_REG_CNT__MASK
;
407 #define REG_HDMI_DDC_DATA 0x00000238
408 #define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001
409 #define HDMI_DDC_DATA_DATA_RW__SHIFT 0
410 static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val
)
412 return ((val
) << HDMI_DDC_DATA_DATA_RW__SHIFT
) & HDMI_DDC_DATA_DATA_RW__MASK
;
414 #define HDMI_DDC_DATA_DATA__MASK 0x0000ff00
415 #define HDMI_DDC_DATA_DATA__SHIFT 8
416 static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val
)
418 return ((val
) << HDMI_DDC_DATA_DATA__SHIFT
) & HDMI_DDC_DATA_DATA__MASK
;
420 #define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000
421 #define HDMI_DDC_DATA_INDEX__SHIFT 16
422 static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val
)
424 return ((val
) << HDMI_DDC_DATA_INDEX__SHIFT
) & HDMI_DDC_DATA_INDEX__MASK
;
426 #define HDMI_DDC_DATA_INDEX_WRITE 0x80000000
428 #define REG_HDMI_HDCP_SHA_CTRL 0x0000023c
430 #define REG_HDMI_HDCP_SHA_STATUS 0x00000240
431 #define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001
432 #define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010
434 #define REG_HDMI_HDCP_SHA_DATA 0x00000244
435 #define HDMI_HDCP_SHA_DATA_DONE 0x00000001
437 #define REG_HDMI_HPD_INT_STATUS 0x00000250
438 #define HDMI_HPD_INT_STATUS_INT 0x00000001
439 #define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002
441 #define REG_HDMI_HPD_INT_CTRL 0x00000254
442 #define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001
443 #define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002
444 #define HDMI_HPD_INT_CTRL_INT_EN 0x00000004
445 #define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010
446 #define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020
447 #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200
449 #define REG_HDMI_HPD_CTRL 0x00000258
450 #define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff
451 #define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0
452 static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val
)
454 return ((val
) << HDMI_HPD_CTRL_TIMEOUT__SHIFT
) & HDMI_HPD_CTRL_TIMEOUT__MASK
;
456 #define HDMI_HPD_CTRL_ENABLE 0x10000000
458 #define REG_HDMI_DDC_REF 0x0000027c
459 #define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000
460 #define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff
461 #define HDMI_DDC_REF_REFTIMER__SHIFT 0
462 static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val
)
464 return ((val
) << HDMI_DDC_REF_REFTIMER__SHIFT
) & HDMI_DDC_REF_REFTIMER__MASK
;
467 #define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284
469 #define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288
471 #define REG_HDMI_CEC_CTRL 0x0000028c
473 #define REG_HDMI_CEC_WR_DATA 0x00000290
475 #define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294
477 #define REG_HDMI_CEC_STATUS 0x00000298
479 #define REG_HDMI_CEC_INT 0x0000029c
481 #define REG_HDMI_CEC_ADDR 0x000002a0
483 #define REG_HDMI_CEC_TIME 0x000002a4
485 #define REG_HDMI_CEC_REFTIMER 0x000002a8
487 #define REG_HDMI_CEC_RD_DATA 0x000002ac
489 #define REG_HDMI_CEC_RD_FILTER 0x000002b0
491 #define REG_HDMI_ACTIVE_HSYNC 0x000002b4
492 #define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff
493 #define HDMI_ACTIVE_HSYNC_START__SHIFT 0
494 static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val
)
496 return ((val
) << HDMI_ACTIVE_HSYNC_START__SHIFT
) & HDMI_ACTIVE_HSYNC_START__MASK
;
498 #define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000
499 #define HDMI_ACTIVE_HSYNC_END__SHIFT 16
500 static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val
)
502 return ((val
) << HDMI_ACTIVE_HSYNC_END__SHIFT
) & HDMI_ACTIVE_HSYNC_END__MASK
;
505 #define REG_HDMI_ACTIVE_VSYNC 0x000002b8
506 #define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff
507 #define HDMI_ACTIVE_VSYNC_START__SHIFT 0
508 static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val
)
510 return ((val
) << HDMI_ACTIVE_VSYNC_START__SHIFT
) & HDMI_ACTIVE_VSYNC_START__MASK
;
512 #define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000
513 #define HDMI_ACTIVE_VSYNC_END__SHIFT 16
514 static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val
)
516 return ((val
) << HDMI_ACTIVE_VSYNC_END__SHIFT
) & HDMI_ACTIVE_VSYNC_END__MASK
;
519 #define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc
520 #define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff
521 #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0
522 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val
)
524 return ((val
) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT
) & HDMI_VSYNC_ACTIVE_F2_START__MASK
;
526 #define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000
527 #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16
528 static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val
)
530 return ((val
) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT
) & HDMI_VSYNC_ACTIVE_F2_END__MASK
;
533 #define REG_HDMI_TOTAL 0x000002c0
534 #define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff
535 #define HDMI_TOTAL_H_TOTAL__SHIFT 0
536 static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val
)
538 return ((val
) << HDMI_TOTAL_H_TOTAL__SHIFT
) & HDMI_TOTAL_H_TOTAL__MASK
;
540 #define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000
541 #define HDMI_TOTAL_V_TOTAL__SHIFT 16
542 static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val
)
544 return ((val
) << HDMI_TOTAL_V_TOTAL__SHIFT
) & HDMI_TOTAL_V_TOTAL__MASK
;
547 #define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4
548 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff
549 #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0
550 static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val
)
552 return ((val
) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT
) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK
;
555 #define REG_HDMI_FRAME_CTRL 0x000002c8
556 #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000
557 #define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000
558 #define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000
559 #define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000
561 #define REG_HDMI_AUD_INT 0x000002cc
562 #define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
563 #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
564 #define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
565 #define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
567 #define REG_HDMI_PHY_CTRL 0x000002d4
568 #define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001
569 #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002
570 #define HDMI_PHY_CTRL_SW_RESET 0x00000004
571 #define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008
573 #define REG_HDMI_CEC_WR_RANGE 0x000002dc
575 #define REG_HDMI_CEC_RD_RANGE 0x000002e0
577 #define REG_HDMI_VERSION 0x000002e4
579 #define REG_HDMI_CEC_COMPL_CTL 0x00000360
581 #define REG_HDMI_CEC_RD_START_RANGE 0x00000364
583 #define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368
585 #define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c
587 #define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
589 #define REG_HDMI_8x60_PHY_REG0 0x00000000
590 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
591 #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2
592 static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val
)
594 return ((val
) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT
) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK
;
597 #define REG_HDMI_8x60_PHY_REG1 0x00000004
598 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0
599 #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4
600 static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val
)
602 return ((val
) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT
) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK
;
604 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f
605 #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0
606 static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val
)
608 return ((val
) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT
) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK
;
611 #define REG_HDMI_8x60_PHY_REG2 0x00000008
612 #define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001
613 #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002
614 #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004
615 #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008
616 #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010
617 #define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020
618 #define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040
619 #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080
621 #define REG_HDMI_8x60_PHY_REG3 0x0000000c
622 #define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001
624 #define REG_HDMI_8x60_PHY_REG4 0x00000010
626 #define REG_HDMI_8x60_PHY_REG5 0x00000014
628 #define REG_HDMI_8x60_PHY_REG6 0x00000018
630 #define REG_HDMI_8x60_PHY_REG7 0x0000001c
632 #define REG_HDMI_8x60_PHY_REG8 0x00000020
634 #define REG_HDMI_8x60_PHY_REG9 0x00000024
636 #define REG_HDMI_8x60_PHY_REG10 0x00000028
638 #define REG_HDMI_8x60_PHY_REG11 0x0000002c
640 #define REG_HDMI_8x60_PHY_REG12 0x00000030
641 #define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001
642 #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002
643 #define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010
645 #define REG_HDMI_8960_PHY_REG0 0x00000000
647 #define REG_HDMI_8960_PHY_REG1 0x00000004
649 #define REG_HDMI_8960_PHY_REG2 0x00000008
651 #define REG_HDMI_8960_PHY_REG3 0x0000000c
653 #define REG_HDMI_8960_PHY_REG4 0x00000010
655 #define REG_HDMI_8960_PHY_REG5 0x00000014
657 #define REG_HDMI_8960_PHY_REG6 0x00000018
659 #define REG_HDMI_8960_PHY_REG7 0x0000001c
661 #define REG_HDMI_8960_PHY_REG8 0x00000020
663 #define REG_HDMI_8960_PHY_REG9 0x00000024
665 #define REG_HDMI_8960_PHY_REG10 0x00000028
667 #define REG_HDMI_8960_PHY_REG11 0x0000002c
669 #define REG_HDMI_8960_PHY_REG12 0x00000030
670 #define HDMI_8960_PHY_REG12_SW_RESET 0x00000020
671 #define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080
673 #define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034
675 #define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038
677 #define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c
679 #define REG_HDMI_8960_PHY_REG13 0x00000040
681 #define REG_HDMI_8960_PHY_REG14 0x00000044
683 #define REG_HDMI_8960_PHY_REG15 0x00000048
685 #define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000
687 #define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004
689 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008
691 #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c
693 #define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010
695 #define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014
697 #define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018
698 #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002
699 #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008
701 #define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c
703 #define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020
705 #define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024
707 #define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028
709 #define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c
711 #define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030
713 #define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034
715 #define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038
717 #define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c
719 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040
721 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044
723 #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048
725 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c
727 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050
729 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054
731 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058
733 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c
735 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060
737 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064
739 #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068
741 #define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c
743 #define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070
745 #define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074
747 #define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078
749 #define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c
751 #define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080
753 #define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084
755 #define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088
757 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c
759 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090
761 #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094
763 #define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098
764 #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001
766 #define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c
768 #define REG_HDMI_8x74_ANA_CFG0 0x00000000
770 #define REG_HDMI_8x74_ANA_CFG1 0x00000004
772 #define REG_HDMI_8x74_PD_CTRL0 0x00000010
774 #define REG_HDMI_8x74_PD_CTRL1 0x00000014
776 #define REG_HDMI_8x74_BIST_CFG0 0x00000034
778 #define REG_HDMI_8x74_BIST_PATN0 0x0000003c
780 #define REG_HDMI_8x74_BIST_PATN1 0x00000040
782 #define REG_HDMI_8x74_BIST_PATN2 0x00000044
784 #define REG_HDMI_8x74_BIST_PATN3 0x00000048
786 #define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
788 #define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
790 #define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
792 #define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
794 #define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010
796 #define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
798 #define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018
800 #define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
802 #define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020
803 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
804 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
805 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
806 #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
808 #define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
810 #define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
812 #define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
814 #define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
816 #define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
818 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038
820 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
822 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040
824 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044
826 #define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048
828 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
830 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050
832 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054
834 #define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058
836 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
838 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
840 #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
842 #define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068
843 #define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
845 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
847 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070
849 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074
851 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078
853 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
855 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080
857 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084
859 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088
861 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
863 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090
865 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094
867 #define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098
869 #define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
871 #define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
873 #define REG_HDMI_8996_PHY_CFG 0x00000000
875 #define REG_HDMI_8996_PHY_PD_CTL 0x00000004
877 #define REG_HDMI_8996_PHY_MODE 0x00000008
879 #define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c
881 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010
883 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014
885 #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018
887 #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c
889 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020
891 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024
893 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028
895 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c
897 #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030
899 #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034
901 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038
903 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c
905 #define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040
907 #define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044
909 #define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048
911 #define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c
913 #define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050
915 #define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054
917 #define REG_HDMI_8996_PHY_CLOCK 0x00000058
919 #define REG_HDMI_8996_PHY_MISC1 0x0000005c
921 #define REG_HDMI_8996_PHY_MISC2 0x00000060
923 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064
925 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068
927 #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c
929 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070
931 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074
933 #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078
935 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c
937 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080
939 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084
941 #define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088
943 #define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c
945 #define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090
947 #define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094
949 #define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098
951 #define REG_HDMI_8996_PHY_STATUS 0x0000009c
953 #define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0
955 #define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4
957 #define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8
959 #define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac
961 #define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0
963 #define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4
965 #define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8
967 #define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc
969 #define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0
971 #define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4
973 #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000
975 #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004
977 #define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008
979 #define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c
981 #define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010
983 #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014
985 #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018
987 #define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c
989 #define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020
991 #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024
993 #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028
995 #define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c
997 #define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030
999 #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034
1001 #define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038
1003 #define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c
1005 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040
1007 #define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044
1009 #define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048
1011 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c
1013 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050
1015 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054
1017 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058
1019 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c
1021 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060
1023 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064
1025 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064
1027 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068
1029 #define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068
1031 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c
1033 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c
1035 #define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070
1037 #define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074
1039 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078
1041 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c
1043 #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080
1045 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080
1047 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084
1049 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088
1051 #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c
1053 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c
1055 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090
1057 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094
1059 #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098
1061 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098
1063 #define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c
1065 #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0
1067 #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4
1069 #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8
1071 #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8
1073 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac
1075 #define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0
1077 #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4
1079 #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8
1081 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc
1083 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0
1085 #define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4
1087 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8
1089 #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc
1091 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0
1093 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4
1095 #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8
1097 #define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8
1099 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc
1101 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0
1103 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4
1105 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8
1107 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec
1109 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0
1111 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4
1113 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4
1115 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8
1117 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8
1119 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc
1121 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc
1123 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100
1125 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104
1127 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108
1129 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c
1131 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110
1133 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114
1135 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118
1137 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118
1139 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c
1141 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c
1143 #define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120
1145 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124
1147 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128
1149 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c
1151 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130
1153 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134
1155 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138
1157 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c
1159 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c
1161 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140
1163 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140
1165 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144
1167 #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148
1169 #define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c
1171 #define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150
1173 #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154
1175 #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158
1177 #define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c
1179 #define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160
1181 #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164
1183 #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168
1185 #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c
1187 #define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170
1189 #define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174
1191 #define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178
1193 #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c
1195 #define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180
1197 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184
1199 #define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188
1201 #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c
1203 #define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190
1205 #define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194
1207 #define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198
1209 #define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c
1211 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0
1213 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4
1215 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8
1217 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac
1219 #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0
1221 #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4
1223 #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8
1225 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc
1227 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0
1229 #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4
1231 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000
1233 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004
1235 #define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008
1237 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c
1239 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010
1241 #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014
1243 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018
1245 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c
1247 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020
1249 #define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024
1251 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028
1253 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c
1255 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030
1257 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034
1259 #define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038
1261 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c
1263 #define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040
1265 #define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044
1267 #define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048
1269 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c
1271 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050
1273 #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054
1275 #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058
1277 #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c
1279 #define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060
1281 #define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064
1283 #define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068
1285 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c
1287 #define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070
1289 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074
1291 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078
1293 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c
1295 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080
1297 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084
1299 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088
1301 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c
1303 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090
1305 #define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094
1307 #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098
1309 #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c
1311 #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0
1313 #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4
1315 #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8
1317 #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac
1319 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0
1321 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4
1323 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8
1325 #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc
1327 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0
1329 #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4
1331 #define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8
1333 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc
1335 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0
1337 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4
1339 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8
1341 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc
1343 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0
1345 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4
1347 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8
1349 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec
1351 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0
1353 #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4
1355 #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8
1357 #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc
1359 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100
1361 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104
1363 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108
1365 #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c
1367 #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110
1370 #endif /* HDMI_XML */
projects / mirror_ubuntu-artful-kernel.git / blob