4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
23 Copyright (C) 2013-2015 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
26 Permission is hereby granted, free of charge, to any person obtaining
27 a copy of this software and associated documentation files (the
28 "Software"), to deal in the Software without restriction, including
29 without limitation the rights to use, copy, modify, merge, publish,
30 distribute, sublicense, and/or sell copies of the Software, and to
31 permit persons to whom the Software is furnished to do so, subject to
32 the following conditions:
34 The above copyright notice and this permission notice (including the
35 next paragraph) shall be included in all copies or substantial
36 portions of the Software.
38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
40 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
41 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
42 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
43 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
44 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
71 enum mdp4_cursor_format
{
76 enum mdp4_frame_format
{
78 FRAME_TILE_ARGB_4X4
= 1,
79 FRAME_TILE_YCBCR_420
= 2,
82 enum mdp4_scale_unit
{
94 #define MDP4_IRQ_OVERLAY0_DONE 0x00000001
95 #define MDP4_IRQ_OVERLAY1_DONE 0x00000002
96 #define MDP4_IRQ_DMA_S_DONE 0x00000004
97 #define MDP4_IRQ_DMA_E_DONE 0x00000008
98 #define MDP4_IRQ_DMA_P_DONE 0x00000010
99 #define MDP4_IRQ_VG1_HISTOGRAM 0x00000020
100 #define MDP4_IRQ_VG2_HISTOGRAM 0x00000040
101 #define MDP4_IRQ_PRIMARY_VSYNC 0x00000080
102 #define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100
103 #define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200
104 #define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400
105 #define MDP4_IRQ_PRIMARY_RDPTR 0x00000800
106 #define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000
107 #define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000
108 #define MDP4_IRQ_OVERLAY2_DONE 0x40000000
109 #define REG_MDP4_VERSION 0x00000000
110 #define MDP4_VERSION_MINOR__MASK 0x00ff0000
111 #define MDP4_VERSION_MINOR__SHIFT 16
112 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val
)
114 return ((val
) << MDP4_VERSION_MINOR__SHIFT
) & MDP4_VERSION_MINOR__MASK
;
116 #define MDP4_VERSION_MAJOR__MASK 0xff000000
117 #define MDP4_VERSION_MAJOR__SHIFT 24
118 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val
)
120 return ((val
) << MDP4_VERSION_MAJOR__SHIFT
) & MDP4_VERSION_MAJOR__MASK
;
123 #define REG_MDP4_OVLP0_KICK 0x00000004
125 #define REG_MDP4_OVLP1_KICK 0x00000008
127 #define REG_MDP4_OVLP2_KICK 0x000000d0
129 #define REG_MDP4_DMA_P_KICK 0x0000000c
131 #define REG_MDP4_DMA_S_KICK 0x00000010
133 #define REG_MDP4_DMA_E_KICK 0x00000014
135 #define REG_MDP4_DISP_STATUS 0x00000018
137 #define REG_MDP4_DISP_INTF_SEL 0x00000038
138 #define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003
139 #define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0
140 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val
)
142 return ((val
) << MDP4_DISP_INTF_SEL_PRIM__SHIFT
) & MDP4_DISP_INTF_SEL_PRIM__MASK
;
144 #define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c
145 #define MDP4_DISP_INTF_SEL_SEC__SHIFT 2
146 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val
)
148 return ((val
) << MDP4_DISP_INTF_SEL_SEC__SHIFT
) & MDP4_DISP_INTF_SEL_SEC__MASK
;
150 #define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030
151 #define MDP4_DISP_INTF_SEL_EXT__SHIFT 4
152 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val
)
154 return ((val
) << MDP4_DISP_INTF_SEL_EXT__SHIFT
) & MDP4_DISP_INTF_SEL_EXT__MASK
;
156 #define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040
157 #define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080
159 #define REG_MDP4_RESET_STATUS 0x0000003c
161 #define REG_MDP4_READ_CNFG 0x0000004c
163 #define REG_MDP4_INTR_ENABLE 0x00000050
165 #define REG_MDP4_INTR_STATUS 0x00000054
167 #define REG_MDP4_INTR_CLEAR 0x00000058
169 #define REG_MDP4_EBI2_LCD0 0x00000060
171 #define REG_MDP4_EBI2_LCD1 0x00000064
173 #define REG_MDP4_PORTMAP_MODE 0x00000070
175 #define REG_MDP4_CS_CONTROLLER0 0x000000c0
177 #define REG_MDP4_CS_CONTROLLER1 0x000000c4
179 #define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
180 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
181 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
182 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val
)
184 return ((val
) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT
) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK
;
186 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
187 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
188 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
189 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val
)
191 return ((val
) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT
) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK
;
193 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
194 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
195 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
196 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val
)
198 return ((val
) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT
) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK
;
200 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
201 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
202 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
203 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val
)
205 return ((val
) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT
) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK
;
207 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
208 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
209 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
210 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val
)
212 return ((val
) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT
) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK
;
214 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
215 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
216 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
217 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val
)
219 return ((val
) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT
) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK
;
221 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
222 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
223 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
224 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val
)
226 return ((val
) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT
) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK
;
228 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
229 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
230 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
231 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val
)
233 return ((val
) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT
) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK
;
235 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000
237 #define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc
239 #define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
240 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
241 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
242 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val
)
244 return ((val
) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT
) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK
;
246 #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
247 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
248 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
249 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val
)
251 return ((val
) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT
) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK
;
253 #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
254 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
255 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
256 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val
)
258 return ((val
) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT
) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK
;
260 #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
261 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
262 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
263 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val
)
265 return ((val
) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT
) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK
;
267 #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
268 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
269 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
270 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val
)
272 return ((val
) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT
) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK
;
274 #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
275 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
276 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
277 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val
)
279 return ((val
) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT
) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK
;
281 #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
282 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
283 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
284 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val
)
286 return ((val
) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT
) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK
;
288 #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
289 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
290 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
291 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val
)
293 return ((val
) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT
) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK
;
295 #define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000
297 #define REG_MDP4_VG2_SRC_FORMAT 0x00030050
299 #define REG_MDP4_VG2_CONST_COLOR 0x00031008
301 #define REG_MDP4_OVERLAY_FLUSH 0x00018000
302 #define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001
303 #define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002
304 #define MDP4_OVERLAY_FLUSH_VG1 0x00000004
305 #define MDP4_OVERLAY_FLUSH_VG2 0x00000008
306 #define MDP4_OVERLAY_FLUSH_RGB1 0x00000010
307 #define MDP4_OVERLAY_FLUSH_RGB2 0x00000020
309 static inline uint32_t __offset_OVLP(uint32_t idx
)
312 case 0: return 0x00010000;
313 case 1: return 0x00018000;
314 case 2: return 0x00088000;
315 default: return INVALID_IDX(idx
);
318 static inline uint32_t REG_MDP4_OVLP(uint32_t i0
) { return 0x00000000 + __offset_OVLP(i0
); }
320 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0
) { return 0x00000004 + __offset_OVLP(i0
); }
322 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0
) { return 0x00000008 + __offset_OVLP(i0
); }
323 #define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000
324 #define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16
325 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val
)
327 return ((val
) << MDP4_OVLP_SIZE_HEIGHT__SHIFT
) & MDP4_OVLP_SIZE_HEIGHT__MASK
;
329 #define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff
330 #define MDP4_OVLP_SIZE_WIDTH__SHIFT 0
331 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val
)
333 return ((val
) << MDP4_OVLP_SIZE_WIDTH__SHIFT
) & MDP4_OVLP_SIZE_WIDTH__MASK
;
336 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0
) { return 0x0000000c + __offset_OVLP(i0
); }
338 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0
) { return 0x00000010 + __offset_OVLP(i0
); }
340 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0
) { return 0x00000014 + __offset_OVLP(i0
); }
342 static inline uint32_t __offset_STAGE(uint32_t idx
)
345 case 0: return 0x00000104;
346 case 1: return 0x00000124;
347 case 2: return 0x00000144;
348 case 3: return 0x00000160;
349 default: return INVALID_IDX(idx
);
352 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0
, uint32_t i1
) { return 0x00000000 + __offset_OVLP(i0
) + __offset_STAGE(i1
); }
354 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0
, uint32_t i1
) { return 0x00000000 + __offset_OVLP(i0
) + __offset_STAGE(i1
); }
355 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
356 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
357 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val
)
359 return ((val
) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT
) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK
;
361 #define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004
362 #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
363 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
364 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
365 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val
)
367 return ((val
) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT
) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK
;
369 #define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040
370 #define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080
371 #define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100
372 #define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200
374 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0
, uint32_t i1
) { return 0x00000004 + __offset_OVLP(i0
) + __offset_STAGE(i1
); }
376 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0
, uint32_t i1
) { return 0x00000008 + __offset_OVLP(i0
) + __offset_STAGE(i1
); }
378 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0
, uint32_t i1
) { return 0x0000000c + __offset_OVLP(i0
) + __offset_STAGE(i1
); }
380 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0
, uint32_t i1
) { return 0x00000010 + __offset_OVLP(i0
) + __offset_STAGE(i1
); }
382 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0
, uint32_t i1
) { return 0x00000014 + __offset_OVLP(i0
) + __offset_STAGE(i1
); }
384 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0
, uint32_t i1
) { return 0x00000018 + __offset_OVLP(i0
) + __offset_STAGE(i1
); }
386 static inline uint32_t __offset_STAGE_CO3(uint32_t idx
)
389 case 0: return 0x00001004;
390 case 1: return 0x00001404;
391 case 2: return 0x00001804;
392 case 3: return 0x00001b84;
393 default: return INVALID_IDX(idx
);
396 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0
, uint32_t i1
) { return 0x00000000 + __offset_OVLP(i0
) + __offset_STAGE_CO3(i1
); }
398 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0
, uint32_t i1
) { return 0x00000000 + __offset_OVLP(i0
) + __offset_STAGE_CO3(i1
); }
399 #define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001
401 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0
) { return 0x00000180 + __offset_OVLP(i0
); }
403 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0
) { return 0x00000184 + __offset_OVLP(i0
); }
405 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0
) { return 0x00000188 + __offset_OVLP(i0
); }
407 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0
) { return 0x0000018c + __offset_OVLP(i0
); }
409 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0
) { return 0x00000200 + __offset_OVLP(i0
); }
411 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0
) { return 0x00002000 + __offset_OVLP(i0
); }
414 static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0
, uint32_t i1
) { return 0x00002400 + __offset_OVLP(i0
) + 0x4*i1
; }
416 static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0
, uint32_t i1
) { return 0x00002400 + __offset_OVLP(i0
) + 0x4*i1
; }
418 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0
, uint32_t i1
) { return 0x00002500 + __offset_OVLP(i0
) + 0x4*i1
; }
420 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0
, uint32_t i1
) { return 0x00002500 + __offset_OVLP(i0
) + 0x4*i1
; }
422 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0
, uint32_t i1
) { return 0x00002580 + __offset_OVLP(i0
) + 0x4*i1
; }
424 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0
, uint32_t i1
) { return 0x00002580 + __offset_OVLP(i0
) + 0x4*i1
; }
426 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0
, uint32_t i1
) { return 0x00002600 + __offset_OVLP(i0
) + 0x4*i1
; }
428 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0
, uint32_t i1
) { return 0x00002600 + __offset_OVLP(i0
) + 0x4*i1
; }
430 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0
, uint32_t i1
) { return 0x00002680 + __offset_OVLP(i0
) + 0x4*i1
; }
432 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0
, uint32_t i1
) { return 0x00002680 + __offset_OVLP(i0
) + 0x4*i1
; }
434 #define REG_MDP4_DMA_P_OP_MODE 0x00090070
436 static inline uint32_t REG_MDP4_LUTN(uint32_t i0
) { return 0x00094800 + 0x400*i0
; }
438 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0
, uint32_t i1
) { return 0x00094800 + 0x400*i0
+ 0x4*i1
; }
440 static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0
, uint32_t i1
) { return 0x00094800 + 0x400*i0
+ 0x4*i1
; }
442 #define REG_MDP4_DMA_S_OP_MODE 0x000a0028
444 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0
) { return 0x000b0070 + 0x4*i0
; }
446 static inline uint32_t __offset_DMA(enum mdp4_dma idx
)
449 case DMA_P
: return 0x00090000;
450 case DMA_S
: return 0x000a0000;
451 case DMA_E
: return 0x000b0000;
452 default: return INVALID_IDX(idx
);
455 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0
) { return 0x00000000 + __offset_DMA(i0
); }
457 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0
) { return 0x00000000 + __offset_DMA(i0
); }
458 #define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
459 #define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
460 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val
)
462 return ((val
) << MDP4_DMA_CONFIG_G_BPC__SHIFT
) & MDP4_DMA_CONFIG_G_BPC__MASK
;
464 #define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
465 #define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
466 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val
)
468 return ((val
) << MDP4_DMA_CONFIG_B_BPC__SHIFT
) & MDP4_DMA_CONFIG_B_BPC__MASK
;
470 #define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
471 #define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
472 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val
)
474 return ((val
) << MDP4_DMA_CONFIG_R_BPC__SHIFT
) & MDP4_DMA_CONFIG_R_BPC__MASK
;
476 #define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080
477 #define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00
478 #define MDP4_DMA_CONFIG_PACK__SHIFT 8
479 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val
)
481 return ((val
) << MDP4_DMA_CONFIG_PACK__SHIFT
) & MDP4_DMA_CONFIG_PACK__MASK
;
483 #define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000
484 #define MDP4_DMA_CONFIG_DITHER_EN 0x01000000
486 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0
) { return 0x00000004 + __offset_DMA(i0
); }
487 #define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000
488 #define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16
489 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val
)
491 return ((val
) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT
) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK
;
493 #define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff
494 #define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0
495 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val
)
497 return ((val
) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT
) & MDP4_DMA_SRC_SIZE_WIDTH__MASK
;
500 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0
) { return 0x00000008 + __offset_DMA(i0
); }
502 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0
) { return 0x0000000c + __offset_DMA(i0
); }
504 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0
) { return 0x00000010 + __offset_DMA(i0
); }
505 #define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000
506 #define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16
507 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val
)
509 return ((val
) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT
) & MDP4_DMA_DST_SIZE_HEIGHT__MASK
;
511 #define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff
512 #define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0
513 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val
)
515 return ((val
) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT
) & MDP4_DMA_DST_SIZE_WIDTH__MASK
;
518 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0
) { return 0x00000044 + __offset_DMA(i0
); }
519 #define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f
520 #define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0
521 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val
)
523 return ((val
) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT
) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK
;
525 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000
526 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16
527 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val
)
529 return ((val
) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT
) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK
;
532 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0
) { return 0x00000048 + __offset_DMA(i0
); }
534 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0
) { return 0x0000004c + __offset_DMA(i0
); }
535 #define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff
536 #define MDP4_DMA_CURSOR_POS_X__SHIFT 0
537 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val
)
539 return ((val
) << MDP4_DMA_CURSOR_POS_X__SHIFT
) & MDP4_DMA_CURSOR_POS_X__MASK
;
541 #define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000
542 #define MDP4_DMA_CURSOR_POS_Y__SHIFT 16
543 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val
)
545 return ((val
) << MDP4_DMA_CURSOR_POS_Y__SHIFT
) & MDP4_DMA_CURSOR_POS_Y__MASK
;
548 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0
) { return 0x00000060 + __offset_DMA(i0
); }
549 #define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001
550 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006
551 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1
552 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val
)
554 return ((val
) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT
) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK
;
556 #define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008
558 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0
) { return 0x00000064 + __offset_DMA(i0
); }
560 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0
) { return 0x00000068 + __offset_DMA(i0
); }
562 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0
) { return 0x0000006c + __offset_DMA(i0
); }
564 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0
) { return 0x00001004 + __offset_DMA(i0
); }
566 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0
) { return 0x00003000 + __offset_DMA(i0
); }
569 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0
, uint32_t i1
) { return 0x00003400 + __offset_DMA(i0
) + 0x4*i1
; }
571 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0
, uint32_t i1
) { return 0x00003400 + __offset_DMA(i0
) + 0x4*i1
; }
573 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0
, uint32_t i1
) { return 0x00003500 + __offset_DMA(i0
) + 0x4*i1
; }
575 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0
, uint32_t i1
) { return 0x00003500 + __offset_DMA(i0
) + 0x4*i1
; }
577 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0
, uint32_t i1
) { return 0x00003580 + __offset_DMA(i0
) + 0x4*i1
; }
579 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0
, uint32_t i1
) { return 0x00003580 + __offset_DMA(i0
) + 0x4*i1
; }
581 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0
, uint32_t i1
) { return 0x00003600 + __offset_DMA(i0
) + 0x4*i1
; }
583 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0
, uint32_t i1
) { return 0x00003600 + __offset_DMA(i0
) + 0x4*i1
; }
585 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0
, uint32_t i1
) { return 0x00003680 + __offset_DMA(i0
) + 0x4*i1
; }
587 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0
, uint32_t i1
) { return 0x00003680 + __offset_DMA(i0
) + 0x4*i1
; }
589 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0
) { return 0x00020000 + 0x10000*i0
; }
591 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0
) { return 0x00020000 + 0x10000*i0
; }
592 #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
593 #define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
594 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val
)
596 return ((val
) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT
) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK
;
598 #define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
599 #define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0
600 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val
)
602 return ((val
) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT
) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK
;
605 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0
) { return 0x00020004 + 0x10000*i0
; }
606 #define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
607 #define MDP4_PIPE_SRC_XY_Y__SHIFT 16
608 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val
)
610 return ((val
) << MDP4_PIPE_SRC_XY_Y__SHIFT
) & MDP4_PIPE_SRC_XY_Y__MASK
;
612 #define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff
613 #define MDP4_PIPE_SRC_XY_X__SHIFT 0
614 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val
)
616 return ((val
) << MDP4_PIPE_SRC_XY_X__SHIFT
) & MDP4_PIPE_SRC_XY_X__MASK
;
619 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0
) { return 0x00020008 + 0x10000*i0
; }
620 #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
621 #define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16
622 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val
)
624 return ((val
) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT
) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK
;
626 #define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff
627 #define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0
628 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val
)
630 return ((val
) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT
) & MDP4_PIPE_DST_SIZE_WIDTH__MASK
;
633 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0
) { return 0x0002000c + 0x10000*i0
; }
634 #define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
635 #define MDP4_PIPE_DST_XY_Y__SHIFT 16
636 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val
)
638 return ((val
) << MDP4_PIPE_DST_XY_Y__SHIFT
) & MDP4_PIPE_DST_XY_Y__MASK
;
640 #define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff
641 #define MDP4_PIPE_DST_XY_X__SHIFT 0
642 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val
)
644 return ((val
) << MDP4_PIPE_DST_XY_X__SHIFT
) & MDP4_PIPE_DST_XY_X__MASK
;
647 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0
) { return 0x00020010 + 0x10000*i0
; }
649 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0
) { return 0x00020014 + 0x10000*i0
; }
651 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0
) { return 0x00020018 + 0x10000*i0
; }
653 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0
) { return 0x0002001c + 0x10000*i0
; }
655 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0
) { return 0x00020040 + 0x10000*i0
; }
656 #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
657 #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
658 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val
)
660 return ((val
) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT
) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK
;
662 #define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
663 #define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16
664 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val
)
666 return ((val
) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT
) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK
;
669 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0
) { return 0x00020044 + 0x10000*i0
; }
670 #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
671 #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
672 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val
)
674 return ((val
) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT
) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK
;
676 #define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
677 #define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16
678 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val
)
680 return ((val
) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT
) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK
;
683 static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0
) { return 0x00020048 + 0x10000*i0
; }
684 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
685 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16
686 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val
)
688 return ((val
) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT
) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK
;
690 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
691 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0
692 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val
)
694 return ((val
) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT
) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK
;
697 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0
) { return 0x00020050 + 0x10000*i0
; }
698 #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
699 #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
700 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val
)
702 return ((val
) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT
) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK
;
704 #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
705 #define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
706 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val
)
708 return ((val
) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT
) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK
;
710 #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
711 #define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
712 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val
)
714 return ((val
) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT
) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK
;
716 #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
717 #define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
718 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val
)
720 return ((val
) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT
) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK
;
722 #define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
723 #define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
724 #define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9
725 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val
)
727 return ((val
) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT
) & MDP4_PIPE_SRC_FORMAT_CPP__MASK
;
729 #define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000
730 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000
731 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13
732 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val
)
734 return ((val
) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT
) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK
;
736 #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
737 #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
738 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000
739 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT 19
740 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val
)
742 return ((val
) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT
) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK
;
744 #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
745 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000
746 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 26
747 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val
)
749 return ((val
) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT
) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK
;
751 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000
752 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT 29
753 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val
)
755 return ((val
) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT
) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK
;
758 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0
) { return 0x00020054 + 0x10000*i0
; }
759 #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
760 #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
761 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val
)
763 return ((val
) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT
) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK
;
765 #define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
766 #define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
767 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val
)
769 return ((val
) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT
) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK
;
771 #define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
772 #define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
773 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val
)
775 return ((val
) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT
) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK
;
777 #define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
778 #define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
779 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val
)
781 return ((val
) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT
) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK
;
784 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0
) { return 0x00020058 + 0x10000*i0
; }
785 #define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
786 #define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
787 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c
788 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT 2
789 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val
)
791 return ((val
) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT
) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK
;
793 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030
794 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT 4
795 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val
)
797 return ((val
) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT
) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK
;
799 #define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
800 #define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400
801 #define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800
802 #define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000
803 #define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000
804 #define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000
805 #define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000
806 #define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
807 #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
809 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0
) { return 0x0002005c + 0x10000*i0
; }
811 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0
) { return 0x00020060 + 0x10000*i0
; }
813 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0
) { return 0x00021004 + 0x10000*i0
; }
815 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0
) { return 0x00021008 + 0x10000*i0
; }
817 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0
) { return 0x00024000 + 0x10000*i0
; }
820 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0
, uint32_t i1
) { return 0x00024400 + 0x10000*i0
+ 0x4*i1
; }
822 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0
, uint32_t i1
) { return 0x00024400 + 0x10000*i0
+ 0x4*i1
; }
824 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0
, uint32_t i1
) { return 0x00024500 + 0x10000*i0
+ 0x4*i1
; }
826 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0
, uint32_t i1
) { return 0x00024500 + 0x10000*i0
+ 0x4*i1
; }
828 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0
, uint32_t i1
) { return 0x00024580 + 0x10000*i0
+ 0x4*i1
; }
830 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0
, uint32_t i1
) { return 0x00024580 + 0x10000*i0
+ 0x4*i1
; }
832 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0
, uint32_t i1
) { return 0x00024600 + 0x10000*i0
+ 0x4*i1
; }
834 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0
, uint32_t i1
) { return 0x00024600 + 0x10000*i0
+ 0x4*i1
; }
836 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0
, uint32_t i1
) { return 0x00024680 + 0x10000*i0
+ 0x4*i1
; }
838 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0
, uint32_t i1
) { return 0x00024680 + 0x10000*i0
+ 0x4*i1
; }
840 #define REG_MDP4_LCDC 0x000c0000
842 #define REG_MDP4_LCDC_ENABLE 0x000c0000
844 #define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004
845 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
846 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0
847 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val
)
849 return ((val
) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT
) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK
;
851 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000
852 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16
853 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val
)
855 return ((val
) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT
) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK
;
858 #define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008
860 #define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c
862 #define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010
863 #define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff
864 #define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0
865 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val
)
867 return ((val
) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT
) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK
;
869 #define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000
870 #define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16
871 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val
)
873 return ((val
) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT
) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK
;
876 #define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014
878 #define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018
880 #define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c
881 #define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff
882 #define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0
883 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val
)
885 return ((val
) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT
) & MDP4_LCDC_ACTIVE_HCTL_START__MASK
;
887 #define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000
888 #define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16
889 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val
)
891 return ((val
) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT
) & MDP4_LCDC_ACTIVE_HCTL_END__MASK
;
893 #define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
895 #define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020
897 #define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024
899 #define REG_MDP4_LCDC_BORDER_CLR 0x000c0028
901 #define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c
902 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
903 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0
904 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val
)
906 return ((val
) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT
) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK
;
908 #define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
910 #define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030
912 #define REG_MDP4_LCDC_TEST_CNTL 0x000c0034
914 #define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038
915 #define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001
916 #define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002
917 #define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004
919 #define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000
920 #define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004
921 #define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008
922 #define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010
923 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020
924 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040
925 #define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080
926 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100
927 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200
928 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400
929 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800
930 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000
931 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000
932 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000
933 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000
934 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000
935 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000
937 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0
) { return 0x000c2014 + 0x8*i0
; }
939 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0
) { return 0x000c2014 + 0x8*i0
; }
940 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff
941 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0
942 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val
)
944 return ((val
) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT
) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK
;
946 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00
947 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT 8
948 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val
)
950 return ((val
) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT
) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK
;
952 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000
953 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT 16
954 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val
)
956 return ((val
) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT
) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK
;
958 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000
959 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT 24
960 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val
)
962 return ((val
) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT
) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK
;
965 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0
) { return 0x000c2018 + 0x8*i0
; }
966 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff
967 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0
968 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val
)
970 return ((val
) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT
) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK
;
972 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00
973 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT 8
974 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val
)
976 return ((val
) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT
) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK
;
978 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000
979 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT 16
980 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val
)
982 return ((val
) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT
) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK
;
985 #define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034
987 #define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000
989 #define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004
991 #define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008
993 #define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c
995 #define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014
997 #define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018
999 #define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c
1001 #define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020
1003 #define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024
1005 #define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080
1007 #define REG_MDP4_LVDS_PHY_CFG2 0x000c3108
1009 #define REG_MDP4_LVDS_PHY_CFG0 0x000c3100
1010 #define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010
1011 #define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040
1012 #define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080
1014 #define REG_MDP4_DTV 0x000d0000
1016 #define REG_MDP4_DTV_ENABLE 0x000d0000
1018 #define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004
1019 #define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1020 #define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0
1021 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val
)
1023 return ((val
) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT
) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK
;
1025 #define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1026 #define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16
1027 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val
)
1029 return ((val
) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT
) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK
;
1032 #define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008
1034 #define REG_MDP4_DTV_VSYNC_LEN 0x000d000c
1036 #define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018
1037 #define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff
1038 #define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0
1039 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val
)
1041 return ((val
) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT
) & MDP4_DTV_DISPLAY_HCTRL_START__MASK
;
1043 #define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000
1044 #define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16
1045 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val
)
1047 return ((val
) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT
) & MDP4_DTV_DISPLAY_HCTRL_END__MASK
;
1050 #define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c
1052 #define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020
1054 #define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c
1055 #define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff
1056 #define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0
1057 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val
)
1059 return ((val
) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT
) & MDP4_DTV_ACTIVE_HCTL_START__MASK
;
1061 #define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000
1062 #define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16
1063 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val
)
1065 return ((val
) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT
) & MDP4_DTV_ACTIVE_HCTL_END__MASK
;
1067 #define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1069 #define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030
1071 #define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038
1073 #define REG_MDP4_DTV_BORDER_CLR 0x000d0040
1075 #define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044
1076 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1077 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0
1078 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val
)
1080 return ((val
) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT
) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK
;
1082 #define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1084 #define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048
1086 #define REG_MDP4_DTV_TEST_CNTL 0x000d004c
1088 #define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050
1089 #define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001
1090 #define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002
1091 #define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004
1093 #define REG_MDP4_DSI 0x000e0000
1095 #define REG_MDP4_DSI_ENABLE 0x000e0000
1097 #define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004
1098 #define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1099 #define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0
1100 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val
)
1102 return ((val
) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT
) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK
;
1104 #define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1105 #define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16
1106 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val
)
1108 return ((val
) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT
) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK
;
1111 #define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008
1113 #define REG_MDP4_DSI_VSYNC_LEN 0x000e000c
1115 #define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010
1116 #define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff
1117 #define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0
1118 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val
)
1120 return ((val
) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT
) & MDP4_DSI_DISPLAY_HCTRL_START__MASK
;
1122 #define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000
1123 #define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16
1124 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val
)
1126 return ((val
) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT
) & MDP4_DSI_DISPLAY_HCTRL_END__MASK
;
1129 #define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014
1131 #define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018
1133 #define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c
1134 #define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff
1135 #define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0
1136 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val
)
1138 return ((val
) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT
) & MDP4_DSI_ACTIVE_HCTL_START__MASK
;
1140 #define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000
1141 #define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16
1142 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val
)
1144 return ((val
) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT
) & MDP4_DSI_ACTIVE_HCTL_END__MASK
;
1146 #define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1148 #define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020
1150 #define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024
1152 #define REG_MDP4_DSI_BORDER_CLR 0x000e0028
1154 #define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c
1155 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1156 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0
1157 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val
)
1159 return ((val
) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT
) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK
;
1161 #define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1163 #define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030
1165 #define REG_MDP4_DSI_TEST_CNTL 0x000e0034
1167 #define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038
1168 #define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001
1169 #define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002
1170 #define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004
1173 #endif /* MDP4_XML */
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