2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/of_irq.h>
26 static const char *iommu_ports
[] = {
30 static int mdp5_hw_init(struct msm_kms
*kms
)
32 struct mdp5_kms
*mdp5_kms
= to_mdp5_kms(to_mdp_kms(kms
));
33 struct platform_device
*pdev
= mdp5_kms
->pdev
;
36 pm_runtime_get_sync(&pdev
->dev
);
37 mdp5_enable(mdp5_kms
);
39 /* Magic unknown register writes:
41 * W VBIF:0x004 00000001 (mdss_mdp.c:839)
42 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
43 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
44 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
45 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
46 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
47 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
48 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
49 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
51 * Downstream fbdev driver gets these register offsets/values
52 * from DT.. not really sure what these registers are or if
53 * different values for different boards/SoC's, etc. I guess
54 * they are the golden registers.
56 * Not setting these does not seem to cause any problem. But
57 * we may be getting lucky with the bootloader initializing
58 * them for us. OTOH, if we can always count on the bootloader
59 * setting the golden registers, then perhaps we don't need to
63 spin_lock_irqsave(&mdp5_kms
->resource_lock
, flags
);
64 mdp5_write(mdp5_kms
, REG_MDP5_DISP_INTF_SEL
, 0);
65 spin_unlock_irqrestore(&mdp5_kms
->resource_lock
, flags
);
67 mdp5_ctlm_hw_reset(mdp5_kms
->ctlm
);
69 mdp5_disable(mdp5_kms
);
70 pm_runtime_put_sync(&pdev
->dev
);
75 struct mdp5_state
*mdp5_get_state(struct drm_atomic_state
*s
)
77 struct msm_drm_private
*priv
= s
->dev
->dev_private
;
78 struct mdp5_kms
*mdp5_kms
= to_mdp5_kms(to_mdp_kms(priv
->kms
));
79 struct msm_kms_state
*state
= to_kms_state(s
);
80 struct mdp5_state
*new_state
;
86 ret
= drm_modeset_lock(&mdp5_kms
->state_lock
, s
->acquire_ctx
);
90 new_state
= kmalloc(sizeof(*mdp5_kms
->state
), GFP_KERNEL
);
92 return ERR_PTR(-ENOMEM
);
95 new_state
->hwpipe
= mdp5_kms
->state
->hwpipe
;
96 new_state
->hwmixer
= mdp5_kms
->state
->hwmixer
;
98 new_state
->smp
= mdp5_kms
->state
->smp
;
100 state
->state
= new_state
;
105 static void mdp5_swap_state(struct msm_kms
*kms
, struct drm_atomic_state
*state
)
107 struct mdp5_kms
*mdp5_kms
= to_mdp5_kms(to_mdp_kms(kms
));
108 swap(to_kms_state(state
)->state
, mdp5_kms
->state
);
111 static void mdp5_prepare_commit(struct msm_kms
*kms
, struct drm_atomic_state
*state
)
113 struct mdp5_kms
*mdp5_kms
= to_mdp5_kms(to_mdp_kms(kms
));
115 mdp5_enable(mdp5_kms
);
118 mdp5_smp_prepare_commit(mdp5_kms
->smp
, &mdp5_kms
->state
->smp
);
121 static void mdp5_complete_commit(struct msm_kms
*kms
, struct drm_atomic_state
*state
)
123 struct mdp5_kms
*mdp5_kms
= to_mdp5_kms(to_mdp_kms(kms
));
126 mdp5_smp_complete_commit(mdp5_kms
->smp
, &mdp5_kms
->state
->smp
);
128 mdp5_disable(mdp5_kms
);
131 static void mdp5_wait_for_crtc_commit_done(struct msm_kms
*kms
,
132 struct drm_crtc
*crtc
)
134 mdp5_crtc_wait_for_commit_done(crtc
);
137 static long mdp5_round_pixclk(struct msm_kms
*kms
, unsigned long rate
,
138 struct drm_encoder
*encoder
)
143 static int mdp5_set_split_display(struct msm_kms
*kms
,
144 struct drm_encoder
*encoder
,
145 struct drm_encoder
*slave_encoder
,
149 return mdp5_cmd_encoder_set_split_display(encoder
,
152 return mdp5_vid_encoder_set_split_display(encoder
,
156 static void mdp5_set_encoder_mode(struct msm_kms
*kms
,
157 struct drm_encoder
*encoder
,
160 mdp5_encoder_set_intf_mode(encoder
, cmd_mode
);
163 static void mdp5_kms_destroy(struct msm_kms
*kms
)
165 struct mdp5_kms
*mdp5_kms
= to_mdp5_kms(to_mdp_kms(kms
));
166 struct msm_gem_address_space
*aspace
= kms
->aspace
;
169 for (i
= 0; i
< mdp5_kms
->num_hwmixers
; i
++)
170 mdp5_mixer_destroy(mdp5_kms
->hwmixers
[i
]);
172 for (i
= 0; i
< mdp5_kms
->num_hwpipes
; i
++)
173 mdp5_pipe_destroy(mdp5_kms
->hwpipes
[i
]);
176 aspace
->mmu
->funcs
->detach(aspace
->mmu
,
177 iommu_ports
, ARRAY_SIZE(iommu_ports
));
178 msm_gem_address_space_put(aspace
);
182 #ifdef CONFIG_DEBUG_FS
183 static int smp_show(struct seq_file
*m
, void *arg
)
185 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
186 struct drm_device
*dev
= node
->minor
->dev
;
187 struct msm_drm_private
*priv
= dev
->dev_private
;
188 struct mdp5_kms
*mdp5_kms
= to_mdp5_kms(to_mdp_kms(priv
->kms
));
189 struct drm_printer p
= drm_seq_file_printer(m
);
191 if (!mdp5_kms
->smp
) {
192 drm_printf(&p
, "no SMP pool\n");
196 mdp5_smp_dump(mdp5_kms
->smp
, &p
);
201 static struct drm_info_list mdp5_debugfs_list
[] = {
205 static int mdp5_kms_debugfs_init(struct msm_kms
*kms
, struct drm_minor
*minor
)
207 struct drm_device
*dev
= minor
->dev
;
210 ret
= drm_debugfs_create_files(mdp5_debugfs_list
,
211 ARRAY_SIZE(mdp5_debugfs_list
),
212 minor
->debugfs_root
, minor
);
215 dev_err(dev
->dev
, "could not install mdp5_debugfs_list\n");
223 static const struct mdp_kms_funcs kms_funcs
= {
225 .hw_init
= mdp5_hw_init
,
226 .irq_preinstall
= mdp5_irq_preinstall
,
227 .irq_postinstall
= mdp5_irq_postinstall
,
228 .irq_uninstall
= mdp5_irq_uninstall
,
230 .enable_vblank
= mdp5_enable_vblank
,
231 .disable_vblank
= mdp5_disable_vblank
,
232 .swap_state
= mdp5_swap_state
,
233 .prepare_commit
= mdp5_prepare_commit
,
234 .complete_commit
= mdp5_complete_commit
,
235 .wait_for_crtc_commit_done
= mdp5_wait_for_crtc_commit_done
,
236 .get_format
= mdp_get_format
,
237 .round_pixclk
= mdp5_round_pixclk
,
238 .set_split_display
= mdp5_set_split_display
,
239 .set_encoder_mode
= mdp5_set_encoder_mode
,
240 .destroy
= mdp5_kms_destroy
,
241 #ifdef CONFIG_DEBUG_FS
242 .debugfs_init
= mdp5_kms_debugfs_init
,
245 .set_irqmask
= mdp5_set_irqmask
,
248 int mdp5_disable(struct mdp5_kms
*mdp5_kms
)
252 clk_disable_unprepare(mdp5_kms
->ahb_clk
);
253 clk_disable_unprepare(mdp5_kms
->axi_clk
);
254 clk_disable_unprepare(mdp5_kms
->core_clk
);
255 if (mdp5_kms
->lut_clk
)
256 clk_disable_unprepare(mdp5_kms
->lut_clk
);
261 int mdp5_enable(struct mdp5_kms
*mdp5_kms
)
265 clk_prepare_enable(mdp5_kms
->ahb_clk
);
266 clk_prepare_enable(mdp5_kms
->axi_clk
);
267 clk_prepare_enable(mdp5_kms
->core_clk
);
268 if (mdp5_kms
->lut_clk
)
269 clk_prepare_enable(mdp5_kms
->lut_clk
);
274 static struct drm_encoder
*construct_encoder(struct mdp5_kms
*mdp5_kms
,
275 struct mdp5_interface
*intf
,
276 struct mdp5_ctl
*ctl
)
278 struct drm_device
*dev
= mdp5_kms
->dev
;
279 struct msm_drm_private
*priv
= dev
->dev_private
;
280 struct drm_encoder
*encoder
;
282 encoder
= mdp5_encoder_init(dev
, intf
, ctl
);
283 if (IS_ERR(encoder
)) {
284 dev_err(dev
->dev
, "failed to construct encoder\n");
288 priv
->encoders
[priv
->num_encoders
++] = encoder
;
293 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw
*hw_cfg
, int intf_num
)
295 const enum mdp5_intf_type
*intfs
= hw_cfg
->intf
.connect
;
296 const int intf_cnt
= ARRAY_SIZE(hw_cfg
->intf
.connect
);
299 for (i
= 0; i
< intf_cnt
; i
++) {
300 if (intfs
[i
] == INTF_DSI
) {
311 static int modeset_init_intf(struct mdp5_kms
*mdp5_kms
,
312 struct mdp5_interface
*intf
)
314 struct drm_device
*dev
= mdp5_kms
->dev
;
315 struct msm_drm_private
*priv
= dev
->dev_private
;
316 struct mdp5_ctl_manager
*ctlm
= mdp5_kms
->ctlm
;
317 struct mdp5_ctl
*ctl
;
318 struct drm_encoder
*encoder
;
321 switch (intf
->type
) {
326 ctl
= mdp5_ctlm_request(ctlm
, intf
->num
);
332 encoder
= construct_encoder(mdp5_kms
, intf
, ctl
);
333 if (IS_ERR(encoder
)) {
334 ret
= PTR_ERR(encoder
);
338 ret
= msm_edp_modeset_init(priv
->edp
, dev
, encoder
);
344 ctl
= mdp5_ctlm_request(ctlm
, intf
->num
);
350 encoder
= construct_encoder(mdp5_kms
, intf
, ctl
);
351 if (IS_ERR(encoder
)) {
352 ret
= PTR_ERR(encoder
);
356 ret
= msm_hdmi_modeset_init(priv
->hdmi
, dev
, encoder
);
360 const struct mdp5_cfg_hw
*hw_cfg
=
361 mdp5_cfg_get_hw_config(mdp5_kms
->cfg
);
362 int dsi_id
= get_dsi_id_from_intf(hw_cfg
, intf
->num
);
364 if ((dsi_id
>= ARRAY_SIZE(priv
->dsi
)) || (dsi_id
< 0)) {
365 dev_err(dev
->dev
, "failed to find dsi from intf %d\n",
371 if (!priv
->dsi
[dsi_id
])
374 ctl
= mdp5_ctlm_request(ctlm
, intf
->num
);
380 encoder
= construct_encoder(mdp5_kms
, intf
, ctl
);
381 if (IS_ERR(encoder
)) {
382 ret
= PTR_ERR(encoder
);
386 ret
= msm_dsi_modeset_init(priv
->dsi
[dsi_id
], dev
, encoder
);
390 dev_err(dev
->dev
, "unknown intf: %d\n", intf
->type
);
398 static int modeset_init(struct mdp5_kms
*mdp5_kms
)
400 struct drm_device
*dev
= mdp5_kms
->dev
;
401 struct msm_drm_private
*priv
= dev
->dev_private
;
402 const struct mdp5_cfg_hw
*hw_cfg
;
403 unsigned int num_crtcs
;
404 int i
, ret
, pi
= 0, ci
= 0;
405 struct drm_plane
*primary
[MAX_BASES
] = { NULL
};
406 struct drm_plane
*cursor
[MAX_BASES
] = { NULL
};
408 hw_cfg
= mdp5_cfg_get_hw_config(mdp5_kms
->cfg
);
411 * Construct encoders and modeset initialize connector devices
412 * for each external display interface.
414 for (i
= 0; i
< mdp5_kms
->num_intfs
; i
++) {
415 ret
= modeset_init_intf(mdp5_kms
, mdp5_kms
->intfs
[i
]);
421 * We should ideally have less number of encoders (set up by parsing
422 * the MDP5 interfaces) than the number of layer mixers present in HW,
423 * but let's be safe here anyway
425 num_crtcs
= min(priv
->num_encoders
, mdp5_kms
->num_hwmixers
);
428 * Construct planes equaling the number of hw pipes, and CRTCs for the
429 * N encoders set up by the driver. The first N planes become primary
430 * planes for the CRTCs, with the remainder as overlay planes:
432 for (i
= 0; i
< mdp5_kms
->num_hwpipes
; i
++) {
433 struct mdp5_hw_pipe
*hwpipe
= mdp5_kms
->hwpipes
[i
];
434 struct drm_plane
*plane
;
435 enum drm_plane_type type
;
438 type
= DRM_PLANE_TYPE_PRIMARY
;
439 else if (hwpipe
->caps
& MDP_PIPE_CAP_CURSOR
)
440 type
= DRM_PLANE_TYPE_CURSOR
;
442 type
= DRM_PLANE_TYPE_OVERLAY
;
444 plane
= mdp5_plane_init(dev
, type
);
446 ret
= PTR_ERR(plane
);
447 dev_err(dev
->dev
, "failed to construct plane %d (%d)\n", i
, ret
);
450 priv
->planes
[priv
->num_planes
++] = plane
;
452 if (type
== DRM_PLANE_TYPE_PRIMARY
)
453 primary
[pi
++] = plane
;
454 if (type
== DRM_PLANE_TYPE_CURSOR
)
455 cursor
[ci
++] = plane
;
458 for (i
= 0; i
< num_crtcs
; i
++) {
459 struct drm_crtc
*crtc
;
461 crtc
= mdp5_crtc_init(dev
, primary
[i
], cursor
[i
], i
);
464 dev_err(dev
->dev
, "failed to construct crtc %d (%d)\n", i
, ret
);
467 priv
->crtcs
[priv
->num_crtcs
++] = crtc
;
471 * Now that we know the number of crtcs we've created, set the possible
472 * crtcs for the encoders
474 for (i
= 0; i
< priv
->num_encoders
; i
++) {
475 struct drm_encoder
*encoder
= priv
->encoders
[i
];
477 encoder
->possible_crtcs
= (1 << priv
->num_crtcs
) - 1;
486 static void read_mdp_hw_revision(struct mdp5_kms
*mdp5_kms
,
487 u32
*major
, u32
*minor
)
491 mdp5_enable(mdp5_kms
);
492 version
= mdp5_read(mdp5_kms
, REG_MDP5_HW_VERSION
);
493 mdp5_disable(mdp5_kms
);
495 *major
= FIELD(version
, MDP5_HW_VERSION_MAJOR
);
496 *minor
= FIELD(version
, MDP5_HW_VERSION_MINOR
);
498 DBG("MDP5 version v%d.%d", *major
, *minor
);
501 static int get_clk(struct platform_device
*pdev
, struct clk
**clkp
,
502 const char *name
, bool mandatory
)
504 struct device
*dev
= &pdev
->dev
;
505 struct clk
*clk
= devm_clk_get(dev
, name
);
506 if (IS_ERR(clk
) && mandatory
) {
507 dev_err(dev
, "failed to get %s (%ld)\n", name
, PTR_ERR(clk
));
511 DBG("skipping %s", name
);
518 static struct drm_encoder
*get_encoder_from_crtc(struct drm_crtc
*crtc
)
520 struct drm_device
*dev
= crtc
->dev
;
521 struct drm_encoder
*encoder
;
523 drm_for_each_encoder(encoder
, dev
)
524 if (encoder
->crtc
== crtc
)
530 static bool mdp5_get_scanoutpos(struct drm_device
*dev
, unsigned int pipe
,
531 bool in_vblank_irq
, int *vpos
, int *hpos
,
532 ktime_t
*stime
, ktime_t
*etime
,
533 const struct drm_display_mode
*mode
)
535 struct msm_drm_private
*priv
= dev
->dev_private
;
536 struct drm_crtc
*crtc
;
537 struct drm_encoder
*encoder
;
538 int line
, vsw
, vbp
, vactive_start
, vactive_end
, vfp_end
;
540 crtc
= priv
->crtcs
[pipe
];
542 DRM_ERROR("Invalid crtc %d\n", pipe
);
546 encoder
= get_encoder_from_crtc(crtc
);
548 DRM_ERROR("no encoder found for crtc %d\n", pipe
);
552 vsw
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
553 vbp
= mode
->crtc_vtotal
- mode
->crtc_vsync_end
;
556 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
557 * the end of VFP. Translate the porch values relative to the line
561 vactive_start
= vsw
+ vbp
+ 1;
563 vactive_end
= vactive_start
+ mode
->crtc_vdisplay
;
565 /* last scan line before VSYNC */
566 vfp_end
= mode
->crtc_vtotal
;
569 *stime
= ktime_get();
571 line
= mdp5_encoder_get_linecount(encoder
);
573 if (line
< vactive_start
) {
574 line
-= vactive_start
;
575 } else if (line
> vactive_end
) {
576 line
= line
- vfp_end
- vactive_start
;
578 line
-= vactive_start
;
585 *etime
= ktime_get();
590 static u32
mdp5_get_vblank_counter(struct drm_device
*dev
, unsigned int pipe
)
592 struct msm_drm_private
*priv
= dev
->dev_private
;
593 struct drm_crtc
*crtc
;
594 struct drm_encoder
*encoder
;
596 if (pipe
< 0 || pipe
>= priv
->num_crtcs
)
599 crtc
= priv
->crtcs
[pipe
];
603 encoder
= get_encoder_from_crtc(crtc
);
607 return mdp5_encoder_get_framecount(encoder
);
610 struct msm_kms
*mdp5_kms_init(struct drm_device
*dev
)
612 struct msm_drm_private
*priv
= dev
->dev_private
;
613 struct platform_device
*pdev
;
614 struct mdp5_kms
*mdp5_kms
;
615 struct mdp5_cfg
*config
;
617 struct msm_gem_address_space
*aspace
;
620 /* priv->kms would have been populated by the MDP5 driver */
625 mdp5_kms
= to_mdp5_kms(to_mdp_kms(kms
));
627 mdp_kms_init(&mdp5_kms
->base
, &kms_funcs
);
629 pdev
= mdp5_kms
->pdev
;
631 irq
= irq_of_parse_and_map(pdev
->dev
.of_node
, 0);
634 dev_err(&pdev
->dev
, "failed to get irq: %d\n", ret
);
640 config
= mdp5_cfg_get_config(mdp5_kms
->cfg
);
642 /* make sure things are off before attaching iommu (bootloader could
643 * have left things on, in which case we'll start getting faults if
646 mdp5_enable(mdp5_kms
);
647 for (i
= 0; i
< MDP5_INTF_NUM_MAX
; i
++) {
648 if (mdp5_cfg_intf_is_virtual(config
->hw
->intf
.connect
[i
]) ||
649 !config
->hw
->intf
.base
[i
])
651 mdp5_write(mdp5_kms
, REG_MDP5_INTF_TIMING_ENGINE_EN(i
), 0);
653 mdp5_write(mdp5_kms
, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i
), 0x3);
655 mdp5_disable(mdp5_kms
);
658 if (config
->platform
.iommu
) {
659 aspace
= msm_gem_address_space_create(&pdev
->dev
,
660 config
->platform
.iommu
, "mdp5");
661 if (IS_ERR(aspace
)) {
662 ret
= PTR_ERR(aspace
);
666 kms
->aspace
= aspace
;
668 ret
= aspace
->mmu
->funcs
->attach(aspace
->mmu
, iommu_ports
,
669 ARRAY_SIZE(iommu_ports
));
671 dev_err(&pdev
->dev
, "failed to attach iommu: %d\n",
677 "no iommu, fallback to phys contig buffers for scanout\n");
681 ret
= modeset_init(mdp5_kms
);
683 dev_err(&pdev
->dev
, "modeset_init failed: %d\n", ret
);
687 dev
->mode_config
.min_width
= 0;
688 dev
->mode_config
.min_height
= 0;
689 dev
->mode_config
.max_width
= 0xffff;
690 dev
->mode_config
.max_height
= 0xffff;
692 dev
->driver
->get_vblank_timestamp
= drm_calc_vbltimestamp_from_scanoutpos
;
693 dev
->driver
->get_scanout_position
= mdp5_get_scanoutpos
;
694 dev
->driver
->get_vblank_counter
= mdp5_get_vblank_counter
;
695 dev
->max_vblank_count
= 0xffffffff;
696 dev
->vblank_disable_immediate
= true;
701 mdp5_kms_destroy(kms
);
705 static void mdp5_destroy(struct platform_device
*pdev
)
707 struct mdp5_kms
*mdp5_kms
= platform_get_drvdata(pdev
);
711 mdp5_ctlm_destroy(mdp5_kms
->ctlm
);
713 mdp5_smp_destroy(mdp5_kms
->smp
);
715 mdp5_cfg_destroy(mdp5_kms
->cfg
);
717 for (i
= 0; i
< mdp5_kms
->num_intfs
; i
++)
718 kfree(mdp5_kms
->intfs
[i
]);
720 if (mdp5_kms
->rpm_enabled
)
721 pm_runtime_disable(&pdev
->dev
);
723 kfree(mdp5_kms
->state
);
726 static int construct_pipes(struct mdp5_kms
*mdp5_kms
, int cnt
,
727 const enum mdp5_pipe
*pipes
, const uint32_t *offsets
,
730 struct drm_device
*dev
= mdp5_kms
->dev
;
733 for (i
= 0; i
< cnt
; i
++) {
734 struct mdp5_hw_pipe
*hwpipe
;
736 hwpipe
= mdp5_pipe_init(pipes
[i
], offsets
[i
], caps
);
737 if (IS_ERR(hwpipe
)) {
738 ret
= PTR_ERR(hwpipe
);
739 dev_err(dev
->dev
, "failed to construct pipe for %s (%d)\n",
740 pipe2name(pipes
[i
]), ret
);
743 hwpipe
->idx
= mdp5_kms
->num_hwpipes
;
744 mdp5_kms
->hwpipes
[mdp5_kms
->num_hwpipes
++] = hwpipe
;
750 static int hwpipe_init(struct mdp5_kms
*mdp5_kms
)
752 static const enum mdp5_pipe rgb_planes
[] = {
753 SSPP_RGB0
, SSPP_RGB1
, SSPP_RGB2
, SSPP_RGB3
,
755 static const enum mdp5_pipe vig_planes
[] = {
756 SSPP_VIG0
, SSPP_VIG1
, SSPP_VIG2
, SSPP_VIG3
,
758 static const enum mdp5_pipe dma_planes
[] = {
759 SSPP_DMA0
, SSPP_DMA1
,
761 static const enum mdp5_pipe cursor_planes
[] = {
762 SSPP_CURSOR0
, SSPP_CURSOR1
,
764 const struct mdp5_cfg_hw
*hw_cfg
;
767 hw_cfg
= mdp5_cfg_get_hw_config(mdp5_kms
->cfg
);
769 /* Construct RGB pipes: */
770 ret
= construct_pipes(mdp5_kms
, hw_cfg
->pipe_rgb
.count
, rgb_planes
,
771 hw_cfg
->pipe_rgb
.base
, hw_cfg
->pipe_rgb
.caps
);
775 /* Construct video (VIG) pipes: */
776 ret
= construct_pipes(mdp5_kms
, hw_cfg
->pipe_vig
.count
, vig_planes
,
777 hw_cfg
->pipe_vig
.base
, hw_cfg
->pipe_vig
.caps
);
781 /* Construct DMA pipes: */
782 ret
= construct_pipes(mdp5_kms
, hw_cfg
->pipe_dma
.count
, dma_planes
,
783 hw_cfg
->pipe_dma
.base
, hw_cfg
->pipe_dma
.caps
);
787 /* Construct cursor pipes: */
788 ret
= construct_pipes(mdp5_kms
, hw_cfg
->pipe_cursor
.count
,
789 cursor_planes
, hw_cfg
->pipe_cursor
.base
,
790 hw_cfg
->pipe_cursor
.caps
);
797 static int hwmixer_init(struct mdp5_kms
*mdp5_kms
)
799 struct drm_device
*dev
= mdp5_kms
->dev
;
800 const struct mdp5_cfg_hw
*hw_cfg
;
803 hw_cfg
= mdp5_cfg_get_hw_config(mdp5_kms
->cfg
);
805 for (i
= 0; i
< hw_cfg
->lm
.count
; i
++) {
806 struct mdp5_hw_mixer
*mixer
;
808 mixer
= mdp5_mixer_init(&hw_cfg
->lm
.instances
[i
]);
810 ret
= PTR_ERR(mixer
);
811 dev_err(dev
->dev
, "failed to construct LM%d (%d)\n",
816 mixer
->idx
= mdp5_kms
->num_hwmixers
;
817 mdp5_kms
->hwmixers
[mdp5_kms
->num_hwmixers
++] = mixer
;
823 static int interface_init(struct mdp5_kms
*mdp5_kms
)
825 struct drm_device
*dev
= mdp5_kms
->dev
;
826 const struct mdp5_cfg_hw
*hw_cfg
;
827 const enum mdp5_intf_type
*intf_types
;
830 hw_cfg
= mdp5_cfg_get_hw_config(mdp5_kms
->cfg
);
831 intf_types
= hw_cfg
->intf
.connect
;
833 for (i
= 0; i
< ARRAY_SIZE(hw_cfg
->intf
.connect
); i
++) {
834 struct mdp5_interface
*intf
;
836 if (intf_types
[i
] == INTF_DISABLED
)
839 intf
= kzalloc(sizeof(*intf
), GFP_KERNEL
);
841 dev_err(dev
->dev
, "failed to construct INTF%d\n", i
);
846 intf
->type
= intf_types
[i
];
847 intf
->mode
= MDP5_INTF_MODE_NONE
;
848 intf
->idx
= mdp5_kms
->num_intfs
;
849 mdp5_kms
->intfs
[mdp5_kms
->num_intfs
++] = intf
;
855 static int mdp5_init(struct platform_device
*pdev
, struct drm_device
*dev
)
857 struct msm_drm_private
*priv
= dev
->dev_private
;
858 struct mdp5_kms
*mdp5_kms
;
859 struct mdp5_cfg
*config
;
863 mdp5_kms
= devm_kzalloc(&pdev
->dev
, sizeof(*mdp5_kms
), GFP_KERNEL
);
869 platform_set_drvdata(pdev
, mdp5_kms
);
871 spin_lock_init(&mdp5_kms
->resource_lock
);
874 mdp5_kms
->pdev
= pdev
;
876 drm_modeset_lock_init(&mdp5_kms
->state_lock
);
877 mdp5_kms
->state
= kzalloc(sizeof(*mdp5_kms
->state
), GFP_KERNEL
);
878 if (!mdp5_kms
->state
) {
883 mdp5_kms
->mmio
= msm_ioremap(pdev
, "mdp_phys", "MDP5");
884 if (IS_ERR(mdp5_kms
->mmio
)) {
885 ret
= PTR_ERR(mdp5_kms
->mmio
);
889 /* mandatory clocks: */
890 ret
= get_clk(pdev
, &mdp5_kms
->axi_clk
, "bus_clk", true);
893 ret
= get_clk(pdev
, &mdp5_kms
->ahb_clk
, "iface_clk", true);
896 ret
= get_clk(pdev
, &mdp5_kms
->core_clk
, "core_clk", true);
899 ret
= get_clk(pdev
, &mdp5_kms
->vsync_clk
, "vsync_clk", true);
903 /* optional clocks: */
904 get_clk(pdev
, &mdp5_kms
->lut_clk
, "lut_clk", false);
906 /* we need to set a default rate before enabling. Set a safe
907 * rate first, then figure out hw revision, and then set a
910 clk_set_rate(mdp5_kms
->core_clk
, 200000000);
912 pm_runtime_enable(&pdev
->dev
);
913 mdp5_kms
->rpm_enabled
= true;
915 read_mdp_hw_revision(mdp5_kms
, &major
, &minor
);
917 mdp5_kms
->cfg
= mdp5_cfg_init(mdp5_kms
, major
, minor
);
918 if (IS_ERR(mdp5_kms
->cfg
)) {
919 ret
= PTR_ERR(mdp5_kms
->cfg
);
920 mdp5_kms
->cfg
= NULL
;
924 config
= mdp5_cfg_get_config(mdp5_kms
->cfg
);
925 mdp5_kms
->caps
= config
->hw
->mdp
.caps
;
927 /* TODO: compute core clock rate at runtime */
928 clk_set_rate(mdp5_kms
->core_clk
, config
->hw
->max_clk
);
931 * Some chipsets have a Shared Memory Pool (SMP), while others
932 * have dedicated latency buffering per source pipe instead;
933 * this section initializes the SMP:
935 if (mdp5_kms
->caps
& MDP_CAP_SMP
) {
936 mdp5_kms
->smp
= mdp5_smp_init(mdp5_kms
, &config
->hw
->smp
);
937 if (IS_ERR(mdp5_kms
->smp
)) {
938 ret
= PTR_ERR(mdp5_kms
->smp
);
939 mdp5_kms
->smp
= NULL
;
944 mdp5_kms
->ctlm
= mdp5_ctlm_init(dev
, mdp5_kms
->mmio
, mdp5_kms
->cfg
);
945 if (IS_ERR(mdp5_kms
->ctlm
)) {
946 ret
= PTR_ERR(mdp5_kms
->ctlm
);
947 mdp5_kms
->ctlm
= NULL
;
951 ret
= hwpipe_init(mdp5_kms
);
955 ret
= hwmixer_init(mdp5_kms
);
959 ret
= interface_init(mdp5_kms
);
963 /* set uninit-ed kms */
964 priv
->kms
= &mdp5_kms
->base
.base
;
972 static int mdp5_bind(struct device
*dev
, struct device
*master
, void *data
)
974 struct drm_device
*ddev
= dev_get_drvdata(master
);
975 struct platform_device
*pdev
= to_platform_device(dev
);
979 return mdp5_init(pdev
, ddev
);
982 static void mdp5_unbind(struct device
*dev
, struct device
*master
,
985 struct platform_device
*pdev
= to_platform_device(dev
);
990 static const struct component_ops mdp5_ops
= {
992 .unbind
= mdp5_unbind
,
995 static int mdp5_dev_probe(struct platform_device
*pdev
)
998 return component_add(&pdev
->dev
, &mdp5_ops
);
1001 static int mdp5_dev_remove(struct platform_device
*pdev
)
1004 component_del(&pdev
->dev
, &mdp5_ops
);
1008 static const struct of_device_id mdp5_dt_match
[] = {
1009 { .compatible
= "qcom,mdp5", },
1010 /* to support downstream DT files */
1011 { .compatible
= "qcom,mdss_mdp", },
1014 MODULE_DEVICE_TABLE(of
, mdp5_dt_match
);
1016 static struct platform_driver mdp5_driver
= {
1017 .probe
= mdp5_dev_probe
,
1018 .remove
= mdp5_dev_remove
,
1021 .of_match_table
= mdp5_dt_match
,
1025 void __init
msm_mdp_register(void)
1028 platform_driver_register(&mdp5_driver
);
1031 void __exit
msm_mdp_unregister(void)
1034 platform_driver_unregister(&mdp5_driver
);