2 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <drm/drm_print.h>
23 struct drm_plane base
;
25 spinlock_t pipe_lock
; /* protect REG_MDP5_PIPE_* registers */
30 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
32 static int mdp5_plane_mode_set(struct drm_plane
*plane
,
33 struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
34 struct drm_rect
*src
, struct drm_rect
*dest
);
36 static int mdp5_update_cursor_plane_legacy(struct drm_plane
*plane
,
37 struct drm_crtc
*crtc
,
38 struct drm_framebuffer
*fb
,
39 int crtc_x
, int crtc_y
,
40 unsigned int crtc_w
, unsigned int crtc_h
,
41 uint32_t src_x
, uint32_t src_y
,
42 uint32_t src_w
, uint32_t src_h
,
43 struct drm_modeset_acquire_ctx
*ctx
);
45 static struct mdp5_kms
*get_kms(struct drm_plane
*plane
)
47 struct msm_drm_private
*priv
= plane
->dev
->dev_private
;
48 return to_mdp5_kms(to_mdp_kms(priv
->kms
));
51 static bool plane_enabled(struct drm_plane_state
*state
)
53 return state
->visible
;
56 static void mdp5_plane_destroy(struct drm_plane
*plane
)
58 struct mdp5_plane
*mdp5_plane
= to_mdp5_plane(plane
);
60 drm_plane_helper_disable(plane
);
61 drm_plane_cleanup(plane
);
66 static void mdp5_plane_install_rotation_property(struct drm_device
*dev
,
67 struct drm_plane
*plane
)
69 drm_plane_create_rotation_property(plane
,
77 /* helper to install properties which are common to planes and crtcs */
78 static void mdp5_plane_install_properties(struct drm_plane
*plane
,
79 struct drm_mode_object
*obj
)
81 struct drm_device
*dev
= plane
->dev
;
82 struct msm_drm_private
*dev_priv
= dev
->dev_private
;
83 struct drm_property
*prop
;
85 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
86 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
88 prop = drm_property_##fnc(dev, 0, #name, \
92 "Create property %s failed\n", \
96 dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
98 drm_object_attach_property(&plane->base, prop, init_val); \
101 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
102 INSTALL_PROPERTY(name, NAME, init_val, \
103 create_range, min, max)
105 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
106 INSTALL_PROPERTY(name, NAME, init_val, \
107 create_enum, name##_prop_enum_list, \
108 ARRAY_SIZE(name##_prop_enum_list))
110 INSTALL_RANGE_PROPERTY(zpos
, ZPOS
, 1, 255, 1);
112 mdp5_plane_install_rotation_property(dev
, plane
);
114 #undef INSTALL_RANGE_PROPERTY
115 #undef INSTALL_ENUM_PROPERTY
116 #undef INSTALL_PROPERTY
119 static int mdp5_plane_atomic_set_property(struct drm_plane
*plane
,
120 struct drm_plane_state
*state
, struct drm_property
*property
,
123 struct drm_device
*dev
= plane
->dev
;
124 struct mdp5_plane_state
*pstate
;
125 struct msm_drm_private
*dev_priv
= dev
->dev_private
;
128 pstate
= to_mdp5_plane_state(state
);
130 #define SET_PROPERTY(name, NAME, type) do { \
131 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
132 pstate->name = (type)val; \
133 DBG("Set property %s %d", #name, (type)val); \
138 SET_PROPERTY(zpos
, ZPOS
, uint8_t);
140 dev_err(dev
->dev
, "Invalid property\n");
147 static int mdp5_plane_atomic_get_property(struct drm_plane
*plane
,
148 const struct drm_plane_state
*state
,
149 struct drm_property
*property
, uint64_t *val
)
151 struct drm_device
*dev
= plane
->dev
;
152 struct mdp5_plane_state
*pstate
;
153 struct msm_drm_private
*dev_priv
= dev
->dev_private
;
156 pstate
= to_mdp5_plane_state(state
);
158 #define GET_PROPERTY(name, NAME, type) do { \
159 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
160 *val = pstate->name; \
161 DBG("Get property %s %lld", #name, *val); \
166 GET_PROPERTY(zpos
, ZPOS
, uint8_t);
168 dev_err(dev
->dev
, "Invalid property\n");
176 mdp5_plane_atomic_print_state(struct drm_printer
*p
,
177 const struct drm_plane_state
*state
)
179 struct mdp5_plane_state
*pstate
= to_mdp5_plane_state(state
);
180 struct mdp5_kms
*mdp5_kms
= get_kms(state
->plane
);
182 drm_printf(p
, "\thwpipe=%s\n", pstate
->hwpipe
?
183 pstate
->hwpipe
->name
: "(null)");
184 if (mdp5_kms
->caps
& MDP_CAP_SRC_SPLIT
)
185 drm_printf(p
, "\tright-hwpipe=%s\n",
186 pstate
->r_hwpipe
? pstate
->r_hwpipe
->name
:
188 drm_printf(p
, "\tpremultiplied=%u\n", pstate
->premultiplied
);
189 drm_printf(p
, "\tzpos=%u\n", pstate
->zpos
);
190 drm_printf(p
, "\talpha=%u\n", pstate
->alpha
);
191 drm_printf(p
, "\tstage=%s\n", stage2name(pstate
->stage
));
194 static void mdp5_plane_reset(struct drm_plane
*plane
)
196 struct mdp5_plane_state
*mdp5_state
;
198 if (plane
->state
&& plane
->state
->fb
)
199 drm_framebuffer_unreference(plane
->state
->fb
);
201 kfree(to_mdp5_plane_state(plane
->state
));
202 mdp5_state
= kzalloc(sizeof(*mdp5_state
), GFP_KERNEL
);
204 /* assign default blend parameters */
205 mdp5_state
->alpha
= 255;
206 mdp5_state
->premultiplied
= 0;
208 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
)
209 mdp5_state
->zpos
= STAGE_BASE
;
211 mdp5_state
->zpos
= STAGE0
+ drm_plane_index(plane
);
213 mdp5_state
->base
.plane
= plane
;
215 plane
->state
= &mdp5_state
->base
;
218 static struct drm_plane_state
*
219 mdp5_plane_duplicate_state(struct drm_plane
*plane
)
221 struct mdp5_plane_state
*mdp5_state
;
223 if (WARN_ON(!plane
->state
))
226 mdp5_state
= kmemdup(to_mdp5_plane_state(plane
->state
),
227 sizeof(*mdp5_state
), GFP_KERNEL
);
229 if (mdp5_state
&& mdp5_state
->base
.fb
)
230 drm_framebuffer_reference(mdp5_state
->base
.fb
);
232 return &mdp5_state
->base
;
235 static void mdp5_plane_destroy_state(struct drm_plane
*plane
,
236 struct drm_plane_state
*state
)
238 struct mdp5_plane_state
*pstate
= to_mdp5_plane_state(state
);
241 drm_framebuffer_unreference(state
->fb
);
246 static const struct drm_plane_funcs mdp5_plane_funcs
= {
247 .update_plane
= drm_atomic_helper_update_plane
,
248 .disable_plane
= drm_atomic_helper_disable_plane
,
249 .destroy
= mdp5_plane_destroy
,
250 .set_property
= drm_atomic_helper_plane_set_property
,
251 .atomic_set_property
= mdp5_plane_atomic_set_property
,
252 .atomic_get_property
= mdp5_plane_atomic_get_property
,
253 .reset
= mdp5_plane_reset
,
254 .atomic_duplicate_state
= mdp5_plane_duplicate_state
,
255 .atomic_destroy_state
= mdp5_plane_destroy_state
,
256 .atomic_print_state
= mdp5_plane_atomic_print_state
,
259 static const struct drm_plane_funcs mdp5_cursor_plane_funcs
= {
260 .update_plane
= mdp5_update_cursor_plane_legacy
,
261 .disable_plane
= drm_atomic_helper_disable_plane
,
262 .destroy
= mdp5_plane_destroy
,
263 .set_property
= drm_atomic_helper_plane_set_property
,
264 .atomic_set_property
= mdp5_plane_atomic_set_property
,
265 .atomic_get_property
= mdp5_plane_atomic_get_property
,
266 .reset
= mdp5_plane_reset
,
267 .atomic_duplicate_state
= mdp5_plane_duplicate_state
,
268 .atomic_destroy_state
= mdp5_plane_destroy_state
,
269 .atomic_print_state
= mdp5_plane_atomic_print_state
,
272 static int mdp5_plane_prepare_fb(struct drm_plane
*plane
,
273 struct drm_plane_state
*new_state
)
275 struct mdp5_kms
*mdp5_kms
= get_kms(plane
);
276 struct drm_framebuffer
*fb
= new_state
->fb
;
281 DBG("%s: prepare: FB[%u]", plane
->name
, fb
->base
.id
);
282 return msm_framebuffer_prepare(fb
, mdp5_kms
->id
);
285 static void mdp5_plane_cleanup_fb(struct drm_plane
*plane
,
286 struct drm_plane_state
*old_state
)
288 struct mdp5_kms
*mdp5_kms
= get_kms(plane
);
289 struct drm_framebuffer
*fb
= old_state
->fb
;
294 DBG("%s: cleanup: FB[%u]", plane
->name
, fb
->base
.id
);
295 msm_framebuffer_cleanup(fb
, mdp5_kms
->id
);
298 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
299 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state
*crtc_state
,
300 struct drm_plane_state
*state
)
302 struct mdp5_plane_state
*mdp5_state
= to_mdp5_plane_state(state
);
303 struct drm_plane
*plane
= state
->plane
;
304 struct drm_plane_state
*old_state
= plane
->state
;
305 struct mdp5_cfg
*config
= mdp5_cfg_get_config(get_kms(plane
)->cfg
);
306 bool new_hwpipe
= false;
307 bool need_right_hwpipe
= false;
308 uint32_t max_width
, max_height
;
309 bool out_of_bounds
= false;
311 struct drm_rect clip
;
312 int min_scale
, max_scale
;
315 DBG("%s: check (%d -> %d)", plane
->name
,
316 plane_enabled(old_state
), plane_enabled(state
));
318 max_width
= config
->hw
->lm
.max_width
<< 16;
319 max_height
= config
->hw
->lm
.max_height
<< 16;
321 /* Make sure source dimensions are within bounds. */
322 if (state
->src_h
> max_height
)
323 out_of_bounds
= true;
325 if (state
->src_w
> max_width
) {
326 /* If source split is supported, we can go up to 2x
327 * the max LM width, but we'd need to stage another
328 * hwpipe to the right LM. So, the drm_plane would
329 * consist of 2 hwpipes.
331 if (config
->hw
->mdp
.caps
& MDP_CAP_SRC_SPLIT
&&
332 (state
->src_w
<= 2 * max_width
))
333 need_right_hwpipe
= true;
335 out_of_bounds
= true;
339 struct drm_rect src
= drm_plane_state_src(state
);
340 DBG("Invalid source size "DRM_RECT_FP_FMT
,
341 DRM_RECT_FP_ARG(&src
));
347 clip
.x2
= crtc_state
->adjusted_mode
.hdisplay
;
348 clip
.y2
= crtc_state
->adjusted_mode
.vdisplay
;
349 min_scale
= FRAC_16_16(1, 8);
350 max_scale
= FRAC_16_16(8, 1);
352 ret
= drm_plane_helper_check_state(state
, &clip
, min_scale
,
353 max_scale
, true, true);
357 if (plane_enabled(state
)) {
358 unsigned int rotation
;
359 const struct mdp_format
*format
;
360 struct mdp5_kms
*mdp5_kms
= get_kms(plane
);
363 format
= to_mdp_format(msm_framebuffer_format(state
->fb
));
364 if (MDP_FORMAT_IS_YUV(format
))
365 caps
|= MDP_PIPE_CAP_SCALE
| MDP_PIPE_CAP_CSC
;
367 if (((state
->src_w
>> 16) != state
->crtc_w
) ||
368 ((state
->src_h
>> 16) != state
->crtc_h
))
369 caps
|= MDP_PIPE_CAP_SCALE
;
371 rotation
= drm_rotation_simplify(state
->rotation
,
376 if (rotation
& DRM_REFLECT_X
)
377 caps
|= MDP_PIPE_CAP_HFLIP
;
379 if (rotation
& DRM_REFLECT_Y
)
380 caps
|= MDP_PIPE_CAP_VFLIP
;
382 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
383 caps
|= MDP_PIPE_CAP_CURSOR
;
385 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
386 if (!mdp5_state
->hwpipe
|| (caps
& ~mdp5_state
->hwpipe
->caps
))
390 * (re)allocte hw pipe if we're either requesting for 2 hw pipes
391 * or we're switching from 2 hw pipes to 1 hw pipe because the
392 * new src_w can be supported by 1 hw pipe itself.
394 if ((need_right_hwpipe
&& !mdp5_state
->r_hwpipe
) ||
395 (!need_right_hwpipe
&& mdp5_state
->r_hwpipe
))
399 const struct mdp_format
*format
=
400 to_mdp_format(msm_framebuffer_format(state
->fb
));
402 blkcfg
= mdp5_smp_calculate(mdp5_kms
->smp
, format
,
403 state
->src_w
>> 16, false);
405 if (mdp5_state
->hwpipe
&& (mdp5_state
->hwpipe
->blkcfg
!= blkcfg
))
409 /* (re)assign hwpipe if needed, otherwise keep old one: */
411 /* TODO maybe we want to re-assign hwpipe sometimes
412 * in cases when we no-longer need some caps to make
413 * it available for other planes?
415 struct mdp5_hw_pipe
*old_hwpipe
= mdp5_state
->hwpipe
;
416 struct mdp5_hw_pipe
*old_right_hwpipe
=
417 mdp5_state
->r_hwpipe
;
419 mdp5_state
->hwpipe
= mdp5_pipe_assign(state
->state
,
420 plane
, caps
, blkcfg
);
421 if (IS_ERR(mdp5_state
->hwpipe
)) {
422 DBG("%s: failed to assign hwpipe!", plane
->name
);
423 return PTR_ERR(mdp5_state
->hwpipe
);
426 if (need_right_hwpipe
) {
427 mdp5_state
->r_hwpipe
=
428 mdp5_pipe_assign(state
->state
, plane
,
430 if (IS_ERR(mdp5_state
->r_hwpipe
)) {
431 DBG("%s: failed to assign right hwpipe",
433 return PTR_ERR(mdp5_state
->r_hwpipe
);
437 * set it to NULL so that the driver knows we
438 * don't have a right hwpipe when committing a
441 mdp5_state
->r_hwpipe
= NULL
;
444 mdp5_pipe_release(state
->state
, old_hwpipe
);
445 mdp5_pipe_release(state
->state
, old_right_hwpipe
);
452 static int mdp5_plane_atomic_check(struct drm_plane
*plane
,
453 struct drm_plane_state
*state
)
455 struct drm_crtc
*crtc
;
456 struct drm_crtc_state
*crtc_state
;
458 crtc
= state
->crtc
? state
->crtc
: plane
->state
->crtc
;
462 crtc_state
= drm_atomic_get_existing_crtc_state(state
->state
, crtc
);
463 if (WARN_ON(!crtc_state
))
466 return mdp5_plane_atomic_check_with_state(crtc_state
, state
);
469 static void mdp5_plane_atomic_update(struct drm_plane
*plane
,
470 struct drm_plane_state
*old_state
)
472 struct drm_plane_state
*state
= plane
->state
;
474 DBG("%s: update", plane
->name
);
476 if (plane_enabled(state
)) {
479 ret
= mdp5_plane_mode_set(plane
,
480 state
->crtc
, state
->fb
,
481 &state
->src
, &state
->dst
);
482 /* atomic_check should have ensured that this doesn't fail */
487 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs
= {
488 .prepare_fb
= mdp5_plane_prepare_fb
,
489 .cleanup_fb
= mdp5_plane_cleanup_fb
,
490 .atomic_check
= mdp5_plane_atomic_check
,
491 .atomic_update
= mdp5_plane_atomic_update
,
494 static void set_scanout_locked(struct mdp5_kms
*mdp5_kms
,
496 struct drm_framebuffer
*fb
)
498 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC_STRIDE_A(pipe
),
499 MDP5_PIPE_SRC_STRIDE_A_P0(fb
->pitches
[0]) |
500 MDP5_PIPE_SRC_STRIDE_A_P1(fb
->pitches
[1]));
502 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC_STRIDE_B(pipe
),
503 MDP5_PIPE_SRC_STRIDE_B_P2(fb
->pitches
[2]) |
504 MDP5_PIPE_SRC_STRIDE_B_P3(fb
->pitches
[3]));
506 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC0_ADDR(pipe
),
507 msm_framebuffer_iova(fb
, mdp5_kms
->id
, 0));
508 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC1_ADDR(pipe
),
509 msm_framebuffer_iova(fb
, mdp5_kms
->id
, 1));
510 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC2_ADDR(pipe
),
511 msm_framebuffer_iova(fb
, mdp5_kms
->id
, 2));
512 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC3_ADDR(pipe
),
513 msm_framebuffer_iova(fb
, mdp5_kms
->id
, 3));
516 /* Note: mdp5_plane->pipe_lock must be locked */
517 static void csc_disable(struct mdp5_kms
*mdp5_kms
, enum mdp5_pipe pipe
)
519 uint32_t value
= mdp5_read(mdp5_kms
, REG_MDP5_PIPE_OP_MODE(pipe
)) &
520 ~MDP5_PIPE_OP_MODE_CSC_1_EN
;
522 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_OP_MODE(pipe
), value
);
525 /* Note: mdp5_plane->pipe_lock must be locked */
526 static void csc_enable(struct mdp5_kms
*mdp5_kms
, enum mdp5_pipe pipe
,
529 uint32_t i
, mode
= 0; /* RGB, no CSC */
535 if ((csc
->type
== CSC_YUV2RGB
) || (CSC_YUV2YUV
== csc
->type
))
536 mode
|= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV
);
537 if ((csc
->type
== CSC_RGB2YUV
) || (CSC_YUV2YUV
== csc
->type
))
538 mode
|= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV
);
539 mode
|= MDP5_PIPE_OP_MODE_CSC_1_EN
;
540 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_OP_MODE(pipe
), mode
);
542 matrix
= csc
->matrix
;
543 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe
),
544 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix
[0]) |
545 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix
[1]));
546 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe
),
547 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix
[2]) |
548 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix
[3]));
549 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe
),
550 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix
[4]) |
551 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix
[5]));
552 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe
),
553 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix
[6]) |
554 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix
[7]));
555 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe
),
556 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix
[8]));
558 for (i
= 0; i
< ARRAY_SIZE(csc
->pre_bias
); i
++) {
559 uint32_t *pre_clamp
= csc
->pre_clamp
;
560 uint32_t *post_clamp
= csc
->post_clamp
;
562 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe
, i
),
563 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp
[2*i
+1]) |
564 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp
[2*i
]));
566 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe
, i
),
567 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp
[2*i
+1]) |
568 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp
[2*i
]));
570 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe
, i
),
571 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc
->pre_bias
[i
]));
573 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe
, i
),
574 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc
->post_bias
[i
]));
578 #define PHASE_STEP_SHIFT 21
579 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
581 static int calc_phase_step(uint32_t src
, uint32_t dst
, uint32_t *out_phase
)
585 if (src
== 0 || dst
== 0)
589 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
590 * where 2^21 represents the unity "1" in fixed-point hardware design.
591 * This leaves 5 bits for the integer part (downscale case):
592 * -> maximum downscale ratio = 0b1_1111 = 31
594 if (src
> (dst
* DOWN_SCALE_RATIO_MAX
))
597 unit
= 1 << PHASE_STEP_SHIFT
;
598 *out_phase
= mult_frac(unit
, src
, dst
);
603 static int calc_scalex_steps(struct drm_plane
*plane
,
604 uint32_t pixel_format
, uint32_t src
, uint32_t dest
,
605 uint32_t phasex_steps
[COMP_MAX
])
607 struct mdp5_kms
*mdp5_kms
= get_kms(plane
);
608 struct device
*dev
= mdp5_kms
->dev
->dev
;
609 uint32_t phasex_step
;
613 ret
= calc_phase_step(src
, dest
, &phasex_step
);
615 dev_err(dev
, "X scaling (%d->%d) failed: %d\n", src
, dest
, ret
);
619 hsub
= drm_format_horz_chroma_subsampling(pixel_format
);
621 phasex_steps
[COMP_0
] = phasex_step
;
622 phasex_steps
[COMP_3
] = phasex_step
;
623 phasex_steps
[COMP_1_2
] = phasex_step
/ hsub
;
628 static int calc_scaley_steps(struct drm_plane
*plane
,
629 uint32_t pixel_format
, uint32_t src
, uint32_t dest
,
630 uint32_t phasey_steps
[COMP_MAX
])
632 struct mdp5_kms
*mdp5_kms
= get_kms(plane
);
633 struct device
*dev
= mdp5_kms
->dev
->dev
;
634 uint32_t phasey_step
;
638 ret
= calc_phase_step(src
, dest
, &phasey_step
);
640 dev_err(dev
, "Y scaling (%d->%d) failed: %d\n", src
, dest
, ret
);
644 vsub
= drm_format_vert_chroma_subsampling(pixel_format
);
646 phasey_steps
[COMP_0
] = phasey_step
;
647 phasey_steps
[COMP_3
] = phasey_step
;
648 phasey_steps
[COMP_1_2
] = phasey_step
/ vsub
;
653 static uint32_t get_scale_config(const struct mdp_format
*format
,
654 uint32_t src
, uint32_t dst
, bool horz
)
656 bool scaling
= format
->is_yuv
? true : (src
!= dst
);
657 uint32_t sub
, pix_fmt
= format
->base
.pixel_format
;
658 uint32_t ya_filter
, uv_filter
;
659 bool yuv
= format
->is_yuv
;
665 sub
= horz
? drm_format_horz_chroma_subsampling(pix_fmt
) :
666 drm_format_vert_chroma_subsampling(pix_fmt
);
667 uv_filter
= ((src
/ sub
) <= dst
) ?
668 SCALE_FILTER_BIL
: SCALE_FILTER_PCMN
;
670 ya_filter
= (src
<= dst
) ? SCALE_FILTER_BIL
: SCALE_FILTER_PCMN
;
673 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN
|
674 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter
) |
675 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter
) |
676 COND(yuv
, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter
));
678 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN
|
679 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter
) |
680 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter
) |
681 COND(yuv
, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter
));
684 static void calc_pixel_ext(const struct mdp_format
*format
,
685 uint32_t src
, uint32_t dst
, uint32_t phase_step
[2],
686 int pix_ext_edge1
[COMP_MAX
], int pix_ext_edge2
[COMP_MAX
],
689 bool scaling
= format
->is_yuv
? true : (src
!= dst
);
694 * We assume here that:
695 * 1. PCMN filter is used for downscale
696 * 2. bilinear filter is used for upscale
697 * 3. we are in a single pipe configuration
700 for (i
= 0; i
< COMP_MAX
; i
++) {
701 pix_ext_edge1
[i
] = 0;
702 pix_ext_edge2
[i
] = scaling
? 1 : 0;
706 static void mdp5_write_pixel_ext(struct mdp5_kms
*mdp5_kms
, enum mdp5_pipe pipe
,
707 const struct mdp_format
*format
,
708 uint32_t src_w
, int pe_left
[COMP_MAX
], int pe_right
[COMP_MAX
],
709 uint32_t src_h
, int pe_top
[COMP_MAX
], int pe_bottom
[COMP_MAX
])
711 uint32_t pix_fmt
= format
->base
.pixel_format
;
712 uint32_t lr
, tb
, req
;
715 for (i
= 0; i
< COMP_MAX
; i
++) {
716 uint32_t roi_w
= src_w
;
717 uint32_t roi_h
= src_h
;
719 if (format
->is_yuv
&& i
== COMP_1_2
) {
720 roi_w
/= drm_format_horz_chroma_subsampling(pix_fmt
);
721 roi_h
/= drm_format_vert_chroma_subsampling(pix_fmt
);
724 lr
= (pe_left
[i
] >= 0) ?
725 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left
[i
]) :
726 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left
[i
]);
728 lr
|= (pe_right
[i
] >= 0) ?
729 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right
[i
]) :
730 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right
[i
]);
732 tb
= (pe_top
[i
] >= 0) ?
733 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top
[i
]) :
734 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top
[i
]);
736 tb
|= (pe_bottom
[i
] >= 0) ?
737 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom
[i
]) :
738 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom
[i
]);
740 req
= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w
+
741 pe_left
[i
] + pe_right
[i
]);
743 req
|= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h
+
744 pe_top
[i
] + pe_bottom
[i
]);
746 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe
, i
), lr
);
747 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe
, i
), tb
);
748 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe
, i
), req
);
750 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i
,
751 FIELD(lr
, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT
),
752 FIELD(lr
, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT
),
753 FIELD(lr
, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF
),
754 FIELD(lr
, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF
),
755 FIELD(req
, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT
));
757 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i
,
758 FIELD(tb
, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT
),
759 FIELD(tb
, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT
),
760 FIELD(tb
, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF
),
761 FIELD(tb
, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF
),
762 FIELD(req
, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM
));
770 int bottom
[COMP_MAX
];
778 static void mdp5_hwpipe_mode_set(struct mdp5_kms
*mdp5_kms
,
779 struct mdp5_hw_pipe
*hwpipe
,
780 struct drm_framebuffer
*fb
,
781 struct phase_step
*step
,
782 struct pixel_ext
*pe
,
783 u32 scale_config
, u32 hdecm
, u32 vdecm
,
784 bool hflip
, bool vflip
,
785 int crtc_x
, int crtc_y
,
786 unsigned int crtc_w
, unsigned int crtc_h
,
787 u32 src_img_w
, u32 src_img_h
,
788 u32 src_x
, u32 src_y
,
789 u32 src_w
, u32 src_h
)
791 enum mdp5_pipe pipe
= hwpipe
->pipe
;
792 bool has_pe
= hwpipe
->caps
& MDP_PIPE_CAP_SW_PIX_EXT
;
793 const struct mdp_format
*format
=
794 to_mdp_format(msm_framebuffer_format(fb
));
796 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe
),
797 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w
) |
798 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h
));
800 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC_SIZE(pipe
),
801 MDP5_PIPE_SRC_SIZE_WIDTH(src_w
) |
802 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h
));
804 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC_XY(pipe
),
805 MDP5_PIPE_SRC_XY_X(src_x
) |
806 MDP5_PIPE_SRC_XY_Y(src_y
));
808 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_OUT_SIZE(pipe
),
809 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w
) |
810 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h
));
812 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_OUT_XY(pipe
),
813 MDP5_PIPE_OUT_XY_X(crtc_x
) |
814 MDP5_PIPE_OUT_XY_Y(crtc_y
));
816 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC_FORMAT(pipe
),
817 MDP5_PIPE_SRC_FORMAT_A_BPC(format
->bpc_a
) |
818 MDP5_PIPE_SRC_FORMAT_R_BPC(format
->bpc_r
) |
819 MDP5_PIPE_SRC_FORMAT_G_BPC(format
->bpc_g
) |
820 MDP5_PIPE_SRC_FORMAT_B_BPC(format
->bpc_b
) |
821 COND(format
->alpha_enable
, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE
) |
822 MDP5_PIPE_SRC_FORMAT_CPP(format
->cpp
- 1) |
823 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format
->unpack_count
- 1) |
824 COND(format
->unpack_tight
, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT
) |
825 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format
->fetch_type
) |
826 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format
->chroma_sample
));
828 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC_UNPACK(pipe
),
829 MDP5_PIPE_SRC_UNPACK_ELEM0(format
->unpack
[0]) |
830 MDP5_PIPE_SRC_UNPACK_ELEM1(format
->unpack
[1]) |
831 MDP5_PIPE_SRC_UNPACK_ELEM2(format
->unpack
[2]) |
832 MDP5_PIPE_SRC_UNPACK_ELEM3(format
->unpack
[3]));
834 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC_OP_MODE(pipe
),
835 (hflip
? MDP5_PIPE_SRC_OP_MODE_FLIP_LR
: 0) |
836 (vflip
? MDP5_PIPE_SRC_OP_MODE_FLIP_UD
: 0) |
837 COND(has_pe
, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE
) |
838 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS
));
840 /* not using secure mode: */
841 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe
), 0);
843 if (hwpipe
->caps
& MDP_PIPE_CAP_SW_PIX_EXT
)
844 mdp5_write_pixel_ext(mdp5_kms
, pipe
, format
,
845 src_w
, pe
->left
, pe
->right
,
846 src_h
, pe
->top
, pe
->bottom
);
848 if (hwpipe
->caps
& MDP_PIPE_CAP_SCALE
) {
849 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe
),
851 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe
),
853 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe
),
855 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe
),
857 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_DECIMATION(pipe
),
858 MDP5_PIPE_DECIMATION_VERT(vdecm
) |
859 MDP5_PIPE_DECIMATION_HORZ(hdecm
));
860 mdp5_write(mdp5_kms
, REG_MDP5_PIPE_SCALE_CONFIG(pipe
),
864 if (hwpipe
->caps
& MDP_PIPE_CAP_CSC
) {
865 if (MDP_FORMAT_IS_YUV(format
))
866 csc_enable(mdp5_kms
, pipe
,
867 mdp_get_default_csc_cfg(CSC_YUV2RGB
));
869 csc_disable(mdp5_kms
, pipe
);
872 set_scanout_locked(mdp5_kms
, pipe
, fb
);
875 static int mdp5_plane_mode_set(struct drm_plane
*plane
,
876 struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
877 struct drm_rect
*src
, struct drm_rect
*dest
)
879 struct mdp5_plane
*mdp5_plane
= to_mdp5_plane(plane
);
880 struct drm_plane_state
*pstate
= plane
->state
;
881 struct mdp5_hw_pipe
*hwpipe
= to_mdp5_plane_state(pstate
)->hwpipe
;
882 struct mdp5_kms
*mdp5_kms
= get_kms(plane
);
883 enum mdp5_pipe pipe
= hwpipe
->pipe
;
884 struct mdp5_hw_pipe
*right_hwpipe
;
885 const struct mdp_format
*format
;
886 uint32_t nplanes
, config
= 0;
887 struct phase_step step
= { 0 };
888 struct pixel_ext pe
= { 0 };
889 uint32_t hdecm
= 0, vdecm
= 0;
891 unsigned int rotation
;
894 unsigned int crtc_w
, crtc_h
;
895 uint32_t src_x
, src_y
;
896 uint32_t src_w
, src_h
;
897 uint32_t src_img_w
, src_img_h
;
903 nplanes
= fb
->format
->num_planes
;
905 /* bad formats should already be rejected: */
906 if (WARN_ON(nplanes
> pipe2nclients(pipe
)))
909 format
= to_mdp_format(msm_framebuffer_format(fb
));
910 pix_format
= format
->base
.pixel_format
;
914 src_w
= drm_rect_width(src
);
915 src_h
= drm_rect_height(src
);
919 crtc_w
= drm_rect_width(dest
);
920 crtc_h
= drm_rect_height(dest
);
922 /* src values are in Q16 fixed point, convert to integer: */
928 src_img_w
= min(fb
->width
, src_w
);
929 src_img_h
= min(fb
->height
, src_h
);
931 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane
->name
,
932 fb
->base
.id
, src_x
, src_y
, src_w
, src_h
,
933 crtc
->base
.id
, crtc_x
, crtc_y
, crtc_w
, crtc_h
);
935 right_hwpipe
= to_mdp5_plane_state(pstate
)->r_hwpipe
;
938 * if the plane comprises of 2 hw pipes, assume that the width
939 * is split equally across them. The only parameters that varies
940 * between the 2 pipes are src_x and crtc_x
946 crtc_x_r
= crtc_x
+ crtc_w
;
947 src_x_r
= src_x
+ src_w
;
950 ret
= calc_scalex_steps(plane
, pix_format
, src_w
, crtc_w
, step
.x
);
954 ret
= calc_scaley_steps(plane
, pix_format
, src_h
, crtc_h
, step
.y
);
958 if (hwpipe
->caps
& MDP_PIPE_CAP_SW_PIX_EXT
) {
959 calc_pixel_ext(format
, src_w
, crtc_w
, step
.x
,
960 pe
.left
, pe
.right
, true);
961 calc_pixel_ext(format
, src_h
, crtc_h
, step
.y
,
962 pe
.top
, pe
.bottom
, false);
965 /* TODO calc hdecm, vdecm */
967 /* SCALE is used to both scale and up-sample chroma components */
968 config
|= get_scale_config(format
, src_w
, crtc_w
, true);
969 config
|= get_scale_config(format
, src_h
, crtc_h
, false);
970 DBG("scale config = %x", config
);
972 rotation
= drm_rotation_simplify(pstate
->rotation
,
976 hflip
= !!(rotation
& DRM_REFLECT_X
);
977 vflip
= !!(rotation
& DRM_REFLECT_Y
);
979 spin_lock_irqsave(&mdp5_plane
->pipe_lock
, flags
);
981 mdp5_hwpipe_mode_set(mdp5_kms
, hwpipe
, fb
, &step
, &pe
,
982 config
, hdecm
, vdecm
, hflip
, vflip
,
983 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
984 src_img_w
, src_img_h
,
985 src_x
, src_y
, src_w
, src_h
);
987 mdp5_hwpipe_mode_set(mdp5_kms
, right_hwpipe
, fb
, &step
, &pe
,
988 config
, hdecm
, vdecm
, hflip
, vflip
,
989 crtc_x_r
, crtc_y
, crtc_w
, crtc_h
,
990 src_img_w
, src_img_h
,
991 src_x_r
, src_y
, src_w
, src_h
);
993 spin_unlock_irqrestore(&mdp5_plane
->pipe_lock
, flags
);
1000 static int mdp5_update_cursor_plane_legacy(struct drm_plane
*plane
,
1001 struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1002 int crtc_x
, int crtc_y
,
1003 unsigned int crtc_w
, unsigned int crtc_h
,
1004 uint32_t src_x
, uint32_t src_y
,
1005 uint32_t src_w
, uint32_t src_h
,
1006 struct drm_modeset_acquire_ctx
*ctx
)
1008 struct drm_plane_state
*plane_state
, *new_plane_state
;
1009 struct mdp5_plane_state
*mdp5_pstate
;
1010 struct drm_crtc_state
*crtc_state
= crtc
->state
;
1013 if (!crtc_state
->active
|| drm_atomic_crtc_needs_modeset(crtc_state
))
1016 plane_state
= plane
->state
;
1017 mdp5_pstate
= to_mdp5_plane_state(plane_state
);
1019 /* don't use fast path if we don't have a hwpipe allocated yet */
1020 if (!mdp5_pstate
->hwpipe
)
1023 /* only allow changing of position(crtc x/y or src x/y) in fast path */
1024 if (plane_state
->crtc
!= crtc
||
1025 plane_state
->src_w
!= src_w
||
1026 plane_state
->src_h
!= src_h
||
1027 plane_state
->crtc_w
!= crtc_w
||
1028 plane_state
->crtc_h
!= crtc_h
||
1030 plane_state
->fb
!= fb
)
1033 new_plane_state
= mdp5_plane_duplicate_state(plane
);
1034 if (!new_plane_state
)
1037 new_plane_state
->src_x
= src_x
;
1038 new_plane_state
->src_y
= src_y
;
1039 new_plane_state
->src_w
= src_w
;
1040 new_plane_state
->src_h
= src_h
;
1041 new_plane_state
->crtc_x
= crtc_x
;
1042 new_plane_state
->crtc_y
= crtc_y
;
1043 new_plane_state
->crtc_w
= crtc_w
;
1044 new_plane_state
->crtc_h
= crtc_h
;
1046 ret
= mdp5_plane_atomic_check_with_state(crtc_state
, new_plane_state
);
1050 if (new_plane_state
->visible
) {
1051 struct mdp5_ctl
*ctl
;
1052 struct mdp5_pipeline
*pipeline
= mdp5_crtc_get_pipeline(crtc
);
1054 ret
= mdp5_plane_mode_set(plane
, crtc
, fb
,
1055 &new_plane_state
->src
,
1056 &new_plane_state
->dst
);
1059 ctl
= mdp5_crtc_get_ctl(crtc
);
1061 mdp5_ctl_commit(ctl
, pipeline
, mdp5_plane_get_flush(plane
));
1064 *to_mdp5_plane_state(plane_state
) =
1065 *to_mdp5_plane_state(new_plane_state
);
1067 mdp5_plane_destroy_state(plane
, new_plane_state
);
1071 mdp5_plane_destroy_state(plane
, new_plane_state
);
1073 return drm_atomic_helper_update_plane(plane
, crtc
, fb
,
1074 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
1075 src_x
, src_y
, src_w
, src_h
, ctx
);
1079 * Use this func and the one below only after the atomic state has been
1080 * successfully swapped
1082 enum mdp5_pipe
mdp5_plane_pipe(struct drm_plane
*plane
)
1084 struct mdp5_plane_state
*pstate
= to_mdp5_plane_state(plane
->state
);
1086 if (WARN_ON(!pstate
->hwpipe
))
1089 return pstate
->hwpipe
->pipe
;
1092 enum mdp5_pipe
mdp5_plane_right_pipe(struct drm_plane
*plane
)
1094 struct mdp5_plane_state
*pstate
= to_mdp5_plane_state(plane
->state
);
1096 if (!pstate
->r_hwpipe
)
1099 return pstate
->r_hwpipe
->pipe
;
1102 uint32_t mdp5_plane_get_flush(struct drm_plane
*plane
)
1104 struct mdp5_plane_state
*pstate
= to_mdp5_plane_state(plane
->state
);
1107 if (WARN_ON(!pstate
->hwpipe
))
1110 mask
= pstate
->hwpipe
->flush_mask
;
1112 if (pstate
->r_hwpipe
)
1113 mask
|= pstate
->r_hwpipe
->flush_mask
;
1118 /* initialize plane */
1119 struct drm_plane
*mdp5_plane_init(struct drm_device
*dev
,
1120 enum drm_plane_type type
)
1122 struct drm_plane
*plane
= NULL
;
1123 struct mdp5_plane
*mdp5_plane
;
1126 mdp5_plane
= kzalloc(sizeof(*mdp5_plane
), GFP_KERNEL
);
1132 plane
= &mdp5_plane
->base
;
1134 mdp5_plane
->nformats
= mdp_get_formats(mdp5_plane
->formats
,
1135 ARRAY_SIZE(mdp5_plane
->formats
), false);
1137 spin_lock_init(&mdp5_plane
->pipe_lock
);
1139 if (type
== DRM_PLANE_TYPE_CURSOR
)
1140 ret
= drm_universal_plane_init(dev
, plane
, 0xff,
1141 &mdp5_cursor_plane_funcs
,
1142 mdp5_plane
->formats
, mdp5_plane
->nformats
,
1145 ret
= drm_universal_plane_init(dev
, plane
, 0xff,
1147 mdp5_plane
->formats
, mdp5_plane
->nformats
,
1152 drm_plane_helper_add(plane
, &mdp5_plane_helper_funcs
);
1154 mdp5_plane_install_properties(plane
, &plane
->base
);
1160 mdp5_plane_destroy(plane
);
1162 return ERR_PTR(ret
);