drivers/gpu/drm/msm/mdp4/mdp4_kms.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18
  19 #include "msm_drv.h"
  20 #include "msm_mmu.h"
  21 #include "mdp4_kms.h"
  22
  23 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
  24
  25 static int mdp4_hw_init(struct msm_kms *kms)
  26 {
  27         struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
  28         struct drm_device *dev = mdp4_kms->dev;
  29         uint32_t version, major, minor, dmap_cfg, vg_cfg;
  30         unsigned long clk;
  31         int ret = 0;
  32
  33         pm_runtime_get_sync(dev->dev);
  34
  35         version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
  36
  37         major = FIELD(version, MDP4_VERSION_MAJOR);
  38         minor = FIELD(version, MDP4_VERSION_MINOR);
  39
  40         DBG("found MDP version v%d.%d", major, minor);
  41
  42         if (major != 4) {
  43                 dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
  44                                 major, minor);
  45                 ret = -ENXIO;
  46                 goto out;
  47         }
  48
  49         mdp4_kms->rev = minor;
  50
  51         if (mdp4_kms->dsi_pll_vdda) {
  52                 if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) {
  53                         ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda,
  54                                         1200000, 1200000);
  55                         if (ret) {
  56                                 dev_err(dev->dev,
  57                                         "failed to set dsi_pll_vdda voltage: %d\n", ret);
  58                                 goto out;
  59                         }
  60                 }
  61         }
  62
  63         if (mdp4_kms->dsi_pll_vddio) {
  64                 if (mdp4_kms->rev == 2) {
  65                         ret = regulator_set_voltage(mdp4_kms->dsi_pll_vddio,
  66                                         1800000, 1800000);
  67                         if (ret) {
  68                                 dev_err(dev->dev,
  69                                         "failed to set dsi_pll_vddio voltage: %d\n", ret);
  70                                 goto out;
  71                         }
  72                 }
  73         }
  74
  75         if (mdp4_kms->rev > 1) {
  76                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
  77                 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
  78         }
  79
  80         mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
  81
  82         /* max read pending cmd config, 3 pending requests: */
  83         mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
  84
  85         clk = clk_get_rate(mdp4_kms->clk);
  86
  87         if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
  88                 dmap_cfg = 0x47;     /* 16 bytes-burst x 8 req */
  89                 vg_cfg = 0x47;       /* 16 bytes-burs x 8 req */
  90         } else {
  91                 dmap_cfg = 0x27;     /* 8 bytes-burst x 8 req */
  92                 vg_cfg = 0x43;       /* 16 bytes-burst x 4 req */
  93         }
  94
  95         DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
  96
  97         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
  98         mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
  99
 100         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
 101         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
 102         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
 103         mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
 104
 105         if (mdp4_kms->rev >= 2)
 106                 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
 107
 108         /* disable CSC matrix / YUV by default: */
 109         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
 110         mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
 111         mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
 112         mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
 113         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
 114         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
 115
 116         if (mdp4_kms->rev > 1)
 117                 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
 118
 119 out:
 120         pm_runtime_put_sync(dev->dev);
 121
 122         return ret;
 123 }
 124
 125 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
 126                 struct drm_encoder *encoder)
 127 {
 128         /* if we had >1 encoder, we'd need something more clever: */
 129         return mdp4_dtv_round_pixclk(encoder, rate);
 130 }
 131
 132 static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file)
 133 {
 134         struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
 135         struct msm_drm_private *priv = mdp4_kms->dev->dev_private;
 136         unsigned i;
 137
 138         for (i = 0; i < priv->num_crtcs; i++)
 139                 mdp4_crtc_cancel_pending_flip(priv->crtcs[i], file);
 140 }
 141
 142 static void mdp4_destroy(struct msm_kms *kms)
 143 {
 144         struct mdp4_kms *mdp4_kms = to_mdp4_kms(kms);
 145         kfree(mdp4_kms);
 146 }
 147
 148 static const struct msm_kms_funcs kms_funcs = {
 149                 .hw_init         = mdp4_hw_init,
 150                 .irq_preinstall  = mdp4_irq_preinstall,
 151                 .irq_postinstall = mdp4_irq_postinstall,
 152                 .irq_uninstall   = mdp4_irq_uninstall,
 153                 .irq             = mdp4_irq,
 154                 .enable_vblank   = mdp4_enable_vblank,
 155                 .disable_vblank  = mdp4_disable_vblank,
 156                 .get_format      = mdp4_get_format,
 157                 .round_pixclk    = mdp4_round_pixclk,
 158                 .preclose        = mdp4_preclose,
 159                 .destroy         = mdp4_destroy,
 160 };
 161
 162 int mdp4_disable(struct mdp4_kms *mdp4_kms)
 163 {
 164         DBG("");
 165
 166         clk_disable_unprepare(mdp4_kms->clk);
 167         if (mdp4_kms->pclk)
 168                 clk_disable_unprepare(mdp4_kms->pclk);
 169         clk_disable_unprepare(mdp4_kms->lut_clk);
 170
 171         return 0;
 172 }
 173
 174 int mdp4_enable(struct mdp4_kms *mdp4_kms)
 175 {
 176         DBG("");
 177
 178         clk_prepare_enable(mdp4_kms->clk);
 179         if (mdp4_kms->pclk)
 180                 clk_prepare_enable(mdp4_kms->pclk);
 181         clk_prepare_enable(mdp4_kms->lut_clk);
 182
 183         return 0;
 184 }
 185
 186 static int modeset_init(struct mdp4_kms *mdp4_kms)
 187 {
 188         struct drm_device *dev = mdp4_kms->dev;
 189         struct msm_drm_private *priv = dev->dev_private;
 190         struct drm_plane *plane;
 191         struct drm_crtc *crtc;
 192         struct drm_encoder *encoder;
 193         int ret;
 194
 195         /*
 196          *  NOTE: this is a bit simplistic until we add support
 197          * for more than just RGB1->DMA_E->DTV->HDMI
 198          */
 199
 200         /* construct non-private planes: */
 201         plane = mdp4_plane_init(dev, VG1, false);
 202         if (IS_ERR(plane)) {
 203                 dev_err(dev->dev, "failed to construct plane for VG1\n");
 204                 ret = PTR_ERR(plane);
 205                 goto fail;
 206         }
 207         priv->planes[priv->num_planes++] = plane;
 208
 209         plane = mdp4_plane_init(dev, VG2, false);
 210         if (IS_ERR(plane)) {
 211                 dev_err(dev->dev, "failed to construct plane for VG2\n");
 212                 ret = PTR_ERR(plane);
 213                 goto fail;
 214         }
 215         priv->planes[priv->num_planes++] = plane;
 216
 217         /* the CRTCs get constructed with a private plane: */
 218         plane = mdp4_plane_init(dev, RGB1, true);
 219         if (IS_ERR(plane)) {
 220                 dev_err(dev->dev, "failed to construct plane for RGB1\n");
 221                 ret = PTR_ERR(plane);
 222                 goto fail;
 223         }
 224
 225         crtc  = mdp4_crtc_init(dev, plane, priv->num_crtcs, 1, DMA_E);
 226         if (IS_ERR(crtc)) {
 227                 dev_err(dev->dev, "failed to construct crtc for DMA_E\n");
 228                 ret = PTR_ERR(crtc);
 229                 goto fail;
 230         }
 231         priv->crtcs[priv->num_crtcs++] = crtc;
 232
 233         encoder = mdp4_dtv_encoder_init(dev);
 234         if (IS_ERR(encoder)) {
 235                 dev_err(dev->dev, "failed to construct DTV encoder\n");
 236                 ret = PTR_ERR(encoder);
 237                 goto fail;
 238         }
 239         encoder->possible_crtcs = 0x1;     /* DTV can be hooked to DMA_E */
 240         priv->encoders[priv->num_encoders++] = encoder;
 241
 242         ret = hdmi_init(dev, encoder);
 243         if (ret) {
 244                 dev_err(dev->dev, "failed to initialize HDMI\n");
 245                 goto fail;
 246         }
 247
 248         return 0;
 249
 250 fail:
 251         return ret;
 252 }
 253
 254 static const char *iommu_ports[] = {
 255                 "mdp_port0_cb0", "mdp_port1_cb0",
 256 };
 257
 258 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
 259 {
 260         struct platform_device *pdev = dev->platformdev;
 261         struct mdp4_platform_config *config = mdp4_get_config(pdev);
 262         struct mdp4_kms *mdp4_kms;
 263         struct msm_kms *kms = NULL;
 264         struct msm_mmu *mmu;
 265         int ret;
 266
 267         mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
 268         if (!mdp4_kms) {
 269                 dev_err(dev->dev, "failed to allocate kms\n");
 270                 ret = -ENOMEM;
 271                 goto fail;
 272         }
 273
 274         kms = &mdp4_kms->base;
 275         kms->funcs = &kms_funcs;
 276
 277         mdp4_kms->dev = dev;
 278
 279         mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
 280         if (IS_ERR(mdp4_kms->mmio)) {
 281                 ret = PTR_ERR(mdp4_kms->mmio);
 282                 goto fail;
 283         }
 284
 285         mdp4_kms->dsi_pll_vdda = devm_regulator_get(&pdev->dev, "dsi_pll_vdda");
 286         if (IS_ERR(mdp4_kms->dsi_pll_vdda))
 287                 mdp4_kms->dsi_pll_vdda = NULL;
 288
 289         mdp4_kms->dsi_pll_vddio = devm_regulator_get(&pdev->dev, "dsi_pll_vddio");
 290         if (IS_ERR(mdp4_kms->dsi_pll_vddio))
 291                 mdp4_kms->dsi_pll_vddio = NULL;
 292
 293         mdp4_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
 294         if (IS_ERR(mdp4_kms->vdd))
 295                 mdp4_kms->vdd = NULL;
 296
 297         if (mdp4_kms->vdd) {
 298                 ret = regulator_enable(mdp4_kms->vdd);
 299                 if (ret) {
 300                         dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
 301                         goto fail;
 302                 }
 303         }
 304
 305         mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
 306         if (IS_ERR(mdp4_kms->clk)) {
 307                 dev_err(dev->dev, "failed to get core_clk\n");
 308                 ret = PTR_ERR(mdp4_kms->clk);
 309                 goto fail;
 310         }
 311
 312         mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
 313         if (IS_ERR(mdp4_kms->pclk))
 314                 mdp4_kms->pclk = NULL;
 315
 316         // XXX if (rev >= MDP_REV_42) { ???
 317         mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
 318         if (IS_ERR(mdp4_kms->lut_clk)) {
 319                 dev_err(dev->dev, "failed to get lut_clk\n");
 320                 ret = PTR_ERR(mdp4_kms->lut_clk);
 321                 goto fail;
 322         }
 323
 324         clk_set_rate(mdp4_kms->clk, config->max_clk);
 325         clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
 326
 327         /* make sure things are off before attaching iommu (bootloader could
 328          * have left things on, in which case we'll start getting faults if
 329          * we don't disable):
 330          */
 331         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
 332         mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
 333         mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
 334         mdelay(16);
 335
 336         if (config->iommu) {
 337                 mmu = msm_iommu_new(dev, config->iommu);
 338                 if (IS_ERR(mmu)) {
 339                         ret = PTR_ERR(mmu);
 340                         goto fail;
 341                 }
 342                 ret = mmu->funcs->attach(mmu, iommu_ports,
 343                                 ARRAY_SIZE(iommu_ports));
 344                 if (ret)
 345                         goto fail;
 346         } else {
 347                 dev_info(dev->dev, "no iommu, fallback to phys "
 348                                 "contig buffers for scanout\n");
 349                 mmu = NULL;
 350         }
 351
 352         mdp4_kms->id = msm_register_mmu(dev, mmu);
 353         if (mdp4_kms->id < 0) {
 354                 ret = mdp4_kms->id;
 355                 dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
 356                 goto fail;
 357         }
 358
 359         ret = modeset_init(mdp4_kms);
 360         if (ret) {
 361                 dev_err(dev->dev, "modeset_init failed: %d\n", ret);
 362                 goto fail;
 363         }
 364
 365         return kms;
 366
 367 fail:
 368         if (kms)
 369                 mdp4_destroy(kms);
 370         return ERR_PTR(ret);
 371 }
 372
 373 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
 374 {
 375         static struct mdp4_platform_config config = {};
 376 #ifdef CONFIG_OF
 377         /* TODO */
 378 #else
 379         if (cpu_is_apq8064())
 380                 config.max_clk = 266667000;
 381         else
 382                 config.max_clk = 200000000;
 383
 384         config.iommu = msm_get_iommu_domain(DISPLAY_READ_DOMAIN);
 385 #endif
 386         return &config;
 387 }