1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/kthread.h>
10 #include <linux/sched/mm.h>
11 #include <linux/uaccess.h>
12 #include <uapi/linux/sched/types.h>
14 #include <drm/drm_drv.h>
15 #include <drm/drm_file.h>
16 #include <drm/drm_ioctl.h>
17 #include <drm/drm_prime.h>
18 #include <drm/drm_of.h>
19 #include <drm/drm_vblank.h>
21 #include "disp/msm_disp_snapshot.h"
23 #include "msm_debugfs.h"
24 #include "msm_fence.h"
28 #include "adreno/adreno_gpu.h"
32 * - 1.0.0 - initial interface
33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
34 * - 1.2.0 - adds explicit fence support for submit ioctl
35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
38 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
39 * GEM object's debug name
40 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
41 * - 1.6.0 - Syncobj support
42 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
43 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
45 #define MSM_VERSION_MAJOR 1
46 #define MSM_VERSION_MINOR 8
47 #define MSM_VERSION_PATCHLEVEL 0
49 static const struct drm_mode_config_funcs mode_config_funcs
= {
50 .fb_create
= msm_framebuffer_create
,
51 .output_poll_changed
= drm_fb_helper_output_poll_changed
,
52 .atomic_check
= drm_atomic_helper_check
,
53 .atomic_commit
= drm_atomic_helper_commit
,
56 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs
= {
57 .atomic_commit_tail
= msm_atomic_commit_tail
,
60 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
61 static bool reglog
= false;
62 MODULE_PARM_DESC(reglog
, "Enable register read/write logging");
63 module_param(reglog
, bool, 0600);
68 #ifdef CONFIG_DRM_FBDEV_EMULATION
69 static bool fbdev
= true;
70 MODULE_PARM_DESC(fbdev
, "Enable fbdev compat layer");
71 module_param(fbdev
, bool, 0600);
74 static char *vram
= "16m";
75 MODULE_PARM_DESC(vram
, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
76 module_param(vram
, charp
, 0);
78 bool dumpstate
= false;
79 MODULE_PARM_DESC(dumpstate
, "Dump KMS state on errors");
80 module_param(dumpstate
, bool, 0600);
82 static bool modeset
= true;
83 MODULE_PARM_DESC(modeset
, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
84 module_param(modeset
, bool, 0600);
90 struct clk
*msm_clk_bulk_get_clock(struct clk_bulk_data
*bulk
, int count
,
96 snprintf(n
, sizeof(n
), "%s_clk", name
);
98 for (i
= 0; bulk
&& i
< count
; i
++) {
99 if (!strcmp(bulk
[i
].id
, name
) || !strcmp(bulk
[i
].id
, n
))
107 struct clk
*msm_clk_get(struct platform_device
*pdev
, const char *name
)
112 clk
= devm_clk_get(&pdev
->dev
, name
);
113 if (!IS_ERR(clk
) || PTR_ERR(clk
) == -EPROBE_DEFER
)
116 snprintf(name2
, sizeof(name2
), "%s_clk", name
);
118 clk
= devm_clk_get(&pdev
->dev
, name2
);
120 dev_warn(&pdev
->dev
, "Using legacy clk name binding. Use "
121 "\"%s\" instead of \"%s\"\n", name
, name2
);
126 static void __iomem
*_msm_ioremap(struct platform_device
*pdev
, const char *name
,
127 const char *dbgname
, bool quiet
, phys_addr_t
*psize
)
129 struct resource
*res
;
134 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, name
);
136 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
140 DRM_DEV_ERROR(&pdev
->dev
, "failed to get memory resource: %s\n", name
);
141 return ERR_PTR(-EINVAL
);
144 size
= resource_size(res
);
146 ptr
= devm_ioremap(&pdev
->dev
, res
->start
, size
);
149 DRM_DEV_ERROR(&pdev
->dev
, "failed to ioremap: %s\n", name
);
150 return ERR_PTR(-ENOMEM
);
154 printk(KERN_DEBUG
"IO:region %s %p %08lx\n", dbgname
, ptr
, size
);
162 void __iomem
*msm_ioremap(struct platform_device
*pdev
, const char *name
,
165 return _msm_ioremap(pdev
, name
, dbgname
, false, NULL
);
168 void __iomem
*msm_ioremap_quiet(struct platform_device
*pdev
, const char *name
,
171 return _msm_ioremap(pdev
, name
, dbgname
, true, NULL
);
174 void __iomem
*msm_ioremap_size(struct platform_device
*pdev
, const char *name
,
175 const char *dbgname
, phys_addr_t
*psize
)
177 return _msm_ioremap(pdev
, name
, dbgname
, false, psize
);
180 void msm_writel(u32 data
, void __iomem
*addr
)
183 printk(KERN_DEBUG
"IO:W %p %08x\n", addr
, data
);
187 u32
msm_readl(const void __iomem
*addr
)
189 u32 val
= readl(addr
);
191 pr_err("IO:R %p %08x\n", addr
, val
);
195 void msm_rmw(void __iomem
*addr
, u32 mask
, u32
or)
197 u32 val
= msm_readl(addr
);
200 msm_writel(val
| or, addr
);
203 static irqreturn_t
msm_irq(int irq
, void *arg
)
205 struct drm_device
*dev
= arg
;
206 struct msm_drm_private
*priv
= dev
->dev_private
;
207 struct msm_kms
*kms
= priv
->kms
;
211 return kms
->funcs
->irq(kms
);
214 static void msm_irq_preinstall(struct drm_device
*dev
)
216 struct msm_drm_private
*priv
= dev
->dev_private
;
217 struct msm_kms
*kms
= priv
->kms
;
221 kms
->funcs
->irq_preinstall(kms
);
224 static int msm_irq_postinstall(struct drm_device
*dev
)
226 struct msm_drm_private
*priv
= dev
->dev_private
;
227 struct msm_kms
*kms
= priv
->kms
;
231 if (kms
->funcs
->irq_postinstall
)
232 return kms
->funcs
->irq_postinstall(kms
);
237 static int msm_irq_install(struct drm_device
*dev
, unsigned int irq
)
241 if (irq
== IRQ_NOTCONNECTED
)
244 msm_irq_preinstall(dev
);
246 ret
= request_irq(irq
, msm_irq
, 0, dev
->driver
->name
, dev
);
250 ret
= msm_irq_postinstall(dev
);
259 static void msm_irq_uninstall(struct drm_device
*dev
)
261 struct msm_drm_private
*priv
= dev
->dev_private
;
262 struct msm_kms
*kms
= priv
->kms
;
264 kms
->funcs
->irq_uninstall(kms
);
265 free_irq(kms
->irq
, dev
);
268 struct msm_vblank_work
{
269 struct work_struct work
;
272 struct msm_drm_private
*priv
;
275 static void vblank_ctrl_worker(struct work_struct
*work
)
277 struct msm_vblank_work
*vbl_work
= container_of(work
,
278 struct msm_vblank_work
, work
);
279 struct msm_drm_private
*priv
= vbl_work
->priv
;
280 struct msm_kms
*kms
= priv
->kms
;
282 if (vbl_work
->enable
)
283 kms
->funcs
->enable_vblank(kms
, priv
->crtcs
[vbl_work
->crtc_id
]);
285 kms
->funcs
->disable_vblank(kms
, priv
->crtcs
[vbl_work
->crtc_id
]);
290 static int vblank_ctrl_queue_work(struct msm_drm_private
*priv
,
291 int crtc_id
, bool enable
)
293 struct msm_vblank_work
*vbl_work
;
295 vbl_work
= kzalloc(sizeof(*vbl_work
), GFP_ATOMIC
);
299 INIT_WORK(&vbl_work
->work
, vblank_ctrl_worker
);
301 vbl_work
->crtc_id
= crtc_id
;
302 vbl_work
->enable
= enable
;
303 vbl_work
->priv
= priv
;
305 queue_work(priv
->wq
, &vbl_work
->work
);
310 static int msm_drm_uninit(struct device
*dev
)
312 struct platform_device
*pdev
= to_platform_device(dev
);
313 struct drm_device
*ddev
= platform_get_drvdata(pdev
);
314 struct msm_drm_private
*priv
= ddev
->dev_private
;
315 struct msm_kms
*kms
= priv
->kms
;
316 struct msm_mdss
*mdss
= priv
->mdss
;
320 * Shutdown the hw if we're far enough along where things might be on.
321 * If we run this too early, we'll end up panicking in any variety of
322 * places. Since we don't register the drm device until late in
323 * msm_drm_init, drm_dev->registered is used as an indicator that the
324 * shutdown will be successful.
326 if (ddev
->registered
) {
327 drm_dev_unregister(ddev
);
328 drm_atomic_helper_shutdown(ddev
);
331 /* We must cancel and cleanup any pending vblank enable/disable
332 * work before msm_irq_uninstall() to avoid work re-enabling an
333 * irq after uninstall has disabled it.
336 flush_workqueue(priv
->wq
);
338 /* clean up event worker threads */
339 for (i
= 0; i
< priv
->num_crtcs
; i
++) {
340 if (priv
->event_thread
[i
].worker
)
341 kthread_destroy_worker(priv
->event_thread
[i
].worker
);
344 msm_gem_shrinker_cleanup(ddev
);
346 drm_kms_helper_poll_fini(ddev
);
348 msm_perf_debugfs_cleanup(priv
);
349 msm_rd_debugfs_cleanup(priv
);
351 #ifdef CONFIG_DRM_FBDEV_EMULATION
352 if (fbdev
&& priv
->fbdev
)
353 msm_fbdev_free(ddev
);
356 msm_disp_snapshot_destroy(ddev
);
358 drm_mode_config_cleanup(ddev
);
360 pm_runtime_get_sync(dev
);
361 msm_irq_uninstall(ddev
);
362 pm_runtime_put_sync(dev
);
364 if (kms
&& kms
->funcs
)
365 kms
->funcs
->destroy(kms
);
367 if (priv
->vram
.paddr
) {
368 unsigned long attrs
= DMA_ATTR_NO_KERNEL_MAPPING
;
369 drm_mm_takedown(&priv
->vram
.mm
);
370 dma_free_attrs(dev
, priv
->vram
.size
, NULL
,
371 priv
->vram
.paddr
, attrs
);
374 component_unbind_all(dev
, ddev
);
376 if (mdss
&& mdss
->funcs
)
377 mdss
->funcs
->destroy(ddev
);
379 ddev
->dev_private
= NULL
;
382 destroy_workqueue(priv
->wq
);
392 static int get_mdp_ver(struct platform_device
*pdev
)
394 struct device
*dev
= &pdev
->dev
;
396 return (int) (unsigned long) of_device_get_match_data(dev
);
399 #include <linux/of_address.h>
401 bool msm_use_mmu(struct drm_device
*dev
)
403 struct msm_drm_private
*priv
= dev
->dev_private
;
405 /* a2xx comes with its own MMU */
406 return priv
->is_a2xx
|| iommu_present(&platform_bus_type
);
409 static int msm_init_vram(struct drm_device
*dev
)
411 struct msm_drm_private
*priv
= dev
->dev_private
;
412 struct device_node
*node
;
413 unsigned long size
= 0;
416 /* In the device-tree world, we could have a 'memory-region'
417 * phandle, which gives us a link to our "vram". Allocating
418 * is all nicely abstracted behind the dma api, but we need
419 * to know the entire size to allocate it all in one go. There
421 * 1) device with no IOMMU, in which case we need exclusive
422 * access to a VRAM carveout big enough for all gpu
424 * 2) device with IOMMU, but where the bootloader puts up
425 * a splash screen. In this case, the VRAM carveout
426 * need only be large enough for fbdev fb. But we need
427 * exclusive access to the buffer to avoid the kernel
428 * using those pages for other purposes (which appears
429 * as corruption on screen before we have a chance to
430 * load and do initial modeset)
433 node
= of_parse_phandle(dev
->dev
->of_node
, "memory-region", 0);
436 ret
= of_address_to_resource(node
, 0, &r
);
440 size
= r
.end
- r
.start
;
441 DRM_INFO("using VRAM carveout: %lx@%pa\n", size
, &r
.start
);
443 /* if we have no IOMMU, then we need to use carveout allocator.
444 * Grab the entire CMA chunk carved out in early startup in
447 } else if (!msm_use_mmu(dev
)) {
448 DRM_INFO("using %s VRAM carveout\n", vram
);
449 size
= memparse(vram
, NULL
);
453 unsigned long attrs
= 0;
456 priv
->vram
.size
= size
;
458 drm_mm_init(&priv
->vram
.mm
, 0, (size
>> PAGE_SHIFT
) - 1);
459 spin_lock_init(&priv
->vram
.lock
);
461 attrs
|= DMA_ATTR_NO_KERNEL_MAPPING
;
462 attrs
|= DMA_ATTR_WRITE_COMBINE
;
464 /* note that for no-kernel-mapping, the vaddr returned
465 * is bogus, but non-null if allocation succeeded:
467 p
= dma_alloc_attrs(dev
->dev
, size
,
468 &priv
->vram
.paddr
, GFP_KERNEL
, attrs
);
470 DRM_DEV_ERROR(dev
->dev
, "failed to allocate VRAM\n");
471 priv
->vram
.paddr
= 0;
475 DRM_DEV_INFO(dev
->dev
, "VRAM: %08x->%08x\n",
476 (uint32_t)priv
->vram
.paddr
,
477 (uint32_t)(priv
->vram
.paddr
+ size
));
483 static int msm_drm_init(struct device
*dev
, const struct drm_driver
*drv
)
485 struct platform_device
*pdev
= to_platform_device(dev
);
486 struct drm_device
*ddev
;
487 struct msm_drm_private
*priv
;
489 struct msm_mdss
*mdss
;
492 ddev
= drm_dev_alloc(drv
, dev
);
494 DRM_DEV_ERROR(dev
, "failed to allocate drm_device\n");
495 return PTR_ERR(ddev
);
498 platform_set_drvdata(pdev
, ddev
);
500 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
503 goto err_put_drm_dev
;
506 ddev
->dev_private
= priv
;
509 switch (get_mdp_ver(pdev
)) {
511 ret
= mdp5_mdss_init(ddev
);
514 ret
= dpu_mdss_init(ddev
);
525 priv
->wq
= alloc_ordered_workqueue("msm", 0);
526 priv
->hangcheck_period
= DRM_MSM_HANGCHECK_DEFAULT_PERIOD
;
528 INIT_LIST_HEAD(&priv
->objects
);
529 mutex_init(&priv
->obj_lock
);
531 INIT_LIST_HEAD(&priv
->inactive_willneed
);
532 INIT_LIST_HEAD(&priv
->inactive_dontneed
);
533 INIT_LIST_HEAD(&priv
->inactive_unpinned
);
534 mutex_init(&priv
->mm_lock
);
536 /* Teach lockdep about lock ordering wrt. shrinker: */
537 fs_reclaim_acquire(GFP_KERNEL
);
538 might_lock(&priv
->mm_lock
);
539 fs_reclaim_release(GFP_KERNEL
);
541 drm_mode_config_init(ddev
);
543 ret
= msm_init_vram(ddev
);
545 goto err_destroy_mdss
;
547 /* Bind all our sub-components: */
548 ret
= component_bind_all(dev
, ddev
);
550 goto err_destroy_mdss
;
552 dma_set_max_seg_size(dev
, UINT_MAX
);
554 msm_gem_shrinker_init(ddev
);
556 switch (get_mdp_ver(pdev
)) {
558 kms
= mdp4_kms_init(ddev
);
562 kms
= mdp5_kms_init(ddev
);
565 kms
= dpu_kms_init(ddev
);
569 /* valid only for the dummy headless case, where of_node=NULL */
570 WARN_ON(dev
->of_node
);
576 DRM_DEV_ERROR(dev
, "failed to load kms\n");
582 /* Enable normalization of plane zpos */
583 ddev
->mode_config
.normalize_zpos
= true;
587 ret
= kms
->funcs
->hw_init(kms
);
589 DRM_DEV_ERROR(dev
, "kms hw init failed: %d\n", ret
);
594 ddev
->mode_config
.funcs
= &mode_config_funcs
;
595 ddev
->mode_config
.helper_private
= &mode_config_helper_funcs
;
597 for (i
= 0; i
< priv
->num_crtcs
; i
++) {
598 /* initialize event thread */
599 priv
->event_thread
[i
].crtc_id
= priv
->crtcs
[i
]->base
.id
;
600 priv
->event_thread
[i
].dev
= ddev
;
601 priv
->event_thread
[i
].worker
= kthread_create_worker(0,
602 "crtc_event:%d", priv
->event_thread
[i
].crtc_id
);
603 if (IS_ERR(priv
->event_thread
[i
].worker
)) {
604 ret
= PTR_ERR(priv
->event_thread
[i
].worker
);
605 DRM_DEV_ERROR(dev
, "failed to create crtc_event kthread\n");
606 ret
= PTR_ERR(priv
->event_thread
[i
].worker
);
610 sched_set_fifo(priv
->event_thread
[i
].worker
->task
);
613 ret
= drm_vblank_init(ddev
, priv
->num_crtcs
);
615 DRM_DEV_ERROR(dev
, "failed to initialize vblank\n");
620 pm_runtime_get_sync(dev
);
621 ret
= msm_irq_install(ddev
, kms
->irq
);
622 pm_runtime_put_sync(dev
);
624 DRM_DEV_ERROR(dev
, "failed to install IRQ handler\n");
629 ret
= drm_dev_register(ddev
, 0);
634 ret
= msm_disp_snapshot_init(ddev
);
636 DRM_DEV_ERROR(dev
, "msm_disp_snapshot_init failed ret = %d\n", ret
);
638 drm_mode_config_reset(ddev
);
640 #ifdef CONFIG_DRM_FBDEV_EMULATION
642 priv
->fbdev
= msm_fbdev_init(ddev
);
645 ret
= msm_debugfs_late_init(ddev
);
649 drm_kms_helper_poll_init(ddev
);
657 if (mdss
&& mdss
->funcs
)
658 mdss
->funcs
->destroy(ddev
);
663 platform_set_drvdata(pdev
, NULL
);
671 static void load_gpu(struct drm_device
*dev
)
673 static DEFINE_MUTEX(init_lock
);
674 struct msm_drm_private
*priv
= dev
->dev_private
;
676 mutex_lock(&init_lock
);
679 priv
->gpu
= adreno_load_gpu(dev
);
681 mutex_unlock(&init_lock
);
684 static int context_init(struct drm_device
*dev
, struct drm_file
*file
)
686 static atomic_t ident
= ATOMIC_INIT(0);
687 struct msm_drm_private
*priv
= dev
->dev_private
;
688 struct msm_file_private
*ctx
;
690 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
694 INIT_LIST_HEAD(&ctx
->submitqueues
);
695 rwlock_init(&ctx
->queuelock
);
697 kref_init(&ctx
->ref
);
698 msm_submitqueue_init(dev
, ctx
);
700 ctx
->aspace
= msm_gpu_create_private_address_space(priv
->gpu
, current
);
701 file
->driver_priv
= ctx
;
703 ctx
->seqno
= atomic_inc_return(&ident
);
708 static int msm_open(struct drm_device
*dev
, struct drm_file
*file
)
710 /* For now, load gpu on open.. to avoid the requirement of having
711 * firmware in the initrd.
715 return context_init(dev
, file
);
718 static void context_close(struct msm_file_private
*ctx
)
720 msm_submitqueue_close(ctx
);
721 msm_file_private_put(ctx
);
724 static void msm_postclose(struct drm_device
*dev
, struct drm_file
*file
)
726 struct msm_drm_private
*priv
= dev
->dev_private
;
727 struct msm_file_private
*ctx
= file
->driver_priv
;
729 mutex_lock(&dev
->struct_mutex
);
730 if (ctx
== priv
->lastctx
)
731 priv
->lastctx
= NULL
;
732 mutex_unlock(&dev
->struct_mutex
);
737 int msm_crtc_enable_vblank(struct drm_crtc
*crtc
)
739 struct drm_device
*dev
= crtc
->dev
;
740 unsigned int pipe
= crtc
->index
;
741 struct msm_drm_private
*priv
= dev
->dev_private
;
742 struct msm_kms
*kms
= priv
->kms
;
745 drm_dbg_vbl(dev
, "crtc=%u", pipe
);
746 return vblank_ctrl_queue_work(priv
, pipe
, true);
749 void msm_crtc_disable_vblank(struct drm_crtc
*crtc
)
751 struct drm_device
*dev
= crtc
->dev
;
752 unsigned int pipe
= crtc
->index
;
753 struct msm_drm_private
*priv
= dev
->dev_private
;
754 struct msm_kms
*kms
= priv
->kms
;
757 drm_dbg_vbl(dev
, "crtc=%u", pipe
);
758 vblank_ctrl_queue_work(priv
, pipe
, false);
765 static int msm_ioctl_get_param(struct drm_device
*dev
, void *data
,
766 struct drm_file
*file
)
768 struct msm_drm_private
*priv
= dev
->dev_private
;
769 struct drm_msm_param
*args
= data
;
772 /* for now, we just have 3d pipe.. eventually this would need to
773 * be more clever to dispatch to appropriate gpu module:
775 if (args
->pipe
!= MSM_PIPE_3D0
)
783 return gpu
->funcs
->get_param(gpu
, args
->param
, &args
->value
);
786 static int msm_ioctl_gem_new(struct drm_device
*dev
, void *data
,
787 struct drm_file
*file
)
789 struct drm_msm_gem_new
*args
= data
;
791 if (args
->flags
& ~MSM_BO_FLAGS
) {
792 DRM_ERROR("invalid flags: %08x\n", args
->flags
);
796 return msm_gem_new_handle(dev
, file
, args
->size
,
797 args
->flags
, &args
->handle
, NULL
);
800 static inline ktime_t
to_ktime(struct drm_msm_timespec timeout
)
802 return ktime_set(timeout
.tv_sec
, timeout
.tv_nsec
);
805 static int msm_ioctl_gem_cpu_prep(struct drm_device
*dev
, void *data
,
806 struct drm_file
*file
)
808 struct drm_msm_gem_cpu_prep
*args
= data
;
809 struct drm_gem_object
*obj
;
810 ktime_t timeout
= to_ktime(args
->timeout
);
813 if (args
->op
& ~MSM_PREP_FLAGS
) {
814 DRM_ERROR("invalid op: %08x\n", args
->op
);
818 obj
= drm_gem_object_lookup(file
, args
->handle
);
822 ret
= msm_gem_cpu_prep(obj
, args
->op
, &timeout
);
824 drm_gem_object_put(obj
);
829 static int msm_ioctl_gem_cpu_fini(struct drm_device
*dev
, void *data
,
830 struct drm_file
*file
)
832 struct drm_msm_gem_cpu_fini
*args
= data
;
833 struct drm_gem_object
*obj
;
836 obj
= drm_gem_object_lookup(file
, args
->handle
);
840 ret
= msm_gem_cpu_fini(obj
);
842 drm_gem_object_put(obj
);
847 static int msm_ioctl_gem_info_iova(struct drm_device
*dev
,
848 struct drm_file
*file
, struct drm_gem_object
*obj
,
851 struct msm_drm_private
*priv
= dev
->dev_private
;
852 struct msm_file_private
*ctx
= file
->driver_priv
;
858 * Don't pin the memory here - just get an address so that userspace can
861 return msm_gem_get_iova(obj
, ctx
->aspace
, iova
);
864 static int msm_ioctl_gem_info(struct drm_device
*dev
, void *data
,
865 struct drm_file
*file
)
867 struct drm_msm_gem_info
*args
= data
;
868 struct drm_gem_object
*obj
;
869 struct msm_gem_object
*msm_obj
;
875 switch (args
->info
) {
876 case MSM_INFO_GET_OFFSET
:
877 case MSM_INFO_GET_IOVA
:
878 /* value returned as immediate, not pointer, so len==0: */
882 case MSM_INFO_SET_NAME
:
883 case MSM_INFO_GET_NAME
:
889 obj
= drm_gem_object_lookup(file
, args
->handle
);
893 msm_obj
= to_msm_bo(obj
);
895 switch (args
->info
) {
896 case MSM_INFO_GET_OFFSET
:
897 args
->value
= msm_gem_mmap_offset(obj
);
899 case MSM_INFO_GET_IOVA
:
900 ret
= msm_ioctl_gem_info_iova(dev
, file
, obj
, &args
->value
);
902 case MSM_INFO_SET_NAME
:
903 /* length check should leave room for terminating null: */
904 if (args
->len
>= sizeof(msm_obj
->name
)) {
908 if (copy_from_user(msm_obj
->name
, u64_to_user_ptr(args
->value
),
910 msm_obj
->name
[0] = '\0';
914 msm_obj
->name
[args
->len
] = '\0';
915 for (i
= 0; i
< args
->len
; i
++) {
916 if (!isprint(msm_obj
->name
[i
])) {
917 msm_obj
->name
[i
] = '\0';
922 case MSM_INFO_GET_NAME
:
923 if (args
->value
&& (args
->len
< strlen(msm_obj
->name
))) {
927 args
->len
= strlen(msm_obj
->name
);
929 if (copy_to_user(u64_to_user_ptr(args
->value
),
930 msm_obj
->name
, args
->len
))
936 drm_gem_object_put(obj
);
941 static int msm_ioctl_wait_fence(struct drm_device
*dev
, void *data
,
942 struct drm_file
*file
)
944 struct msm_drm_private
*priv
= dev
->dev_private
;
945 struct drm_msm_wait_fence
*args
= data
;
946 ktime_t timeout
= to_ktime(args
->timeout
);
947 struct msm_gpu_submitqueue
*queue
;
948 struct msm_gpu
*gpu
= priv
->gpu
;
949 struct dma_fence
*fence
;
953 DRM_ERROR("invalid pad: %08x\n", args
->pad
);
960 queue
= msm_submitqueue_get(file
->driver_priv
, args
->queueid
);
965 * Map submitqueue scoped "seqno" (which is actually an idr key)
966 * back to underlying dma-fence
968 * The fence is removed from the fence_idr when the submit is
969 * retired, so if the fence is not found it means there is nothing
972 ret
= mutex_lock_interruptible(&queue
->lock
);
975 fence
= idr_find(&queue
->fence_idr
, args
->fence
);
977 fence
= dma_fence_get_rcu(fence
);
978 mutex_unlock(&queue
->lock
);
983 ret
= dma_fence_wait_timeout(fence
, true, timeout_to_jiffies(&timeout
));
986 } else if (ret
!= -ERESTARTSYS
) {
990 dma_fence_put(fence
);
991 msm_submitqueue_put(queue
);
996 static int msm_ioctl_gem_madvise(struct drm_device
*dev
, void *data
,
997 struct drm_file
*file
)
999 struct drm_msm_gem_madvise
*args
= data
;
1000 struct drm_gem_object
*obj
;
1003 switch (args
->madv
) {
1004 case MSM_MADV_DONTNEED
:
1005 case MSM_MADV_WILLNEED
:
1011 obj
= drm_gem_object_lookup(file
, args
->handle
);
1016 ret
= msm_gem_madvise(obj
, args
->madv
);
1018 args
->retained
= ret
;
1022 drm_gem_object_put(obj
);
1028 static int msm_ioctl_submitqueue_new(struct drm_device
*dev
, void *data
,
1029 struct drm_file
*file
)
1031 struct drm_msm_submitqueue
*args
= data
;
1033 if (args
->flags
& ~MSM_SUBMITQUEUE_FLAGS
)
1036 return msm_submitqueue_create(dev
, file
->driver_priv
, args
->prio
,
1037 args
->flags
, &args
->id
);
1040 static int msm_ioctl_submitqueue_query(struct drm_device
*dev
, void *data
,
1041 struct drm_file
*file
)
1043 return msm_submitqueue_query(dev
, file
->driver_priv
, data
);
1046 static int msm_ioctl_submitqueue_close(struct drm_device
*dev
, void *data
,
1047 struct drm_file
*file
)
1049 u32 id
= *(u32
*) data
;
1051 return msm_submitqueue_remove(file
->driver_priv
, id
);
1054 static const struct drm_ioctl_desc msm_ioctls
[] = {
1055 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM
, msm_ioctl_get_param
, DRM_RENDER_ALLOW
),
1056 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW
, msm_ioctl_gem_new
, DRM_RENDER_ALLOW
),
1057 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO
, msm_ioctl_gem_info
, DRM_RENDER_ALLOW
),
1058 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP
, msm_ioctl_gem_cpu_prep
, DRM_RENDER_ALLOW
),
1059 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI
, msm_ioctl_gem_cpu_fini
, DRM_RENDER_ALLOW
),
1060 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT
, msm_ioctl_gem_submit
, DRM_RENDER_ALLOW
),
1061 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE
, msm_ioctl_wait_fence
, DRM_RENDER_ALLOW
),
1062 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE
, msm_ioctl_gem_madvise
, DRM_RENDER_ALLOW
),
1063 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW
, msm_ioctl_submitqueue_new
, DRM_RENDER_ALLOW
),
1064 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE
, msm_ioctl_submitqueue_close
, DRM_RENDER_ALLOW
),
1065 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY
, msm_ioctl_submitqueue_query
, DRM_RENDER_ALLOW
),
1068 DEFINE_DRM_GEM_FOPS(fops
);
1070 static const struct drm_driver msm_driver
= {
1071 .driver_features
= DRIVER_GEM
|
1077 .postclose
= msm_postclose
,
1078 .lastclose
= drm_fb_helper_lastclose
,
1079 .dumb_create
= msm_gem_dumb_create
,
1080 .dumb_map_offset
= msm_gem_dumb_map_offset
,
1081 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1082 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1083 .gem_prime_import_sg_table
= msm_gem_prime_import_sg_table
,
1084 .gem_prime_mmap
= drm_gem_prime_mmap
,
1085 #ifdef CONFIG_DEBUG_FS
1086 .debugfs_init
= msm_debugfs_init
,
1088 .ioctls
= msm_ioctls
,
1089 .num_ioctls
= ARRAY_SIZE(msm_ioctls
),
1092 .desc
= "MSM Snapdragon DRM",
1094 .major
= MSM_VERSION_MAJOR
,
1095 .minor
= MSM_VERSION_MINOR
,
1096 .patchlevel
= MSM_VERSION_PATCHLEVEL
,
1099 static int __maybe_unused
msm_runtime_suspend(struct device
*dev
)
1101 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1102 struct msm_drm_private
*priv
= ddev
->dev_private
;
1103 struct msm_mdss
*mdss
= priv
->mdss
;
1107 if (mdss
&& mdss
->funcs
)
1108 return mdss
->funcs
->disable(mdss
);
1113 static int __maybe_unused
msm_runtime_resume(struct device
*dev
)
1115 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1116 struct msm_drm_private
*priv
= ddev
->dev_private
;
1117 struct msm_mdss
*mdss
= priv
->mdss
;
1121 if (mdss
&& mdss
->funcs
)
1122 return mdss
->funcs
->enable(mdss
);
1127 static int __maybe_unused
msm_pm_suspend(struct device
*dev
)
1130 if (pm_runtime_suspended(dev
))
1133 return msm_runtime_suspend(dev
);
1136 static int __maybe_unused
msm_pm_resume(struct device
*dev
)
1138 if (pm_runtime_suspended(dev
))
1141 return msm_runtime_resume(dev
);
1144 static int __maybe_unused
msm_pm_prepare(struct device
*dev
)
1146 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1147 struct msm_drm_private
*priv
= ddev
? ddev
->dev_private
: NULL
;
1149 if (!priv
|| !priv
->kms
)
1152 return drm_mode_config_helper_suspend(ddev
);
1155 static void __maybe_unused
msm_pm_complete(struct device
*dev
)
1157 struct drm_device
*ddev
= dev_get_drvdata(dev
);
1158 struct msm_drm_private
*priv
= ddev
? ddev
->dev_private
: NULL
;
1160 if (!priv
|| !priv
->kms
)
1163 drm_mode_config_helper_resume(ddev
);
1166 static const struct dev_pm_ops msm_pm_ops
= {
1167 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend
, msm_pm_resume
)
1168 SET_RUNTIME_PM_OPS(msm_runtime_suspend
, msm_runtime_resume
, NULL
)
1169 .prepare
= msm_pm_prepare
,
1170 .complete
= msm_pm_complete
,
1174 * Componentized driver support:
1178 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1179 * so probably some room for some helpers
1181 static int compare_of(struct device
*dev
, void *data
)
1183 return dev
->of_node
== data
;
1187 * Identify what components need to be added by parsing what remote-endpoints
1188 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1189 * is no external component that we need to add since LVDS is within MDP4
1192 static int add_components_mdp(struct device
*mdp_dev
,
1193 struct component_match
**matchptr
)
1195 struct device_node
*np
= mdp_dev
->of_node
;
1196 struct device_node
*ep_node
;
1197 struct device
*master_dev
;
1200 * on MDP4 based platforms, the MDP platform device is the component
1201 * master that adds other display interface components to itself.
1203 * on MDP5 based platforms, the MDSS platform device is the component
1204 * master that adds MDP5 and other display interface components to
1207 if (of_device_is_compatible(np
, "qcom,mdp4"))
1208 master_dev
= mdp_dev
;
1210 master_dev
= mdp_dev
->parent
;
1212 for_each_endpoint_of_node(np
, ep_node
) {
1213 struct device_node
*intf
;
1214 struct of_endpoint ep
;
1217 ret
= of_graph_parse_endpoint(ep_node
, &ep
);
1219 DRM_DEV_ERROR(mdp_dev
, "unable to parse port endpoint\n");
1220 of_node_put(ep_node
);
1225 * The LCDC/LVDS port on MDP4 is a speacial case where the
1226 * remote-endpoint isn't a component that we need to add
1228 if (of_device_is_compatible(np
, "qcom,mdp4") &&
1233 * It's okay if some of the ports don't have a remote endpoint
1234 * specified. It just means that the port isn't connected to
1235 * any external interface.
1237 intf
= of_graph_get_remote_port_parent(ep_node
);
1241 if (of_device_is_available(intf
))
1242 drm_of_component_match_add(master_dev
, matchptr
,
1251 static int compare_name_mdp(struct device
*dev
, void *data
)
1253 return (strstr(dev_name(dev
), "mdp") != NULL
);
1256 static int add_display_components(struct platform_device
*pdev
,
1257 struct component_match
**matchptr
)
1259 struct device
*mdp_dev
;
1260 struct device
*dev
= &pdev
->dev
;
1264 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1265 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1266 * Populate the children devices, find the MDP5/DPU node, and then add
1267 * the interfaces to our components list.
1269 switch (get_mdp_ver(pdev
)) {
1272 ret
= of_platform_populate(dev
->of_node
, NULL
, NULL
, dev
);
1274 DRM_DEV_ERROR(dev
, "failed to populate children devices\n");
1278 mdp_dev
= device_find_child(dev
, NULL
, compare_name_mdp
);
1280 DRM_DEV_ERROR(dev
, "failed to find MDSS MDP node\n");
1281 of_platform_depopulate(dev
);
1285 put_device(mdp_dev
);
1287 /* add the MDP component itself */
1288 drm_of_component_match_add(dev
, matchptr
, compare_of
,
1297 ret
= add_components_mdp(mdp_dev
, matchptr
);
1299 of_platform_depopulate(dev
);
1305 * We don't know what's the best binding to link the gpu with the drm device.
1306 * Fow now, we just hunt for all the possible gpus that we support, and add them
1309 static const struct of_device_id msm_gpu_match
[] = {
1310 { .compatible
= "qcom,adreno" },
1311 { .compatible
= "qcom,adreno-3xx" },
1312 { .compatible
= "amd,imageon" },
1313 { .compatible
= "qcom,kgsl-3d0" },
1317 static int add_gpu_components(struct device
*dev
,
1318 struct component_match
**matchptr
)
1320 struct device_node
*np
;
1322 np
= of_find_matching_node(NULL
, msm_gpu_match
);
1326 if (of_device_is_available(np
))
1327 drm_of_component_match_add(dev
, matchptr
, compare_of
, np
);
1334 static int msm_drm_bind(struct device
*dev
)
1336 return msm_drm_init(dev
, &msm_driver
);
1339 static void msm_drm_unbind(struct device
*dev
)
1341 msm_drm_uninit(dev
);
1344 static const struct component_master_ops msm_drm_ops
= {
1345 .bind
= msm_drm_bind
,
1346 .unbind
= msm_drm_unbind
,
1353 static int msm_pdev_probe(struct platform_device
*pdev
)
1355 struct component_match
*match
= NULL
;
1358 if (get_mdp_ver(pdev
)) {
1359 ret
= add_display_components(pdev
, &match
);
1364 ret
= add_gpu_components(&pdev
->dev
, &match
);
1368 /* on all devices that I am aware of, iommu's which can map
1369 * any address the cpu can see are used:
1371 ret
= dma_set_mask_and_coherent(&pdev
->dev
, ~0);
1375 ret
= component_master_add_with_match(&pdev
->dev
, &msm_drm_ops
, match
);
1382 of_platform_depopulate(&pdev
->dev
);
1386 static int msm_pdev_remove(struct platform_device
*pdev
)
1388 component_master_del(&pdev
->dev
, &msm_drm_ops
);
1389 of_platform_depopulate(&pdev
->dev
);
1394 static void msm_pdev_shutdown(struct platform_device
*pdev
)
1396 struct drm_device
*drm
= platform_get_drvdata(pdev
);
1397 struct msm_drm_private
*priv
= drm
? drm
->dev_private
: NULL
;
1399 if (!priv
|| !priv
->kms
)
1402 drm_atomic_helper_shutdown(drm
);
1405 static const struct of_device_id dt_match
[] = {
1406 { .compatible
= "qcom,mdp4", .data
= (void *)KMS_MDP4
},
1407 { .compatible
= "qcom,mdss", .data
= (void *)KMS_MDP5
},
1408 { .compatible
= "qcom,sdm845-mdss", .data
= (void *)KMS_DPU
},
1409 { .compatible
= "qcom,sc7180-mdss", .data
= (void *)KMS_DPU
},
1410 { .compatible
= "qcom,sc7280-mdss", .data
= (void *)KMS_DPU
},
1411 { .compatible
= "qcom,sm8150-mdss", .data
= (void *)KMS_DPU
},
1412 { .compatible
= "qcom,sm8250-mdss", .data
= (void *)KMS_DPU
},
1415 MODULE_DEVICE_TABLE(of
, dt_match
);
1417 static struct platform_driver msm_platform_driver
= {
1418 .probe
= msm_pdev_probe
,
1419 .remove
= msm_pdev_remove
,
1420 .shutdown
= msm_pdev_shutdown
,
1423 .of_match_table
= dt_match
,
1428 static int __init
msm_drm_register(void)
1438 msm_hdmi_register();
1441 return platform_driver_register(&msm_platform_driver
);
1444 static void __exit
msm_drm_unregister(void)
1447 platform_driver_unregister(&msm_platform_driver
);
1448 msm_dp_unregister();
1449 msm_hdmi_unregister();
1450 adreno_unregister();
1451 msm_edp_unregister();
1452 msm_dsi_unregister();
1453 msm_mdp_unregister();
1454 msm_dpu_unregister();
1457 module_init(msm_drm_register
);
1458 module_exit(msm_drm_unregister
);
1460 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1461 MODULE_DESCRIPTION("MSM DRM Driver");
1462 MODULE_LICENSE("GPL");