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Merge branch 'tda998x-fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-cubox into...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / msm / msm_drv.c
1 /*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include "msm_drv.h"
19 #include "msm_gpu.h"
20 #include "msm_kms.h"
21
22 static void msm_fb_output_poll_changed(struct drm_device *dev)
23 {
24 struct msm_drm_private *priv = dev->dev_private;
25 if (priv->fbdev)
26 drm_fb_helper_hotplug_event(priv->fbdev);
27 }
28
29 static const struct drm_mode_config_funcs mode_config_funcs = {
30 .fb_create = msm_framebuffer_create,
31 .output_poll_changed = msm_fb_output_poll_changed,
32 };
33
34 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
35 {
36 struct msm_drm_private *priv = dev->dev_private;
37 int idx = priv->num_mmus++;
38
39 if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
40 return -EINVAL;
41
42 priv->mmus[idx] = mmu;
43
44 return idx;
45 }
46
47 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
48 static bool reglog = false;
49 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
50 module_param(reglog, bool, 0600);
51 #else
52 #define reglog 0
53 #endif
54
55 static char *vram;
56 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
57 module_param(vram, charp, 0);
58
59 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
60 const char *dbgname)
61 {
62 struct resource *res;
63 unsigned long size;
64 void __iomem *ptr;
65
66 if (name)
67 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
68 else
69 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
70
71 if (!res) {
72 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
73 return ERR_PTR(-EINVAL);
74 }
75
76 size = resource_size(res);
77
78 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
79 if (!ptr) {
80 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
81 return ERR_PTR(-ENOMEM);
82 }
83
84 if (reglog)
85 printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size);
86
87 return ptr;
88 }
89
90 void msm_writel(u32 data, void __iomem *addr)
91 {
92 if (reglog)
93 printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data);
94 writel(data, addr);
95 }
96
97 u32 msm_readl(const void __iomem *addr)
98 {
99 u32 val = readl(addr);
100 if (reglog)
101 printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val);
102 return val;
103 }
104
105 /*
106 * DRM operations:
107 */
108
109 static int msm_unload(struct drm_device *dev)
110 {
111 struct msm_drm_private *priv = dev->dev_private;
112 struct msm_kms *kms = priv->kms;
113 struct msm_gpu *gpu = priv->gpu;
114
115 drm_kms_helper_poll_fini(dev);
116 drm_mode_config_cleanup(dev);
117 drm_vblank_cleanup(dev);
118
119 pm_runtime_get_sync(dev->dev);
120 drm_irq_uninstall(dev);
121 pm_runtime_put_sync(dev->dev);
122
123 flush_workqueue(priv->wq);
124 destroy_workqueue(priv->wq);
125
126 if (kms) {
127 pm_runtime_disable(dev->dev);
128 kms->funcs->destroy(kms);
129 }
130
131 if (gpu) {
132 mutex_lock(&dev->struct_mutex);
133 gpu->funcs->pm_suspend(gpu);
134 gpu->funcs->destroy(gpu);
135 mutex_unlock(&dev->struct_mutex);
136 }
137
138 if (priv->vram.paddr) {
139 DEFINE_DMA_ATTRS(attrs);
140 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
141 drm_mm_takedown(&priv->vram.mm);
142 dma_free_attrs(dev->dev, priv->vram.size, NULL,
143 priv->vram.paddr, &attrs);
144 }
145
146 dev->dev_private = NULL;
147
148 kfree(priv);
149
150 return 0;
151 }
152
153 static int get_mdp_ver(struct platform_device *pdev)
154 {
155 #ifdef CONFIG_OF
156 const static struct of_device_id match_types[] = { {
157 .compatible = "qcom,mdss_mdp",
158 .data = (void *)5,
159 }, {
160 /* end node */
161 } };
162 struct device *dev = &pdev->dev;
163 const struct of_device_id *match;
164 match = of_match_node(match_types, dev->of_node);
165 if (match)
166 return (int)match->data;
167 #endif
168 return 4;
169 }
170
171 static int msm_load(struct drm_device *dev, unsigned long flags)
172 {
173 struct platform_device *pdev = dev->platformdev;
174 struct msm_drm_private *priv;
175 struct msm_kms *kms;
176 int ret;
177
178 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
179 if (!priv) {
180 dev_err(dev->dev, "failed to allocate private data\n");
181 return -ENOMEM;
182 }
183
184 dev->dev_private = priv;
185
186 priv->wq = alloc_ordered_workqueue("msm", 0);
187 init_waitqueue_head(&priv->fence_event);
188
189 INIT_LIST_HEAD(&priv->inactive_list);
190 INIT_LIST_HEAD(&priv->fence_cbs);
191
192 drm_mode_config_init(dev);
193
194 /* if we have no IOMMU, then we need to use carveout allocator.
195 * Grab the entire CMA chunk carved out in early startup in
196 * mach-msm:
197 */
198 if (!iommu_present(&platform_bus_type)) {
199 DEFINE_DMA_ATTRS(attrs);
200 unsigned long size;
201 void *p;
202
203 DBG("using %s VRAM carveout", vram);
204 size = memparse(vram, NULL);
205 priv->vram.size = size;
206
207 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
208
209 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
210 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
211
212 /* note that for no-kernel-mapping, the vaddr returned
213 * is bogus, but non-null if allocation succeeded:
214 */
215 p = dma_alloc_attrs(dev->dev, size,
216 &priv->vram.paddr, 0, &attrs);
217 if (!p) {
218 dev_err(dev->dev, "failed to allocate VRAM\n");
219 priv->vram.paddr = 0;
220 ret = -ENOMEM;
221 goto fail;
222 }
223
224 dev_info(dev->dev, "VRAM: %08x->%08x\n",
225 (uint32_t)priv->vram.paddr,
226 (uint32_t)(priv->vram.paddr + size));
227 }
228
229 switch (get_mdp_ver(pdev)) {
230 case 4:
231 kms = mdp4_kms_init(dev);
232 break;
233 case 5:
234 kms = mdp5_kms_init(dev);
235 break;
236 default:
237 kms = ERR_PTR(-ENODEV);
238 break;
239 }
240
241 if (IS_ERR(kms)) {
242 /*
243 * NOTE: once we have GPU support, having no kms should not
244 * be considered fatal.. ideally we would still support gpu
245 * and (for example) use dmabuf/prime to share buffers with
246 * imx drm driver on iMX5
247 */
248 dev_err(dev->dev, "failed to load kms\n");
249 ret = PTR_ERR(kms);
250 goto fail;
251 }
252
253 priv->kms = kms;
254
255 if (kms) {
256 pm_runtime_enable(dev->dev);
257 ret = kms->funcs->hw_init(kms);
258 if (ret) {
259 dev_err(dev->dev, "kms hw init failed: %d\n", ret);
260 goto fail;
261 }
262 }
263
264 dev->mode_config.min_width = 0;
265 dev->mode_config.min_height = 0;
266 dev->mode_config.max_width = 2048;
267 dev->mode_config.max_height = 2048;
268 dev->mode_config.funcs = &mode_config_funcs;
269
270 ret = drm_vblank_init(dev, 1);
271 if (ret < 0) {
272 dev_err(dev->dev, "failed to initialize vblank\n");
273 goto fail;
274 }
275
276 pm_runtime_get_sync(dev->dev);
277 ret = drm_irq_install(dev);
278 pm_runtime_put_sync(dev->dev);
279 if (ret < 0) {
280 dev_err(dev->dev, "failed to install IRQ handler\n");
281 goto fail;
282 }
283
284 platform_set_drvdata(pdev, dev);
285
286 #ifdef CONFIG_DRM_MSM_FBDEV
287 priv->fbdev = msm_fbdev_init(dev);
288 #endif
289
290 drm_kms_helper_poll_init(dev);
291
292 return 0;
293
294 fail:
295 msm_unload(dev);
296 return ret;
297 }
298
299 static void load_gpu(struct drm_device *dev)
300 {
301 struct msm_drm_private *priv = dev->dev_private;
302 struct msm_gpu *gpu;
303
304 if (priv->gpu)
305 return;
306
307 mutex_lock(&dev->struct_mutex);
308 gpu = a3xx_gpu_init(dev);
309 if (IS_ERR(gpu)) {
310 dev_warn(dev->dev, "failed to load a3xx gpu\n");
311 gpu = NULL;
312 /* not fatal */
313 }
314 mutex_unlock(&dev->struct_mutex);
315
316 if (gpu) {
317 int ret;
318 gpu->funcs->pm_resume(gpu);
319 ret = gpu->funcs->hw_init(gpu);
320 if (ret) {
321 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
322 gpu->funcs->destroy(gpu);
323 gpu = NULL;
324 }
325 }
326
327 priv->gpu = gpu;
328 }
329
330 static int msm_open(struct drm_device *dev, struct drm_file *file)
331 {
332 struct msm_file_private *ctx;
333
334 /* For now, load gpu on open.. to avoid the requirement of having
335 * firmware in the initrd.
336 */
337 load_gpu(dev);
338
339 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
340 if (!ctx)
341 return -ENOMEM;
342
343 file->driver_priv = ctx;
344
345 return 0;
346 }
347
348 static void msm_preclose(struct drm_device *dev, struct drm_file *file)
349 {
350 struct msm_drm_private *priv = dev->dev_private;
351 struct msm_file_private *ctx = file->driver_priv;
352 struct msm_kms *kms = priv->kms;
353
354 if (kms)
355 kms->funcs->preclose(kms, file);
356
357 mutex_lock(&dev->struct_mutex);
358 if (ctx == priv->lastctx)
359 priv->lastctx = NULL;
360 mutex_unlock(&dev->struct_mutex);
361
362 kfree(ctx);
363 }
364
365 static void msm_lastclose(struct drm_device *dev)
366 {
367 struct msm_drm_private *priv = dev->dev_private;
368 if (priv->fbdev) {
369 drm_modeset_lock_all(dev);
370 drm_fb_helper_restore_fbdev_mode(priv->fbdev);
371 drm_modeset_unlock_all(dev);
372 }
373 }
374
375 static irqreturn_t msm_irq(int irq, void *arg)
376 {
377 struct drm_device *dev = arg;
378 struct msm_drm_private *priv = dev->dev_private;
379 struct msm_kms *kms = priv->kms;
380 BUG_ON(!kms);
381 return kms->funcs->irq(kms);
382 }
383
384 static void msm_irq_preinstall(struct drm_device *dev)
385 {
386 struct msm_drm_private *priv = dev->dev_private;
387 struct msm_kms *kms = priv->kms;
388 BUG_ON(!kms);
389 kms->funcs->irq_preinstall(kms);
390 }
391
392 static int msm_irq_postinstall(struct drm_device *dev)
393 {
394 struct msm_drm_private *priv = dev->dev_private;
395 struct msm_kms *kms = priv->kms;
396 BUG_ON(!kms);
397 return kms->funcs->irq_postinstall(kms);
398 }
399
400 static void msm_irq_uninstall(struct drm_device *dev)
401 {
402 struct msm_drm_private *priv = dev->dev_private;
403 struct msm_kms *kms = priv->kms;
404 BUG_ON(!kms);
405 kms->funcs->irq_uninstall(kms);
406 }
407
408 static int msm_enable_vblank(struct drm_device *dev, int crtc_id)
409 {
410 struct msm_drm_private *priv = dev->dev_private;
411 struct msm_kms *kms = priv->kms;
412 if (!kms)
413 return -ENXIO;
414 DBG("dev=%p, crtc=%d", dev, crtc_id);
415 return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]);
416 }
417
418 static void msm_disable_vblank(struct drm_device *dev, int crtc_id)
419 {
420 struct msm_drm_private *priv = dev->dev_private;
421 struct msm_kms *kms = priv->kms;
422 if (!kms)
423 return;
424 DBG("dev=%p, crtc=%d", dev, crtc_id);
425 kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]);
426 }
427
428 /*
429 * DRM debugfs:
430 */
431
432 #ifdef CONFIG_DEBUG_FS
433 static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
434 {
435 struct msm_drm_private *priv = dev->dev_private;
436 struct msm_gpu *gpu = priv->gpu;
437
438 if (gpu) {
439 seq_printf(m, "%s Status:\n", gpu->name);
440 gpu->funcs->show(gpu, m);
441 }
442
443 return 0;
444 }
445
446 static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
447 {
448 struct msm_drm_private *priv = dev->dev_private;
449 struct msm_gpu *gpu = priv->gpu;
450
451 if (gpu) {
452 seq_printf(m, "Active Objects (%s):\n", gpu->name);
453 msm_gem_describe_objects(&gpu->active_list, m);
454 }
455
456 seq_printf(m, "Inactive Objects:\n");
457 msm_gem_describe_objects(&priv->inactive_list, m);
458
459 return 0;
460 }
461
462 static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
463 {
464 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
465 }
466
467 static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
468 {
469 struct msm_drm_private *priv = dev->dev_private;
470 struct drm_framebuffer *fb, *fbdev_fb = NULL;
471
472 if (priv->fbdev) {
473 seq_printf(m, "fbcon ");
474 fbdev_fb = priv->fbdev->fb;
475 msm_framebuffer_describe(fbdev_fb, m);
476 }
477
478 mutex_lock(&dev->mode_config.fb_lock);
479 list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
480 if (fb == fbdev_fb)
481 continue;
482
483 seq_printf(m, "user ");
484 msm_framebuffer_describe(fb, m);
485 }
486 mutex_unlock(&dev->mode_config.fb_lock);
487
488 return 0;
489 }
490
491 static int show_locked(struct seq_file *m, void *arg)
492 {
493 struct drm_info_node *node = (struct drm_info_node *) m->private;
494 struct drm_device *dev = node->minor->dev;
495 int (*show)(struct drm_device *dev, struct seq_file *m) =
496 node->info_ent->data;
497 int ret;
498
499 ret = mutex_lock_interruptible(&dev->struct_mutex);
500 if (ret)
501 return ret;
502
503 ret = show(dev, m);
504
505 mutex_unlock(&dev->struct_mutex);
506
507 return ret;
508 }
509
510 static struct drm_info_list msm_debugfs_list[] = {
511 {"gpu", show_locked, 0, msm_gpu_show},
512 {"gem", show_locked, 0, msm_gem_show},
513 { "mm", show_locked, 0, msm_mm_show },
514 { "fb", show_locked, 0, msm_fb_show },
515 };
516
517 static int msm_debugfs_init(struct drm_minor *minor)
518 {
519 struct drm_device *dev = minor->dev;
520 int ret;
521
522 ret = drm_debugfs_create_files(msm_debugfs_list,
523 ARRAY_SIZE(msm_debugfs_list),
524 minor->debugfs_root, minor);
525
526 if (ret) {
527 dev_err(dev->dev, "could not install msm_debugfs_list\n");
528 return ret;
529 }
530
531 return ret;
532 }
533
534 static void msm_debugfs_cleanup(struct drm_minor *minor)
535 {
536 drm_debugfs_remove_files(msm_debugfs_list,
537 ARRAY_SIZE(msm_debugfs_list), minor);
538 }
539 #endif
540
541 /*
542 * Fences:
543 */
544
545 int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
546 struct timespec *timeout)
547 {
548 struct msm_drm_private *priv = dev->dev_private;
549 int ret;
550
551 if (!priv->gpu)
552 return 0;
553
554 if (fence > priv->gpu->submitted_fence) {
555 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
556 fence, priv->gpu->submitted_fence);
557 return -EINVAL;
558 }
559
560 if (!timeout) {
561 /* no-wait: */
562 ret = fence_completed(dev, fence) ? 0 : -EBUSY;
563 } else {
564 unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
565 unsigned long start_jiffies = jiffies;
566 unsigned long remaining_jiffies;
567
568 if (time_after(start_jiffies, timeout_jiffies))
569 remaining_jiffies = 0;
570 else
571 remaining_jiffies = timeout_jiffies - start_jiffies;
572
573 ret = wait_event_interruptible_timeout(priv->fence_event,
574 fence_completed(dev, fence),
575 remaining_jiffies);
576
577 if (ret == 0) {
578 DBG("timeout waiting for fence: %u (completed: %u)",
579 fence, priv->completed_fence);
580 ret = -ETIMEDOUT;
581 } else if (ret != -ERESTARTSYS) {
582 ret = 0;
583 }
584 }
585
586 return ret;
587 }
588
589 /* called from workqueue */
590 void msm_update_fence(struct drm_device *dev, uint32_t fence)
591 {
592 struct msm_drm_private *priv = dev->dev_private;
593
594 mutex_lock(&dev->struct_mutex);
595 priv->completed_fence = max(fence, priv->completed_fence);
596
597 while (!list_empty(&priv->fence_cbs)) {
598 struct msm_fence_cb *cb;
599
600 cb = list_first_entry(&priv->fence_cbs,
601 struct msm_fence_cb, work.entry);
602
603 if (cb->fence > priv->completed_fence)
604 break;
605
606 list_del_init(&cb->work.entry);
607 queue_work(priv->wq, &cb->work);
608 }
609
610 mutex_unlock(&dev->struct_mutex);
611
612 wake_up_all(&priv->fence_event);
613 }
614
615 void __msm_fence_worker(struct work_struct *work)
616 {
617 struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
618 cb->func(cb);
619 }
620
621 /*
622 * DRM ioctls:
623 */
624
625 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
626 struct drm_file *file)
627 {
628 struct msm_drm_private *priv = dev->dev_private;
629 struct drm_msm_param *args = data;
630 struct msm_gpu *gpu;
631
632 /* for now, we just have 3d pipe.. eventually this would need to
633 * be more clever to dispatch to appropriate gpu module:
634 */
635 if (args->pipe != MSM_PIPE_3D0)
636 return -EINVAL;
637
638 gpu = priv->gpu;
639
640 if (!gpu)
641 return -ENXIO;
642
643 return gpu->funcs->get_param(gpu, args->param, &args->value);
644 }
645
646 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
647 struct drm_file *file)
648 {
649 struct drm_msm_gem_new *args = data;
650 return msm_gem_new_handle(dev, file, args->size,
651 args->flags, &args->handle);
652 }
653
654 #define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec })
655
656 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
657 struct drm_file *file)
658 {
659 struct drm_msm_gem_cpu_prep *args = data;
660 struct drm_gem_object *obj;
661 int ret;
662
663 obj = drm_gem_object_lookup(dev, file, args->handle);
664 if (!obj)
665 return -ENOENT;
666
667 ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout));
668
669 drm_gem_object_unreference_unlocked(obj);
670
671 return ret;
672 }
673
674 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
675 struct drm_file *file)
676 {
677 struct drm_msm_gem_cpu_fini *args = data;
678 struct drm_gem_object *obj;
679 int ret;
680
681 obj = drm_gem_object_lookup(dev, file, args->handle);
682 if (!obj)
683 return -ENOENT;
684
685 ret = msm_gem_cpu_fini(obj);
686
687 drm_gem_object_unreference_unlocked(obj);
688
689 return ret;
690 }
691
692 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
693 struct drm_file *file)
694 {
695 struct drm_msm_gem_info *args = data;
696 struct drm_gem_object *obj;
697 int ret = 0;
698
699 if (args->pad)
700 return -EINVAL;
701
702 obj = drm_gem_object_lookup(dev, file, args->handle);
703 if (!obj)
704 return -ENOENT;
705
706 args->offset = msm_gem_mmap_offset(obj);
707
708 drm_gem_object_unreference_unlocked(obj);
709
710 return ret;
711 }
712
713 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
714 struct drm_file *file)
715 {
716 struct drm_msm_wait_fence *args = data;
717 return msm_wait_fence_interruptable(dev, args->fence, &TS(args->timeout));
718 }
719
720 static const struct drm_ioctl_desc msm_ioctls[] = {
721 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
722 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
723 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
724 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
725 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
726 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
727 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
728 };
729
730 static const struct vm_operations_struct vm_ops = {
731 .fault = msm_gem_fault,
732 .open = drm_gem_vm_open,
733 .close = drm_gem_vm_close,
734 };
735
736 static const struct file_operations fops = {
737 .owner = THIS_MODULE,
738 .open = drm_open,
739 .release = drm_release,
740 .unlocked_ioctl = drm_ioctl,
741 #ifdef CONFIG_COMPAT
742 .compat_ioctl = drm_compat_ioctl,
743 #endif
744 .poll = drm_poll,
745 .read = drm_read,
746 .llseek = no_llseek,
747 .mmap = msm_gem_mmap,
748 };
749
750 static struct drm_driver msm_driver = {
751 .driver_features = DRIVER_HAVE_IRQ |
752 DRIVER_GEM |
753 DRIVER_PRIME |
754 DRIVER_RENDER |
755 DRIVER_MODESET,
756 .load = msm_load,
757 .unload = msm_unload,
758 .open = msm_open,
759 .preclose = msm_preclose,
760 .lastclose = msm_lastclose,
761 .irq_handler = msm_irq,
762 .irq_preinstall = msm_irq_preinstall,
763 .irq_postinstall = msm_irq_postinstall,
764 .irq_uninstall = msm_irq_uninstall,
765 .get_vblank_counter = drm_vblank_count,
766 .enable_vblank = msm_enable_vblank,
767 .disable_vblank = msm_disable_vblank,
768 .gem_free_object = msm_gem_free_object,
769 .gem_vm_ops = &vm_ops,
770 .dumb_create = msm_gem_dumb_create,
771 .dumb_map_offset = msm_gem_dumb_map_offset,
772 .dumb_destroy = drm_gem_dumb_destroy,
773 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
774 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
775 .gem_prime_export = drm_gem_prime_export,
776 .gem_prime_import = drm_gem_prime_import,
777 .gem_prime_pin = msm_gem_prime_pin,
778 .gem_prime_unpin = msm_gem_prime_unpin,
779 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
780 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
781 .gem_prime_vmap = msm_gem_prime_vmap,
782 .gem_prime_vunmap = msm_gem_prime_vunmap,
783 #ifdef CONFIG_DEBUG_FS
784 .debugfs_init = msm_debugfs_init,
785 .debugfs_cleanup = msm_debugfs_cleanup,
786 #endif
787 .ioctls = msm_ioctls,
788 .num_ioctls = DRM_MSM_NUM_IOCTLS,
789 .fops = &fops,
790 .name = "msm",
791 .desc = "MSM Snapdragon DRM",
792 .date = "20130625",
793 .major = 1,
794 .minor = 0,
795 };
796
797 #ifdef CONFIG_PM_SLEEP
798 static int msm_pm_suspend(struct device *dev)
799 {
800 struct drm_device *ddev = dev_get_drvdata(dev);
801
802 drm_kms_helper_poll_disable(ddev);
803
804 return 0;
805 }
806
807 static int msm_pm_resume(struct device *dev)
808 {
809 struct drm_device *ddev = dev_get_drvdata(dev);
810
811 drm_kms_helper_poll_enable(ddev);
812
813 return 0;
814 }
815 #endif
816
817 static const struct dev_pm_ops msm_pm_ops = {
818 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
819 };
820
821 /*
822 * Platform driver:
823 */
824
825 static int msm_pdev_probe(struct platform_device *pdev)
826 {
827 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
828 return drm_platform_init(&msm_driver, pdev);
829 }
830
831 static int msm_pdev_remove(struct platform_device *pdev)
832 {
833 drm_put_dev(platform_get_drvdata(pdev));
834
835 return 0;
836 }
837
838 static const struct platform_device_id msm_id[] = {
839 { "mdp", 0 },
840 { }
841 };
842
843 static const struct of_device_id dt_match[] = {
844 { .compatible = "qcom,mdss_mdp" },
845 {}
846 };
847 MODULE_DEVICE_TABLE(of, dt_match);
848
849 static struct platform_driver msm_platform_driver = {
850 .probe = msm_pdev_probe,
851 .remove = msm_pdev_remove,
852 .driver = {
853 .owner = THIS_MODULE,
854 .name = "msm",
855 .of_match_table = dt_match,
856 .pm = &msm_pm_ops,
857 },
858 .id_table = msm_id,
859 };
860
861 static int __init msm_drm_register(void)
862 {
863 DBG("init");
864 hdmi_register();
865 a3xx_register();
866 return platform_driver_register(&msm_platform_driver);
867 }
868
869 static void __exit msm_drm_unregister(void)
870 {
871 DBG("fini");
872 platform_driver_unregister(&msm_platform_driver);
873 hdmi_unregister();
874 a3xx_unregister();
875 }
876
877 module_init(msm_drm_register);
878 module_exit(msm_drm_unregister);
879
880 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
881 MODULE_DESCRIPTION("MSM DRM Driver");
882 MODULE_LICENSE("GPL");