2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "msm_debugfs.h"
20 #include "msm_fence.h"
27 * - 1.0.0 - initial interface
28 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
30 #define MSM_VERSION_MAJOR 1
31 #define MSM_VERSION_MINOR 1
32 #define MSM_VERSION_PATCHLEVEL 0
34 static void msm_fb_output_poll_changed(struct drm_device
*dev
)
36 struct msm_drm_private
*priv
= dev
->dev_private
;
38 drm_fb_helper_hotplug_event(priv
->fbdev
);
41 static const struct drm_mode_config_funcs mode_config_funcs
= {
42 .fb_create
= msm_framebuffer_create
,
43 .output_poll_changed
= msm_fb_output_poll_changed
,
44 .atomic_check
= msm_atomic_check
,
45 .atomic_commit
= msm_atomic_commit
,
48 int msm_register_mmu(struct drm_device
*dev
, struct msm_mmu
*mmu
)
50 struct msm_drm_private
*priv
= dev
->dev_private
;
51 int idx
= priv
->num_mmus
++;
53 if (WARN_ON(idx
>= ARRAY_SIZE(priv
->mmus
)))
56 priv
->mmus
[idx
] = mmu
;
61 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
62 static bool reglog
= false;
63 MODULE_PARM_DESC(reglog
, "Enable register read/write logging");
64 module_param(reglog
, bool, 0600);
69 #ifdef CONFIG_DRM_FBDEV_EMULATION
70 static bool fbdev
= true;
71 MODULE_PARM_DESC(fbdev
, "Enable fbdev compat layer");
72 module_param(fbdev
, bool, 0600);
75 static char *vram
= "16m";
76 MODULE_PARM_DESC(vram
, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
77 module_param(vram
, charp
, 0);
83 void __iomem
*msm_ioremap(struct platform_device
*pdev
, const char *name
,
91 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, name
);
93 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
96 dev_err(&pdev
->dev
, "failed to get memory resource: %s\n", name
);
97 return ERR_PTR(-EINVAL
);
100 size
= resource_size(res
);
102 ptr
= devm_ioremap_nocache(&pdev
->dev
, res
->start
, size
);
104 dev_err(&pdev
->dev
, "failed to ioremap: %s\n", name
);
105 return ERR_PTR(-ENOMEM
);
109 printk(KERN_DEBUG
"IO:region %s %p %08lx\n", dbgname
, ptr
, size
);
114 void msm_writel(u32 data
, void __iomem
*addr
)
117 printk(KERN_DEBUG
"IO:W %p %08x\n", addr
, data
);
121 u32
msm_readl(const void __iomem
*addr
)
123 u32 val
= readl(addr
);
125 printk(KERN_ERR
"IO:R %p %08x\n", addr
, val
);
129 struct vblank_event
{
130 struct list_head node
;
135 static void vblank_ctrl_worker(struct work_struct
*work
)
137 struct msm_vblank_ctrl
*vbl_ctrl
= container_of(work
,
138 struct msm_vblank_ctrl
, work
);
139 struct msm_drm_private
*priv
= container_of(vbl_ctrl
,
140 struct msm_drm_private
, vblank_ctrl
);
141 struct msm_kms
*kms
= priv
->kms
;
142 struct vblank_event
*vbl_ev
, *tmp
;
145 spin_lock_irqsave(&vbl_ctrl
->lock
, flags
);
146 list_for_each_entry_safe(vbl_ev
, tmp
, &vbl_ctrl
->event_list
, node
) {
147 list_del(&vbl_ev
->node
);
148 spin_unlock_irqrestore(&vbl_ctrl
->lock
, flags
);
151 kms
->funcs
->enable_vblank(kms
,
152 priv
->crtcs
[vbl_ev
->crtc_id
]);
154 kms
->funcs
->disable_vblank(kms
,
155 priv
->crtcs
[vbl_ev
->crtc_id
]);
159 spin_lock_irqsave(&vbl_ctrl
->lock
, flags
);
162 spin_unlock_irqrestore(&vbl_ctrl
->lock
, flags
);
165 static int vblank_ctrl_queue_work(struct msm_drm_private
*priv
,
166 int crtc_id
, bool enable
)
168 struct msm_vblank_ctrl
*vbl_ctrl
= &priv
->vblank_ctrl
;
169 struct vblank_event
*vbl_ev
;
172 vbl_ev
= kzalloc(sizeof(*vbl_ev
), GFP_ATOMIC
);
176 vbl_ev
->crtc_id
= crtc_id
;
177 vbl_ev
->enable
= enable
;
179 spin_lock_irqsave(&vbl_ctrl
->lock
, flags
);
180 list_add_tail(&vbl_ev
->node
, &vbl_ctrl
->event_list
);
181 spin_unlock_irqrestore(&vbl_ctrl
->lock
, flags
);
183 queue_work(priv
->wq
, &vbl_ctrl
->work
);
188 static int msm_drm_uninit(struct device
*dev
)
190 struct platform_device
*pdev
= to_platform_device(dev
);
191 struct drm_device
*ddev
= platform_get_drvdata(pdev
);
192 struct msm_drm_private
*priv
= ddev
->dev_private
;
193 struct msm_kms
*kms
= priv
->kms
;
194 struct msm_gpu
*gpu
= priv
->gpu
;
195 struct msm_vblank_ctrl
*vbl_ctrl
= &priv
->vblank_ctrl
;
196 struct vblank_event
*vbl_ev
, *tmp
;
198 /* We must cancel and cleanup any pending vblank enable/disable
199 * work before drm_irq_uninstall() to avoid work re-enabling an
200 * irq after uninstall has disabled it.
202 cancel_work_sync(&vbl_ctrl
->work
);
203 list_for_each_entry_safe(vbl_ev
, tmp
, &vbl_ctrl
->event_list
, node
) {
204 list_del(&vbl_ev
->node
);
208 msm_gem_shrinker_cleanup(ddev
);
210 drm_kms_helper_poll_fini(ddev
);
212 drm_dev_unregister(ddev
);
214 #ifdef CONFIG_DRM_FBDEV_EMULATION
215 if (fbdev
&& priv
->fbdev
)
216 msm_fbdev_free(ddev
);
218 drm_mode_config_cleanup(ddev
);
220 pm_runtime_get_sync(dev
);
221 drm_irq_uninstall(ddev
);
222 pm_runtime_put_sync(dev
);
224 flush_workqueue(priv
->wq
);
225 destroy_workqueue(priv
->wq
);
227 flush_workqueue(priv
->atomic_wq
);
228 destroy_workqueue(priv
->atomic_wq
);
231 kms
->funcs
->destroy(kms
);
234 mutex_lock(&ddev
->struct_mutex
);
235 gpu
->funcs
->pm_suspend(gpu
);
236 mutex_unlock(&ddev
->struct_mutex
);
237 gpu
->funcs
->destroy(gpu
);
240 if (priv
->vram
.paddr
) {
241 unsigned long attrs
= DMA_ATTR_NO_KERNEL_MAPPING
;
242 drm_mm_takedown(&priv
->vram
.mm
);
243 dma_free_attrs(dev
, priv
->vram
.size
, NULL
,
244 priv
->vram
.paddr
, attrs
);
247 component_unbind_all(dev
, ddev
);
249 msm_mdss_destroy(ddev
);
251 ddev
->dev_private
= NULL
;
259 static int get_mdp_ver(struct platform_device
*pdev
)
261 struct device
*dev
= &pdev
->dev
;
263 return (int) (unsigned long) of_device_get_match_data(dev
);
266 #include <linux/of_address.h>
268 static int msm_init_vram(struct drm_device
*dev
)
270 struct msm_drm_private
*priv
= dev
->dev_private
;
271 struct device_node
*node
;
272 unsigned long size
= 0;
275 /* In the device-tree world, we could have a 'memory-region'
276 * phandle, which gives us a link to our "vram". Allocating
277 * is all nicely abstracted behind the dma api, but we need
278 * to know the entire size to allocate it all in one go. There
280 * 1) device with no IOMMU, in which case we need exclusive
281 * access to a VRAM carveout big enough for all gpu
283 * 2) device with IOMMU, but where the bootloader puts up
284 * a splash screen. In this case, the VRAM carveout
285 * need only be large enough for fbdev fb. But we need
286 * exclusive access to the buffer to avoid the kernel
287 * using those pages for other purposes (which appears
288 * as corruption on screen before we have a chance to
289 * load and do initial modeset)
292 node
= of_parse_phandle(dev
->dev
->of_node
, "memory-region", 0);
295 ret
= of_address_to_resource(node
, 0, &r
);
299 size
= r
.end
- r
.start
;
300 DRM_INFO("using VRAM carveout: %lx@%pa\n", size
, &r
.start
);
302 /* if we have no IOMMU, then we need to use carveout allocator.
303 * Grab the entire CMA chunk carved out in early startup in
306 } else if (!iommu_present(&platform_bus_type
)) {
307 DRM_INFO("using %s VRAM carveout\n", vram
);
308 size
= memparse(vram
, NULL
);
312 unsigned long attrs
= 0;
315 priv
->vram
.size
= size
;
317 drm_mm_init(&priv
->vram
.mm
, 0, (size
>> PAGE_SHIFT
) - 1);
319 attrs
|= DMA_ATTR_NO_KERNEL_MAPPING
;
320 attrs
|= DMA_ATTR_WRITE_COMBINE
;
322 /* note that for no-kernel-mapping, the vaddr returned
323 * is bogus, but non-null if allocation succeeded:
325 p
= dma_alloc_attrs(dev
->dev
, size
,
326 &priv
->vram
.paddr
, GFP_KERNEL
, attrs
);
328 dev_err(dev
->dev
, "failed to allocate VRAM\n");
329 priv
->vram
.paddr
= 0;
333 dev_info(dev
->dev
, "VRAM: %08x->%08x\n",
334 (uint32_t)priv
->vram
.paddr
,
335 (uint32_t)(priv
->vram
.paddr
+ size
));
341 static int msm_drm_init(struct device
*dev
, struct drm_driver
*drv
)
343 struct platform_device
*pdev
= to_platform_device(dev
);
344 struct drm_device
*ddev
;
345 struct msm_drm_private
*priv
;
349 ddev
= drm_dev_alloc(drv
, dev
);
351 dev_err(dev
, "failed to allocate drm_device\n");
355 platform_set_drvdata(pdev
, ddev
);
356 ddev
->platformdev
= pdev
;
358 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
364 ddev
->dev_private
= priv
;
367 ret
= msm_mdss_init(ddev
);
374 priv
->wq
= alloc_ordered_workqueue("msm", 0);
375 priv
->atomic_wq
= alloc_ordered_workqueue("msm:atomic", 0);
376 init_waitqueue_head(&priv
->pending_crtcs_event
);
378 INIT_LIST_HEAD(&priv
->inactive_list
);
379 INIT_LIST_HEAD(&priv
->vblank_ctrl
.event_list
);
380 INIT_WORK(&priv
->vblank_ctrl
.work
, vblank_ctrl_worker
);
381 spin_lock_init(&priv
->vblank_ctrl
.lock
);
383 drm_mode_config_init(ddev
);
385 /* Bind all our sub-components: */
386 ret
= component_bind_all(dev
, ddev
);
388 msm_mdss_destroy(ddev
);
394 ret
= msm_init_vram(ddev
);
398 msm_gem_shrinker_init(ddev
);
400 switch (get_mdp_ver(pdev
)) {
402 kms
= mdp4_kms_init(ddev
);
406 kms
= mdp5_kms_init(ddev
);
409 kms
= ERR_PTR(-ENODEV
);
415 * NOTE: once we have GPU support, having no kms should not
416 * be considered fatal.. ideally we would still support gpu
417 * and (for example) use dmabuf/prime to share buffers with
418 * imx drm driver on iMX5
420 dev_err(dev
, "failed to load kms\n");
426 ret
= kms
->funcs
->hw_init(kms
);
428 dev_err(dev
, "kms hw init failed: %d\n", ret
);
433 ddev
->mode_config
.funcs
= &mode_config_funcs
;
435 ret
= drm_vblank_init(ddev
, priv
->num_crtcs
);
437 dev_err(dev
, "failed to initialize vblank\n");
442 pm_runtime_get_sync(dev
);
443 ret
= drm_irq_install(ddev
, kms
->irq
);
444 pm_runtime_put_sync(dev
);
446 dev_err(dev
, "failed to install IRQ handler\n");
451 ret
= drm_dev_register(ddev
, 0);
455 drm_mode_config_reset(ddev
);
457 #ifdef CONFIG_DRM_FBDEV_EMULATION
459 priv
->fbdev
= msm_fbdev_init(ddev
);
462 ret
= msm_debugfs_late_init(ddev
);
466 drm_kms_helper_poll_init(ddev
);
479 static void load_gpu(struct drm_device
*dev
)
481 static DEFINE_MUTEX(init_lock
);
482 struct msm_drm_private
*priv
= dev
->dev_private
;
484 mutex_lock(&init_lock
);
487 priv
->gpu
= adreno_load_gpu(dev
);
489 mutex_unlock(&init_lock
);
492 static int msm_open(struct drm_device
*dev
, struct drm_file
*file
)
494 struct msm_file_private
*ctx
;
496 /* For now, load gpu on open.. to avoid the requirement of having
497 * firmware in the initrd.
501 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
505 file
->driver_priv
= ctx
;
510 static void msm_preclose(struct drm_device
*dev
, struct drm_file
*file
)
512 struct msm_drm_private
*priv
= dev
->dev_private
;
513 struct msm_file_private
*ctx
= file
->driver_priv
;
515 mutex_lock(&dev
->struct_mutex
);
516 if (ctx
== priv
->lastctx
)
517 priv
->lastctx
= NULL
;
518 mutex_unlock(&dev
->struct_mutex
);
523 static void msm_lastclose(struct drm_device
*dev
)
525 struct msm_drm_private
*priv
= dev
->dev_private
;
527 drm_fb_helper_restore_fbdev_mode_unlocked(priv
->fbdev
);
530 static irqreturn_t
msm_irq(int irq
, void *arg
)
532 struct drm_device
*dev
= arg
;
533 struct msm_drm_private
*priv
= dev
->dev_private
;
534 struct msm_kms
*kms
= priv
->kms
;
536 return kms
->funcs
->irq(kms
);
539 static void msm_irq_preinstall(struct drm_device
*dev
)
541 struct msm_drm_private
*priv
= dev
->dev_private
;
542 struct msm_kms
*kms
= priv
->kms
;
544 kms
->funcs
->irq_preinstall(kms
);
547 static int msm_irq_postinstall(struct drm_device
*dev
)
549 struct msm_drm_private
*priv
= dev
->dev_private
;
550 struct msm_kms
*kms
= priv
->kms
;
552 return kms
->funcs
->irq_postinstall(kms
);
555 static void msm_irq_uninstall(struct drm_device
*dev
)
557 struct msm_drm_private
*priv
= dev
->dev_private
;
558 struct msm_kms
*kms
= priv
->kms
;
560 kms
->funcs
->irq_uninstall(kms
);
563 static int msm_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
565 struct msm_drm_private
*priv
= dev
->dev_private
;
566 struct msm_kms
*kms
= priv
->kms
;
569 DBG("dev=%p, crtc=%u", dev
, pipe
);
570 return vblank_ctrl_queue_work(priv
, pipe
, true);
573 static void msm_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
575 struct msm_drm_private
*priv
= dev
->dev_private
;
576 struct msm_kms
*kms
= priv
->kms
;
579 DBG("dev=%p, crtc=%u", dev
, pipe
);
580 vblank_ctrl_queue_work(priv
, pipe
, false);
587 static int msm_ioctl_get_param(struct drm_device
*dev
, void *data
,
588 struct drm_file
*file
)
590 struct msm_drm_private
*priv
= dev
->dev_private
;
591 struct drm_msm_param
*args
= data
;
594 /* for now, we just have 3d pipe.. eventually this would need to
595 * be more clever to dispatch to appropriate gpu module:
597 if (args
->pipe
!= MSM_PIPE_3D0
)
605 return gpu
->funcs
->get_param(gpu
, args
->param
, &args
->value
);
608 static int msm_ioctl_gem_new(struct drm_device
*dev
, void *data
,
609 struct drm_file
*file
)
611 struct drm_msm_gem_new
*args
= data
;
613 if (args
->flags
& ~MSM_BO_FLAGS
) {
614 DRM_ERROR("invalid flags: %08x\n", args
->flags
);
618 return msm_gem_new_handle(dev
, file
, args
->size
,
619 args
->flags
, &args
->handle
);
622 static inline ktime_t
to_ktime(struct drm_msm_timespec timeout
)
624 return ktime_set(timeout
.tv_sec
, timeout
.tv_nsec
);
627 static int msm_ioctl_gem_cpu_prep(struct drm_device
*dev
, void *data
,
628 struct drm_file
*file
)
630 struct drm_msm_gem_cpu_prep
*args
= data
;
631 struct drm_gem_object
*obj
;
632 ktime_t timeout
= to_ktime(args
->timeout
);
635 if (args
->op
& ~MSM_PREP_FLAGS
) {
636 DRM_ERROR("invalid op: %08x\n", args
->op
);
640 obj
= drm_gem_object_lookup(file
, args
->handle
);
644 ret
= msm_gem_cpu_prep(obj
, args
->op
, &timeout
);
646 drm_gem_object_unreference_unlocked(obj
);
651 static int msm_ioctl_gem_cpu_fini(struct drm_device
*dev
, void *data
,
652 struct drm_file
*file
)
654 struct drm_msm_gem_cpu_fini
*args
= data
;
655 struct drm_gem_object
*obj
;
658 obj
= drm_gem_object_lookup(file
, args
->handle
);
662 ret
= msm_gem_cpu_fini(obj
);
664 drm_gem_object_unreference_unlocked(obj
);
669 static int msm_ioctl_gem_info(struct drm_device
*dev
, void *data
,
670 struct drm_file
*file
)
672 struct drm_msm_gem_info
*args
= data
;
673 struct drm_gem_object
*obj
;
679 obj
= drm_gem_object_lookup(file
, args
->handle
);
683 args
->offset
= msm_gem_mmap_offset(obj
);
685 drm_gem_object_unreference_unlocked(obj
);
690 static int msm_ioctl_wait_fence(struct drm_device
*dev
, void *data
,
691 struct drm_file
*file
)
693 struct msm_drm_private
*priv
= dev
->dev_private
;
694 struct drm_msm_wait_fence
*args
= data
;
695 ktime_t timeout
= to_ktime(args
->timeout
);
698 DRM_ERROR("invalid pad: %08x\n", args
->pad
);
705 return msm_wait_fence(priv
->gpu
->fctx
, args
->fence
, &timeout
, true);
708 static int msm_ioctl_gem_madvise(struct drm_device
*dev
, void *data
,
709 struct drm_file
*file
)
711 struct drm_msm_gem_madvise
*args
= data
;
712 struct drm_gem_object
*obj
;
715 switch (args
->madv
) {
716 case MSM_MADV_DONTNEED
:
717 case MSM_MADV_WILLNEED
:
723 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
727 obj
= drm_gem_object_lookup(file
, args
->handle
);
733 ret
= msm_gem_madvise(obj
, args
->madv
);
735 args
->retained
= ret
;
739 drm_gem_object_unreference(obj
);
742 mutex_unlock(&dev
->struct_mutex
);
746 static const struct drm_ioctl_desc msm_ioctls
[] = {
747 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM
, msm_ioctl_get_param
, DRM_AUTH
|DRM_RENDER_ALLOW
),
748 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW
, msm_ioctl_gem_new
, DRM_AUTH
|DRM_RENDER_ALLOW
),
749 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO
, msm_ioctl_gem_info
, DRM_AUTH
|DRM_RENDER_ALLOW
),
750 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP
, msm_ioctl_gem_cpu_prep
, DRM_AUTH
|DRM_RENDER_ALLOW
),
751 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI
, msm_ioctl_gem_cpu_fini
, DRM_AUTH
|DRM_RENDER_ALLOW
),
752 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT
, msm_ioctl_gem_submit
, DRM_AUTH
|DRM_RENDER_ALLOW
),
753 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE
, msm_ioctl_wait_fence
, DRM_AUTH
|DRM_RENDER_ALLOW
),
754 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE
, msm_ioctl_gem_madvise
, DRM_AUTH
|DRM_RENDER_ALLOW
),
757 static const struct vm_operations_struct vm_ops
= {
758 .fault
= msm_gem_fault
,
759 .open
= drm_gem_vm_open
,
760 .close
= drm_gem_vm_close
,
763 static const struct file_operations fops
= {
764 .owner
= THIS_MODULE
,
766 .release
= drm_release
,
767 .unlocked_ioctl
= drm_ioctl
,
769 .compat_ioctl
= drm_compat_ioctl
,
774 .mmap
= msm_gem_mmap
,
777 static struct drm_driver msm_driver
= {
778 .driver_features
= DRIVER_HAVE_IRQ
|
785 .preclose
= msm_preclose
,
786 .lastclose
= msm_lastclose
,
787 .irq_handler
= msm_irq
,
788 .irq_preinstall
= msm_irq_preinstall
,
789 .irq_postinstall
= msm_irq_postinstall
,
790 .irq_uninstall
= msm_irq_uninstall
,
791 .get_vblank_counter
= drm_vblank_no_hw_counter
,
792 .enable_vblank
= msm_enable_vblank
,
793 .disable_vblank
= msm_disable_vblank
,
794 .gem_free_object
= msm_gem_free_object
,
795 .gem_vm_ops
= &vm_ops
,
796 .dumb_create
= msm_gem_dumb_create
,
797 .dumb_map_offset
= msm_gem_dumb_map_offset
,
798 .dumb_destroy
= drm_gem_dumb_destroy
,
799 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
800 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
801 .gem_prime_export
= drm_gem_prime_export
,
802 .gem_prime_import
= drm_gem_prime_import
,
803 .gem_prime_pin
= msm_gem_prime_pin
,
804 .gem_prime_unpin
= msm_gem_prime_unpin
,
805 .gem_prime_get_sg_table
= msm_gem_prime_get_sg_table
,
806 .gem_prime_import_sg_table
= msm_gem_prime_import_sg_table
,
807 .gem_prime_vmap
= msm_gem_prime_vmap
,
808 .gem_prime_vunmap
= msm_gem_prime_vunmap
,
809 .gem_prime_mmap
= msm_gem_prime_mmap
,
810 #ifdef CONFIG_DEBUG_FS
811 .debugfs_init
= msm_debugfs_init
,
812 .debugfs_cleanup
= msm_debugfs_cleanup
,
814 .ioctls
= msm_ioctls
,
815 .num_ioctls
= DRM_MSM_NUM_IOCTLS
,
818 .desc
= "MSM Snapdragon DRM",
820 .major
= MSM_VERSION_MAJOR
,
821 .minor
= MSM_VERSION_MINOR
,
822 .patchlevel
= MSM_VERSION_PATCHLEVEL
,
825 #ifdef CONFIG_PM_SLEEP
826 static int msm_pm_suspend(struct device
*dev
)
828 struct drm_device
*ddev
= dev_get_drvdata(dev
);
830 drm_kms_helper_poll_disable(ddev
);
835 static int msm_pm_resume(struct device
*dev
)
837 struct drm_device
*ddev
= dev_get_drvdata(dev
);
839 drm_kms_helper_poll_enable(ddev
);
845 static const struct dev_pm_ops msm_pm_ops
= {
846 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend
, msm_pm_resume
)
850 * Componentized driver support:
854 * NOTE: duplication of the same code as exynos or imx (or probably any other).
855 * so probably some room for some helpers
857 static int compare_of(struct device
*dev
, void *data
)
859 return dev
->of_node
== data
;
863 * Identify what components need to be added by parsing what remote-endpoints
864 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
865 * is no external component that we need to add since LVDS is within MDP4
868 static int add_components_mdp(struct device
*mdp_dev
,
869 struct component_match
**matchptr
)
871 struct device_node
*np
= mdp_dev
->of_node
;
872 struct device_node
*ep_node
;
873 struct device
*master_dev
;
876 * on MDP4 based platforms, the MDP platform device is the component
877 * master that adds other display interface components to itself.
879 * on MDP5 based platforms, the MDSS platform device is the component
880 * master that adds MDP5 and other display interface components to
883 if (of_device_is_compatible(np
, "qcom,mdp4"))
884 master_dev
= mdp_dev
;
886 master_dev
= mdp_dev
->parent
;
888 for_each_endpoint_of_node(np
, ep_node
) {
889 struct device_node
*intf
;
890 struct of_endpoint ep
;
893 ret
= of_graph_parse_endpoint(ep_node
, &ep
);
895 dev_err(mdp_dev
, "unable to parse port endpoint\n");
896 of_node_put(ep_node
);
901 * The LCDC/LVDS port on MDP4 is a speacial case where the
902 * remote-endpoint isn't a component that we need to add
904 if (of_device_is_compatible(np
, "qcom,mdp4") &&
906 of_node_put(ep_node
);
911 * It's okay if some of the ports don't have a remote endpoint
912 * specified. It just means that the port isn't connected to
913 * any external interface.
915 intf
= of_graph_get_remote_port_parent(ep_node
);
917 of_node_put(ep_node
);
921 component_match_add(master_dev
, matchptr
, compare_of
, intf
);
924 of_node_put(ep_node
);
930 static int compare_name_mdp(struct device
*dev
, void *data
)
932 return (strstr(dev_name(dev
), "mdp") != NULL
);
935 static int add_display_components(struct device
*dev
,
936 struct component_match
**matchptr
)
938 struct device
*mdp_dev
;
942 * MDP5 based devices don't have a flat hierarchy. There is a top level
943 * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the
944 * children devices, find the MDP5 node, and then add the interfaces
945 * to our components list.
947 if (of_device_is_compatible(dev
->of_node
, "qcom,mdss")) {
948 ret
= of_platform_populate(dev
->of_node
, NULL
, NULL
, dev
);
950 dev_err(dev
, "failed to populate children devices\n");
954 mdp_dev
= device_find_child(dev
, NULL
, compare_name_mdp
);
956 dev_err(dev
, "failed to find MDSS MDP node\n");
957 of_platform_depopulate(dev
);
963 /* add the MDP component itself */
964 component_match_add(dev
, matchptr
, compare_of
,
971 ret
= add_components_mdp(mdp_dev
, matchptr
);
973 of_platform_depopulate(dev
);
979 * We don't know what's the best binding to link the gpu with the drm device.
980 * Fow now, we just hunt for all the possible gpus that we support, and add them
983 static const struct of_device_id msm_gpu_match
[] = {
984 { .compatible
= "qcom,adreno-3xx" },
985 { .compatible
= "qcom,kgsl-3d0" },
989 static int add_gpu_components(struct device
*dev
,
990 struct component_match
**matchptr
)
992 struct device_node
*np
;
994 np
= of_find_matching_node(NULL
, msm_gpu_match
);
998 component_match_add(dev
, matchptr
, compare_of
, np
);
1005 static int msm_drm_bind(struct device
*dev
)
1007 return msm_drm_init(dev
, &msm_driver
);
1010 static void msm_drm_unbind(struct device
*dev
)
1012 msm_drm_uninit(dev
);
1015 static const struct component_master_ops msm_drm_ops
= {
1016 .bind
= msm_drm_bind
,
1017 .unbind
= msm_drm_unbind
,
1024 static int msm_pdev_probe(struct platform_device
*pdev
)
1026 struct component_match
*match
= NULL
;
1029 ret
= add_display_components(&pdev
->dev
, &match
);
1033 ret
= add_gpu_components(&pdev
->dev
, &match
);
1037 pdev
->dev
.coherent_dma_mask
= DMA_BIT_MASK(32);
1038 return component_master_add_with_match(&pdev
->dev
, &msm_drm_ops
, match
);
1041 static int msm_pdev_remove(struct platform_device
*pdev
)
1043 component_master_del(&pdev
->dev
, &msm_drm_ops
);
1044 of_platform_depopulate(&pdev
->dev
);
1049 static const struct of_device_id dt_match
[] = {
1050 { .compatible
= "qcom,mdp4", .data
= (void *)4 }, /* MDP4 */
1051 { .compatible
= "qcom,mdss", .data
= (void *)5 }, /* MDP5 MDSS */
1054 MODULE_DEVICE_TABLE(of
, dt_match
);
1056 static struct platform_driver msm_platform_driver
= {
1057 .probe
= msm_pdev_probe
,
1058 .remove
= msm_pdev_remove
,
1061 .of_match_table
= dt_match
,
1066 static int __init
msm_drm_register(void)
1072 msm_hdmi_register();
1074 return platform_driver_register(&msm_platform_driver
);
1077 static void __exit
msm_drm_unregister(void)
1080 platform_driver_unregister(&msm_platform_driver
);
1081 msm_hdmi_unregister();
1082 adreno_unregister();
1083 msm_edp_unregister();
1084 msm_dsi_unregister();
1085 msm_mdp_unregister();
1088 module_init(msm_drm_register
);
1089 module_exit(msm_drm_unregister
);
1091 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1092 MODULE_DESCRIPTION("MSM DRM Driver");
1093 MODULE_LICENSE("GPL");