drivers/gpu/drm/nouveau/core/engine/disp/nv04.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <engine/disp.h>
  26
  27 #include <core/event.h>
  28 #include <core/class.h>
  29
  30 struct nv04_disp_priv {
  31         struct nouveau_disp base;
  32 };
  33
  34 static int
  35 nv04_disp_scanoutpos(struct nouveau_object *object, u32 mthd,
  36                      void *data, u32 size)
  37 {
  38         struct nv04_disp_priv *priv = (void *)object->engine;
  39         struct nv04_display_scanoutpos *args = data;
  40         const int head = (mthd & NV04_DISP_MTHD_HEAD);
  41         u32 line;
  42
  43         if (size < sizeof(*args))
  44                 return -EINVAL;
  45
  46         args->vblanks = nv_rd32(priv, 0x680800 + (head * 0x2000)) & 0xffff;
  47         args->vtotal  = nv_rd32(priv, 0x680804 + (head * 0x2000)) & 0xffff;
  48         args->vblanke = args->vtotal - 1;
  49
  50         args->hblanks = nv_rd32(priv, 0x680820 + (head * 0x2000)) & 0xffff;
  51         args->htotal  = nv_rd32(priv, 0x680824 + (head * 0x2000)) & 0xffff;
  52         args->hblanke = args->htotal - 1;
  53
  54         args->time[0] = ktime_to_ns(ktime_get());
  55         line = nv_rd32(priv, 0x600868 + (head * 0x2000));
  56         args->time[1] = ktime_to_ns(ktime_get());
  57         args->hline = (line & 0xffff0000) >> 16;
  58         args->vline = (line & 0x0000ffff);
  59         return 0;
  60 }
  61
  62 #define HEAD_MTHD(n) (n), (n) + 0x01
  63
  64 static struct nouveau_omthds
  65 nv04_disp_omthds[] = {
  66         { HEAD_MTHD(NV04_DISP_SCANOUTPOS), nv04_disp_scanoutpos },
  67         {}
  68 };
  69
  70 static struct nouveau_oclass
  71 nv04_disp_sclass[] = {
  72         { NV04_DISP_CLASS, &nouveau_object_ofuncs, nv04_disp_omthds },
  73         {},
  74 };
  75
  76 /*******************************************************************************
  77  * Display engine implementation
  78  ******************************************************************************/
  79
  80 static void
  81 nv04_disp_vblank_enable(struct nouveau_event *event, int head)
  82 {
  83         nv_wr32(event->priv, 0x600140 + (head * 0x2000) , 0x00000001);
  84 }
  85
  86 static void
  87 nv04_disp_vblank_disable(struct nouveau_event *event, int head)
  88 {
  89         nv_wr32(event->priv, 0x600140 + (head * 0x2000) , 0x00000000);
  90 }
  91
  92 static void
  93 nv04_disp_intr(struct nouveau_subdev *subdev)
  94 {
  95         struct nv04_disp_priv *priv = (void *)subdev;
  96         u32 crtc0 = nv_rd32(priv, 0x600100);
  97         u32 crtc1 = nv_rd32(priv, 0x602100);
  98         u32 pvideo;
  99
 100         if (crtc0 & 0x00000001) {
 101                 nouveau_event_trigger(priv->base.vblank, 0);
 102                 nv_wr32(priv, 0x600100, 0x00000001);
 103         }
 104
 105         if (crtc1 & 0x00000001) {
 106                 nouveau_event_trigger(priv->base.vblank, 1);
 107                 nv_wr32(priv, 0x602100, 0x00000001);
 108         }
 109
 110         if (nv_device(priv)->chipset >= 0x10 &&
 111             nv_device(priv)->chipset <= 0x40) {
 112                 pvideo = nv_rd32(priv, 0x8100);
 113                 if (pvideo & ~0x11)
 114                         nv_info(priv, "PVIDEO intr: %08x\n", pvideo);
 115                 nv_wr32(priv, 0x8100, pvideo);
 116         }
 117 }
 118
 119 static int
 120 nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 121                struct nouveau_oclass *oclass, void *data, u32 size,
 122                struct nouveau_object **pobject)
 123 {
 124         struct nv04_disp_priv *priv;
 125         int ret;
 126
 127         ret = nouveau_disp_create(parent, engine, oclass, 2, "DISPLAY",
 128                                   "display", &priv);
 129         *pobject = nv_object(priv);
 130         if (ret)
 131                 return ret;
 132
 133         nv_engine(priv)->sclass = nv04_disp_sclass;
 134         nv_subdev(priv)->intr = nv04_disp_intr;
 135         priv->base.vblank->priv = priv;
 136         priv->base.vblank->enable = nv04_disp_vblank_enable;
 137         priv->base.vblank->disable = nv04_disp_vblank_disable;
 138         return 0;
 139 }
 140
 141 struct nouveau_oclass
 142 nv04_disp_oclass = {
 143         .handle = NV_ENGINE(DISP, 0x04),
 144         .ofuncs = &(struct nouveau_ofuncs) {
 145                 .ctor = nv04_disp_ctor,
 146                 .dtor = _nouveau_disp_dtor,
 147                 .init = _nouveau_disp_init,
 148                 .fini = _nouveau_disp_fini,
 149         },
 150 };