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git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/bar.h>
27 #include <engine/software.h>
28 #include <engine/disp.h>
30 struct nv50_disp_priv
{
31 struct nouveau_disp base
;
34 static struct nouveau_oclass
35 nv50_disp_sclass
[] = {
40 nv50_disp_intr_vblank(struct nv50_disp_priv
*priv
, int crtc
)
42 struct nouveau_bar
*bar
= nouveau_bar(priv
);
43 struct nouveau_disp
*disp
= &priv
->base
;
44 struct nouveau_software_chan
*chan
, *temp
;
47 spin_lock_irqsave(&disp
->vblank
.lock
, flags
);
48 list_for_each_entry_safe(chan
, temp
, &disp
->vblank
.list
, vblank
.head
) {
49 if (chan
->vblank
.crtc
!= crtc
)
52 if (nv_device(priv
)->chipset
== 0x50) {
53 nv_wr32(priv
, 0x001704, chan
->vblank
.channel
);
54 nv_wr32(priv
, 0x001710, 0x80000000 | chan
->vblank
.ctxdma
);
56 nv_wr32(priv
, 0x001570, chan
->vblank
.offset
);
57 nv_wr32(priv
, 0x001574, chan
->vblank
.value
);
59 nv_wr32(priv
, 0x001718, 0x80000000 | chan
->vblank
.channel
);
61 nv_wr32(priv
, 0x06000c,
62 upper_32_bits(chan
->vblank
.offset
));
63 nv_wr32(priv
, 0x060010,
64 lower_32_bits(chan
->vblank
.offset
));
65 nv_wr32(priv
, 0x060014, chan
->vblank
.value
);
68 list_del(&chan
->vblank
.head
);
70 disp
->vblank
.put(disp
->vblank
.data
, crtc
);
72 spin_unlock_irqrestore(&disp
->vblank
.lock
, flags
);
74 if (disp
->vblank
.notify
)
75 disp
->vblank
.notify(disp
->vblank
.data
, crtc
);
79 nv50_disp_intr(struct nouveau_subdev
*subdev
)
81 struct nv50_disp_priv
*priv
= (void *)subdev
;
82 u32 stat1
= nv_rd32(priv
, 0x610024);
84 if (stat1
& 0x00000004) {
85 nv50_disp_intr_vblank(priv
, 0);
86 nv_wr32(priv
, 0x610024, 0x00000004);
90 if (stat1
& 0x00000008) {
91 nv50_disp_intr_vblank(priv
, 1);
92 nv_wr32(priv
, 0x610024, 0x00000008);
99 nv50_disp_ctor(struct nouveau_object
*parent
, struct nouveau_object
*engine
,
100 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
101 struct nouveau_object
**pobject
)
103 struct nv50_disp_priv
*priv
;
106 ret
= nouveau_disp_create(parent
, engine
, oclass
, "PDISP",
108 *pobject
= nv_object(priv
);
112 nv_engine(priv
)->sclass
= nv50_disp_sclass
;
113 nv_subdev(priv
)->intr
= nv50_disp_intr
;
115 INIT_LIST_HEAD(&priv
->base
.vblank
.list
);
116 spin_lock_init(&priv
->base
.vblank
.lock
);
120 struct nouveau_oclass
122 .handle
= NV_ENGINE(DISP
, 0x50),
123 .ofuncs
= &(struct nouveau_ofuncs
) {
124 .ctor
= nv50_disp_ctor
,
125 .dtor
= _nouveau_disp_dtor
,
126 .init
= _nouveau_disp_init
,
127 .fini
= _nouveau_disp_fini
,