drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <engine/software.h>
  26 #include <engine/disp.h>
  27
  28 #include <core/class.h>
  29
  30 #include "nv50.h"
  31
  32 /*******************************************************************************
  33  * Base display object
  34  ******************************************************************************/
  35
  36 static struct nouveau_oclass
  37 nvf0_disp_sclass[] = {
  38         { NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base },
  39         { NVF0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base },
  40         { NVF0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base },
  41         { NVF0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base },
  42         { NVF0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base },
  43         {}
  44 };
  45
  46 static struct nouveau_oclass
  47 nvf0_disp_base_oclass[] = {
  48         { NVF0_DISP_CLASS, &nvd0_disp_base_ofuncs },
  49         {}
  50 };
  51
  52 /*******************************************************************************
  53  * Display engine implementation
  54  ******************************************************************************/
  55
  56 static int
  57 nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  58                struct nouveau_oclass *oclass, void *data, u32 size,
  59                struct nouveau_object **pobject)
  60 {
  61         struct nv50_disp_priv *priv;
  62         int heads = nv_rd32(parent, 0x022448);
  63         int ret;
  64
  65         ret = nouveau_disp_create(parent, engine, oclass, heads,
  66                                   "PDISP", "display", &priv);
  67         *pobject = nv_object(priv);
  68         if (ret)
  69                 return ret;
  70
  71         nv_engine(priv)->sclass = nvf0_disp_base_oclass;
  72         nv_engine(priv)->cclass = &nv50_disp_cclass;
  73         nv_subdev(priv)->intr = nvd0_disp_intr;
  74         INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
  75         priv->sclass = nvf0_disp_sclass;
  76         priv->head.nr = heads;
  77         priv->dac.nr = 3;
  78         priv->sor.nr = 4;
  79         priv->dac.power = nv50_dac_power;
  80         priv->dac.sense = nv50_dac_sense;
  81         priv->sor.power = nv50_sor_power;
  82         priv->sor.hda_eld = nvd0_hda_eld;
  83         priv->sor.hdmi = nvd0_hdmi_ctrl;
  84         return 0;
  85 }
  86
  87 struct nouveau_oclass *
  88 nvf0_disp_oclass = &(struct nv50_disp_impl) {
  89         .base.base.handle = NV_ENGINE(DISP, 0x92),
  90         .base.base.ofuncs = &(struct nouveau_ofuncs) {
  91                 .ctor = nvf0_disp_ctor,
  92                 .dtor = _nouveau_disp_dtor,
  93                 .init = _nouveau_disp_init,
  94                 .fini = _nouveau_disp_fini,
  95         },
  96         .base.vblank = &nvd0_disp_vblank_func,
  97         .base.outp =  nvd0_disp_outp_sclass,
  98         .mthd.core = &nve0_disp_mast_mthd_chan,
  99         .mthd.base = &nvd0_disp_sync_mthd_chan,
 100         .mthd.ovly = &nve0_disp_ovly_mthd_chan,
 101         .mthd.prev = -0x020000,
 102         .head.scanoutpos = nvd0_disp_base_scanoutpos,
 103 }.base.base;