drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <nvif/unpack.h>
  27 #include <nvif/class.h>
  28 #include <core/engctx.h>
  29 #include <core/ramht.h>
  30
  31 #include <subdev/instmem.h>
  32 #include <subdev/instmem/nv04.h>
  33 #include <subdev/fb.h>
  34
  35 #include <engine/fifo.h>
  36
  37 #include "nv04.h"
  38
  39 static struct ramfc_desc
  40 nv17_ramfc[] = {
  41         { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
  42         { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
  43         { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
  44         { 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
  45         { 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
  46         { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
  47         { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
  48         { 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
  49         { 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
  50         { 32,  0, 0x20,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
  51         { 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
  52         { 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
  53         { 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
  54         { 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
  55         {}
  56 };
  57
  58 /*******************************************************************************
  59  * FIFO channel objects
  60  ******************************************************************************/
  61
  62 static int
  63 nv17_fifo_chan_ctor(struct nouveau_object *parent,
  64                     struct nouveau_object *engine,
  65                     struct nouveau_oclass *oclass, void *data, u32 size,
  66                     struct nouveau_object **pobject)
  67 {
  68         union {
  69                 struct nv03_channel_dma_v0 v0;
  70         } *args = data;
  71         struct nv04_fifo_priv *priv = (void *)engine;
  72         struct nv04_fifo_chan *chan;
  73         int ret;
  74
  75         nv_ioctl(parent, "create channel dma size %d\n", size);
  76         if (nvif_unpack(args->v0, 0, 0, false)) {
  77                 nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
  78                                  "offset %016llx\n", args->v0.version,
  79                          args->v0.pushbuf, args->v0.offset);
  80         } else
  81                 return ret;
  82
  83         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000,
  84                                           0x10000, args->v0.pushbuf,
  85                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
  86                                           (1ULL << NVDEV_ENGINE_SW) |
  87                                           (1ULL << NVDEV_ENGINE_GR) |
  88                                           (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */
  89                                           &chan);
  90         *pobject = nv_object(chan);
  91         if (ret)
  92                 return ret;
  93
  94         args->v0.chid = chan->base.chid;
  95
  96         nv_parent(chan)->object_attach = nv04_fifo_object_attach;
  97         nv_parent(chan)->object_detach = nv04_fifo_object_detach;
  98         nv_parent(chan)->context_attach = nv04_fifo_context_attach;
  99         chan->ramfc = chan->base.chid * 64;
 100
 101         nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset);
 102         nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);
 103         nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
 104         nv_wo32(priv->ramfc, chan->ramfc + 0x14,
 105                              NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 106                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 107 #ifdef __BIG_ENDIAN
 108                              NV_PFIFO_CACHE1_BIG_ENDIAN |
 109 #endif
 110                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
 111         return 0;
 112 }
 113
 114 static struct nouveau_ofuncs
 115 nv17_fifo_ofuncs = {
 116         .ctor = nv17_fifo_chan_ctor,
 117         .dtor = nv04_fifo_chan_dtor,
 118         .init = nv04_fifo_chan_init,
 119         .fini = nv04_fifo_chan_fini,
 120         .rd32 = _nouveau_fifo_channel_rd32,
 121         .wr32 = _nouveau_fifo_channel_wr32,
 122 };
 123
 124 static struct nouveau_oclass
 125 nv17_fifo_sclass[] = {
 126         { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs },
 127         {}
 128 };
 129
 130 /*******************************************************************************
 131  * FIFO context - basically just the instmem reserved for the channel
 132  ******************************************************************************/
 133
 134 static struct nouveau_oclass
 135 nv17_fifo_cclass = {
 136         .handle = NV_ENGCTX(FIFO, 0x17),
 137         .ofuncs = &(struct nouveau_ofuncs) {
 138                 .ctor = nv04_fifo_context_ctor,
 139                 .dtor = _nouveau_fifo_context_dtor,
 140                 .init = _nouveau_fifo_context_init,
 141                 .fini = _nouveau_fifo_context_fini,
 142                 .rd32 = _nouveau_fifo_context_rd32,
 143                 .wr32 = _nouveau_fifo_context_wr32,
 144         },
 145 };
 146
 147 /*******************************************************************************
 148  * PFIFO engine
 149  ******************************************************************************/
 150
 151 static int
 152 nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 153                struct nouveau_oclass *oclass, void *data, u32 size,
 154                struct nouveau_object **pobject)
 155 {
 156         struct nv04_instmem_priv *imem = nv04_instmem(parent);
 157         struct nv04_fifo_priv *priv;
 158         int ret;
 159
 160         ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
 161         *pobject = nv_object(priv);
 162         if (ret)
 163                 return ret;
 164
 165         nouveau_ramht_ref(imem->ramht, &priv->ramht);
 166         nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
 167         nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
 168
 169         nv_subdev(priv)->unit = 0x00000100;
 170         nv_subdev(priv)->intr = nv04_fifo_intr;
 171         nv_engine(priv)->cclass = &nv17_fifo_cclass;
 172         nv_engine(priv)->sclass = nv17_fifo_sclass;
 173         priv->base.pause = nv04_fifo_pause;
 174         priv->base.start = nv04_fifo_start;
 175         priv->ramfc_desc = nv17_ramfc;
 176         return 0;
 177 }
 178
 179 static int
 180 nv17_fifo_init(struct nouveau_object *object)
 181 {
 182         struct nv04_fifo_priv *priv = (void *)object;
 183         int ret;
 184
 185         ret = nouveau_fifo_init(&priv->base);
 186         if (ret)
 187                 return ret;
 188
 189         nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff);
 190         nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
 191
 192         nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 193                                        ((priv->ramht->bits - 9) << 16) |
 194                                         (priv->ramht->base.addr >> 8));
 195         nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
 196         nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000);
 197
 198         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
 199
 200         nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
 201         nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);
 202
 203         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
 204         nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
 205         nv_wr32(priv, NV03_PFIFO_CACHES, 1);
 206         return 0;
 207 }
 208
 209 struct nouveau_oclass *
 210 nv17_fifo_oclass = &(struct nouveau_oclass) {
 211         .handle = NV_ENGINE(FIFO, 0x17),
 212         .ofuncs = &(struct nouveau_ofuncs) {
 213                 .ctor = nv17_fifo_ctor,
 214                 .dtor = nv04_fifo_dtor,
 215                 .init = nv17_fifo_init,
 216                 .fini = _nouveau_fifo_fini,
 217         },
 218 };