1 /* fuc microcode for nvc0 PGRAPH/GPC
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27 * - bracket certain functions with scratch writes, useful for debugging
28 * - watchdog timer around ctx operations
33 gpc_mmio_list_head: .b32 0
34 gpc_mmio_list_tail: .b32 0
38 tpc_mmio_list_head: .b32 0
39 tpc_mmio_list_tail: .b32 0
45 // reports an exception to the host
47 // In: $r15 error code (see nvc0.fuc)
51 mov $r14 -0x67ec // 0x9814
53 call #nv_wr32 // HUB_CTXCTL_CC_SCRATCH[5] = error code
56 call #nv_wr32 // HUB_CTXCTL_INTR_UP_SET
60 // GPC fuc initialisation, executed by triggering ucode start, will
61 // fall through to main loop after completion.
64 // CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
65 // CC_SCRATCH[1]: context base
69 // 31:31: set to signal completion
71 // 31:0: GPC context size
80 iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
82 // setup i0 handler, and route all interrupts to it
86 iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
88 // enable fifo interrupt
90 iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
95 // figure out which GPC we are, and how many TPCs we have
98 iord $r2 I[$r1 + 0x000] // UNITS
103 st b32 D[$r0 + #tpc_count] $r2
104 st b32 D[$r0 + #tpc_mask] $r3
106 iord $r2 I[$r1 + 0x000] // MYINDEX
107 st b32 D[$r0 + #gpc_id] $r2
109 // find context data for this chipset
112 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
113 mov $r1 #chipsets - 12
116 ld b32 $r3 D[$r1 + 0x00]
120 bra ne #init_find_chipset
124 // initialise context base, and size tracking
128 iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
129 clear b32 $r3 // track GPC context size here
131 // set mmctx base addresses now so we don't have to do it later,
132 // they don't currently ever change
136 iowr I[$r4 + 0x000] $r5 // MMCTX_SAVE_SWBASE
137 iowr I[$r4 + 0x100] $r5 // MMCTX_LOAD_SWBASE
139 // calculate GPC mmio context size, store the chipset-specific
140 // mmio list pointers somewhere we can get at them later without
141 // re-parsing the chipset list
144 ld b16 $r14 D[$r1 + 4]
145 ld b16 $r15 D[$r1 + 6]
146 st b16 D[$r0 + #gpc_mmio_list_head] $r14
147 st b16 D[$r0 + #gpc_mmio_list_tail] $r15
152 // calculate per-TPC mmio context size, store the list pointers
153 ld b16 $r14 D[$r1 + 8]
154 ld b16 $r15 D[$r1 + 10]
155 st b16 D[$r0 + #tpc_mmio_list_head] $r14
156 st b16 D[$r0 + #tpc_mmio_list_tail] $r15
158 ld b32 $r14 D[$r0 + #tpc_count]
163 // round up base/size to 256 byte boundary (for strand SWBASE)
166 iowr I[$r4 + 0x000] $r3 // MMCTX_LOAD_COUNT, wtf for?!?
174 // calculate size of strand context data
176 call #strand_ctx_init
179 // save context size, and tell HUB we're done
182 iowr I[$r1 + 0x100] $r3 // CC_SCRATCH[1] = context size
186 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
188 // Main program loop, very simple, sleeps until woken up by the interrupt
189 // handler, pulls a command from the queue and executes its handler
198 // 0x0000-0x0003 are all context transfers
200 bra nc #main_not_ctx_xfer
201 // fetch $flags and mask off $p1/$p2
206 // set $p1/$p2 according to transfer type
210 // transfer context data
216 or $r15 E_BAD_COMMAND
232 // incoming fifo command?
233 iord $r10 I[$r0 + 0x200] // INTR
234 and $r11 $r10 0x00000004
236 // queue incoming fifo command for later processing
239 iord $r14 I[$r11 + 0x100] // FIFO_CMD
240 iord $r15 I[$r11 + 0x000] // FIFO_DATA
244 iowr I[$r11 + 0x000] $r14 // FIFO_ACK
246 // ack, and wake up main()
248 iowr I[$r0 + 0x100] $r10 // INTR_ACK
262 // Set this GPC's bit in HUB_BAR, used to signal completion of various
263 // activities to the HUB fuc
267 ld b32 $r14 D[$r0 + #gpc_id]
269 mov $r14 -0x6be8 // 0x409418 - HUB_BAR_SET
274 // Disables various things, waits a bit, and re-enables them..
276 // Not sure how exactly this helps, perhaps "ENABLE" is not such a
277 // good description for the bits we turn off? Anyways, without this,
278 // funny things happen.
284 iowr I[$r14] $r15 // GPC_RED_SWITCH = POWER
288 bra ne #ctx_redswitch_delay
290 iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER
293 // Transfer GPC context data between GPU and storage area
295 // In: $r15 context base address
296 // $p1 clear on save, set on load
297 // $p2 set if opposite direction done/will be done, so:
298 // on save it means: "a load will follow this save"
299 // on load it means: "a save preceeded this load"
302 // set context base address
305 iowr I[$r1 + 0x000] $r15// MEM_BASE
306 bra not $p1 #ctx_xfer_not_load
314 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
318 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
321 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
324 xbit $r10 $flags $p1 // direction
328 ld b32 $r12 D[$r0 + #gpc_id]
330 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn
331 ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
332 ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
333 mov $r14 0 // not multi
336 // per-TPC mmio context
337 xbit $r10 $flags $p1 // direction
340 sethi $r11 0x500000 // base = NV_PGRAPH_GPC0_TPC0
341 ld b32 $r12 D[$r0 + #gpc_id]
343 add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0
344 ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
345 ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
346 ld b32 $r15 D[$r0 + #tpc_mask]
347 mov $r14 0x800 // stride = 0x800
350 // wait for strands to finish
353 // if load, or a save without a load following, do some
354 // unknown stuff that's done after finishing a block of
356 bra $p1 #ctx_xfer_post
357 bra not $p2 #ctx_xfer_done
362 iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0d
365 // mark completion in HUB's barrier
367 call #hub_barrier_done