1 #include <core/client.h>
3 #include <core/engctx.h>
4 #include <core/handle.h>
7 #include <subdev/timer.h>
10 #include <engine/graph.h>
11 #include <engine/fifo.h>
16 /*******************************************************************************
17 * Graphics object classes
18 ******************************************************************************/
20 static struct nouveau_oclass
21 nv20_graph_sclass
[] = {
22 { 0x0012, &nv04_graph_ofuncs
, NULL
}, /* beta1 */
23 { 0x0019, &nv04_graph_ofuncs
, NULL
}, /* clip */
24 { 0x0030, &nv04_graph_ofuncs
, NULL
}, /* null */
25 { 0x0039, &nv04_graph_ofuncs
, NULL
}, /* m2mf */
26 { 0x0043, &nv04_graph_ofuncs
, NULL
}, /* rop */
27 { 0x0044, &nv04_graph_ofuncs
, NULL
}, /* patt */
28 { 0x004a, &nv04_graph_ofuncs
, NULL
}, /* gdi */
29 { 0x0062, &nv04_graph_ofuncs
, NULL
}, /* surf2d */
30 { 0x0072, &nv04_graph_ofuncs
, NULL
}, /* beta4 */
31 { 0x0089, &nv04_graph_ofuncs
, NULL
}, /* sifm */
32 { 0x008a, &nv04_graph_ofuncs
, NULL
}, /* ifc */
33 { 0x0096, &nv04_graph_ofuncs
, NULL
}, /* celcius */
34 { 0x0097, &nv04_graph_ofuncs
, NULL
}, /* kelvin */
35 { 0x009e, &nv04_graph_ofuncs
, NULL
}, /* swzsurf */
36 { 0x009f, &nv04_graph_ofuncs
, NULL
}, /* imageblit */
40 /*******************************************************************************
42 ******************************************************************************/
45 nv20_graph_context_ctor(struct nouveau_object
*parent
,
46 struct nouveau_object
*engine
,
47 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
48 struct nouveau_object
**pobject
)
50 struct nv20_graph_chan
*chan
;
53 ret
= nouveau_graph_context_create(parent
, engine
, oclass
, NULL
,
54 0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC
,
56 *pobject
= nv_object(chan
);
60 chan
->chid
= nouveau_fifo_chan(parent
)->chid
;
62 nv_wo32(chan
, 0x0000, 0x00000001 | (chan
->chid
<< 24));
63 nv_wo32(chan
, 0x033c, 0xffff0000);
64 nv_wo32(chan
, 0x03a0, 0x0fff0000);
65 nv_wo32(chan
, 0x03a4, 0x0fff0000);
66 nv_wo32(chan
, 0x047c, 0x00000101);
67 nv_wo32(chan
, 0x0490, 0x00000111);
68 nv_wo32(chan
, 0x04a8, 0x44400000);
69 for (i
= 0x04d4; i
<= 0x04e0; i
+= 4)
70 nv_wo32(chan
, i
, 0x00030303);
71 for (i
= 0x04f4; i
<= 0x0500; i
+= 4)
72 nv_wo32(chan
, i
, 0x00080000);
73 for (i
= 0x050c; i
<= 0x0518; i
+= 4)
74 nv_wo32(chan
, i
, 0x01012000);
75 for (i
= 0x051c; i
<= 0x0528; i
+= 4)
76 nv_wo32(chan
, i
, 0x000105b8);
77 for (i
= 0x052c; i
<= 0x0538; i
+= 4)
78 nv_wo32(chan
, i
, 0x00080008);
79 for (i
= 0x055c; i
<= 0x0598; i
+= 4)
80 nv_wo32(chan
, i
, 0x07ff0000);
81 nv_wo32(chan
, 0x05a4, 0x4b7fffff);
82 nv_wo32(chan
, 0x05fc, 0x00000001);
83 nv_wo32(chan
, 0x0604, 0x00004000);
84 nv_wo32(chan
, 0x0610, 0x00000001);
85 nv_wo32(chan
, 0x0618, 0x00040000);
86 nv_wo32(chan
, 0x061c, 0x00010000);
87 for (i
= 0x1c1c; i
<= 0x248c; i
+= 16) {
88 nv_wo32(chan
, (i
+ 0), 0x10700ff9);
89 nv_wo32(chan
, (i
+ 4), 0x0436086c);
90 nv_wo32(chan
, (i
+ 8), 0x000c001b);
92 nv_wo32(chan
, 0x281c, 0x3f800000);
93 nv_wo32(chan
, 0x2830, 0x3f800000);
94 nv_wo32(chan
, 0x285c, 0x40000000);
95 nv_wo32(chan
, 0x2860, 0x3f800000);
96 nv_wo32(chan
, 0x2864, 0x3f000000);
97 nv_wo32(chan
, 0x286c, 0x40000000);
98 nv_wo32(chan
, 0x2870, 0x3f800000);
99 nv_wo32(chan
, 0x2878, 0xbf800000);
100 nv_wo32(chan
, 0x2880, 0xbf800000);
101 nv_wo32(chan
, 0x34a4, 0x000fe000);
102 nv_wo32(chan
, 0x3530, 0x000003f8);
103 nv_wo32(chan
, 0x3540, 0x002fe000);
104 for (i
= 0x355c; i
<= 0x3578; i
+= 4)
105 nv_wo32(chan
, i
, 0x001c527c);
110 nv20_graph_context_init(struct nouveau_object
*object
)
112 struct nv20_graph_priv
*priv
= (void *)object
->engine
;
113 struct nv20_graph_chan
*chan
= (void *)object
;
116 ret
= nouveau_graph_context_init(&chan
->base
);
120 nv_wo32(priv
->ctxtab
, chan
->chid
* 4, nv_gpuobj(chan
)->addr
>> 4);
125 nv20_graph_context_fini(struct nouveau_object
*object
, bool suspend
)
127 struct nv20_graph_priv
*priv
= (void *)object
->engine
;
128 struct nv20_graph_chan
*chan
= (void *)object
;
131 nv_mask(priv
, 0x400720, 0x00000001, 0x00000000);
132 if (nv_rd32(priv
, 0x400144) & 0x00010000)
133 chid
= (nv_rd32(priv
, 0x400148) & 0x1f000000) >> 24;
134 if (chan
->chid
== chid
) {
135 nv_wr32(priv
, 0x400784, nv_gpuobj(chan
)->addr
>> 4);
136 nv_wr32(priv
, 0x400788, 0x00000002);
137 nv_wait(priv
, 0x400700, 0xffffffff, 0x00000000);
138 nv_wr32(priv
, 0x400144, 0x10000000);
139 nv_mask(priv
, 0x400148, 0xff000000, 0x1f000000);
141 nv_mask(priv
, 0x400720, 0x00000001, 0x00000001);
143 nv_wo32(priv
->ctxtab
, chan
->chid
* 4, 0x00000000);
144 return nouveau_graph_context_fini(&chan
->base
, suspend
);
147 static struct nouveau_oclass
148 nv20_graph_cclass
= {
149 .handle
= NV_ENGCTX(GR
, 0x20),
150 .ofuncs
= &(struct nouveau_ofuncs
) {
151 .ctor
= nv20_graph_context_ctor
,
152 .dtor
= _nouveau_graph_context_dtor
,
153 .init
= nv20_graph_context_init
,
154 .fini
= nv20_graph_context_fini
,
155 .rd32
= _nouveau_graph_context_rd32
,
156 .wr32
= _nouveau_graph_context_wr32
,
160 /*******************************************************************************
161 * PGRAPH engine/subdev functions
162 ******************************************************************************/
165 nv20_graph_tile_prog(struct nouveau_engine
*engine
, int i
)
167 struct nouveau_fb_tile
*tile
= &nouveau_fb(engine
)->tile
.region
[i
];
168 struct nouveau_fifo
*pfifo
= nouveau_fifo(engine
);
169 struct nv20_graph_priv
*priv
= (void *)engine
;
172 pfifo
->pause(pfifo
, &flags
);
173 nv04_graph_idle(priv
);
175 nv_wr32(priv
, NV20_PGRAPH_TLIMIT(i
), tile
->limit
);
176 nv_wr32(priv
, NV20_PGRAPH_TSIZE(i
), tile
->pitch
);
177 nv_wr32(priv
, NV20_PGRAPH_TILE(i
), tile
->addr
);
179 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0030 + 4 * i
);
180 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, tile
->limit
);
181 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0050 + 4 * i
);
182 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, tile
->pitch
);
183 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0010 + 4 * i
);
184 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, tile
->addr
);
186 if (nv_device(engine
)->chipset
!= 0x34) {
187 nv_wr32(priv
, NV20_PGRAPH_ZCOMP(i
), tile
->zcomp
);
188 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00ea0090 + 4 * i
);
189 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, tile
->zcomp
);
192 pfifo
->start(pfifo
, &flags
);
196 nv20_graph_intr(struct nouveau_subdev
*subdev
)
198 struct nouveau_engine
*engine
= nv_engine(subdev
);
199 struct nouveau_object
*engctx
;
200 struct nouveau_handle
*handle
;
201 struct nv20_graph_priv
*priv
= (void *)subdev
;
202 u32 stat
= nv_rd32(priv
, NV03_PGRAPH_INTR
);
203 u32 nsource
= nv_rd32(priv
, NV03_PGRAPH_NSOURCE
);
204 u32 nstatus
= nv_rd32(priv
, NV03_PGRAPH_NSTATUS
);
205 u32 addr
= nv_rd32(priv
, NV04_PGRAPH_TRAPPED_ADDR
);
206 u32 chid
= (addr
& 0x01f00000) >> 20;
207 u32 subc
= (addr
& 0x00070000) >> 16;
208 u32 mthd
= (addr
& 0x00001ffc);
209 u32 data
= nv_rd32(priv
, NV04_PGRAPH_TRAPPED_DATA
);
210 u32
class = nv_rd32(priv
, 0x400160 + subc
* 4) & 0xfff;
213 engctx
= nouveau_engctx_get(engine
, chid
);
214 if (stat
& NV_PGRAPH_INTR_ERROR
) {
215 if (nsource
& NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD
) {
216 handle
= nouveau_handle_get_class(engctx
, class);
217 if (handle
&& !nv_call(handle
->object
, mthd
, data
))
218 show
&= ~NV_PGRAPH_INTR_ERROR
;
219 nouveau_handle_put(handle
);
223 nv_wr32(priv
, NV03_PGRAPH_INTR
, stat
);
224 nv_wr32(priv
, NV04_PGRAPH_FIFO
, 0x00000001);
227 nv_error(priv
, "%s", "");
228 nouveau_bitfield_print(nv10_graph_intr_name
, show
);
229 pr_cont(" nsource:");
230 nouveau_bitfield_print(nv04_graph_nsource
, nsource
);
231 pr_cont(" nstatus:");
232 nouveau_bitfield_print(nv10_graph_nstatus
, nstatus
);
235 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
236 chid
, nouveau_client_name(engctx
), subc
, class, mthd
,
240 nouveau_engctx_put(engctx
);
244 nv20_graph_ctor(struct nouveau_object
*parent
, struct nouveau_object
*engine
,
245 struct nouveau_oclass
*oclass
, void *data
, u32 size
,
246 struct nouveau_object
**pobject
)
248 struct nv20_graph_priv
*priv
;
251 ret
= nouveau_graph_create(parent
, engine
, oclass
, true, &priv
);
252 *pobject
= nv_object(priv
);
256 ret
= nouveau_gpuobj_new(nv_object(priv
), NULL
, 32 * 4, 16,
257 NVOBJ_FLAG_ZERO_ALLOC
, &priv
->ctxtab
);
261 nv_subdev(priv
)->unit
= 0x00001000;
262 nv_subdev(priv
)->intr
= nv20_graph_intr
;
263 nv_engine(priv
)->cclass
= &nv20_graph_cclass
;
264 nv_engine(priv
)->sclass
= nv20_graph_sclass
;
265 nv_engine(priv
)->tile_prog
= nv20_graph_tile_prog
;
270 nv20_graph_dtor(struct nouveau_object
*object
)
272 struct nv20_graph_priv
*priv
= (void *)object
;
273 nouveau_gpuobj_ref(NULL
, &priv
->ctxtab
);
274 nouveau_graph_destroy(&priv
->base
);
278 nv20_graph_init(struct nouveau_object
*object
)
280 struct nouveau_engine
*engine
= nv_engine(object
);
281 struct nv20_graph_priv
*priv
= (void *)engine
;
282 struct nouveau_fb
*pfb
= nouveau_fb(object
);
286 ret
= nouveau_graph_init(&priv
->base
);
290 nv_wr32(priv
, NV20_PGRAPH_CHANNEL_CTX_TABLE
, priv
->ctxtab
->addr
>> 4);
292 if (nv_device(priv
)->chipset
== 0x20) {
293 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x003d0000);
294 for (i
= 0; i
< 15; i
++)
295 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, 0x00000000);
296 nv_wait(priv
, 0x400700, 0xffffffff, 0x00000000);
298 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x02c80000);
299 for (i
= 0; i
< 32; i
++)
300 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, 0x00000000);
301 nv_wait(priv
, 0x400700, 0xffffffff, 0x00000000);
304 nv_wr32(priv
, NV03_PGRAPH_INTR
, 0xFFFFFFFF);
305 nv_wr32(priv
, NV03_PGRAPH_INTR_EN
, 0xFFFFFFFF);
307 nv_wr32(priv
, NV04_PGRAPH_DEBUG_0
, 0xFFFFFFFF);
308 nv_wr32(priv
, NV04_PGRAPH_DEBUG_0
, 0x00000000);
309 nv_wr32(priv
, NV04_PGRAPH_DEBUG_1
, 0x00118700);
310 nv_wr32(priv
, NV04_PGRAPH_DEBUG_3
, 0xF3CE0475); /* 0x4 = auto ctx switch */
311 nv_wr32(priv
, NV10_PGRAPH_DEBUG_4
, 0x00000000);
312 nv_wr32(priv
, 0x40009C , 0x00000040);
314 if (nv_device(priv
)->chipset
>= 0x25) {
315 nv_wr32(priv
, 0x400890, 0x00a8cfff);
316 nv_wr32(priv
, 0x400610, 0x304B1FB6);
317 nv_wr32(priv
, 0x400B80, 0x1cbd3883);
318 nv_wr32(priv
, 0x400B84, 0x44000000);
319 nv_wr32(priv
, 0x400098, 0x40000080);
320 nv_wr32(priv
, 0x400B88, 0x000000ff);
323 nv_wr32(priv
, 0x400880, 0x0008c7df);
324 nv_wr32(priv
, 0x400094, 0x00000005);
325 nv_wr32(priv
, 0x400B80, 0x45eae20e);
326 nv_wr32(priv
, 0x400B84, 0x24000000);
327 nv_wr32(priv
, 0x400098, 0x00000040);
328 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00E00038);
329 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, 0x00000030);
330 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00E10038);
331 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, 0x00000030);
334 /* Turn all the tiling regions off. */
335 for (i
= 0; i
< pfb
->tile
.regions
; i
++)
336 engine
->tile_prog(engine
, i
);
338 nv_wr32(priv
, 0x4009a0, nv_rd32(priv
, 0x100324));
339 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00EA000C);
340 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, nv_rd32(priv
, 0x100324));
342 nv_wr32(priv
, NV10_PGRAPH_CTX_CONTROL
, 0x10000100);
343 nv_wr32(priv
, NV10_PGRAPH_STATE
, 0xFFFFFFFF);
345 tmp
= nv_rd32(priv
, NV10_PGRAPH_SURFACE
) & 0x0007ff00;
346 nv_wr32(priv
, NV10_PGRAPH_SURFACE
, tmp
);
347 tmp
= nv_rd32(priv
, NV10_PGRAPH_SURFACE
) | 0x00020100;
348 nv_wr32(priv
, NV10_PGRAPH_SURFACE
, tmp
);
350 /* begin RAM config */
351 vramsz
= nv_device_resource_len(nv_device(priv
), 0) - 1;
352 nv_wr32(priv
, 0x4009A4, nv_rd32(priv
, 0x100200));
353 nv_wr32(priv
, 0x4009A8, nv_rd32(priv
, 0x100204));
354 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0000);
355 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, nv_rd32(priv
, 0x100200));
356 nv_wr32(priv
, NV10_PGRAPH_RDI_INDEX
, 0x00EA0004);
357 nv_wr32(priv
, NV10_PGRAPH_RDI_DATA
, nv_rd32(priv
, 0x100204));
358 nv_wr32(priv
, 0x400820, 0);
359 nv_wr32(priv
, 0x400824, 0);
360 nv_wr32(priv
, 0x400864, vramsz
- 1);
361 nv_wr32(priv
, 0x400868, vramsz
- 1);
363 /* interesting.. the below overwrites some of the tile setup above.. */
364 nv_wr32(priv
, 0x400B20, 0x00000000);
365 nv_wr32(priv
, 0x400B04, 0xFFFFFFFF);
367 nv_wr32(priv
, NV03_PGRAPH_ABS_UCLIP_XMIN
, 0);
368 nv_wr32(priv
, NV03_PGRAPH_ABS_UCLIP_YMIN
, 0);
369 nv_wr32(priv
, NV03_PGRAPH_ABS_UCLIP_XMAX
, 0x7fff);
370 nv_wr32(priv
, NV03_PGRAPH_ABS_UCLIP_YMAX
, 0x7fff);
374 struct nouveau_oclass
375 nv20_graph_oclass
= {
376 .handle
= NV_ENGINE(GR
, 0x20),
377 .ofuncs
= &(struct nouveau_ofuncs
) {
378 .ctor
= nv20_graph_ctor
,
379 .dtor
= nv20_graph_dtor
,
380 .init
= nv20_graph_init
,
381 .fini
= _nouveau_graph_fini
,