drivers/gpu/drm/nouveau/core/include/core/class.h

   1 #ifndef __NOUVEAU_CLASS_H__
   2 #define __NOUVEAU_CLASS_H__
   3
   4 #include <nvif/class.h>
   5
   6 /* 0046: NV04_DISP
   7  */
   8
   9 #define NV04_DISP_CLASS                                              0x00000046
  10
  11 struct nv04_display_class {
  12 };
  13
  14 /* 5070: NV50_DISP
  15  * 8270: NV84_DISP
  16  * 8370: NVA0_DISP
  17  * 8870: NV94_DISP
  18  * 8570: NVA3_DISP
  19  * 9070: NVD0_DISP
  20  * 9170: NVE0_DISP
  21  * 9270: NVF0_DISP
  22  * 9470: GM107_DISP
  23  */
  24
  25 #define NV50_DISP_CLASS                                              0x00005070
  26 #define NV84_DISP_CLASS                                              0x00008270
  27 #define NVA0_DISP_CLASS                                              0x00008370
  28 #define NV94_DISP_CLASS                                              0x00008870
  29 #define NVA3_DISP_CLASS                                              0x00008570
  30 #define NVD0_DISP_CLASS                                              0x00009070
  31 #define NVE0_DISP_CLASS                                              0x00009170
  32 #define NVF0_DISP_CLASS                                              0x00009270
  33 #define GM107_DISP_CLASS                                             0x00009470
  34
  35 struct nv50_display_class {
  36 };
  37
  38 /* 507a: NV50_DISP_CURS
  39  * 827a: NV84_DISP_CURS
  40  * 837a: NVA0_DISP_CURS
  41  * 887a: NV94_DISP_CURS
  42  * 857a: NVA3_DISP_CURS
  43  * 907a: NVD0_DISP_CURS
  44  * 917a: NVE0_DISP_CURS
  45  * 927a: NVF0_DISP_CURS
  46  * 947a: GM107_DISP_CURS
  47  */
  48
  49 #define NV50_DISP_CURS_CLASS                                         0x0000507a
  50 #define NV84_DISP_CURS_CLASS                                         0x0000827a
  51 #define NVA0_DISP_CURS_CLASS                                         0x0000837a
  52 #define NV94_DISP_CURS_CLASS                                         0x0000887a
  53 #define NVA3_DISP_CURS_CLASS                                         0x0000857a
  54 #define NVD0_DISP_CURS_CLASS                                         0x0000907a
  55 #define NVE0_DISP_CURS_CLASS                                         0x0000917a
  56 #define NVF0_DISP_CURS_CLASS                                         0x0000927a
  57 #define GM107_DISP_CURS_CLASS                                        0x0000947a
  58
  59 struct nv50_display_curs_class {
  60         u32 head;
  61 };
  62
  63 /* 507b: NV50_DISP_OIMM
  64  * 827b: NV84_DISP_OIMM
  65  * 837b: NVA0_DISP_OIMM
  66  * 887b: NV94_DISP_OIMM
  67  * 857b: NVA3_DISP_OIMM
  68  * 907b: NVD0_DISP_OIMM
  69  * 917b: NVE0_DISP_OIMM
  70  * 927b: NVE0_DISP_OIMM
  71  * 947b: GM107_DISP_OIMM
  72  */
  73
  74 #define NV50_DISP_OIMM_CLASS                                         0x0000507b
  75 #define NV84_DISP_OIMM_CLASS                                         0x0000827b
  76 #define NVA0_DISP_OIMM_CLASS                                         0x0000837b
  77 #define NV94_DISP_OIMM_CLASS                                         0x0000887b
  78 #define NVA3_DISP_OIMM_CLASS                                         0x0000857b
  79 #define NVD0_DISP_OIMM_CLASS                                         0x0000907b
  80 #define NVE0_DISP_OIMM_CLASS                                         0x0000917b
  81 #define NVF0_DISP_OIMM_CLASS                                         0x0000927b
  82 #define GM107_DISP_OIMM_CLASS                                        0x0000947b
  83
  84 struct nv50_display_oimm_class {
  85         u32 head;
  86 };
  87
  88 /* 507c: NV50_DISP_SYNC
  89  * 827c: NV84_DISP_SYNC
  90  * 837c: NVA0_DISP_SYNC
  91  * 887c: NV94_DISP_SYNC
  92  * 857c: NVA3_DISP_SYNC
  93  * 907c: NVD0_DISP_SYNC
  94  * 917c: NVE0_DISP_SYNC
  95  * 927c: NVF0_DISP_SYNC
  96  * 947c: GM107_DISP_SYNC
  97  */
  98
  99 #define NV50_DISP_SYNC_CLASS                                         0x0000507c
 100 #define NV84_DISP_SYNC_CLASS                                         0x0000827c
 101 #define NVA0_DISP_SYNC_CLASS                                         0x0000837c
 102 #define NV94_DISP_SYNC_CLASS                                         0x0000887c
 103 #define NVA3_DISP_SYNC_CLASS                                         0x0000857c
 104 #define NVD0_DISP_SYNC_CLASS                                         0x0000907c
 105 #define NVE0_DISP_SYNC_CLASS                                         0x0000917c
 106 #define NVF0_DISP_SYNC_CLASS                                         0x0000927c
 107 #define GM107_DISP_SYNC_CLASS                                        0x0000947c
 108
 109 struct nv50_display_sync_class {
 110         u32 pushbuf;
 111         u32 head;
 112 };
 113
 114 /* 507d: NV50_DISP_MAST
 115  * 827d: NV84_DISP_MAST
 116  * 837d: NVA0_DISP_MAST
 117  * 887d: NV94_DISP_MAST
 118  * 857d: NVA3_DISP_MAST
 119  * 907d: NVD0_DISP_MAST
 120  * 917d: NVE0_DISP_MAST
 121  * 927d: NVF0_DISP_MAST
 122  * 947d: GM107_DISP_MAST
 123  */
 124
 125 #define NV50_DISP_MAST_CLASS                                         0x0000507d
 126 #define NV84_DISP_MAST_CLASS                                         0x0000827d
 127 #define NVA0_DISP_MAST_CLASS                                         0x0000837d
 128 #define NV94_DISP_MAST_CLASS                                         0x0000887d
 129 #define NVA3_DISP_MAST_CLASS                                         0x0000857d
 130 #define NVD0_DISP_MAST_CLASS                                         0x0000907d
 131 #define NVE0_DISP_MAST_CLASS                                         0x0000917d
 132 #define NVF0_DISP_MAST_CLASS                                         0x0000927d
 133 #define GM107_DISP_MAST_CLASS                                        0x0000947d
 134
 135 struct nv50_display_mast_class {
 136         u32 pushbuf;
 137 };
 138
 139 /* 507e: NV50_DISP_OVLY
 140  * 827e: NV84_DISP_OVLY
 141  * 837e: NVA0_DISP_OVLY
 142  * 887e: NV94_DISP_OVLY
 143  * 857e: NVA3_DISP_OVLY
 144  * 907e: NVD0_DISP_OVLY
 145  * 917e: NVE0_DISP_OVLY
 146  * 927e: NVF0_DISP_OVLY
 147  * 947e: GM107_DISP_OVLY
 148  */
 149
 150 #define NV50_DISP_OVLY_CLASS                                         0x0000507e
 151 #define NV84_DISP_OVLY_CLASS                                         0x0000827e
 152 #define NVA0_DISP_OVLY_CLASS                                         0x0000837e
 153 #define NV94_DISP_OVLY_CLASS                                         0x0000887e
 154 #define NVA3_DISP_OVLY_CLASS                                         0x0000857e
 155 #define NVD0_DISP_OVLY_CLASS                                         0x0000907e
 156 #define NVE0_DISP_OVLY_CLASS                                         0x0000917e
 157 #define NVF0_DISP_OVLY_CLASS                                         0x0000927e
 158 #define GM107_DISP_OVLY_CLASS                                        0x0000947e
 159
 160 struct nv50_display_ovly_class {
 161         u32 pushbuf;
 162         u32 head;
 163 };
 164
 165 #endif