drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/clock.h>
  26 #include <subdev/bios.h>
  27 #include <subdev/bios/pll.h>
  28
  29 #include "pll.h"
  30
  31 struct nva3_clock_priv {
  32         struct nouveau_clock base;
  33 };
  34
  35 static int
  36 nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
  37 {
  38         struct nva3_clock_priv *priv = (void *)clk;
  39         struct nouveau_bios *bios = nouveau_bios(priv);
  40         struct nvbios_pll info;
  41         int N, fN, M, P;
  42         int ret;
  43
  44         ret = nvbios_pll_parse(bios, type, &info);
  45         if (ret)
  46                 return ret;
  47
  48         ret = nva3_pll_calc(clk, &info, freq, &N, &fN, &M, &P);
  49         if (ret < 0)
  50                 return ret;
  51
  52         switch (info.type) {
  53         case PLL_VPLL0:
  54         case PLL_VPLL1:
  55                 nv_wr32(priv, info.reg + 0, 0x50000610);
  56                 nv_mask(priv, info.reg + 4, 0x003fffff,
  57                                             (P << 16) | (M << 8) | N);
  58                 nv_wr32(priv, info.reg + 8, fN);
  59                 break;
  60         default:
  61                 nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
  62                 ret = -EINVAL;
  63                 break;
  64         }
  65
  66         return ret;
  67 }
  68
  69 static int
  70 nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
  71                 struct nouveau_oclass *oclass, void *data, u32 size,
  72                 struct nouveau_object **pobject)
  73 {
  74         struct nva3_clock_priv *priv;
  75         int ret;
  76
  77         ret = nouveau_clock_create(parent, engine, oclass, &priv);
  78         *pobject = nv_object(priv);
  79         if (ret)
  80                 return ret;
  81
  82         priv->base.pll_set = nva3_clock_pll_set;
  83         return 0;
  84 }
  85
  86 struct nouveau_oclass
  87 nva3_clock_oclass = {
  88         .handle = NV_SUBDEV(CLOCK, 0xa3),
  89         .ofuncs = &(struct nouveau_ofuncs) {
  90                 .ctor = nva3_clock_ctor,
  91                 .dtor = _nouveau_clock_dtor,
  92                 .init = _nouveau_clock_init,
  93                 .fini = _nouveau_clock_fini,
  94         },
  95 };