drivers/gpu/drm/nouveau/dispnv04/cursor.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <drm/drmP.h>
   3 #include <drm/drm_mode.h>
   4 #include "nouveau_drv.h"
   5 #include "nouveau_reg.h"
   6 #include "nouveau_crtc.h"
   7 #include "hw.h"
   8
   9 static void
  10 nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
  11 {
  12         nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true);
  13 }
  14
  15 static void
  16 nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
  17 {
  18         nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false);
  19 }
  20
  21 static void
  22 nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
  23 {
  24         nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y;
  25         NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index,
  26                       NV_PRAMDAC_CU_START_POS,
  27                       XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) |
  28                       XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X));
  29 }
  30
  31 static void
  32 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
  33 {
  34         NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
  35                        crtcstate->CRTC[index]);
  36 }
  37
  38 static void
  39 nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
  40 {
  41         struct drm_device *dev = nv_crtc->base.dev;
  42         struct nouveau_drm *drm = nouveau_drm(dev);
  43         struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
  44         struct drm_crtc *crtc = &nv_crtc->base;
  45
  46         regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] =
  47                 MASK(NV_CIO_CRE_HCUR_ASI) |
  48                 XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR);
  49         regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] =
  50                 XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR);
  51         if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
  52                 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |=
  53                         MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL);
  54         regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24;
  55
  56         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
  57         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
  58         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
  59         if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
  60                 nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
  61 }
  62
  63 int
  64 nv04_cursor_init(struct nouveau_crtc *crtc)
  65 {
  66         crtc->cursor.set_offset = nv04_cursor_set_offset;
  67         crtc->cursor.set_pos = nv04_cursor_set_pos;
  68         crtc->cursor.hide = nv04_cursor_hide;
  69         crtc->cursor.show = nv04_cursor_show;
  70         return 0;
  71 }