drivers/gpu/drm/nouveau/dispnv04/hw.c

   1 /*
   2  * Copyright 2006 Dave Airlie
   3  * Copyright 2007 Maarten Maathuis
   4  * Copyright 2007-2009 Stuart Bennett
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  20  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  21  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include <drm/drmP.h>
  26 #include "nouveau_drv.h"
  27 #include "hw.h"
  28
  29 #include <subdev/bios/pll.h>
  30
  31 #define CHIPSET_NFORCE 0x01a0
  32 #define CHIPSET_NFORCE2 0x01f0
  33
  34 /*
  35  * misc hw access wrappers/control functions
  36  */
  37
  38 void
  39 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)
  40 {
  41         NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
  42         NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value);
  43 }
  44
  45 uint8_t
  46 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index)
  47 {
  48         NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
  49         return NVReadPRMVIO(dev, head, NV_PRMVIO_SR);
  50 }
  51
  52 void
  53 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value)
  54 {
  55         NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
  56         NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value);
  57 }
  58
  59 uint8_t
  60 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)
  61 {
  62         NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
  63         return NVReadPRMVIO(dev, head, NV_PRMVIO_GX);
  64 }
  65
  66 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
  67  * it affects only the 8 bit vga io regs, which we access using mmio at
  68  * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
  69  * in general, the set value of cr44 does not matter: reg access works as
  70  * expected and values can be set for the appropriate head by using a 0x2000
  71  * offset as required
  72  * however:
  73  * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
  74  *    cr44 must be set to 0 or 3 for accessing values on the correct head
  75  *    through the common 0xc03c* addresses
  76  * b) in tied mode (4) head B is programmed to the values set on head A, and
  77  *    access using the head B addresses can have strange results, ergo we leave
  78  *    tied mode in init once we know to what cr44 should be restored on exit
  79  *
  80  * the owner parameter is slightly abused:
  81  * 0 and 1 are treated as head values and so the set value is (owner * 3)
  82  * other values are treated as literal values to set
  83  */
  84 void
  85 NVSetOwner(struct drm_device *dev, int owner)
  86 {
  87         struct nouveau_drm *drm = nouveau_drm(dev);
  88
  89         if (owner == 1)
  90                 owner *= 3;
  91
  92         if (drm->device.info.chipset == 0x11) {
  93                 /* This might seem stupid, but the blob does it and
  94                  * omitting it often locks the system up.
  95                  */
  96                 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
  97                 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX);
  98         }
  99
 100         /* CR44 is always changed on CRTC0 */
 101         NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
 102
 103         if (drm->device.info.chipset == 0x11) { /* set me harder */
 104                 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
 105                 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
 106         }
 107 }
 108
 109 void
 110 NVBlankScreen(struct drm_device *dev, int head, bool blank)
 111 {
 112         unsigned char seq1;
 113
 114         if (nv_two_heads(dev))
 115                 NVSetOwner(dev, head);
 116
 117         seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
 118
 119         NVVgaSeqReset(dev, head, true);
 120         if (blank)
 121                 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
 122         else
 123                 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
 124         NVVgaSeqReset(dev, head, false);
 125 }
 126
 127 /*
 128  * PLL getting
 129  */
 130
 131 static void
 132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
 133                       uint32_t pll2, struct nvkm_pll_vals *pllvals)
 134 {
 135         struct nouveau_drm *drm = nouveau_drm(dev);
 136
 137         /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
 138
 139         /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */
 140         pllvals->log2P = (pll1 >> 16) & 0x7;
 141         pllvals->N2 = pllvals->M2 = 1;
 142
 143         if (reg1 <= 0x405c) {
 144                 pllvals->NM1 = pll2 & 0xffff;
 145                 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
 146                 if (!(pll1 & 0x1100))
 147                         pllvals->NM2 = pll2 >> 16;
 148         } else {
 149                 pllvals->NM1 = pll1 & 0xffff;
 150                 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
 151                         pllvals->NM2 = pll2 & 0xffff;
 152                 else if (drm->device.info.chipset == 0x30 || drm->device.info.chipset == 0x35) {
 153                         pllvals->M1 &= 0xf; /* only 4 bits */
 154                         if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
 155                                 pllvals->M2 = (pll1 >> 4) & 0x7;
 156                                 pllvals->N2 = ((pll1 >> 21) & 0x18) |
 157                                               ((pll1 >> 19) & 0x7);
 158                         }
 159                 }
 160         }
 161 }
 162
 163 int
 164 nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
 165                        struct nvkm_pll_vals *pllvals)
 166 {
 167         struct nouveau_drm *drm = nouveau_drm(dev);
 168         struct nvif_object *device = &drm->device.object;
 169         struct nvkm_bios *bios = nvxx_bios(&drm->device);
 170         uint32_t reg1, pll1, pll2 = 0;
 171         struct nvbios_pll pll_lim;
 172         int ret;
 173
 174         ret = nvbios_pll_parse(bios, plltype, &pll_lim);
 175         if (ret || !(reg1 = pll_lim.reg))
 176                 return -ENOENT;
 177
 178         pll1 = nvif_rd32(device, reg1);
 179         if (reg1 <= 0x405c)
 180                 pll2 = nvif_rd32(device, reg1 + 4);
 181         else if (nv_two_reg_pll(dev)) {
 182                 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
 183
 184                 pll2 = nvif_rd32(device, reg2);
 185         }
 186
 187         if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
 188                 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
 189
 190                 /* check whether vpll has been forced into single stage mode */
 191                 if (reg1 == NV_PRAMDAC_VPLL_COEFF) {
 192                         if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE)
 193                                 pll2 = 0;
 194                 } else
 195                         if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE)
 196                                 pll2 = 0;
 197         }
 198
 199         nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);
 200         pllvals->refclk = pll_lim.refclk;
 201         return 0;
 202 }
 203
 204 int
 205 nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv)
 206 {
 207         /* Avoid divide by zero if called at an inappropriate time */
 208         if (!pv->M1 || !pv->M2)
 209                 return 0;
 210
 211         return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
 212 }
 213
 214 int
 215 nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
 216 {
 217         struct nvkm_pll_vals pllvals;
 218         int ret;
 219
 220         if (plltype == PLL_MEMORY &&
 221             (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
 222                 uint32_t mpllP;
 223
 224                 pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
 225                 if (!mpllP)
 226                         mpllP = 4;
 227
 228                 return 400000 / mpllP;
 229         } else
 230         if (plltype == PLL_MEMORY &&
 231             (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) {
 232                 uint32_t clock;
 233
 234                 pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
 235                 return clock;
 236         }
 237
 238         ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
 239         if (ret)
 240                 return ret;
 241
 242         return nouveau_hw_pllvals_to_clk(&pllvals);
 243 }
 244
 245 static void
 246 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
 247 {
 248         /* the vpll on an unused head can come up with a random value, way
 249          * beyond the pll limits.  for some reason this causes the chip to
 250          * lock up when reading the dac palette regs, so set a valid pll here
 251          * when such a condition detected.  only seen on nv11 to date
 252          */
 253
 254         struct nouveau_drm *drm = nouveau_drm(dev);
 255         struct nvif_device *device = &drm->device;
 256         struct nvkm_clk *clk = nvxx_clk(device);
 257         struct nvkm_bios *bios = nvxx_bios(device);
 258         struct nvbios_pll pll_lim;
 259         struct nvkm_pll_vals pv;
 260         enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
 261
 262         if (nvbios_pll_parse(bios, pll, &pll_lim))
 263                 return;
 264         nouveau_hw_get_pllvals(dev, pll, &pv);
 265
 266         if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
 267             pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
 268             pv.log2P <= pll_lim.max_p)
 269                 return;
 270
 271         NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1);
 272
 273         /* set lowest clock within static limits */
 274         pv.M1 = pll_lim.vco1.max_m;
 275         pv.N1 = pll_lim.vco1.min_n;
 276         pv.log2P = pll_lim.max_p_usable;
 277         clk->pll_prog(clk, pll_lim.reg, &pv);
 278 }
 279
 280 /*
 281  * vga font save/restore
 282  */
 283
 284 static void nouveau_vga_font_io(struct drm_device *dev,
 285                                 void __iomem *iovram,
 286                                 bool save, unsigned plane)
 287 {
 288         unsigned i;
 289
 290         NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane);
 291         NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane);
 292         for (i = 0; i < 16384; i++) {
 293                 if (save) {
 294                         nv04_display(dev)->saved_vga_font[plane][i] =
 295                                         ioread32_native(iovram + i * 4);
 296                 } else {
 297                         iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i],
 298                                                         iovram + i * 4);
 299                 }
 300         }
 301 }
 302
 303 void
 304 nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
 305 {
 306         struct nouveau_drm *drm = nouveau_drm(dev);
 307         uint8_t misc, gr4, gr5, gr6, seq2, seq4;
 308         bool graphicsmode;
 309         unsigned plane;
 310         void __iomem *iovram;
 311
 312         if (nv_two_heads(dev))
 313                 NVSetOwner(dev, 0);
 314
 315         NVSetEnablePalette(dev, 0, true);
 316         graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1;
 317         NVSetEnablePalette(dev, 0, false);
 318
 319         if (graphicsmode) /* graphics mode => framebuffer => no need to save */
 320                 return;
 321
 322         NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor");
 323
 324         /* map first 64KiB of VRAM, holds VGA fonts etc */
 325         iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536);
 326         if (!iovram) {
 327                 NV_ERROR(drm, "Failed to map VRAM, "
 328                                         "cannot save/restore VGA fonts.\n");
 329                 return;
 330         }
 331
 332         if (nv_two_heads(dev))
 333                 NVBlankScreen(dev, 1, true);
 334         NVBlankScreen(dev, 0, true);
 335
 336         /* save control regs */
 337         misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ);
 338         seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX);
 339         seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX);
 340         gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX);
 341         gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX);
 342         gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX);
 343
 344         NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67);
 345         NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
 346         NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0);
 347         NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5);
 348
 349         /* store font in planes 0..3 */
 350         for (plane = 0; plane < 4; plane++)
 351                 nouveau_vga_font_io(dev, iovram, save, plane);
 352
 353         /* restore control regs */
 354         NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc);
 355         NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4);
 356         NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5);
 357         NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6);
 358         NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
 359         NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
 360
 361         if (nv_two_heads(dev))
 362                 NVBlankScreen(dev, 1, false);
 363         NVBlankScreen(dev, 0, false);
 364
 365         iounmap(iovram);
 366 }
 367
 368 /*
 369  * mode state save/load
 370  */
 371
 372 static void
 373 rd_cio_state(struct drm_device *dev, int head,
 374              struct nv04_crtc_reg *crtcstate, int index)
 375 {
 376         crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
 377 }
 378
 379 static void
 380 wr_cio_state(struct drm_device *dev, int head,
 381              struct nv04_crtc_reg *crtcstate, int index)
 382 {
 383         NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
 384 }
 385
 386 static void
 387 nv_save_state_ramdac(struct drm_device *dev, int head,
 388                      struct nv04_mode_state *state)
 389 {
 390         struct nouveau_drm *drm = nouveau_drm(dev);
 391         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 392         int i;
 393
 394         if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
 395                 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
 396
 397         nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
 398         state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
 399         if (nv_two_heads(dev))
 400                 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
 401         if (drm->device.info.chipset == 0x11)
 402                 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
 403
 404         regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
 405
 406         if (nv_gf4_disp_arch(dev))
 407                 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
 408         if (drm->device.info.chipset >= 0x30)
 409                 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
 410
 411         regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
 412         regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
 413         regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
 414         regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
 415         regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
 416         regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
 417         regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
 418         regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
 419
 420         for (i = 0; i < 7; i++) {
 421                 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
 422                 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
 423                 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
 424         }
 425
 426         if (nv_gf4_disp_arch(dev)) {
 427                 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
 428                 for (i = 0; i < 3; i++) {
 429                         regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
 430                         regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
 431                 }
 432         }
 433
 434         regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
 435         regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
 436         if (!nv_gf4_disp_arch(dev) && head == 0) {
 437                 /* early chips don't allow access to PRAMDAC_TMDS_* without
 438                  * the head A FPCLK on (nv11 even locks up) */
 439                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
 440                               ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK);
 441         }
 442         regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
 443         regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
 444
 445         regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
 446
 447         if (nv_gf4_disp_arch(dev))
 448                 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
 449
 450         if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
 451                 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
 452                 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
 453                 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
 454
 455                 for (i = 0; i < 38; i++)
 456                         regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
 457                                                          NV_PRAMDAC_CTV + 4*i);
 458         }
 459 }
 460
 461 static void
 462 nv_load_state_ramdac(struct drm_device *dev, int head,
 463                      struct nv04_mode_state *state)
 464 {
 465         struct nouveau_drm *drm = nouveau_drm(dev);
 466         struct nvkm_clk *clk = nvxx_clk(&drm->device);
 467         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 468         uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
 469         int i;
 470
 471         if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
 472                 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
 473
 474         clk->pll_prog(clk, pllreg, &regp->pllvals);
 475         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
 476         if (nv_two_heads(dev))
 477                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
 478         if (drm->device.info.chipset == 0x11)
 479                 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
 480
 481         NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
 482
 483         if (nv_gf4_disp_arch(dev))
 484                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
 485         if (drm->device.info.chipset >= 0x30)
 486                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
 487
 488         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
 489         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
 490         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
 491         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
 492         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
 493         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
 494         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
 495         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
 496
 497         for (i = 0; i < 7; i++) {
 498                 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
 499
 500                 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
 501                 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
 502         }
 503
 504         if (nv_gf4_disp_arch(dev)) {
 505                 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
 506                 for (i = 0; i < 3; i++) {
 507                         NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
 508                         NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
 509                 }
 510         }
 511
 512         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
 513         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
 514         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
 515         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
 516
 517         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
 518
 519         if (nv_gf4_disp_arch(dev))
 520                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
 521
 522         if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
 523                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
 524                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
 525                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
 526
 527                 for (i = 0; i < 38; i++)
 528                         NVWriteRAMDAC(dev, head,
 529                                       NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
 530         }
 531 }
 532
 533 static void
 534 nv_save_state_vga(struct drm_device *dev, int head,
 535                   struct nv04_mode_state *state)
 536 {
 537         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 538         int i;
 539
 540         regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
 541
 542         for (i = 0; i < 25; i++)
 543                 rd_cio_state(dev, head, regp, i);
 544
 545         NVSetEnablePalette(dev, head, true);
 546         for (i = 0; i < 21; i++)
 547                 regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
 548         NVSetEnablePalette(dev, head, false);
 549
 550         for (i = 0; i < 9; i++)
 551                 regp->Graphics[i] = NVReadVgaGr(dev, head, i);
 552
 553         for (i = 0; i < 5; i++)
 554                 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
 555 }
 556
 557 static void
 558 nv_load_state_vga(struct drm_device *dev, int head,
 559                   struct nv04_mode_state *state)
 560 {
 561         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 562         int i;
 563
 564         NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
 565
 566         for (i = 0; i < 5; i++)
 567                 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
 568
 569         nv_lock_vga_crtc_base(dev, head, false);
 570         for (i = 0; i < 25; i++)
 571                 wr_cio_state(dev, head, regp, i);
 572         nv_lock_vga_crtc_base(dev, head, true);
 573
 574         for (i = 0; i < 9; i++)
 575                 NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
 576
 577         NVSetEnablePalette(dev, head, true);
 578         for (i = 0; i < 21; i++)
 579                 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
 580         NVSetEnablePalette(dev, head, false);
 581 }
 582
 583 static void
 584 nv_save_state_ext(struct drm_device *dev, int head,
 585                   struct nv04_mode_state *state)
 586 {
 587         struct nouveau_drm *drm = nouveau_drm(dev);
 588         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 589         int i;
 590
 591         rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
 592         rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
 593         rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
 594         rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
 595         rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
 596         rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
 597         rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
 598
 599         rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
 600         rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
 601         rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
 602
 603         if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN)
 604                 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
 605
 606         if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
 607                 rd_cio_state(dev, head, regp, 0x9f);
 608
 609         rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
 610         rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
 611         rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
 612         rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
 613         rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
 614
 615         if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
 616                 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
 617                 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
 618
 619                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
 620                         regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
 621
 622                 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
 623                         regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
 624
 625                 if (nv_two_heads(dev))
 626                         regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
 627                 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
 628         }
 629
 630         regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
 631
 632         rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
 633         rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
 634         if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
 635                 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
 636                 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
 637                 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
 638                 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
 639         }
 640         /* NV11 and NV20 don't have this, they stop at 0x52. */
 641         if (nv_gf4_disp_arch(dev)) {
 642                 rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
 643                 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
 644                 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
 645
 646                 for (i = 0; i < 0x10; i++)
 647                         regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
 648                 rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
 649                 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
 650
 651                 rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
 652                 rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
 653         }
 654
 655         regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
 656 }
 657
 658 static void
 659 nv_load_state_ext(struct drm_device *dev, int head,
 660                   struct nv04_mode_state *state)
 661 {
 662         struct nouveau_drm *drm = nouveau_drm(dev);
 663         struct nvif_object *device = &drm->device.object;
 664         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
 665         uint32_t reg900;
 666         int i;
 667
 668         if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
 669                 if (nv_two_heads(dev))
 670                         /* setting ENGINE_CTRL (EC) *must* come before
 671                          * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
 672                          * EC that should not be overwritten by writing stale EC
 673                          */
 674                         NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
 675
 676                 nvif_wr32(device, NV_PVIDEO_STOP, 1);
 677                 nvif_wr32(device, NV_PVIDEO_INTR_EN, 0);
 678                 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
 679                 nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
 680                 nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->device.info.ram_size - 1);
 681                 nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->device.info.ram_size - 1);
 682                 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->device.info.ram_size - 1);
 683                 nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->device.info.ram_size - 1);
 684                 nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);
 685
 686                 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
 687                 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
 688                 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
 689
 690                 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
 691                         NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
 692
 693                 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
 694                         NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
 695
 696                         reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
 697                         if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC)
 698                                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
 699                         else
 700                                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
 701                 }
 702         }
 703
 704         NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
 705
 706         wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
 707         wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
 708         wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
 709         wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
 710         wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
 711         wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
 712         wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
 713         wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
 714         wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
 715
 716         if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN)
 717                 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
 718
 719         if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
 720                 wr_cio_state(dev, head, regp, 0x9f);
 721
 722         wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
 723         wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
 724         wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
 725         wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
 726         if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
 727                 nv_fix_nv40_hw_cursor(dev, head);
 728         wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
 729
 730         wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
 731         wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
 732         if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
 733                 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
 734                 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
 735                 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
 736                 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
 737         }
 738         /* NV11 and NV20 stop at 0x52. */
 739         if (nv_gf4_disp_arch(dev)) {
 740                 if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
 741                         /* Not waiting for vertical retrace before modifying
 742                            CRE_53/CRE_54 causes lockups. */
 743                         nvif_msec(&drm->device, 650,
 744                                 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
 745                                         break;
 746                         );
 747                         nvif_msec(&drm->device, 650,
 748                                 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8))
 749                                         break;
 750                         );
 751                 }
 752
 753                 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
 754                 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
 755                 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
 756
 757                 for (i = 0; i < 0x10; i++)
 758                         NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
 759                 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
 760                 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
 761
 762                 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
 763                 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
 764         }
 765
 766         NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
 767 }
 768
 769 static void
 770 nv_save_state_palette(struct drm_device *dev, int head,
 771                       struct nv04_mode_state *state)
 772 {
 773         struct nvif_object *device = &nouveau_drm(dev)->device.object;
 774         int head_offset = head * NV_PRMDIO_SIZE, i;
 775
 776         nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
 777                                 NV_PRMDIO_PIXEL_MASK_MASK);
 778         nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
 779
 780         for (i = 0; i < 768; i++) {
 781                 state->crtc_reg[head].DAC[i] = nvif_rd08(device,
 782                                 NV_PRMDIO_PALETTE_DATA + head_offset);
 783         }
 784
 785         NVSetEnablePalette(dev, head, false);
 786 }
 787
 788 void
 789 nouveau_hw_load_state_palette(struct drm_device *dev, int head,
 790                               struct nv04_mode_state *state)
 791 {
 792         struct nvif_object *device = &nouveau_drm(dev)->device.object;
 793         int head_offset = head * NV_PRMDIO_SIZE, i;
 794
 795         nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
 796                                 NV_PRMDIO_PIXEL_MASK_MASK);
 797         nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
 798
 799         for (i = 0; i < 768; i++) {
 800                 nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset,
 801                                 state->crtc_reg[head].DAC[i]);
 802         }
 803
 804         NVSetEnablePalette(dev, head, false);
 805 }
 806
 807 void nouveau_hw_save_state(struct drm_device *dev, int head,
 808                            struct nv04_mode_state *state)
 809 {
 810         struct nouveau_drm *drm = nouveau_drm(dev);
 811
 812         if (drm->device.info.chipset == 0x11)
 813                 /* NB: no attempt is made to restore the bad pll later on */
 814                 nouveau_hw_fix_bad_vpll(dev, head);
 815         nv_save_state_ramdac(dev, head, state);
 816         nv_save_state_vga(dev, head, state);
 817         nv_save_state_palette(dev, head, state);
 818         nv_save_state_ext(dev, head, state);
 819 }
 820
 821 void nouveau_hw_load_state(struct drm_device *dev, int head,
 822                            struct nv04_mode_state *state)
 823 {
 824         NVVgaProtect(dev, head, true);
 825         nv_load_state_ramdac(dev, head, state);
 826         nv_load_state_ext(dev, head, state);
 827         nouveau_hw_load_state_palette(dev, head, state);
 828         nv_load_state_vga(dev, head, state);
 829         NVVgaProtect(dev, head, false);
 830 }