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UBUNTU: Ubuntu-5.4.0-117.132
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / nouveau / dispnv50 / disp.c
1 /*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "disp.h"
25 #include "atom.h"
26 #include "core.h"
27 #include "head.h"
28 #include "wndw.h"
29
30 #include <linux/dma-mapping.h>
31 #include <linux/hdmi.h>
32
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_dp_helper.h>
35 #include <drm/drm_edid.h>
36 #include <drm/drm_fb_helper.h>
37 #include <drm/drm_plane_helper.h>
38 #include <drm/drm_probe_helper.h>
39 #include <drm/drm_scdc_helper.h>
40 #include <drm/drm_vblank.h>
41
42 #include <nvif/class.h>
43 #include <nvif/cl0002.h>
44 #include <nvif/cl5070.h>
45 #include <nvif/cl507d.h>
46 #include <nvif/event.h>
47
48 #include "nouveau_drv.h"
49 #include "nouveau_dma.h"
50 #include "nouveau_gem.h"
51 #include "nouveau_connector.h"
52 #include "nouveau_encoder.h"
53 #include "nouveau_fence.h"
54 #include "nouveau_fbcon.h"
55
56 #include <subdev/bios/dp.h>
57
58 /******************************************************************************
59 * Atomic state
60 *****************************************************************************/
61
62 struct nv50_outp_atom {
63 struct list_head head;
64
65 struct drm_encoder *encoder;
66 bool flush_disable;
67
68 union nv50_outp_atom_mask {
69 struct {
70 bool ctrl:1;
71 };
72 u8 mask;
73 } set, clr;
74 };
75
76 /******************************************************************************
77 * EVO channel
78 *****************************************************************************/
79
80 static int
81 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
82 const s32 *oclass, u8 head, void *data, u32 size,
83 struct nv50_chan *chan)
84 {
85 struct nvif_sclass *sclass;
86 int ret, i, n;
87
88 chan->device = device;
89
90 ret = n = nvif_object_sclass_get(disp, &sclass);
91 if (ret < 0)
92 return ret;
93
94 while (oclass[0]) {
95 for (i = 0; i < n; i++) {
96 if (sclass[i].oclass == oclass[0]) {
97 ret = nvif_object_init(disp, 0, oclass[0],
98 data, size, &chan->user);
99 if (ret == 0)
100 nvif_object_map(&chan->user, NULL, 0);
101 nvif_object_sclass_put(&sclass);
102 return ret;
103 }
104 }
105 oclass++;
106 }
107
108 nvif_object_sclass_put(&sclass);
109 return -ENOSYS;
110 }
111
112 static void
113 nv50_chan_destroy(struct nv50_chan *chan)
114 {
115 nvif_object_fini(&chan->user);
116 }
117
118 /******************************************************************************
119 * DMA EVO channel
120 *****************************************************************************/
121
122 void
123 nv50_dmac_destroy(struct nv50_dmac *dmac)
124 {
125 nvif_object_fini(&dmac->vram);
126 nvif_object_fini(&dmac->sync);
127
128 nv50_chan_destroy(&dmac->base);
129
130 nvif_mem_fini(&dmac->push);
131 }
132
133 int
134 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
135 const s32 *oclass, u8 head, void *data, u32 size, s64 syncbuf,
136 struct nv50_dmac *dmac)
137 {
138 struct nouveau_cli *cli = (void *)device->object.client;
139 struct nv50_disp_core_channel_dma_v0 *args = data;
140 u8 type = NVIF_MEM_COHERENT;
141 int ret;
142
143 mutex_init(&dmac->lock);
144
145 /* Pascal added support for 47-bit physical addresses, but some
146 * parts of EVO still only accept 40-bit PAs.
147 *
148 * To avoid issues on systems with large amounts of RAM, and on
149 * systems where an IOMMU maps pages at a high address, we need
150 * to allocate push buffers in VRAM instead.
151 *
152 * This appears to match NVIDIA's behaviour on Pascal.
153 */
154 if (device->info.family == NV_DEVICE_INFO_V0_PASCAL)
155 type |= NVIF_MEM_VRAM;
156
157 ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push);
158 if (ret)
159 return ret;
160
161 dmac->ptr = dmac->push.object.map.ptr;
162
163 args->pushbuf = nvif_handle(&dmac->push.object);
164
165 ret = nv50_chan_create(device, disp, oclass, head, data, size,
166 &dmac->base);
167 if (ret)
168 return ret;
169
170 if (syncbuf < 0)
171 return 0;
172
173 ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
174 &(struct nv_dma_v0) {
175 .target = NV_DMA_V0_TARGET_VRAM,
176 .access = NV_DMA_V0_ACCESS_RDWR,
177 .start = syncbuf + 0x0000,
178 .limit = syncbuf + 0x0fff,
179 }, sizeof(struct nv_dma_v0),
180 &dmac->sync);
181 if (ret)
182 return ret;
183
184 ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
185 &(struct nv_dma_v0) {
186 .target = NV_DMA_V0_TARGET_VRAM,
187 .access = NV_DMA_V0_ACCESS_RDWR,
188 .start = 0,
189 .limit = device->info.ram_user - 1,
190 }, sizeof(struct nv_dma_v0),
191 &dmac->vram);
192 if (ret)
193 return ret;
194
195 return ret;
196 }
197
198 /******************************************************************************
199 * EVO channel helpers
200 *****************************************************************************/
201 static void
202 evo_flush(struct nv50_dmac *dmac)
203 {
204 /* Push buffer fetches are not coherent with BAR1, we need to ensure
205 * writes have been flushed right through to VRAM before writing PUT.
206 */
207 if (dmac->push.type & NVIF_MEM_VRAM) {
208 struct nvif_device *device = dmac->base.device;
209 nvif_wr32(&device->object, 0x070000, 0x00000001);
210 nvif_msec(device, 2000,
211 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
212 break;
213 );
214 }
215 }
216
217 u32 *
218 evo_wait(struct nv50_dmac *evoc, int nr)
219 {
220 struct nv50_dmac *dmac = evoc;
221 struct nvif_device *device = dmac->base.device;
222 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
223
224 mutex_lock(&dmac->lock);
225 if (put + nr >= (PAGE_SIZE / 4) - 8) {
226 dmac->ptr[put] = 0x20000000;
227 evo_flush(dmac);
228
229 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
230 if (nvif_msec(device, 2000,
231 if (!nvif_rd32(&dmac->base.user, 0x0004))
232 break;
233 ) < 0) {
234 mutex_unlock(&dmac->lock);
235 pr_err("nouveau: evo channel stalled\n");
236 return NULL;
237 }
238
239 put = 0;
240 }
241
242 return dmac->ptr + put;
243 }
244
245 void
246 evo_kick(u32 *push, struct nv50_dmac *evoc)
247 {
248 struct nv50_dmac *dmac = evoc;
249
250 evo_flush(dmac);
251
252 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
253 mutex_unlock(&dmac->lock);
254 }
255
256 /******************************************************************************
257 * Output path helpers
258 *****************************************************************************/
259 static void
260 nv50_outp_release(struct nouveau_encoder *nv_encoder)
261 {
262 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
263 struct {
264 struct nv50_disp_mthd_v1 base;
265 } args = {
266 .base.version = 1,
267 .base.method = NV50_DISP_MTHD_V1_RELEASE,
268 .base.hasht = nv_encoder->dcb->hasht,
269 .base.hashm = nv_encoder->dcb->hashm,
270 };
271
272 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
273 nv_encoder->or = -1;
274 nv_encoder->link = 0;
275 }
276
277 static int
278 nv50_outp_acquire(struct nouveau_encoder *nv_encoder)
279 {
280 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
281 struct nv50_disp *disp = nv50_disp(drm->dev);
282 struct {
283 struct nv50_disp_mthd_v1 base;
284 struct nv50_disp_acquire_v0 info;
285 } args = {
286 .base.version = 1,
287 .base.method = NV50_DISP_MTHD_V1_ACQUIRE,
288 .base.hasht = nv_encoder->dcb->hasht,
289 .base.hashm = nv_encoder->dcb->hashm,
290 };
291 int ret;
292
293 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
294 if (ret) {
295 NV_ERROR(drm, "error acquiring output path: %d\n", ret);
296 return ret;
297 }
298
299 nv_encoder->or = args.info.or;
300 nv_encoder->link = args.info.link;
301 return 0;
302 }
303
304 static int
305 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
306 struct drm_crtc_state *crtc_state,
307 struct drm_connector_state *conn_state,
308 struct drm_display_mode *native_mode)
309 {
310 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
311 struct drm_display_mode *mode = &crtc_state->mode;
312 struct drm_connector *connector = conn_state->connector;
313 struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
314 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
315
316 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
317 asyc->scaler.full = false;
318 if (!native_mode)
319 return 0;
320
321 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
322 switch (connector->connector_type) {
323 case DRM_MODE_CONNECTOR_LVDS:
324 case DRM_MODE_CONNECTOR_eDP:
325 /* Don't force scaler for EDID modes with
326 * same size as the native one (e.g. different
327 * refresh rate)
328 */
329 if (mode->hdisplay == native_mode->hdisplay &&
330 mode->vdisplay == native_mode->vdisplay &&
331 mode->type & DRM_MODE_TYPE_DRIVER)
332 break;
333 mode = native_mode;
334 asyc->scaler.full = true;
335 break;
336 default:
337 break;
338 }
339 } else {
340 mode = native_mode;
341 }
342
343 if (!drm_mode_equal(adjusted_mode, mode)) {
344 drm_mode_copy(adjusted_mode, mode);
345 crtc_state->mode_changed = true;
346 }
347
348 return 0;
349 }
350
351 static int
352 nv50_outp_atomic_check(struct drm_encoder *encoder,
353 struct drm_crtc_state *crtc_state,
354 struct drm_connector_state *conn_state)
355 {
356 struct drm_connector *connector = conn_state->connector;
357 struct nouveau_connector *nv_connector = nouveau_connector(connector);
358 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
359 int ret;
360
361 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
362 nv_connector->native_mode);
363 if (ret)
364 return ret;
365
366 if (crtc_state->mode_changed || crtc_state->connectors_changed)
367 asyh->or.bpc = connector->display_info.bpc;
368
369 return 0;
370 }
371
372 /******************************************************************************
373 * DAC
374 *****************************************************************************/
375 static void
376 nv50_dac_disable(struct drm_encoder *encoder)
377 {
378 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
379 struct nv50_core *core = nv50_disp(encoder->dev)->core;
380 if (nv_encoder->crtc)
381 core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL);
382 nv_encoder->crtc = NULL;
383 nv50_outp_release(nv_encoder);
384 }
385
386 static void
387 nv50_dac_enable(struct drm_encoder *encoder)
388 {
389 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
390 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
391 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
392 struct nv50_core *core = nv50_disp(encoder->dev)->core;
393
394 nv50_outp_acquire(nv_encoder);
395
396 core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);
397 asyh->or.depth = 0;
398
399 nv_encoder->crtc = encoder->crtc;
400 }
401
402 static enum drm_connector_status
403 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
404 {
405 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
406 struct nv50_disp *disp = nv50_disp(encoder->dev);
407 struct {
408 struct nv50_disp_mthd_v1 base;
409 struct nv50_disp_dac_load_v0 load;
410 } args = {
411 .base.version = 1,
412 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
413 .base.hasht = nv_encoder->dcb->hasht,
414 .base.hashm = nv_encoder->dcb->hashm,
415 };
416 int ret;
417
418 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
419 if (args.load.data == 0)
420 args.load.data = 340;
421
422 ret = nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
423 if (ret || !args.load.load)
424 return connector_status_disconnected;
425
426 return connector_status_connected;
427 }
428
429 static const struct drm_encoder_helper_funcs
430 nv50_dac_help = {
431 .atomic_check = nv50_outp_atomic_check,
432 .enable = nv50_dac_enable,
433 .disable = nv50_dac_disable,
434 .detect = nv50_dac_detect
435 };
436
437 static void
438 nv50_dac_destroy(struct drm_encoder *encoder)
439 {
440 drm_encoder_cleanup(encoder);
441 kfree(encoder);
442 }
443
444 static const struct drm_encoder_funcs
445 nv50_dac_func = {
446 .destroy = nv50_dac_destroy,
447 };
448
449 static int
450 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
451 {
452 struct nouveau_drm *drm = nouveau_drm(connector->dev);
453 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
454 struct nvkm_i2c_bus *bus;
455 struct nouveau_encoder *nv_encoder;
456 struct drm_encoder *encoder;
457 int type = DRM_MODE_ENCODER_DAC;
458
459 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
460 if (!nv_encoder)
461 return -ENOMEM;
462 nv_encoder->dcb = dcbe;
463
464 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
465 if (bus)
466 nv_encoder->i2c = &bus->i2c;
467
468 encoder = to_drm_encoder(nv_encoder);
469 encoder->possible_crtcs = dcbe->heads;
470 encoder->possible_clones = 0;
471 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
472 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
473 drm_encoder_helper_add(encoder, &nv50_dac_help);
474
475 drm_connector_attach_encoder(connector, encoder);
476 return 0;
477 }
478
479 /******************************************************************************
480 * Audio
481 *****************************************************************************/
482 static void
483 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
484 {
485 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
486 struct nv50_disp *disp = nv50_disp(encoder->dev);
487 struct {
488 struct nv50_disp_mthd_v1 base;
489 struct nv50_disp_sor_hda_eld_v0 eld;
490 } args = {
491 .base.version = 1,
492 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
493 .base.hasht = nv_encoder->dcb->hasht,
494 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
495 (0x0100 << nv_crtc->index),
496 };
497
498 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
499 }
500
501 static void
502 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
503 {
504 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
505 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
506 struct nouveau_connector *nv_connector;
507 struct nv50_disp *disp = nv50_disp(encoder->dev);
508 struct __packed {
509 struct {
510 struct nv50_disp_mthd_v1 mthd;
511 struct nv50_disp_sor_hda_eld_v0 eld;
512 } base;
513 u8 data[sizeof(nv_connector->base.eld)];
514 } args = {
515 .base.mthd.version = 1,
516 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
517 .base.mthd.hasht = nv_encoder->dcb->hasht,
518 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
519 (0x0100 << nv_crtc->index),
520 };
521
522 nv_connector = nouveau_encoder_connector_get(nv_encoder);
523 if (!drm_detect_monitor_audio(nv_connector->edid))
524 return;
525
526 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
527
528 nvif_mthd(&disp->disp->object, 0, &args,
529 sizeof(args.base) + drm_eld_size(args.data));
530 }
531
532 /******************************************************************************
533 * HDMI
534 *****************************************************************************/
535 static void
536 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
537 {
538 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
539 struct nv50_disp *disp = nv50_disp(encoder->dev);
540 struct {
541 struct nv50_disp_mthd_v1 base;
542 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
543 } args = {
544 .base.version = 1,
545 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
546 .base.hasht = nv_encoder->dcb->hasht,
547 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
548 (0x0100 << nv_crtc->index),
549 };
550
551 nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));
552 }
553
554 static void
555 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
556 {
557 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
558 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
559 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
560 struct nv50_disp *disp = nv50_disp(encoder->dev);
561 struct {
562 struct nv50_disp_mthd_v1 base;
563 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
564 u8 infoframes[2 * 17]; /* two frames, up to 17 bytes each */
565 } args = {
566 .base.version = 1,
567 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
568 .base.hasht = nv_encoder->dcb->hasht,
569 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
570 (0x0100 << nv_crtc->index),
571 .pwr.state = 1,
572 .pwr.rekey = 56, /* binary driver, and tegra, constant */
573 };
574 struct nouveau_connector *nv_connector;
575 struct drm_hdmi_info *hdmi;
576 u32 max_ac_packet;
577 union hdmi_infoframe avi_frame;
578 union hdmi_infoframe vendor_frame;
579 bool high_tmds_clock_ratio = false, scrambling = false;
580 u8 config;
581 int ret;
582 int size;
583
584 nv_connector = nouveau_encoder_connector_get(nv_encoder);
585 if (!drm_detect_hdmi_monitor(nv_connector->edid))
586 return;
587
588 hdmi = &nv_connector->base.display_info.hdmi;
589
590 ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi,
591 &nv_connector->base, mode);
592 if (!ret) {
593 /* We have an AVI InfoFrame, populate it to the display */
594 args.pwr.avi_infoframe_length
595 = hdmi_infoframe_pack(&avi_frame, args.infoframes, 17);
596 }
597
598 ret = drm_hdmi_vendor_infoframe_from_display_mode(&vendor_frame.vendor.hdmi,
599 &nv_connector->base, mode);
600 if (!ret) {
601 /* We have a Vendor InfoFrame, populate it to the display */
602 args.pwr.vendor_infoframe_length
603 = hdmi_infoframe_pack(&vendor_frame,
604 args.infoframes
605 + args.pwr.avi_infoframe_length,
606 17);
607 }
608
609 max_ac_packet = mode->htotal - mode->hdisplay;
610 max_ac_packet -= args.pwr.rekey;
611 max_ac_packet -= 18; /* constant from tegra */
612 args.pwr.max_ac_packet = max_ac_packet / 32;
613
614 if (hdmi->scdc.scrambling.supported) {
615 high_tmds_clock_ratio = mode->clock > 340000;
616 scrambling = high_tmds_clock_ratio ||
617 hdmi->scdc.scrambling.low_rates;
618 }
619
620 args.pwr.scdc =
621 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling |
622 NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio;
623
624 size = sizeof(args.base)
625 + sizeof(args.pwr)
626 + args.pwr.avi_infoframe_length
627 + args.pwr.vendor_infoframe_length;
628 nvif_mthd(&disp->disp->object, 0, &args, size);
629
630 nv50_audio_enable(encoder, mode);
631
632 /* If SCDC is supported by the downstream monitor, update
633 * divider / scrambling settings to what we programmed above.
634 */
635 if (!hdmi->scdc.scrambling.supported)
636 return;
637
638 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config);
639 if (ret < 0) {
640 NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret);
641 return;
642 }
643 config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE);
644 config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio;
645 config |= SCDC_SCRAMBLING_ENABLE * scrambling;
646 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config);
647 if (ret < 0)
648 NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n",
649 config, ret);
650 }
651
652 /******************************************************************************
653 * MST
654 *****************************************************************************/
655 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
656 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
657 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
658
659 struct nv50_mstm {
660 struct nouveau_encoder *outp;
661
662 struct drm_dp_mst_topology_mgr mgr;
663 struct nv50_msto *msto[4];
664
665 bool modified;
666 bool disabled;
667 int links;
668 };
669
670 struct nv50_mstc {
671 struct nv50_mstm *mstm;
672 struct drm_dp_mst_port *port;
673 struct drm_connector connector;
674
675 struct drm_display_mode *native;
676 struct edid *edid;
677 };
678
679 struct nv50_msto {
680 struct drm_encoder encoder;
681
682 struct nv50_head *head;
683 struct nv50_mstc *mstc;
684 bool disabled;
685 };
686
687 static struct drm_dp_payload *
688 nv50_msto_payload(struct nv50_msto *msto)
689 {
690 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
691 struct nv50_mstc *mstc = msto->mstc;
692 struct nv50_mstm *mstm = mstc->mstm;
693 int vcpi = mstc->port->vcpi.vcpi, i;
694
695 WARN_ON(!mutex_is_locked(&mstm->mgr.payload_lock));
696
697 NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
698 for (i = 0; i < mstm->mgr.max_payloads; i++) {
699 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
700 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
701 mstm->outp->base.base.name, i, payload->vcpi,
702 payload->start_slot, payload->num_slots);
703 }
704
705 for (i = 0; i < mstm->mgr.max_payloads; i++) {
706 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
707 if (payload->vcpi == vcpi)
708 return payload;
709 }
710
711 return NULL;
712 }
713
714 static void
715 nv50_msto_cleanup(struct nv50_msto *msto)
716 {
717 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
718 struct nv50_mstc *mstc = msto->mstc;
719 struct nv50_mstm *mstm = mstc->mstm;
720
721 if (!msto->disabled)
722 return;
723
724 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
725
726 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
727
728 msto->mstc = NULL;
729 msto->head = NULL;
730 msto->disabled = false;
731 }
732
733 static void
734 nv50_msto_prepare(struct nv50_msto *msto)
735 {
736 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
737 struct nv50_mstc *mstc = msto->mstc;
738 struct nv50_mstm *mstm = mstc->mstm;
739 struct {
740 struct nv50_disp_mthd_v1 base;
741 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
742 } args = {
743 .base.version = 1,
744 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
745 .base.hasht = mstm->outp->dcb->hasht,
746 .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) |
747 (0x0100 << msto->head->base.index),
748 };
749
750 mutex_lock(&mstm->mgr.payload_lock);
751
752 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
753 if (mstc->port->vcpi.vcpi > 0) {
754 struct drm_dp_payload *payload = nv50_msto_payload(msto);
755 if (payload) {
756 args.vcpi.start_slot = payload->start_slot;
757 args.vcpi.num_slots = payload->num_slots;
758 args.vcpi.pbn = mstc->port->vcpi.pbn;
759 args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
760 }
761 }
762
763 NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
764 msto->encoder.name, msto->head->base.base.name,
765 args.vcpi.start_slot, args.vcpi.num_slots,
766 args.vcpi.pbn, args.vcpi.aligned_pbn);
767
768 nvif_mthd(&drm->display->disp.object, 0, &args, sizeof(args));
769 mutex_unlock(&mstm->mgr.payload_lock);
770 }
771
772 static int
773 nv50_msto_atomic_check(struct drm_encoder *encoder,
774 struct drm_crtc_state *crtc_state,
775 struct drm_connector_state *conn_state)
776 {
777 struct drm_atomic_state *state = crtc_state->state;
778 struct drm_connector *connector = conn_state->connector;
779 struct nv50_mstc *mstc = nv50_mstc(connector);
780 struct nv50_mstm *mstm = mstc->mstm;
781 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
782 int slots;
783 int ret;
784
785 ret = nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
786 mstc->native);
787 if (ret)
788 return ret;
789
790 if (!crtc_state->mode_changed && !crtc_state->connectors_changed)
791 return 0;
792
793 /*
794 * When restoring duplicated states, we need to make sure that the bw
795 * remains the same and avoid recalculating it, as the connector's bpc
796 * may have changed after the state was duplicated
797 */
798 if (!state->duplicated) {
799 const int clock = crtc_state->adjusted_mode.clock;
800
801 /*
802 * XXX: Since we don't use HDR in userspace quite yet, limit
803 * the bpc to 8 to save bandwidth on the topology. In the
804 * future, we'll want to properly fix this by dynamically
805 * selecting the highest possible bpc that would fit in the
806 * topology
807 */
808 asyh->or.bpc = min(connector->display_info.bpc, 8U);
809 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3);
810 }
811
812 slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
813 asyh->dp.pbn);
814 if (slots < 0)
815 return slots;
816
817 asyh->dp.tu = slots;
818
819 return 0;
820 }
821
822 static u8
823 nv50_dp_bpc_to_depth(unsigned int bpc)
824 {
825 switch (bpc) {
826 case 6: return 0x2;
827 case 8: return 0x5;
828 case 10: /* fall-through */
829 default: return 0x6;
830 }
831 }
832
833 static void
834 nv50_msto_enable(struct drm_encoder *encoder)
835 {
836 struct nv50_head *head = nv50_head(encoder->crtc);
837 struct nv50_head_atom *armh = nv50_head_atom(head->base.base.state);
838 struct nv50_msto *msto = nv50_msto(encoder);
839 struct nv50_mstc *mstc = NULL;
840 struct nv50_mstm *mstm = NULL;
841 struct drm_connector *connector;
842 struct drm_connector_list_iter conn_iter;
843 u8 proto;
844 bool r;
845
846 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
847 drm_for_each_connector_iter(connector, &conn_iter) {
848 if (connector->state->best_encoder == &msto->encoder) {
849 mstc = nv50_mstc(connector);
850 mstm = mstc->mstm;
851 break;
852 }
853 }
854 drm_connector_list_iter_end(&conn_iter);
855
856 if (WARN_ON(!mstc))
857 return;
858
859 r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, armh->dp.pbn,
860 armh->dp.tu);
861 if (!r)
862 DRM_DEBUG_KMS("Failed to allocate VCPI\n");
863
864 if (!mstm->links++)
865 nv50_outp_acquire(mstm->outp);
866
867 if (mstm->outp->link & 1)
868 proto = 0x8;
869 else
870 proto = 0x9;
871
872 mstm->outp->update(mstm->outp, head->base.index, armh, proto,
873 nv50_dp_bpc_to_depth(armh->or.bpc));
874
875 msto->head = head;
876 msto->mstc = mstc;
877 mstm->modified = true;
878 }
879
880 static void
881 nv50_msto_disable(struct drm_encoder *encoder)
882 {
883 struct nv50_msto *msto = nv50_msto(encoder);
884 struct nv50_mstc *mstc = msto->mstc;
885 struct nv50_mstm *mstm = mstc->mstm;
886
887 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
888
889 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
890 mstm->modified = true;
891 if (!--mstm->links)
892 mstm->disabled = true;
893 msto->disabled = true;
894 }
895
896 static const struct drm_encoder_helper_funcs
897 nv50_msto_help = {
898 .disable = nv50_msto_disable,
899 .enable = nv50_msto_enable,
900 .atomic_check = nv50_msto_atomic_check,
901 };
902
903 static void
904 nv50_msto_destroy(struct drm_encoder *encoder)
905 {
906 struct nv50_msto *msto = nv50_msto(encoder);
907 drm_encoder_cleanup(&msto->encoder);
908 kfree(msto);
909 }
910
911 static const struct drm_encoder_funcs
912 nv50_msto = {
913 .destroy = nv50_msto_destroy,
914 };
915
916 static int
917 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
918 struct nv50_msto **pmsto)
919 {
920 struct nv50_msto *msto;
921 int ret;
922
923 if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
924 return -ENOMEM;
925
926 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
927 DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
928 if (ret) {
929 kfree(*pmsto);
930 *pmsto = NULL;
931 return ret;
932 }
933
934 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
935 msto->encoder.possible_crtcs = heads;
936 return 0;
937 }
938
939 static struct drm_encoder *
940 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
941 struct drm_connector_state *connector_state)
942 {
943 struct nv50_head *head = nv50_head(connector_state->crtc);
944 struct nv50_mstc *mstc = nv50_mstc(connector);
945
946 return &mstc->mstm->msto[head->base.index]->encoder;
947 }
948
949 static struct drm_encoder *
950 nv50_mstc_best_encoder(struct drm_connector *connector)
951 {
952 struct nv50_mstc *mstc = nv50_mstc(connector);
953
954 return &mstc->mstm->msto[0]->encoder;
955 }
956
957 static enum drm_mode_status
958 nv50_mstc_mode_valid(struct drm_connector *connector,
959 struct drm_display_mode *mode)
960 {
961 return MODE_OK;
962 }
963
964 static int
965 nv50_mstc_get_modes(struct drm_connector *connector)
966 {
967 struct nv50_mstc *mstc = nv50_mstc(connector);
968 int ret = 0;
969
970 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
971 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
972 if (mstc->edid)
973 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
974
975 if (!mstc->connector.display_info.bpc)
976 mstc->connector.display_info.bpc = 8;
977
978 if (mstc->native)
979 drm_mode_destroy(mstc->connector.dev, mstc->native);
980 mstc->native = nouveau_conn_native_mode(&mstc->connector);
981 return ret;
982 }
983
984 static int
985 nv50_mstc_atomic_check(struct drm_connector *connector,
986 struct drm_atomic_state *state)
987 {
988 struct nv50_mstc *mstc = nv50_mstc(connector);
989 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
990 struct drm_connector_state *new_conn_state =
991 drm_atomic_get_new_connector_state(state, connector);
992 struct drm_connector_state *old_conn_state =
993 drm_atomic_get_old_connector_state(state, connector);
994 struct drm_crtc_state *crtc_state;
995 struct drm_crtc *new_crtc = new_conn_state->crtc;
996
997 if (!old_conn_state->crtc)
998 return 0;
999
1000 /* We only want to free VCPI if this state disables the CRTC on this
1001 * connector
1002 */
1003 if (new_crtc) {
1004 crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
1005
1006 if (!crtc_state ||
1007 !drm_atomic_crtc_needs_modeset(crtc_state) ||
1008 crtc_state->enable)
1009 return 0;
1010 }
1011
1012 return drm_dp_atomic_release_vcpi_slots(state, mgr, mstc->port);
1013 }
1014
1015 static const struct drm_connector_helper_funcs
1016 nv50_mstc_help = {
1017 .get_modes = nv50_mstc_get_modes,
1018 .mode_valid = nv50_mstc_mode_valid,
1019 .best_encoder = nv50_mstc_best_encoder,
1020 .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
1021 .atomic_check = nv50_mstc_atomic_check,
1022 };
1023
1024 static enum drm_connector_status
1025 nv50_mstc_detect(struct drm_connector *connector, bool force)
1026 {
1027 struct nv50_mstc *mstc = nv50_mstc(connector);
1028 enum drm_connector_status conn_status;
1029 int ret;
1030
1031 if (drm_connector_is_unregistered(connector))
1032 return connector_status_disconnected;
1033
1034 ret = pm_runtime_get_sync(connector->dev->dev);
1035 if (ret < 0 && ret != -EACCES) {
1036 pm_runtime_put_autosuspend(connector->dev->dev);
1037 return connector_status_disconnected;
1038 }
1039
1040 conn_status = drm_dp_mst_detect_port(connector, mstc->port->mgr,
1041 mstc->port);
1042
1043 pm_runtime_mark_last_busy(connector->dev->dev);
1044 pm_runtime_put_autosuspend(connector->dev->dev);
1045 return conn_status;
1046 }
1047
1048 static void
1049 nv50_mstc_destroy(struct drm_connector *connector)
1050 {
1051 struct nv50_mstc *mstc = nv50_mstc(connector);
1052
1053 drm_connector_cleanup(&mstc->connector);
1054 drm_dp_mst_put_port_malloc(mstc->port);
1055
1056 kfree(mstc);
1057 }
1058
1059 static const struct drm_connector_funcs
1060 nv50_mstc = {
1061 .reset = nouveau_conn_reset,
1062 .detect = nv50_mstc_detect,
1063 .fill_modes = drm_helper_probe_single_connector_modes,
1064 .destroy = nv50_mstc_destroy,
1065 .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
1066 .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
1067 .atomic_set_property = nouveau_conn_atomic_set_property,
1068 .atomic_get_property = nouveau_conn_atomic_get_property,
1069 };
1070
1071 static int
1072 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1073 const char *path, struct nv50_mstc **pmstc)
1074 {
1075 struct drm_device *dev = mstm->outp->base.base.dev;
1076 struct nv50_mstc *mstc;
1077 int ret, i;
1078
1079 if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
1080 return -ENOMEM;
1081 mstc->mstm = mstm;
1082 mstc->port = port;
1083
1084 ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
1085 DRM_MODE_CONNECTOR_DisplayPort);
1086 if (ret) {
1087 kfree(*pmstc);
1088 *pmstc = NULL;
1089 return ret;
1090 }
1091
1092 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1093
1094 mstc->connector.funcs->reset(&mstc->connector);
1095 nouveau_conn_attach_properties(&mstc->connector);
1096
1097 for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto[i]; i++)
1098 drm_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
1099
1100 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1101 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1102 drm_connector_set_path_property(&mstc->connector, path);
1103 drm_dp_mst_get_port_malloc(port);
1104 return 0;
1105 }
1106
1107 static void
1108 nv50_mstm_cleanup(struct nv50_mstm *mstm)
1109 {
1110 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1111 struct drm_encoder *encoder;
1112 int ret;
1113
1114 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1115 ret = drm_dp_check_act_status(&mstm->mgr);
1116
1117 ret = drm_dp_update_payload_part2(&mstm->mgr);
1118
1119 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1120 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1121 struct nv50_msto *msto = nv50_msto(encoder);
1122 struct nv50_mstc *mstc = msto->mstc;
1123 if (mstc && mstc->mstm == mstm)
1124 nv50_msto_cleanup(msto);
1125 }
1126 }
1127
1128 mstm->modified = false;
1129 }
1130
1131 static void
1132 nv50_mstm_prepare(struct nv50_mstm *mstm)
1133 {
1134 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1135 struct drm_encoder *encoder;
1136 int ret;
1137
1138 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1139 ret = drm_dp_update_payload_part1(&mstm->mgr);
1140
1141 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1142 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1143 struct nv50_msto *msto = nv50_msto(encoder);
1144 struct nv50_mstc *mstc = msto->mstc;
1145 if (mstc && mstc->mstm == mstm)
1146 nv50_msto_prepare(msto);
1147 }
1148 }
1149
1150 if (mstm->disabled) {
1151 if (!mstm->links)
1152 nv50_outp_release(mstm->outp);
1153 mstm->disabled = false;
1154 }
1155 }
1156
1157 static void
1158 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
1159 struct drm_connector *connector)
1160 {
1161 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1162 struct nv50_mstc *mstc = nv50_mstc(connector);
1163
1164 drm_connector_unregister(&mstc->connector);
1165
1166 drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
1167
1168 drm_connector_put(&mstc->connector);
1169 }
1170
1171 static void
1172 nv50_mstm_register_connector(struct drm_connector *connector)
1173 {
1174 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1175
1176 drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
1177
1178 drm_connector_register(connector);
1179 }
1180
1181 static struct drm_connector *
1182 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
1183 struct drm_dp_mst_port *port, const char *path)
1184 {
1185 struct nv50_mstm *mstm = nv50_mstm(mgr);
1186 struct nv50_mstc *mstc;
1187 int ret;
1188
1189 ret = nv50_mstc_new(mstm, port, path, &mstc);
1190 if (ret)
1191 return NULL;
1192
1193 return &mstc->connector;
1194 }
1195
1196 static const struct drm_dp_mst_topology_cbs
1197 nv50_mstm = {
1198 .add_connector = nv50_mstm_add_connector,
1199 .register_connector = nv50_mstm_register_connector,
1200 .destroy_connector = nv50_mstm_destroy_connector,
1201 };
1202
1203 void
1204 nv50_mstm_service(struct nv50_mstm *mstm)
1205 {
1206 struct drm_dp_aux *aux = mstm ? mstm->mgr.aux : NULL;
1207 bool handled = true;
1208 int ret;
1209 u8 esi[8] = {};
1210
1211 if (!aux)
1212 return;
1213
1214 while (handled) {
1215 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
1216 if (ret != 8) {
1217 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1218 return;
1219 }
1220
1221 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
1222 if (!handled)
1223 break;
1224
1225 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
1226 }
1227 }
1228
1229 void
1230 nv50_mstm_remove(struct nv50_mstm *mstm)
1231 {
1232 if (mstm)
1233 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1234 }
1235
1236 static int
1237 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
1238 {
1239 struct nouveau_encoder *outp = mstm->outp;
1240 struct {
1241 struct nv50_disp_mthd_v1 base;
1242 struct nv50_disp_sor_dp_mst_link_v0 mst;
1243 } args = {
1244 .base.version = 1,
1245 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
1246 .base.hasht = outp->dcb->hasht,
1247 .base.hashm = outp->dcb->hashm,
1248 .mst.state = state,
1249 };
1250 struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
1251 struct nvif_object *disp = &drm->display->disp.object;
1252 int ret;
1253
1254 if (dpcd >= 0x12) {
1255 /* Even if we're enabling MST, start with disabling the
1256 * branching unit to clear any sink-side MST topology state
1257 * that wasn't set by us
1258 */
1259 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, 0);
1260 if (ret < 0)
1261 return ret;
1262
1263 if (state) {
1264 /* Now, start initializing */
1265 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL,
1266 DP_MST_EN);
1267 if (ret < 0)
1268 return ret;
1269 }
1270 }
1271
1272 return nvif_mthd(disp, 0, &args, sizeof(args));
1273 }
1274
1275 int
1276 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
1277 {
1278 struct drm_dp_aux *aux;
1279 int ret;
1280 bool old_state, new_state;
1281 u8 mstm_ctrl;
1282
1283 if (!mstm)
1284 return 0;
1285
1286 mutex_lock(&mstm->mgr.lock);
1287
1288 old_state = mstm->mgr.mst_state;
1289 new_state = old_state;
1290 aux = mstm->mgr.aux;
1291
1292 if (old_state) {
1293 /* Just check that the MST hub is still as we expect it */
1294 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CTRL, &mstm_ctrl);
1295 if (ret < 0 || !(mstm_ctrl & DP_MST_EN)) {
1296 DRM_DEBUG_KMS("Hub gone, disabling MST topology\n");
1297 new_state = false;
1298 }
1299 } else if (dpcd[0] >= 0x12) {
1300 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]);
1301 if (ret < 0)
1302 goto probe_error;
1303
1304 if (!(dpcd[1] & DP_MST_CAP))
1305 dpcd[0] = 0x11;
1306 else
1307 new_state = allow;
1308 }
1309
1310 if (new_state == old_state) {
1311 mutex_unlock(&mstm->mgr.lock);
1312 return new_state;
1313 }
1314
1315 ret = nv50_mstm_enable(mstm, dpcd[0], new_state);
1316 if (ret)
1317 goto probe_error;
1318
1319 mutex_unlock(&mstm->mgr.lock);
1320
1321 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, new_state);
1322 if (ret)
1323 return nv50_mstm_enable(mstm, dpcd[0], 0);
1324
1325 return new_state;
1326
1327 probe_error:
1328 mutex_unlock(&mstm->mgr.lock);
1329 return ret;
1330 }
1331
1332 static void
1333 nv50_mstm_fini(struct nv50_mstm *mstm)
1334 {
1335 if (mstm && mstm->mgr.mst_state)
1336 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1337 }
1338
1339 static void
1340 nv50_mstm_init(struct nv50_mstm *mstm)
1341 {
1342 int ret;
1343
1344 if (!mstm || !mstm->mgr.mst_state)
1345 return;
1346
1347 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr);
1348 if (ret == -1) {
1349 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1350 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1351 }
1352 }
1353
1354 static void
1355 nv50_mstm_del(struct nv50_mstm **pmstm)
1356 {
1357 struct nv50_mstm *mstm = *pmstm;
1358 if (mstm) {
1359 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1360 kfree(*pmstm);
1361 *pmstm = NULL;
1362 }
1363 }
1364
1365 static int
1366 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
1367 int conn_base_id, struct nv50_mstm **pmstm)
1368 {
1369 const int max_payloads = hweight8(outp->dcb->heads);
1370 struct drm_device *dev = outp->base.base.dev;
1371 struct nv50_mstm *mstm;
1372 int ret, i;
1373 u8 dpcd;
1374
1375 /* This is a workaround for some monitors not functioning
1376 * correctly in MST mode on initial module load. I think
1377 * some bad interaction with the VBIOS may be responsible.
1378 *
1379 * A good ol' off and on again seems to work here ;)
1380 */
1381 ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
1382 if (ret >= 0 && dpcd >= 0x12)
1383 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
1384
1385 if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
1386 return -ENOMEM;
1387 mstm->outp = outp;
1388 mstm->mgr.cbs = &nv50_mstm;
1389
1390 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1391 max_payloads, conn_base_id);
1392 if (ret)
1393 return ret;
1394
1395 for (i = 0; i < max_payloads; i++) {
1396 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
1397 i, &mstm->msto[i]);
1398 if (ret)
1399 return ret;
1400 }
1401
1402 return 0;
1403 }
1404
1405 /******************************************************************************
1406 * SOR
1407 *****************************************************************************/
1408 static void
1409 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
1410 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1411 {
1412 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1413 struct nv50_core *core = disp->core;
1414
1415 if (!asyh) {
1416 nv_encoder->ctrl &= ~BIT(head);
1417 if (!(nv_encoder->ctrl & 0x0000000f))
1418 nv_encoder->ctrl = 0;
1419 } else {
1420 nv_encoder->ctrl |= proto << 8;
1421 nv_encoder->ctrl |= BIT(head);
1422 asyh->or.depth = depth;
1423 }
1424
1425 core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
1426 }
1427
1428 static void
1429 nv50_sor_disable(struct drm_encoder *encoder)
1430 {
1431 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1432 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1433
1434 nv_encoder->crtc = NULL;
1435
1436 if (nv_crtc) {
1437 struct nvkm_i2c_aux *aux = nv_encoder->aux;
1438 u8 pwr;
1439
1440 if (aux) {
1441 int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
1442 if (ret == 0) {
1443 pwr &= ~DP_SET_POWER_MASK;
1444 pwr |= DP_SET_POWER_D3;
1445 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
1446 }
1447 }
1448
1449 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
1450 nv50_audio_disable(encoder, nv_crtc);
1451 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
1452 nv50_outp_release(nv_encoder);
1453 }
1454 }
1455
1456 static void
1457 nv50_sor_enable(struct drm_encoder *encoder)
1458 {
1459 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1460 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1461 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1462 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1463 struct {
1464 struct nv50_disp_mthd_v1 base;
1465 struct nv50_disp_sor_lvds_script_v0 lvds;
1466 } lvds = {
1467 .base.version = 1,
1468 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1469 .base.hasht = nv_encoder->dcb->hasht,
1470 .base.hashm = nv_encoder->dcb->hashm,
1471 };
1472 struct nv50_disp *disp = nv50_disp(encoder->dev);
1473 struct drm_device *dev = encoder->dev;
1474 struct nouveau_drm *drm = nouveau_drm(dev);
1475 struct nouveau_connector *nv_connector;
1476 struct nvbios *bios = &drm->vbios;
1477 u8 proto = 0xf;
1478 u8 depth = 0x0;
1479
1480 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1481 nv_encoder->crtc = encoder->crtc;
1482 nv50_outp_acquire(nv_encoder);
1483
1484 switch (nv_encoder->dcb->type) {
1485 case DCB_OUTPUT_TMDS:
1486 if (nv_encoder->link & 1) {
1487 proto = 0x1;
1488 /* Only enable dual-link if:
1489 * - Need to (i.e. rate > 165MHz)
1490 * - DCB says we can
1491 * - Not an HDMI monitor, since there's no dual-link
1492 * on HDMI.
1493 */
1494 if (mode->clock >= 165000 &&
1495 nv_encoder->dcb->duallink_possible &&
1496 !drm_detect_hdmi_monitor(nv_connector->edid))
1497 proto |= 0x4;
1498 } else {
1499 proto = 0x2;
1500 }
1501
1502 nv50_hdmi_enable(&nv_encoder->base.base, mode);
1503 break;
1504 case DCB_OUTPUT_LVDS:
1505 proto = 0x0;
1506
1507 if (bios->fp_no_ddc) {
1508 if (bios->fp.dual_link)
1509 lvds.lvds.script |= 0x0100;
1510 if (bios->fp.if_is_24bit)
1511 lvds.lvds.script |= 0x0200;
1512 } else {
1513 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1514 if (((u8 *)nv_connector->edid)[121] == 2)
1515 lvds.lvds.script |= 0x0100;
1516 } else
1517 if (mode->clock >= bios->fp.duallink_transition_clk) {
1518 lvds.lvds.script |= 0x0100;
1519 }
1520
1521 if (lvds.lvds.script & 0x0100) {
1522 if (bios->fp.strapless_is_24bit & 2)
1523 lvds.lvds.script |= 0x0200;
1524 } else {
1525 if (bios->fp.strapless_is_24bit & 1)
1526 lvds.lvds.script |= 0x0200;
1527 }
1528
1529 if (asyh->or.bpc == 8)
1530 lvds.lvds.script |= 0x0200;
1531 }
1532
1533 nvif_mthd(&disp->disp->object, 0, &lvds, sizeof(lvds));
1534 break;
1535 case DCB_OUTPUT_DP:
1536 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1537
1538 if (nv_encoder->link & 1)
1539 proto = 0x8;
1540 else
1541 proto = 0x9;
1542
1543 nv50_audio_enable(encoder, mode);
1544 break;
1545 default:
1546 BUG();
1547 break;
1548 }
1549
1550 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1551 }
1552
1553 static const struct drm_encoder_helper_funcs
1554 nv50_sor_help = {
1555 .atomic_check = nv50_outp_atomic_check,
1556 .enable = nv50_sor_enable,
1557 .disable = nv50_sor_disable,
1558 };
1559
1560 static void
1561 nv50_sor_destroy(struct drm_encoder *encoder)
1562 {
1563 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1564 nv50_mstm_del(&nv_encoder->dp.mstm);
1565 drm_encoder_cleanup(encoder);
1566 kfree(encoder);
1567 }
1568
1569 static const struct drm_encoder_funcs
1570 nv50_sor_func = {
1571 .destroy = nv50_sor_destroy,
1572 };
1573
1574 static int
1575 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1576 {
1577 struct nouveau_connector *nv_connector = nouveau_connector(connector);
1578 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1579 struct nvkm_bios *bios = nvxx_bios(&drm->client.device);
1580 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1581 struct nouveau_encoder *nv_encoder;
1582 struct drm_encoder *encoder;
1583 u8 ver, hdr, cnt, len;
1584 u32 data;
1585 int type, ret;
1586
1587 switch (dcbe->type) {
1588 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1589 case DCB_OUTPUT_TMDS:
1590 case DCB_OUTPUT_DP:
1591 default:
1592 type = DRM_MODE_ENCODER_TMDS;
1593 break;
1594 }
1595
1596 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1597 if (!nv_encoder)
1598 return -ENOMEM;
1599 nv_encoder->dcb = dcbe;
1600 nv_encoder->update = nv50_sor_update;
1601
1602 encoder = to_drm_encoder(nv_encoder);
1603 encoder->possible_crtcs = dcbe->heads;
1604 encoder->possible_clones = 0;
1605 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1606 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1607 drm_encoder_helper_add(encoder, &nv50_sor_help);
1608
1609 drm_connector_attach_encoder(connector, encoder);
1610
1611 if (dcbe->type == DCB_OUTPUT_DP) {
1612 struct nv50_disp *disp = nv50_disp(encoder->dev);
1613 struct nvkm_i2c_aux *aux =
1614 nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1615 if (aux) {
1616 if (disp->disp->object.oclass < GF110_DISP) {
1617 /* HW has no support for address-only
1618 * transactions, so we're required to
1619 * use custom I2C-over-AUX code.
1620 */
1621 nv_encoder->i2c = &aux->i2c;
1622 } else {
1623 nv_encoder->i2c = &nv_connector->aux.ddc;
1624 }
1625 nv_encoder->aux = aux;
1626 }
1627
1628 if (nv_connector->type != DCB_CONNECTOR_eDP &&
1629 (data = nvbios_dp_table(bios, &ver, &hdr, &cnt, &len)) &&
1630 ver >= 0x40 && (nvbios_rd08(bios, data + 0x08) & 0x04)) {
1631 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
1632 nv_connector->base.base.id,
1633 &nv_encoder->dp.mstm);
1634 if (ret)
1635 return ret;
1636 }
1637 } else {
1638 struct nvkm_i2c_bus *bus =
1639 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1640 if (bus)
1641 nv_encoder->i2c = &bus->i2c;
1642 }
1643
1644 return 0;
1645 }
1646
1647 /******************************************************************************
1648 * PIOR
1649 *****************************************************************************/
1650 static int
1651 nv50_pior_atomic_check(struct drm_encoder *encoder,
1652 struct drm_crtc_state *crtc_state,
1653 struct drm_connector_state *conn_state)
1654 {
1655 int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
1656 if (ret)
1657 return ret;
1658 crtc_state->adjusted_mode.clock *= 2;
1659 return 0;
1660 }
1661
1662 static void
1663 nv50_pior_disable(struct drm_encoder *encoder)
1664 {
1665 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1666 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1667 if (nv_encoder->crtc)
1668 core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL);
1669 nv_encoder->crtc = NULL;
1670 nv50_outp_release(nv_encoder);
1671 }
1672
1673 static void
1674 nv50_pior_enable(struct drm_encoder *encoder)
1675 {
1676 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1677 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1678 struct nouveau_connector *nv_connector;
1679 struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);
1680 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1681 u8 owner = 1 << nv_crtc->index;
1682 u8 proto;
1683
1684 nv50_outp_acquire(nv_encoder);
1685
1686 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1687 switch (asyh->or.bpc) {
1688 case 10: asyh->or.depth = 0x6; break;
1689 case 8: asyh->or.depth = 0x5; break;
1690 case 6: asyh->or.depth = 0x2; break;
1691 default: asyh->or.depth = 0x0; break;
1692 }
1693
1694 switch (nv_encoder->dcb->type) {
1695 case DCB_OUTPUT_TMDS:
1696 case DCB_OUTPUT_DP:
1697 proto = 0x0;
1698 break;
1699 default:
1700 BUG();
1701 break;
1702 }
1703
1704 core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);
1705 nv_encoder->crtc = encoder->crtc;
1706 }
1707
1708 static const struct drm_encoder_helper_funcs
1709 nv50_pior_help = {
1710 .atomic_check = nv50_pior_atomic_check,
1711 .enable = nv50_pior_enable,
1712 .disable = nv50_pior_disable,
1713 };
1714
1715 static void
1716 nv50_pior_destroy(struct drm_encoder *encoder)
1717 {
1718 drm_encoder_cleanup(encoder);
1719 kfree(encoder);
1720 }
1721
1722 static const struct drm_encoder_funcs
1723 nv50_pior_func = {
1724 .destroy = nv50_pior_destroy,
1725 };
1726
1727 static int
1728 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
1729 {
1730 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1731 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
1732 struct nvkm_i2c_bus *bus = NULL;
1733 struct nvkm_i2c_aux *aux = NULL;
1734 struct i2c_adapter *ddc;
1735 struct nouveau_encoder *nv_encoder;
1736 struct drm_encoder *encoder;
1737 int type;
1738
1739 switch (dcbe->type) {
1740 case DCB_OUTPUT_TMDS:
1741 bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
1742 ddc = bus ? &bus->i2c : NULL;
1743 type = DRM_MODE_ENCODER_TMDS;
1744 break;
1745 case DCB_OUTPUT_DP:
1746 aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
1747 ddc = aux ? &aux->i2c : NULL;
1748 type = DRM_MODE_ENCODER_TMDS;
1749 break;
1750 default:
1751 return -ENODEV;
1752 }
1753
1754 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1755 if (!nv_encoder)
1756 return -ENOMEM;
1757 nv_encoder->dcb = dcbe;
1758 nv_encoder->i2c = ddc;
1759 nv_encoder->aux = aux;
1760
1761 encoder = to_drm_encoder(nv_encoder);
1762 encoder->possible_crtcs = dcbe->heads;
1763 encoder->possible_clones = 0;
1764 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
1765 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
1766 drm_encoder_helper_add(encoder, &nv50_pior_help);
1767
1768 drm_connector_attach_encoder(connector, encoder);
1769 return 0;
1770 }
1771
1772 /******************************************************************************
1773 * Atomic
1774 *****************************************************************************/
1775
1776 static void
1777 nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
1778 {
1779 struct nouveau_drm *drm = nouveau_drm(state->dev);
1780 struct nv50_disp *disp = nv50_disp(drm->dev);
1781 struct nv50_core *core = disp->core;
1782 struct nv50_mstm *mstm;
1783 struct drm_encoder *encoder;
1784
1785 NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
1786
1787 drm_for_each_encoder(encoder, drm->dev) {
1788 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1789 mstm = nouveau_encoder(encoder)->dp.mstm;
1790 if (mstm && mstm->modified)
1791 nv50_mstm_prepare(mstm);
1792 }
1793 }
1794
1795 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
1796 core->func->update(core, interlock, true);
1797 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
1798 disp->core->chan.base.device))
1799 NV_ERROR(drm, "core notifier timeout\n");
1800
1801 drm_for_each_encoder(encoder, drm->dev) {
1802 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
1803 mstm = nouveau_encoder(encoder)->dp.mstm;
1804 if (mstm && mstm->modified)
1805 nv50_mstm_cleanup(mstm);
1806 }
1807 }
1808 }
1809
1810 static void
1811 nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
1812 {
1813 struct drm_plane_state *new_plane_state;
1814 struct drm_plane *plane;
1815 int i;
1816
1817 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1818 struct nv50_wndw *wndw = nv50_wndw(plane);
1819 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
1820 if (wndw->func->update)
1821 wndw->func->update(wndw, interlock);
1822 }
1823 }
1824 }
1825
1826 static void
1827 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
1828 {
1829 struct drm_device *dev = state->dev;
1830 struct drm_crtc_state *new_crtc_state, *old_crtc_state;
1831 struct drm_crtc *crtc;
1832 struct drm_plane_state *new_plane_state;
1833 struct drm_plane *plane;
1834 struct nouveau_drm *drm = nouveau_drm(dev);
1835 struct nv50_disp *disp = nv50_disp(dev);
1836 struct nv50_atom *atom = nv50_atom(state);
1837 struct nv50_outp_atom *outp, *outt;
1838 u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
1839 int i;
1840
1841 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
1842 drm_atomic_helper_wait_for_fences(dev, state, false);
1843 drm_atomic_helper_wait_for_dependencies(state);
1844 drm_atomic_helper_update_legacy_modeset_state(dev, state);
1845
1846 if (atom->lock_core)
1847 mutex_lock(&disp->mutex);
1848
1849 /* Disable head(s). */
1850 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1851 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1852 struct nv50_head *head = nv50_head(crtc);
1853
1854 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
1855 asyh->clr.mask, asyh->set.mask);
1856
1857 if (old_crtc_state->active && !new_crtc_state->active) {
1858 pm_runtime_put_noidle(dev->dev);
1859 drm_crtc_vblank_off(crtc);
1860 }
1861
1862 if (asyh->clr.mask) {
1863 nv50_head_flush_clr(head, asyh, atom->flush_disable);
1864 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1865 }
1866 }
1867
1868 /* Disable plane(s). */
1869 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1870 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1871 struct nv50_wndw *wndw = nv50_wndw(plane);
1872
1873 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
1874 asyw->clr.mask, asyw->set.mask);
1875 if (!asyw->clr.mask)
1876 continue;
1877
1878 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
1879 }
1880
1881 /* Disable output path(s). */
1882 list_for_each_entry(outp, &atom->outp, head) {
1883 const struct drm_encoder_helper_funcs *help;
1884 struct drm_encoder *encoder;
1885
1886 encoder = outp->encoder;
1887 help = encoder->helper_private;
1888
1889 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
1890 outp->clr.mask, outp->set.mask);
1891
1892 if (outp->clr.mask) {
1893 help->disable(encoder);
1894 interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
1895 if (outp->flush_disable) {
1896 nv50_disp_atomic_commit_wndw(state, interlock);
1897 nv50_disp_atomic_commit_core(state, interlock);
1898 memset(interlock, 0x00, sizeof(interlock));
1899 }
1900 }
1901 }
1902
1903 /* Flush disable. */
1904 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1905 if (atom->flush_disable) {
1906 nv50_disp_atomic_commit_wndw(state, interlock);
1907 nv50_disp_atomic_commit_core(state, interlock);
1908 memset(interlock, 0x00, sizeof(interlock));
1909 }
1910 }
1911
1912 /* Update output path(s). */
1913 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
1914 const struct drm_encoder_helper_funcs *help;
1915 struct drm_encoder *encoder;
1916
1917 encoder = outp->encoder;
1918 help = encoder->helper_private;
1919
1920 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
1921 outp->set.mask, outp->clr.mask);
1922
1923 if (outp->set.mask) {
1924 help->enable(encoder);
1925 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1926 }
1927
1928 list_del(&outp->head);
1929 kfree(outp);
1930 }
1931
1932 /* Update head(s). */
1933 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1934 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
1935 struct nv50_head *head = nv50_head(crtc);
1936
1937 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
1938 asyh->set.mask, asyh->clr.mask);
1939
1940 if (asyh->set.mask) {
1941 nv50_head_flush_set(head, asyh);
1942 interlock[NV50_DISP_INTERLOCK_CORE] = 1;
1943 }
1944
1945 if (new_crtc_state->active) {
1946 if (!old_crtc_state->active) {
1947 drm_crtc_vblank_on(crtc);
1948 pm_runtime_get_noresume(dev->dev);
1949 }
1950 if (new_crtc_state->event)
1951 drm_crtc_vblank_get(crtc);
1952 }
1953 }
1954
1955 /* Update plane(s). */
1956 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1957 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1958 struct nv50_wndw *wndw = nv50_wndw(plane);
1959
1960 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
1961 asyw->set.mask, asyw->clr.mask);
1962 if ( !asyw->set.mask &&
1963 (!asyw->clr.mask || atom->flush_disable))
1964 continue;
1965
1966 nv50_wndw_flush_set(wndw, interlock, asyw);
1967 }
1968
1969 /* Flush update. */
1970 nv50_disp_atomic_commit_wndw(state, interlock);
1971
1972 if (interlock[NV50_DISP_INTERLOCK_CORE]) {
1973 if (interlock[NV50_DISP_INTERLOCK_BASE] ||
1974 interlock[NV50_DISP_INTERLOCK_OVLY] ||
1975 interlock[NV50_DISP_INTERLOCK_WNDW] ||
1976 !atom->state.legacy_cursor_update)
1977 nv50_disp_atomic_commit_core(state, interlock);
1978 else
1979 disp->core->func->update(disp->core, interlock, false);
1980 }
1981
1982 if (atom->lock_core)
1983 mutex_unlock(&disp->mutex);
1984
1985 /* Wait for HW to signal completion. */
1986 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
1987 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
1988 struct nv50_wndw *wndw = nv50_wndw(plane);
1989 int ret = nv50_wndw_wait_armed(wndw, asyw);
1990 if (ret)
1991 NV_ERROR(drm, "%s: timeout\n", plane->name);
1992 }
1993
1994 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
1995 if (new_crtc_state->event) {
1996 unsigned long flags;
1997 /* Get correct count/ts if racing with vblank irq */
1998 if (new_crtc_state->active)
1999 drm_crtc_accurate_vblank_count(crtc);
2000 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2001 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2002 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2003
2004 new_crtc_state->event = NULL;
2005 if (new_crtc_state->active)
2006 drm_crtc_vblank_put(crtc);
2007 }
2008 }
2009
2010 drm_atomic_helper_commit_hw_done(state);
2011 drm_atomic_helper_cleanup_planes(dev, state);
2012 drm_atomic_helper_commit_cleanup_done(state);
2013 drm_atomic_state_put(state);
2014
2015 /* Drop the RPM ref we got from nv50_disp_atomic_commit() */
2016 pm_runtime_mark_last_busy(dev->dev);
2017 pm_runtime_put_autosuspend(dev->dev);
2018 }
2019
2020 static void
2021 nv50_disp_atomic_commit_work(struct work_struct *work)
2022 {
2023 struct drm_atomic_state *state =
2024 container_of(work, typeof(*state), commit_work);
2025 nv50_disp_atomic_commit_tail(state);
2026 }
2027
2028 static int
2029 nv50_disp_atomic_commit(struct drm_device *dev,
2030 struct drm_atomic_state *state, bool nonblock)
2031 {
2032 struct drm_plane_state *new_plane_state;
2033 struct drm_plane *plane;
2034 int ret, i;
2035
2036 ret = pm_runtime_get_sync(dev->dev);
2037 if (ret < 0 && ret != -EACCES) {
2038 pm_runtime_put_autosuspend(dev->dev);
2039 return ret;
2040 }
2041
2042 ret = drm_atomic_helper_setup_commit(state, nonblock);
2043 if (ret)
2044 goto done;
2045
2046 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2047
2048 ret = drm_atomic_helper_prepare_planes(dev, state);
2049 if (ret)
2050 goto done;
2051
2052 if (!nonblock) {
2053 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
2054 if (ret)
2055 goto err_cleanup;
2056 }
2057
2058 ret = drm_atomic_helper_swap_state(state, true);
2059 if (ret)
2060 goto err_cleanup;
2061
2062 for_each_new_plane_in_state(state, plane, new_plane_state, i) {
2063 struct nv50_wndw_atom *asyw = nv50_wndw_atom(new_plane_state);
2064 struct nv50_wndw *wndw = nv50_wndw(plane);
2065
2066 if (asyw->set.image)
2067 nv50_wndw_ntfy_enable(wndw, asyw);
2068 }
2069
2070 drm_atomic_state_get(state);
2071
2072 /*
2073 * Grab another RPM ref for the commit tail, which will release the
2074 * ref when it's finished
2075 */
2076 pm_runtime_get_noresume(dev->dev);
2077
2078 if (nonblock)
2079 queue_work(system_unbound_wq, &state->commit_work);
2080 else
2081 nv50_disp_atomic_commit_tail(state);
2082
2083 err_cleanup:
2084 if (ret)
2085 drm_atomic_helper_cleanup_planes(dev, state);
2086 done:
2087 pm_runtime_put_autosuspend(dev->dev);
2088 return ret;
2089 }
2090
2091 static struct nv50_outp_atom *
2092 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
2093 {
2094 struct nv50_outp_atom *outp;
2095
2096 list_for_each_entry(outp, &atom->outp, head) {
2097 if (outp->encoder == encoder)
2098 return outp;
2099 }
2100
2101 outp = kzalloc(sizeof(*outp), GFP_KERNEL);
2102 if (!outp)
2103 return ERR_PTR(-ENOMEM);
2104
2105 list_add(&outp->head, &atom->outp);
2106 outp->encoder = encoder;
2107 return outp;
2108 }
2109
2110 static int
2111 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
2112 struct drm_connector_state *old_connector_state)
2113 {
2114 struct drm_encoder *encoder = old_connector_state->best_encoder;
2115 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2116 struct drm_crtc *crtc;
2117 struct nv50_outp_atom *outp;
2118
2119 if (!(crtc = old_connector_state->crtc))
2120 return 0;
2121
2122 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2123 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2124 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2125 outp = nv50_disp_outp_atomic_add(atom, encoder);
2126 if (IS_ERR(outp))
2127 return PTR_ERR(outp);
2128
2129 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
2130 outp->flush_disable = true;
2131 atom->flush_disable = true;
2132 }
2133 outp->clr.ctrl = true;
2134 atom->lock_core = true;
2135 }
2136
2137 return 0;
2138 }
2139
2140 static int
2141 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
2142 struct drm_connector_state *connector_state)
2143 {
2144 struct drm_encoder *encoder = connector_state->best_encoder;
2145 struct drm_crtc_state *new_crtc_state;
2146 struct drm_crtc *crtc;
2147 struct nv50_outp_atom *outp;
2148
2149 if (!(crtc = connector_state->crtc))
2150 return 0;
2151
2152 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2153 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2154 outp = nv50_disp_outp_atomic_add(atom, encoder);
2155 if (IS_ERR(outp))
2156 return PTR_ERR(outp);
2157
2158 outp->set.ctrl = true;
2159 atom->lock_core = true;
2160 }
2161
2162 return 0;
2163 }
2164
2165 static int
2166 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
2167 {
2168 struct nv50_atom *atom = nv50_atom(state);
2169 struct drm_connector_state *old_connector_state, *new_connector_state;
2170 struct drm_connector *connector;
2171 struct drm_crtc_state *new_crtc_state;
2172 struct drm_crtc *crtc;
2173 int ret, i;
2174
2175 /* We need to handle colour management on a per-plane basis. */
2176 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2177 if (new_crtc_state->color_mgmt_changed) {
2178 ret = drm_atomic_add_affected_planes(state, crtc);
2179 if (ret)
2180 return ret;
2181 }
2182 }
2183
2184 ret = drm_atomic_helper_check(dev, state);
2185 if (ret)
2186 return ret;
2187
2188 for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) {
2189 ret = nv50_disp_outp_atomic_check_clr(atom, old_connector_state);
2190 if (ret)
2191 return ret;
2192
2193 ret = nv50_disp_outp_atomic_check_set(atom, new_connector_state);
2194 if (ret)
2195 return ret;
2196 }
2197
2198 ret = drm_dp_mst_atomic_check(state);
2199 if (ret)
2200 return ret;
2201
2202 return 0;
2203 }
2204
2205 static void
2206 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
2207 {
2208 struct nv50_atom *atom = nv50_atom(state);
2209 struct nv50_outp_atom *outp, *outt;
2210
2211 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2212 list_del(&outp->head);
2213 kfree(outp);
2214 }
2215
2216 drm_atomic_state_default_clear(state);
2217 }
2218
2219 static void
2220 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
2221 {
2222 struct nv50_atom *atom = nv50_atom(state);
2223 drm_atomic_state_default_release(&atom->state);
2224 kfree(atom);
2225 }
2226
2227 static struct drm_atomic_state *
2228 nv50_disp_atomic_state_alloc(struct drm_device *dev)
2229 {
2230 struct nv50_atom *atom;
2231 if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
2232 drm_atomic_state_init(dev, &atom->state) < 0) {
2233 kfree(atom);
2234 return NULL;
2235 }
2236 INIT_LIST_HEAD(&atom->outp);
2237 return &atom->state;
2238 }
2239
2240 static const struct drm_mode_config_funcs
2241 nv50_disp_func = {
2242 .fb_create = nouveau_user_framebuffer_create,
2243 .output_poll_changed = nouveau_fbcon_output_poll_changed,
2244 .atomic_check = nv50_disp_atomic_check,
2245 .atomic_commit = nv50_disp_atomic_commit,
2246 .atomic_state_alloc = nv50_disp_atomic_state_alloc,
2247 .atomic_state_clear = nv50_disp_atomic_state_clear,
2248 .atomic_state_free = nv50_disp_atomic_state_free,
2249 };
2250
2251 /******************************************************************************
2252 * Init
2253 *****************************************************************************/
2254
2255 static void
2256 nv50_display_fini(struct drm_device *dev, bool suspend)
2257 {
2258 struct nouveau_encoder *nv_encoder;
2259 struct drm_encoder *encoder;
2260 struct drm_plane *plane;
2261
2262 drm_for_each_plane(plane, dev) {
2263 struct nv50_wndw *wndw = nv50_wndw(plane);
2264 if (plane->funcs != &nv50_wndw)
2265 continue;
2266 nv50_wndw_fini(wndw);
2267 }
2268
2269 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2270 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2271 nv_encoder = nouveau_encoder(encoder);
2272 nv50_mstm_fini(nv_encoder->dp.mstm);
2273 }
2274 }
2275 }
2276
2277 static int
2278 nv50_display_init(struct drm_device *dev, bool resume, bool runtime)
2279 {
2280 struct nv50_core *core = nv50_disp(dev)->core;
2281 struct drm_encoder *encoder;
2282 struct drm_plane *plane;
2283
2284 core->func->init(core);
2285
2286 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2287 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2288 struct nouveau_encoder *nv_encoder =
2289 nouveau_encoder(encoder);
2290 nv50_mstm_init(nv_encoder->dp.mstm);
2291 }
2292 }
2293
2294 drm_for_each_plane(plane, dev) {
2295 struct nv50_wndw *wndw = nv50_wndw(plane);
2296 if (plane->funcs != &nv50_wndw)
2297 continue;
2298 nv50_wndw_init(wndw);
2299 }
2300
2301 return 0;
2302 }
2303
2304 static void
2305 nv50_display_destroy(struct drm_device *dev)
2306 {
2307 struct nv50_disp *disp = nv50_disp(dev);
2308
2309 nv50_core_del(&disp->core);
2310
2311 nouveau_bo_unmap(disp->sync);
2312 if (disp->sync)
2313 nouveau_bo_unpin(disp->sync);
2314 nouveau_bo_ref(NULL, &disp->sync);
2315
2316 nouveau_display(dev)->priv = NULL;
2317 kfree(disp);
2318 }
2319
2320 int
2321 nv50_display_create(struct drm_device *dev)
2322 {
2323 struct nvif_device *device = &nouveau_drm(dev)->client.device;
2324 struct nouveau_drm *drm = nouveau_drm(dev);
2325 struct dcb_table *dcb = &drm->vbios.dcb;
2326 struct drm_connector *connector, *tmp;
2327 struct nv50_disp *disp;
2328 struct dcb_output *dcbe;
2329 int crtcs, ret, i;
2330
2331 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2332 if (!disp)
2333 return -ENOMEM;
2334
2335 mutex_init(&disp->mutex);
2336
2337 nouveau_display(dev)->priv = disp;
2338 nouveau_display(dev)->dtor = nv50_display_destroy;
2339 nouveau_display(dev)->init = nv50_display_init;
2340 nouveau_display(dev)->fini = nv50_display_fini;
2341 disp->disp = &nouveau_display(dev)->disp;
2342 dev->mode_config.funcs = &nv50_disp_func;
2343 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2344 dev->mode_config.normalize_zpos = true;
2345
2346 /* small shared memory area we use for notifiers and semaphores */
2347 ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2348 0, 0x0000, NULL, NULL, &disp->sync);
2349 if (!ret) {
2350 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2351 if (!ret) {
2352 ret = nouveau_bo_map(disp->sync);
2353 if (ret)
2354 nouveau_bo_unpin(disp->sync);
2355 }
2356 if (ret)
2357 nouveau_bo_ref(NULL, &disp->sync);
2358 }
2359
2360 if (ret)
2361 goto out;
2362
2363 /* allocate master evo channel */
2364 ret = nv50_core_new(drm, &disp->core);
2365 if (ret)
2366 goto out;
2367
2368 /* create crtc objects to represent the hw heads */
2369 if (disp->disp->object.oclass >= GV100_DISP)
2370 crtcs = nvif_rd32(&device->object, 0x610060) & 0xff;
2371 else
2372 if (disp->disp->object.oclass >= GF110_DISP)
2373 crtcs = nvif_rd32(&device->object, 0x612004) & 0xf;
2374 else
2375 crtcs = 0x3;
2376
2377 for (i = 0; i < fls(crtcs); i++) {
2378 if (!(crtcs & (1 << i)))
2379 continue;
2380 ret = nv50_head_create(dev, i);
2381 if (ret)
2382 goto out;
2383 }
2384
2385 /* create encoder/connector objects based on VBIOS DCB table */
2386 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2387 connector = nouveau_connector_create(dev, dcbe);
2388 if (IS_ERR(connector))
2389 continue;
2390
2391 if (dcbe->location == DCB_LOC_ON_CHIP) {
2392 switch (dcbe->type) {
2393 case DCB_OUTPUT_TMDS:
2394 case DCB_OUTPUT_LVDS:
2395 case DCB_OUTPUT_DP:
2396 ret = nv50_sor_create(connector, dcbe);
2397 break;
2398 case DCB_OUTPUT_ANALOG:
2399 ret = nv50_dac_create(connector, dcbe);
2400 break;
2401 default:
2402 ret = -ENODEV;
2403 break;
2404 }
2405 } else {
2406 ret = nv50_pior_create(connector, dcbe);
2407 }
2408
2409 if (ret) {
2410 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2411 dcbe->location, dcbe->type,
2412 ffs(dcbe->or) - 1, ret);
2413 ret = 0;
2414 }
2415 }
2416
2417 /* cull any connectors we created that don't have an encoder */
2418 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2419 if (connector->encoder_ids[0])
2420 continue;
2421
2422 NV_WARN(drm, "%s has no encoders, removing\n",
2423 connector->name);
2424 connector->funcs->destroy(connector);
2425 }
2426
2427 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
2428 dev->vblank_disable_immediate = true;
2429
2430 out:
2431 if (ret)
2432 nv50_display_destroy(dev);
2433 return ret;
2434 }
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